* [PATCH 01/17] i.MX35 stack: Fix mc9sdz60 reset register offset
2010-04-29 7:51 patches for next v2 Sascha Hauer
@ 2010-04-29 7:51 ` Sascha Hauer
2010-04-29 7:52 ` [PATCH 02/17] ARM: use memalign in dma_alloc_coherent to assure alignment Sascha Hauer
` (15 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:51 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
board/freescale-mx35-3-stack/3stack.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale-mx35-3-stack/3stack.c b/board/freescale-mx35-3-stack/3stack.c
index 481f9f0..fcb87cf 100644
--- a/board/freescale-mx35-3-stack/3stack.c
+++ b/board/freescale-mx35-3-stack/3stack.c
@@ -396,9 +396,9 @@ static int f3s_pmic_init_all(struct mc9sdz60 *mc9sdz60)
err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_GPIO_1, 0x04, 0x04);
- err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_2, 0x80, 0x00);
+ err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x00);
mdelay(200);
- err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_2, 0x80, 0x80);
+ err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x80);
if (err)
dev_err(&mc9sdz60->client->dev,
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 02/17] ARM: use memalign in dma_alloc_coherent to assure alignment
2010-04-29 7:51 patches for next v2 Sascha Hauer
2010-04-29 7:51 ` [PATCH 01/17] i.MX35 stack: Fix mc9sdz60 reset register offset Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
2010-04-29 7:52 ` [PATCH 03/17] fsl_udc: make it work with MMU on Sascha Hauer
` (14 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/mmu.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 66ee987..5bf31c0 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -99,7 +99,7 @@ void *dma_alloc_coherent(size_t size)
{
void *mem;
- mem = malloc(size);
+ mem = memalign(4096, size);
if (mem)
return mem + dma_coherent_offset;
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 03/17] fsl_udc: make it work with MMU on
2010-04-29 7:51 patches for next v2 Sascha Hauer
2010-04-29 7:51 ` [PATCH 01/17] i.MX35 stack: Fix mc9sdz60 reset register offset Sascha Hauer
2010-04-29 7:52 ` [PATCH 02/17] ARM: use memalign in dma_alloc_coherent to assure alignment Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
2010-04-29 7:52 ` [PATCH 04/17] Increase MAX_FILES to 128 Sascha Hauer
` (13 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/usb/gadget/fsl_udc.c | 11 ++++++-----
1 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/gadget/fsl_udc.c b/drivers/usb/gadget/fsl_udc.c
index 95f3bdd..119afcb 100644
--- a/drivers/usb/gadget/fsl_udc.c
+++ b/drivers/usb/gadget/fsl_udc.c
@@ -560,7 +560,7 @@ static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
if (j != req->dtd_count - 1) {
next_td = curr_td->next_td_virt;
}
- free(curr_td);
+ dma_free_coherent(curr_td);
}
dma_inv_range(req->req.buf, req->req.buf + req->req.length);
@@ -1112,11 +1112,11 @@ static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
*length = min(req->req.length - req->req.actual,
(unsigned)EP_MAX_LENGTH_TRANSFER);
- dtd = memalign(32, sizeof(struct ep_td_struct));
+ dtd = dma_alloc_coherent(sizeof(struct ep_td_struct));
if (dtd == NULL)
return dtd;
- *dma = (dma_addr_t)dtd;
+ *dma = (dma_addr_t)virt_to_phys(dtd);
dtd->td_dma = *dma;
/* Clear reserved field */
swap_temp = cpu_to_le32(dtd->size_ioc_sts);
@@ -2078,13 +2078,14 @@ static int struct_udc_setup(struct fsl_udc *udc,
size += QH_ALIGNMENT + 1;
size &= ~(QH_ALIGNMENT - 1);
}
- udc->ep_qh = memalign(2048, size);
+
+ udc->ep_qh = dma_alloc_coherent(size);
if (!udc->ep_qh) {
ERR("malloc QHs for udc failed\n");
kfree(udc->eps);
return -1;
}
- udc->ep_qh_dma = (dma_addr_t)udc->ep_qh;
+ udc->ep_qh_dma = (dma_addr_t)virt_to_phys(udc->ep_qh);
udc->ep_qh_size = size;
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 04/17] Increase MAX_FILES to 128
2010-04-29 7:51 patches for next v2 Sascha Hauer
` (2 preceding siblings ...)
2010-04-29 7:52 ` [PATCH 03/17] fsl_udc: make it work with MMU on Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
2010-04-29 7:52 ` [PATCH 05/17] fix _update scripts Sascha Hauer
` (12 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
I already hit the limit while doing DFU on a custom board. Increase the
value to a safe limit.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/stdio.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/stdio.h b/include/stdio.h
index cd1a913..d591b6a 100644
--- a/include/stdio.h
+++ b/include/stdio.h
@@ -49,7 +49,7 @@ int vsnprintf(char *buf, size_t size, const char *fmt, va_list args);
#define stdin 0
#define stdout 1
#define stderr 2
-#define MAX_FILES 16
+#define MAX_FILES 128
void fprintf(int file, const char *fmt, ...);
int fputs(int file, const char *s);
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 05/17] fix _update scripts
2010-04-29 7:51 patches for next v2 Sascha Hauer
` (3 preceding siblings ...)
2010-04-29 7:52 ` [PATCH 04/17] Increase MAX_FILES to 128 Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
2010-04-29 7:52 ` [PATCH 06/17] define __LINUX_ARM_ARCH__ for armv6 processors Sascha Hauer
` (11 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
board/a9m2410/env/bin/_update | 2 +-
board/a9m2440/env/bin/_update | 2 +-
board/at91sam9260ek/env/bin/_update | 2 +-
board/at91sam9263ek/env/bin/_update | 2 +-
board/eukrea_cpuimx27/env/bin/_update | 2 +-
board/freescale-mx25-3-stack/env/bin/_update | 2 +-
board/freescale-mx35-3-stack/env/bin/_update | 2 +-
board/imx27ads/env/bin/_update | 2 +-
board/ipe337/env/bin/_update | 2 +-
board/kp_ukd_r1_num/env/bin/_update | 2 +-
board/mmccpu/env/bin/_update | 2 +-
board/pcm037/env/bin/_update | 2 +-
board/pcm038/env/bin/_update | 2 +-
board/pcm043/env/bin/_update | 2 +-
board/phycard-i.MX27/env/bin/_update | 2 +-
board/phycore_mcf54xx/env/bin/_update | 2 +-
board/pm9263/env/bin/_update | 2 +-
17 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/board/a9m2410/env/bin/_update b/board/a9m2410/env/bin/_update
index fb7cbe8..014bce3 100644
--- a/board/a9m2410/env/bin/_update
+++ b/board/a9m2410/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/a9m2440/env/bin/_update b/board/a9m2440/env/bin/_update
index e76eac9..b10682e 100644
--- a/board/a9m2440/env/bin/_update
+++ b/board/a9m2440/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/at91sam9260ek/env/bin/_update b/board/at91sam9260ek/env/bin/_update
index fb7cbe8..014bce3 100644
--- a/board/at91sam9260ek/env/bin/_update
+++ b/board/at91sam9260ek/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/at91sam9263ek/env/bin/_update b/board/at91sam9263ek/env/bin/_update
index fb7cbe8..014bce3 100644
--- a/board/at91sam9263ek/env/bin/_update
+++ b/board/at91sam9263ek/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/eukrea_cpuimx27/env/bin/_update b/board/eukrea_cpuimx27/env/bin/_update
index fb7cbe8..014bce3 100644
--- a/board/eukrea_cpuimx27/env/bin/_update
+++ b/board/eukrea_cpuimx27/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/freescale-mx25-3-stack/env/bin/_update b/board/freescale-mx25-3-stack/env/bin/_update
index fb7cbe8..014bce3 100644
--- a/board/freescale-mx25-3-stack/env/bin/_update
+++ b/board/freescale-mx25-3-stack/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/freescale-mx35-3-stack/env/bin/_update b/board/freescale-mx35-3-stack/env/bin/_update
index 4f0839f..ddd6b84 100644
--- a/board/freescale-mx35-3-stack/env/bin/_update
+++ b/board/freescale-mx35-3-stack/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/imx27ads/env/bin/_update b/board/imx27ads/env/bin/_update
index fb7cbe8..014bce3 100644
--- a/board/imx27ads/env/bin/_update
+++ b/board/imx27ads/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/ipe337/env/bin/_update b/board/ipe337/env/bin/_update
index 124e285..5419ece 100644
--- a/board/ipe337/env/bin/_update
+++ b/board/ipe337/env/bin/_update
@@ -9,7 +9,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/kp_ukd_r1_num/env/bin/_update b/board/kp_ukd_r1_num/env/bin/_update
index fb7cbe8..014bce3 100644
--- a/board/kp_ukd_r1_num/env/bin/_update
+++ b/board/kp_ukd_r1_num/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/mmccpu/env/bin/_update b/board/mmccpu/env/bin/_update
index fb7cbe8..014bce3 100644
--- a/board/mmccpu/env/bin/_update
+++ b/board/mmccpu/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/pcm037/env/bin/_update b/board/pcm037/env/bin/_update
index fb7cbe8..014bce3 100644
--- a/board/pcm037/env/bin/_update
+++ b/board/pcm037/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/pcm038/env/bin/_update b/board/pcm038/env/bin/_update
index fb7cbe8..014bce3 100644
--- a/board/pcm038/env/bin/_update
+++ b/board/pcm038/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/pcm043/env/bin/_update b/board/pcm043/env/bin/_update
index fb7cbe8..014bce3 100644
--- a/board/pcm043/env/bin/_update
+++ b/board/pcm043/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/phycard-i.MX27/env/bin/_update b/board/phycard-i.MX27/env/bin/_update
index fb7cbe8..014bce3 100644
--- a/board/phycard-i.MX27/env/bin/_update
+++ b/board/phycard-i.MX27/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/phycore_mcf54xx/env/bin/_update b/board/phycore_mcf54xx/env/bin/_update
index fb7cbe8..014bce3 100644
--- a/board/phycore_mcf54xx/env/bin/_update
+++ b/board/phycore_mcf54xx/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
diff --git a/board/pm9263/env/bin/_update b/board/pm9263/env/bin/_update
index fb7cbe8..014bce3 100644
--- a/board/pm9263/env/bin/_update
+++ b/board/pm9263/env/bin/_update
@@ -5,7 +5,7 @@ if [ -z "$part" -o -z "$image" ]; then
exit 1
fi
-if [ \! -e "$part" ]; then
+if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 06/17] define __LINUX_ARM_ARCH__ for armv6 processors
2010-04-29 7:51 patches for next v2 Sascha Hauer
` (4 preceding siblings ...)
2010-04-29 7:52 ` [PATCH 05/17] fix _update scripts Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
2010-04-29 7:52 ` [PATCH 07/17] ARM: Add get_cr/set_cr functions Sascha Hauer
` (10 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/Makefile | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index fbbea42..b1991c3 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -20,6 +20,7 @@ comma = ,
# macro, but instead defines a whole series of macros which makes
# testing for a specific architecture or later rather impossible.
arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
+arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
arch-$(CONFIG_CPU_32v5) :=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
arch-$(CONFIG_CPU_32v4T) :=-D__LINUX_ARM_ARCH__=4 -march=armv4t
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 07/17] ARM: Add get_cr/set_cr functions
2010-04-29 7:51 patches for next v2 Sascha Hauer
` (5 preceding siblings ...)
2010-04-29 7:52 ` [PATCH 06/17] define __LINUX_ARM_ARCH__ for armv6 processors Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
2010-04-29 7:52 ` [PATCH 08/17] ARM: update icache functions to use get_cr/set_cr Sascha Hauer
` (9 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/include/asm/system.h | 72 +++++++++++++++++++++++++++++++++++++++++
1 files changed, 72 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/system.h
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
new file mode 100644
index 0000000..77d6305
--- /dev/null
+++ b/arch/arm/include/asm/system.h
@@ -0,0 +1,72 @@
+#ifndef __ASM_ARM_SYSTEM_H
+#define __ASM_ARM_SYSTEM_H
+
+#if __LINUX_ARM_ARCH__ >= 7
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
+#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
+ : : "r" (0) : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+ : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
+ : : "r" (0) : "memory")
+#elif defined(CONFIG_CPU_FA526)
+#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
+ : : "r" (0) : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+ : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#else
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+ : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#endif
+
+/*
+ * CR1 bits (CP#15 CR1)
+ */
+#define CR_M (1 << 0) /* MMU enable */
+#define CR_A (1 << 1) /* Alignment abort enable */
+#define CR_C (1 << 2) /* Dcache enable */
+#define CR_W (1 << 3) /* Write buffer enable */
+#define CR_P (1 << 4) /* 32-bit exception handler */
+#define CR_D (1 << 5) /* 32-bit data address range */
+#define CR_L (1 << 6) /* Implementation defined */
+#define CR_B (1 << 7) /* Big endian */
+#define CR_S (1 << 8) /* System MMU protection */
+#define CR_R (1 << 9) /* ROM MMU protection */
+#define CR_F (1 << 10) /* Implementation defined */
+#define CR_Z (1 << 11) /* Implementation defined */
+#define CR_I (1 << 12) /* Icache enable */
+#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
+#define CR_RR (1 << 14) /* Round Robin cache replacement */
+#define CR_L4 (1 << 15) /* LDR pc can set T bit */
+#define CR_DT (1 << 16)
+#define CR_IT (1 << 18)
+#define CR_ST (1 << 19)
+#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
+#define CR_U (1 << 22) /* Unaligned access operation */
+#define CR_XP (1 << 23) /* Extended page tables */
+#define CR_VE (1 << 24) /* Vectored interrupts */
+#define CR_EE (1 << 25) /* Exception (Big) Endian */
+#define CR_TRE (1 << 28) /* TEX remap enable */
+#define CR_AFE (1 << 29) /* Access flag enable */
+#define CR_TE (1 << 30) /* Thumb exception enable */
+
+static inline unsigned int get_cr(void)
+{
+ unsigned int val;
+ asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
+ return val;
+}
+
+static inline void set_cr(unsigned int val)
+{
+ asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
+ : : "r" (val) : "cc");
+ isb();
+}
+#endif /* __ASM_ARM_SYSTEM_H */
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 08/17] ARM: update icache functions to use get_cr/set_cr
2010-04-29 7:51 patches for next v2 Sascha Hauer
` (6 preceding siblings ...)
2010-04-29 7:52 ` [PATCH 07/17] ARM: Add get_cr/set_cr functions Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
2010-04-29 7:52 ` [PATCH 09/17] pcm043: Speed up NAND controller before copying barebox image Sascha Hauer
` (8 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/cpu.c | 94 +++++++--------------------------------------------
1 files changed, 13 insertions(+), 81 deletions(-)
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index a5e2fe2..fbc91aa 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -28,107 +28,39 @@
#include <common.h>
#include <command.h>
#include <asm/mmu.h>
-
-/**
- * Read special processor register
- * @return co-processor 15, register #1 (control register)
- */
-static unsigned long read_p15_c1 (void)
-{
- unsigned long value;
-
- __asm__ __volatile__(
- "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
- : "=r" (value)
- :
- : "memory");
-
-#ifdef MMU_DEBUG
- printf ("p15/c1 is = %08lx\n", value);
-#endif
- return value;
-}
-
-/**
- *
- * Write special processor register
- * @param[in] value to write
- * @return to co-processor 15, register #1 (control register)
- */
-static void write_p15_c1 (unsigned long value)
-{
-#ifdef MMU_DEBUG
- printf ("write %08lx to p15/c1\n", value);
-#endif
- __asm__ __volatile__(
- "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
- :
- : "r" (value)
- : "memory");
-
- read_p15_c1 ();
-}
-
-/**
- * Wait for co prozessor (waste time)
- * Co processor seems to need some delay between accesses
- */
-static void cp_delay (void)
-{
- volatile int i;
-
- for (i = 0; i < 100; i++) /* FIXME does it work as expected?? */
- ;
-}
-
-/** mmu off/on */
-#define C1_MMU (1<<0)
-/** alignment faults off/on */
-#define C1_ALIGN (1<<1)
-/** dcache off/on */
-#define C1_DC (1<<2)
-/** big endian off/on */
-#define C1_BIG_ENDIAN (1<<7)
-/** system protection */
-#define C1_SYS_PROT (1<<8)
-/** ROM protection */
-#define C1_ROM_PROT (1<<9)
-/** icache off/on */
-#define C1_IC (1<<12)
-/** location of vectors: low/high addresses */
-#define C1_HIGH_VECTORS (1<<13)
+#include <asm/system.h>
/**
* Enable processor's instruction cache
*/
-void icache_enable (void)
+void icache_enable(void)
{
- ulong reg;
+ u32 r;
- reg = read_p15_c1 (); /* get control reg. */
- cp_delay ();
- write_p15_c1 (reg | C1_IC);
+ r = get_cr();
+ r |= CR_I;
+ set_cr(r);
}
/**
* Disable processor's instruction cache
*/
-void icache_disable (void)
+void icache_disable(void)
{
- ulong reg;
+ u32 r;
- reg = read_p15_c1 ();
- cp_delay ();
- write_p15_c1 (reg & ~C1_IC);
+ r = get_cr();
+ r &= ~CR_I;
+ set_cr(r);
}
/**
* Detect processor's current instruction cache status
* @return 0=disabled, 1=enabled
*/
-int icache_status (void)
+int icache_status(void)
{
- return (read_p15_c1 () & C1_IC) != 0;
+ return (get_cr () & CR_I) != 0;
}
/**
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 09/17] pcm043: Speed up NAND controller before copying barebox image
2010-04-29 7:51 patches for next v2 Sascha Hauer
` (7 preceding siblings ...)
2010-04-29 7:52 ` [PATCH 08/17] ARM: update icache functions to use get_cr/set_cr Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
2010-05-03 11:29 ` Peter Korsgaard
2010-04-29 7:52 ` [PATCH 10/17] add arm helper function to determine the program counter Sascha Hauer
` (7 subsequent siblings)
16 siblings, 1 reply; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
board/pcm043/pcm043.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/board/pcm043/pcm043.c b/board/pcm043/pcm043.c
index 2ce7e3a..d8cd7b8 100644
--- a/board/pcm043/pcm043.c
+++ b/board/pcm043/pcm043.c
@@ -393,6 +393,13 @@ BAREBOX_CMD_END
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
+ u32 val;
+
+ val = readl(IMX_CCM_BASE + CCM_PDR4);
+ val &= ~(0xf << 28);
+ val |= 0x1 << 28;
+ writel(val, IMX_CCM_BASE + CCM_PDR4);
+
/*
* The driver is able to detect NAND's pagesize by CPU internal
* fuses or external pull ups. But not the blocksize...
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 09/17] pcm043: Speed up NAND controller before copying barebox image
2010-04-29 7:52 ` [PATCH 09/17] pcm043: Speed up NAND controller before copying barebox image Sascha Hauer
@ 2010-05-03 11:29 ` Peter Korsgaard
2010-05-03 13:09 ` Sascha Hauer
0 siblings, 1 reply; 20+ messages in thread
From: Peter Korsgaard @ 2010-05-03 11:29 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
>>>>> "Sascha" == Sascha Hauer <s.hauer@pengutronix.de> writes:
Sascha> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha> ---
Sascha> board/pcm043/pcm043.c | 7 +++++++
Sascha> 1 files changed, 7 insertions(+), 0 deletions(-)
Sascha> diff --git a/board/pcm043/pcm043.c b/board/pcm043/pcm043.c
Sascha> index 2ce7e3a..d8cd7b8 100644
Sascha> --- a/board/pcm043/pcm043.c
Sascha> +++ b/board/pcm043/pcm043.c
Sascha> @@ -393,6 +393,13 @@ BAREBOX_CMD_END
Sascha> #ifdef CONFIG_NAND_IMX_BOOT
Sascha> void __bare_init nand_boot(void)
Sascha> {
Sascha> + u32 val;
Sascha> +
Sascha> + val = readl(IMX_CCM_BASE + CCM_PDR4);
Sascha> + val &= ~(0xf << 28);
Sascha> + val |= 0x1 << 28;
Sascha> + writel(val, IMX_CCM_BASE + CCM_PDR4);
A comment describing what this does might be nice.
--
Bye, Peter Korsgaard
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 09/17] pcm043: Speed up NAND controller before copying barebox image
2010-05-03 11:29 ` Peter Korsgaard
@ 2010-05-03 13:09 ` Sascha Hauer
0 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-05-03 13:09 UTC (permalink / raw)
To: Peter Korsgaard; +Cc: barebox
Hi Peter,
On Mon, May 03, 2010 at 01:29:40PM +0200, Peter Korsgaard wrote:
> >>>>> "Sascha" == Sascha Hauer <s.hauer@pengutronix.de> writes:
>
> Sascha> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> Sascha> ---
> Sascha> board/pcm043/pcm043.c | 7 +++++++
> Sascha> 1 files changed, 7 insertions(+), 0 deletions(-)
>
> Sascha> diff --git a/board/pcm043/pcm043.c b/board/pcm043/pcm043.c
> Sascha> index 2ce7e3a..d8cd7b8 100644
> Sascha> --- a/board/pcm043/pcm043.c
> Sascha> +++ b/board/pcm043/pcm043.c
> Sascha> @@ -393,6 +393,13 @@ BAREBOX_CMD_END
> Sascha> #ifdef CONFIG_NAND_IMX_BOOT
> Sascha> void __bare_init nand_boot(void)
> Sascha> {
> Sascha> + u32 val;
> Sascha> +
> Sascha> + val = readl(IMX_CCM_BASE + CCM_PDR4);
> Sascha> + val &= ~(0xf << 28);
> Sascha> + val |= 0x1 << 28;
> Sascha> + writel(val, IMX_CCM_BASE + CCM_PDR4);
>
> A comment describing what this does might be nice.
I dropped this patch since this is being touched in the reimplement-in-C
patch later anyway. The other patch also adds a comment.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 10/17] add arm helper function to determine the program counter
2010-04-29 7:51 patches for next v2 Sascha Hauer
` (8 preceding siblings ...)
2010-04-29 7:52 ` [PATCH 09/17] pcm043: Speed up NAND controller before copying barebox image Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
2010-04-29 7:52 ` [PATCH 11/17] arm: remove unused variables from header file Sascha Hauer
` (6 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/include/asm/common.h | 18 ++++++++++++++++++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/common.h b/arch/arm/include/asm/common.h
index 9afcff7..f3a87c8 100644
--- a/arch/arm/include/asm/common.h
+++ b/arch/arm/include/asm/common.h
@@ -1 +1,19 @@
+#ifndef __ASM_ARM_COMMON_H
+#define __ASM_ARM_COMMON_H
+
#define ARCH_SHUTDOWN
+
+static inline unsigned long get_pc(void)
+{
+ unsigned long pc;
+
+ __asm__ __volatile__(
+ "mov %0, pc\n"
+ : "=r" (pc)
+ :
+ : "memory");
+
+ return pc;
+}
+
+#endif /* __ASM_ARM_COMMON_H */
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 11/17] arm: remove unused variables from header file
2010-04-29 7:51 patches for next v2 Sascha Hauer
` (9 preceding siblings ...)
2010-04-29 7:52 ` [PATCH 10/17] add arm helper function to determine the program counter Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
2010-04-29 7:52 ` [PATCH 12/17] arm: move __mmu_cache_flush to bare_init section Sascha Hauer
` (5 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/include/asm/barebox-arm.h | 7 +------
1 files changed, 1 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
index 6a00d10..ff3a60d 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -27,12 +27,7 @@
*/
#ifndef _BAREBOX_ARM_H_
-#define _BAREBOX_ARM_H_ 1
-
-/* for the following variables, see start.S */
-extern ulong _armboot_start; /* code start */
-extern ulong _bss_start; /* code + data end == BSS start */
-extern ulong _bss_end; /* BSS end */
+#define _BAREBOX_ARM_H_
/* cpu/.../cpu.c */
int cleanup_before_linux(void);
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 12/17] arm: move __mmu_cache_flush to bare_init section
2010-04-29 7:51 patches for next v2 Sascha Hauer
` (10 preceding siblings ...)
2010-04-29 7:52 ` [PATCH 11/17] arm: remove unused variables from header file Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
2010-04-29 7:52 ` [PATCH 13/17] arm: reimplement startup code in C Sascha Hauer
` (4 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
Instead of having seperate cache flush functions in the startup code
we want to call the generic functions. To accomplish this they have
to be in the bare_init section.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/cache-armv4.S | 2 ++
arch/arm/cpu/cache-armv5.S | 2 ++
arch/arm/cpu/cache-armv6.S | 3 +++
arch/arm/cpu/cache-armv7.S | 2 ++
4 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S
index a79cc27..3cec4dd 100644
--- a/arch/arm/cpu/cache-armv4.S
+++ b/arch/arm/cpu/cache-armv4.S
@@ -41,6 +41,7 @@ ENTRY(__mmu_cache_off)
mov pc, lr
ENDPROC(__mmu_cache_off)
+.section ".text_bare_init.text"
ENTRY(__mmu_cache_flush)
mrc p15, 0, r6, c0, c0 @ get processor ID
mov r2, #64*1024 @ default: 32K dcache size (*2)
@@ -73,6 +74,7 @@ no_cache_id:
mov pc, lr
ENDPROC(__mmu_cache_flush)
+.section ".text.text"
/*
* dma_inv_range(start, end)
*
diff --git a/arch/arm/cpu/cache-armv5.S b/arch/arm/cpu/cache-armv5.S
index f52bcb7..9fb320f 100644
--- a/arch/arm/cpu/cache-armv5.S
+++ b/arch/arm/cpu/cache-armv5.S
@@ -41,6 +41,7 @@ ENTRY(__mmu_cache_off)
mov pc, lr
ENDPROC(__mmu_cache_off)
+.section ".text_bare_init.text"
ENTRY(__mmu_cache_flush)
1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
bne 1b
@@ -48,6 +49,7 @@ ENTRY(__mmu_cache_flush)
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mov pc, lr
ENDPROC(__mmu_cache_flush)
+.section ".text.text"
/*
* dma_inv_range(start, end)
diff --git a/arch/arm/cpu/cache-armv6.S b/arch/arm/cpu/cache-armv6.S
index e3498bb..25476d5 100644
--- a/arch/arm/cpu/cache-armv6.S
+++ b/arch/arm/cpu/cache-armv6.S
@@ -31,6 +31,7 @@ __common_mmu_cache_on:
mrc p15, 0, r0, c1, c0, 0 @ and read it back to
sub pc, lr, r0, lsr #32 @ properly flush pipeline
+
ENTRY(__mmu_cache_off)
#ifdef CONFIG_MMU
mrc p15, 0, r0, c1, c0
@@ -42,6 +43,7 @@ ENTRY(__mmu_cache_off)
#endif
mov pc, lr
+.section ".text_bare_init.text"
ENTRY(__mmu_cache_flush)
mov r1, #0
mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
@@ -50,6 +52,7 @@ ENTRY(__mmu_cache_flush)
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
ENDPROC(__mmu_cache_flush)
+.section ".text.text"
/*
* v6_dma_inv_range(start,end)
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index 9afa20d..a303dc1 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -49,6 +49,7 @@ ENTRY(__mmu_cache_off)
mov pc, r12
ENDPROC(__mmu_cache_on)
+.section ".text_bare_init.text"
ENTRY(__mmu_cache_flush)
mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
@@ -105,6 +106,7 @@ iflush:
mcr p15, 0, r10, c7, c5, 4 @ ISB
mov pc, lr
ENDPROC(__mmu_cache_flush)
+.section ".text.text"
/*
* cache_line_size - get the cache line size from the CSIDR register
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 13/17] arm: reimplement startup code in C
2010-04-29 7:51 patches for next v2 Sascha Hauer
` (11 preceding siblings ...)
2010-04-29 7:52 ` [PATCH 12/17] arm: move __mmu_cache_flush to bare_init section Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
2010-04-29 7:52 ` [PATCH 14/17] i.MX: remove __REG from esd controller regs. use readl/writel instead Sascha Hauer
` (3 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
[-- Attachment #1: Type: text/plain, Size: 12715 bytes --]
Lets translate the startup code to a language we all understand better.
Tested on pcm038 (arm v5) and pcm043 (arm v6).
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/Makefile | 6 +-
arch/arm/cpu/start-arm.S | 248 ------------------------------------
arch/arm/cpu/start.c | 108 ++++++++++++++++
arch/arm/include/asm/barebox-arm.h | 3 +
arch/arm/lib/barebox.lds.S | 2 +-
5 files changed, 113 insertions(+), 254 deletions(-)
delete mode 100644 arch/arm/cpu/start-arm.S
create mode 100644 arch/arm/cpu/start.c
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index ae1f762..036768e 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -1,15 +1,11 @@
obj-y += cpu.o
obj-y += exceptions.o
obj-y += interrupts.o
+obj-y += start.o
#
# Any variants can be called as start-armxyz.S
#
-obj-$(CONFIG_CPU_ARM920T) += start-arm.o
-obj-$(CONFIG_CPU_ARM926T) += start-arm.o
-obj-$(CONFIG_CPU_V7) += start-arm.o
-obj-$(CONFIG_ARCH_IMX31) += start-arm.o
-obj-$(CONFIG_ARCH_IMX35) += start-arm.o
obj-$(CONFIG_CMD_ARM_CPUINFO) += cpuinfo.o
obj-$(CONFIG_MMU) += mmu.o
obj-$(CONFIG_CPU_32v4T) += cache-armv4.o
diff --git a/arch/arm/cpu/start-arm.S b/arch/arm/cpu/start-arm.S
deleted file mode 100644
index 4d61cee..0000000
--- a/arch/arm/cpu/start-arm.S
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * armboot - Startup Code for ARM CPU-cores
- *
- * Copyright (c) 2001 Marius Gr���ger <mag@sysgo.de>
- * Copyright (c) 2002 Alex Z���pke <azu@sysgo.de>
- * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/**
- * @file
- * @brief The very basic beginning of each CPU after reset
- *
- * @note
- * This reset code can be used at least for:
- * - ARM920T
- * - i.MX1
- * - i.MX27
- * - i.MX31
- *
- */
- .section ".text_entry","ax"
-
-#include <config.h>
-#include <asm-generic/memory_layout.h>
-
-/*************************************************************************
- * Jump vector table as in table 3.1 in [1]
- *************************************************************************/
-
-.globl _start
-_start:
- b reset
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_undefined_instruction: .word undefined_instruction
-_software_interrupt: .word software_interrupt
-_prefetch_abort: .word prefetch_abort
-_data_abort: .word data_abort
-_not_used: .word not_used
-_irq: .word irq
-_fiq: .word fiq
-
- .balignl 16,0xdeadbeef
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************
- */
-
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _barebox_start
-_barebox_start:
- .word _start
-
-.globl _bss_start
-_bss_start:
- .word __bss_start
-
-.globl _bss_end
-_bss_end:
- .word _end
-
-
-_TEXT_BASE:
- .word _stext
-
-_MALLOC_BASE:
- .word MALLOC_BASE
-
-_STACK_START:
- .word STACK_BASE + STACK_SIZE - 4
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory */
-IRQ_STACK_START:
- .word STACK_BASE + CONFIG_STACKSIZE_IRQ - 4
-
-/* IRQ stack memory */
-FIQ_STACK_START:
- .word STACK_BASE + CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ - 4
-#endif
-
-/*************************************************************************
- * the actual reset code
- *************************************************************************/
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0xd3
- msr cpsr,r0
-
-#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT
- bl arch_init_lowlevel
-#endif
-
-#ifdef CONFIG_CPU_V7
- /*
- * Invalidate v7 I/D caches
- */
- mov r0, #0 /* set up for MCR */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
- mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
- /* Invalidate all Dcaches */
-#ifndef CONFIG_CPU_V7_DCACHE_SKIP
- /* If Arch specific ROM code SMI handling does not exist */
- mrc p15, 1, r0, c0, c0, 1 /* read clidr */
- ands r3, r0, #0x7000000 /* extract loc from clidr */
- mov r3, r3, lsr #23 /* left align loc bit field */
- beq finished_inval /* if loc is 0, then no need to clean */
- mov r10, #0 /* start clean at cache level 0 */
-inval_loop1:
- add r2, r10, r10, lsr #1 /* work out 3x current cache level */
- mov r1, r0, lsr r2 /* extract cache type bits from clidr */
- and r1, r1, # 7 /* mask of the bits for current cache only */
- cmp r1, #2 /* see what cache we have at this level */
- blt skip_inval /* skip if no cache, or just i-cache */
- mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
- isb /* isb to sych the new cssr&csidr */
- mrc p15, 1, r1, c0, c0, 0 /* read the new csidr */
- and r2, r1, #7 /* extract the length of the cache lines */
- add r2, r2, #4 /* add 4 (line length offset) */
- ldr r4, =0x3ff
- ands r4, r4, r1, lsr #3 /* find maximum number on the way size*/
- clz r5, r4 /* find bit position of way size increment */
- ldr r7, =0x7fff
- ands r7, r7, r1, lsr #13 /* extract max number of the index size */
-inval_loop2:
- mov r9, r4 /* create working copy of max way size */
-inval_loop3:
- orr r11, r10, r9, lsl r5 /* factor way and cache number into r11*/
- orr r11, r11, r7, lsl r2 /* factor index number into r11 */
- mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
- subs r9, r9, #1 /* decrement the way */
- bge inval_loop3
- subs r7, r7, #1 /* decrement the index */
- bge inval_loop2
-skip_inval:
- add r10, r10, #2 /* increment cache number */
- cmp r3, r10
- bgt inval_loop1
-finished_inval:
- mov r10, #0 /* swith back to cache level 0 */
- mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
- isb
-#endif /* CONFIG_CPU_V7_DCACHE_SKIP */
-
-#else
- /*
- * flush v4 I/D caches
- */
- mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
-#endif
-
- /*
- * disable MMU stuff and caches
- */
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
- bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
- orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
- orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
- mcr p15, 0, r0, c1, c0, 0
-
- /*
- * before relocating, we have to setup RAM timing
- * because memory timing is board-dependend, you will
- * find a lowlevel_init.S in your board directory.
- */
-#ifdef CONFIG_MACH_DO_LOWLEVEL_INIT
- bl board_init_lowlevel
-#endif
-
-relocate: /* relocate barebox to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-
- ldr r2, _barebox_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _STACK_START
- sub sp, r0, #12 /* leave 3 words for abort-stack */
-
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-clbss_l:
- str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- ble clbss_l
-
- ldr pc, _start_armboot
-
-_start_armboot:
- .word start_barebox
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
new file mode 100644
index 0000000..67d54a6
--- /dev/null
+++ b/arch/arm/cpu/start.c
@@ -0,0 +1,108 @@
+/*
+ * start-arm.c
+ *
+ * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/barebox-arm.h>
+#include <asm/system.h>
+#include <asm-generic/memory_layout.h>
+
+void __naked __section(.text_entry) exception_vectors(void)
+{
+ __asm__ __volatile__ (
+ "b reset\n" /* reset */
+ "ldr pc, =undefined_instruction\n" /* undefined instruction */
+ "ldr pc, =software_interrupt\n" /* software interrupt (SWI) */
+ "ldr pc, =prefetch_abort\n" /* prefetch abort */
+ "ldr pc, =data_abort\n" /* data abort */
+ "ldr pc, =not_used\n" /* (reserved) */
+ "ldr pc, =irq\n" /* irq (interrupt) */
+ "ldr pc, =fiq\n" /* fiq (fast interrupt) */
+ );
+}
+
+extern char __bss_start, _end;
+
+/*
+ * The actual reset vector. This code is position independent and usually
+ * does not run at the address it's linked at.
+ */
+void __naked __bare_init reset(void)
+{
+ uint32_t r;
+
+ /* set the cpu to SVC32 mode */
+ __asm__ __volatile__("mrs %0, cpsr":"=r"(r));
+ r &= ~0x1f;
+ r |= 0xd3;
+ __asm__ __volatile__("msr cpsr, %0" : : "r"(r));
+
+ __asm__ __volatile__ (
+ "bl __mmu_cache_flush;"
+ :
+ :
+ : "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory"
+ );
+
+ /* disable MMU stuff and caches */
+ r = get_cr();
+ r &= ~(CR_M | CR_C | CR_B | CR_S | CR_R | CR_V);
+ r |= CR_A | CR_I;
+ set_cr(r);
+
+#ifdef CONFIG_MACH_DO_LOWLEVEL_INIT
+ board_init_lowlevel();
+#endif
+ board_init_lowlevel_return();
+}
+
+/*
+ * Board code can jump here by either returning from board_init_lowlevel
+ * or by calling this funtion directly.
+ */
+void __naked __bare_init board_init_lowlevel_return(void)
+{
+ uint32_t r;
+
+ /* Setup the stack */
+ r = STACK_BASE + STACK_SIZE - 16;
+ __asm__ __volatile__("mov sp, %0" : : "r"(r));
+
+ /* Get runtime address of this function */
+ __asm__ __volatile__("adr %0, 0":"=r"(r));
+
+ /* Get start of binary image */
+ r -= (uint32_t)&board_init_lowlevel_return - TEXT_BASE;
+
+ /* relocate to link address if necessary */
+ if (r != TEXT_BASE)
+ memcpy((void *)TEXT_BASE, (void *)r,
+ (unsigned int)&__bss_start - TEXT_BASE);
+
+ /* clear bss */
+ memset(&__bss_start, 0, &_end - &__bss_start);
+
+ /* call start_barebox with its absolute address */
+ r = (unsigned int)&start_barebox;
+ __asm__ __volatile__("mov pc, %0" : : "r"(r));
+}
+
diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
index ff3a60d..54561c3 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -36,4 +36,7 @@ int cleanup_before_linux(void);
int board_init(void);
int dram_init (void);
+void board_init_lowlevel(void);
+void board_init_lowlevel_return(void);
+
#endif /* _BAREBOX_ARM_H_ */
diff --git a/arch/arm/lib/barebox.lds.S b/arch/arm/lib/barebox.lds.S
index a5eaefa..5bee0a1 100644
--- a/arch/arm/lib/barebox.lds.S
+++ b/arch/arm/lib/barebox.lds.S
@@ -26,7 +26,7 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
-ENTRY(_start)
+ENTRY(exception_vectors)
SECTIONS
{
. = TEXT_BASE;
--
1.7.0
[-- Attachment #2: Type: text/plain, Size: 149 bytes --]
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 14/17] i.MX: remove __REG from esd controller regs. use readl/writel instead
2010-04-29 7:51 patches for next v2 Sascha Hauer
` (12 preceding siblings ...)
2010-04-29 7:52 ` [PATCH 13/17] arm: reimplement startup code in C Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
2010-04-29 7:52 ` [PATCH 15/17] pcm043: reimplement lowlevel code in C Sascha Hauer
` (2 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
So far these registers are unused in C, so we can remove the __REG without
harm.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/include/mach/esdctl.h | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h
index 7f3c66f..d15f52b 100644
--- a/arch/arm/mach-imx/include/mach/esdctl.h
+++ b/arch/arm/mach-imx/include/mach/esdctl.h
@@ -1,10 +1,10 @@
/* SDRAM Controller registers */
-#define ESDCTL0 __REG(IMX_ESD_BASE + 0x00) /* Enhanced SDRAM Control Register 0 */
-#define ESDCFG0 __REG(IMX_ESD_BASE + 0x04) /* Enhanced SDRAM Configuration Register 0 */
-#define ESDCTL1 __REG(IMX_ESD_BASE + 0x08) /* Enhanced SDRAM Control Register 1 */
-#define ESDCFG1 __REG(IMX_ESD_BASE + 0x0C) /* Enhanced SDRAM Configuration Register 1 */
-#define ESDMISC __REG(IMX_ESD_BASE + 0x10) /* Enhanced SDRAM Miscellanious Register */
+#define ESDCTL0 (IMX_ESD_BASE + 0x00) /* Enhanced SDRAM Control Register 0 */
+#define ESDCFG0 (IMX_ESD_BASE + 0x04) /* Enhanced SDRAM Configuration Register 0 */
+#define ESDCTL1 (IMX_ESD_BASE + 0x08) /* Enhanced SDRAM Control Register 1 */
+#define ESDCFG1 (IMX_ESD_BASE + 0x0C) /* Enhanced SDRAM Configuration Register 1 */
+#define ESDMISC (IMX_ESD_BASE + 0x10) /* Enhanced SDRAM Miscellanious Register */
#define ESDCTL0_SDE (1 << 31)
#define ESDCTL0_SMODE_NORMAL (0 << 28)
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 15/17] pcm043: reimplement lowlevel code in C
2010-04-29 7:51 patches for next v2 Sascha Hauer
` (13 preceding siblings ...)
2010-04-29 7:52 ` [PATCH 14/17] i.MX: remove __REG from esd controller regs. use readl/writel instead Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
2010-04-29 7:52 ` [PATCH 16/17] i.MX35: Fix ahbclock calculation Sascha Hauer
2010-04-29 7:52 ` [PATCH 17/17] pcm038: reimplement lowlevel code in C Sascha Hauer
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
board/pcm043/Makefile | 2 +-
board/pcm043/lowlevel.c | 214 ++++++++++++++++++++++++++++++++++++++
board/pcm043/lowlevel_init.S | 231 ------------------------------------------
board/pcm043/pcm043.c | 17 ---
4 files changed, 215 insertions(+), 249 deletions(-)
create mode 100644 board/pcm043/lowlevel.c
delete mode 100644 board/pcm043/lowlevel_init.S
diff --git a/board/pcm043/Makefile b/board/pcm043/Makefile
index 62c0ba5..6753bbe 100644
--- a/board/pcm043/Makefile
+++ b/board/pcm043/Makefile
@@ -20,5 +20,5 @@
# MA 02111-1307 USA
#
-obj-y += lowlevel_init.o
+obj-y += lowlevel.o
obj-y += pcm043.o
diff --git a/board/pcm043/lowlevel.c b/board/pcm043/lowlevel.c
new file mode 100644
index 0000000..fbbe836
--- /dev/null
+++ b/board/pcm043/lowlevel.c
@@ -0,0 +1,214 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <init.h>
+#include <mach/imx-regs.h>
+#include <mach/imx-pll.h>
+#include <mach/esdctl.h>
+#include <asm/cache-l2x0.h>
+#include <asm/io.h>
+#include <mach/imx-nand.h>
+#include <asm/barebox-arm.h>
+#include <asm-generic/memory_layout.h>
+#include <asm/system.h>
+
+/* Assuming 24MHz input clock */
+#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
+#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
+#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
+
+static void __bare_init __naked insdram(void)
+{
+ uint32_t r;
+
+ /* Speed up NAND controller */
+ r = readl(IMX_CCM_BASE + CCM_PDR4);
+ r &= ~(0xf << 28);
+ r |= 0x1 << 28;
+ writel(r, IMX_CCM_BASE + CCM_PDR4);
+
+ /* setup a stack to be able to call imx_nand_load_image() */
+ r = STACK_BASE + STACK_SIZE - 12;
+ __asm__ __volatile__("mov sp, %0" : : "r"(r));
+
+ imx_nand_load_image((void *)TEXT_BASE, 256 * 1024);
+
+ board_init_lowlevel_return();
+}
+
+void __bare_init __naked board_init_lowlevel(void)
+{
+ uint32_t r, s;
+ unsigned long ccm_base = IMX_CCM_BASE;
+ unsigned long iomuxc_base = IMX_IOMUXC_BASE;
+ unsigned int *trg, *src;
+ int i;
+
+ r = get_cr();
+ r |= CR_Z; /* Flow prediction (Z) */
+ r |= CR_U; /* unaligned accesses */
+ r |= CR_FI; /* Low Int Latency */
+
+ __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(s));
+ s |= 0x7;
+ __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s));
+
+ set_cr(r);
+
+ r = 0;
+ __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
+
+ /*
+ * Branch predicition is now enabled. Flush the BTAC to ensure a valid
+ * starting point. Don't flush BTAC while it is disabled to avoid
+ * ARM1136 erratum 408023.
+ */
+ __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r));
+
+ /* invalidate I cache and D cache */
+ __asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r));
+
+ /* invalidate TLBs */
+ __asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r));
+
+ /* Drain the write buffer */
+ __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r));
+
+ /* Also setup the Peripheral Port Remap register inside the core */
+ r = 0x40000015; /* start from AIPS 2GB region */
+ __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
+
+ /*
+ * End of ARM1136 init
+ */
+
+ writel(0x003F4208, ccm_base + CCM_CCMR);
+
+ /* Set MPLL , arm clock and ahb clock*/
+ writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL);
+
+ writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL);
+ writel(0x00001000, ccm_base + CCM_PDR0);
+
+ r = readl(ccm_base + CCM_CGR0);
+ r |= 0x00300000;
+ writel(r, ccm_base + CCM_CGR0);
+
+ r = readl(ccm_base + CCM_CGR1);
+ r |= 0x00000C00;
+ r |= 0x00000003;
+ writel(r, ccm_base + CCM_CGR1);
+
+ r = readl(IMX_L2CC_BASE + L2X0_AUX_CTRL);
+ r |= 0x1000;
+ writel(r, IMX_L2CC_BASE + L2X0_AUX_CTRL);
+
+ /* Skip SDRAM initialization if we run from RAM */
+ r = get_pc();
+ if (r > 0x80000000 && r < 0x90000000)
+ board_init_lowlevel_return();
+
+ /* Set DDR Type to SDRAM, drive strength workaround *
+ * 0x00000000 MDDR *
+ * 0x00000800 3,3V SDRAM */
+
+ r = 0x00000800;
+ writel(r, iomuxc_base + 0x794);
+ writel(r, iomuxc_base + 0x798);
+ writel(r, iomuxc_base + 0x79c);
+ writel(r, iomuxc_base + 0x7a0);
+ writel(r, iomuxc_base + 0x7a4);
+
+ /* MDDR init, enable mDDR*/
+ writel(0x00000304, ESDMISC); /* was 0x00000004 */
+
+ /* set timing paramters */
+ writel(0x00255417, ESDCFG0);
+ /* select Precharge-All mode */
+ writel(0x92220000, ESDCTL0);
+ /* Precharge-All */
+ writel(0x12345678, IMX_SDRAM_CS0 + 0x400);
+
+ /* select Load-Mode-Register mode */
+ writel(0xB8001000, ESDCTL0);
+ /* Load reg EMR2 */
+ writeb(0xda, 0x84000000);
+ /* Load reg EMR3 */
+ writeb(0xda, 0x86000000);
+ /* Load reg EMR1 -- enable DLL */
+ writeb(0xda, 0x82000400);
+ /* Load reg MR -- reset DLL */
+ writeb(0xda, 0x80000333);
+
+ /* select Precharge-All mode */
+ writel(0x92220000, ESDCTL0);
+ /* Precharge-All */
+ writel(0x12345678, IMX_SDRAM_CS0 + 0x400);
+
+ /* select Manual-Refresh mode */
+ writel(0xA2220000, ESDCTL0);
+ /* Manual-Refresh 2 times */
+ writel(0x87654321, IMX_SDRAM_CS0);
+ writel(0x87654321, IMX_SDRAM_CS0);
+
+ /* select Load-Mode-Register mode */
+ writel(0xB2220000, ESDCTL0);
+ /* Load reg MR -- CL3, BL8, end DLL reset */
+ writeb(0xda, 0x80000233);
+ /* Load reg EMR1 -- OCD default */
+ writeb(0xda, 0x82000780);
+ /* Load reg EMR1 -- OCD exit */
+ writeb(0xda, 0x82000400);
+
+ /* select normal-operation mode
+ * DSIZ32-bit, BL8, COL10-bit, ROW13-bit
+ * disable PWT & PRCT
+ * disable Auto-Refresh */
+ writel(0x82220080, ESDCTL0);
+
+ /* enable Auto-Refresh */
+ writel(0x82228080, ESDCTL0);
+ /* enable Auto-Refresh */
+ writel(0x00002000, ESDCTL1);
+
+#ifdef CONFIG_NAND_IMX_BOOT
+ /* skip NAND boot if not running from NFC space */
+ r = get_pc();
+ if (r < IMX_NFC_BASE && r > IMX_NFC_BASE + 0x800)
+ board_init_lowlevel_return();
+
+ src = (unsigned int *)IMX_NFC_BASE;
+ trg = (unsigned int *)TEXT_BASE;
+
+ /* Move ourselves out of NFC SRAM */
+ for (i = 0; i < 0x800 / sizeof(int); i++)
+ *trg++ = *src++;
+
+ /* Jump to SDRAM */
+ r = (unsigned int)&insdram;
+ __asm__ __volatile__("mov pc, %0" : : "r"(r));
+#else
+ board_init_lowlevel_return();
+#endif
+}
+
diff --git a/board/pcm043/lowlevel_init.S b/board/pcm043/lowlevel_init.S
deleted file mode 100644
index abbc72c..0000000
--- a/board/pcm043/lowlevel_init.S
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <mach/imx-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/esdctl.h>
-#include <asm/cache-l2x0.h>
-
-#define writel(val, reg) \
- ldr r0, =reg; \
- ldr r1, =val; \
- str r1, [r0];
-
-#define writeb(val, reg) \
- ldr r0, =reg; \
- ldr r1, =val; \
- strb r1, [r0];
-
-/* Assuming 24MHz input clock */
-#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
-#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
-#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
-
- .section ".text_bare_init","ax"
-
-ARM_PPMRR: .word 0x40000015
-L2CACHE_PARAM: .word 0x00030024
-CCM_CCMR_W: .word 0x003F4208
-CCM_PDR0_W: .word 0x00001000
-MPCTL_PARAM_399_W: .word MPCTL_PARAM_399
-MPCTL_PARAM_532_W: .word MPCTL_PARAM_532
-PPCTL_PARAM_W: .word PPCTL_PARAM_300
-CCM_BASE_ADDR_W: .word IMX_CCM_BASE
-
-.globl board_init_lowlevel
-board_init_lowlevel:
- mov r10, lr
-
- mrc 15, 0, r1, c1, c0, 0
-
- mrc 15, 0, r0, c1, c0, 1
- orr r0, r0, #7
- mcr 15, 0, r0, c1, c0, 1
-
- orr r1, r1, #(1<<11) /* Flow prediction (Z) */
- orr r1, r1, #(1<<22) /* unaligned accesses */
- orr r1, r1, #(1<<21) /* Low Int Latency */
-
- mcr 15, 0, r1, c1, c0, 0
-
- mov r0, #0
- mcr 15, 0, r0, c15, c2, 4
-
- /*
- * Branch predicition is now enabled. Flush the BTAC to ensure a valid
- * starting point. Don't flush BTAC while it is disabled to avoid
- * ARM1136 erratum 408023.
- */
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 6 /* flush entire BTAC */
-
- mov r0, #0
- mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
- mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
- mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
-
- /* Also setup the Peripheral Port Remap register inside the core */
- ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
- mcr p15, 0, r0, c15, c2, 4
-
-/*
- * End of ARM1136 init
- */
- ldr r0, CCM_BASE_ADDR_W
-
- ldr r2, CCM_CCMR_W
- str r2, [r0, #CCM_CCMR]
-
- ldr r3, MPCTL_PARAM_532_W /* consumer path*/
-
- /*Set MPLL , arm clock and ahb clock*/
- str r3, [r0, #CCM_MPCTL]
-
- ldr r1, PPCTL_PARAM_W
- str r1, [r0, #CCM_PPCTL]
-
- ldr r1, CCM_PDR0_W
- str r1, [r0, #CCM_PDR0]
-
- ldr r1, [r0, #CCM_CGR0]
- orr r1, r1, #0x00300000
- str r1, [r0, #CCM_CGR0]
-
- ldr r1, [r0, #CCM_CGR1]
- orr r1, r1, #0x00000C00
- orr r1, r1, #0x00000003
- str r1, [r0, #CCM_CGR1]
-
- /* Skip SDRAM initialization if we run from RAM */
- cmp pc, #0x80000000
- bls 1f
- cmp pc, #0x90000000
- bhi 1f
-
- mov pc, r10
-
-1:
- /* Set DDR Type to SDRAM, drive strength workaround *
- * 0x00000000 MDDR *
- * 0x00000800 3,3V SDRAM */
-
- #define DDRTYPE 0x00000800
-
- ldr r0, =IMX_IOMUXC_BASE + 0x794
- ldr r1, =DDRTYPE
- str r1, [r0], #4 /* IMX_IOMUXC_BASE + 0x794 */
- str r1, [r0], #4 /* IMX_IOMUXC_BASE + 0x798 */
- str r1, [r0], #4 /* IMX_IOMUXC_BASE + 0x79c */
- str r1, [r0], #4 /* IMX_IOMUXC_BASE + 0x7a0 */
- str r1, [r0] /* IMX_IOMUXC_BASE + 0x7a4 */
-
- /* MDDR init, enable mDDR*/
- writel(0x00000304, ESDMISC) /* was 0x00000004 */
-
- /* set timing paramters */
- writel(0x00255417, ESDCFG0)
- /* select Prechare-All mode */
- writel(0x92220000, ESDCTL0)
- /* Prechare-All */
- writel(0x12345678, IMX_SDRAM_CS0 + 0x400)
-
- /* select Load-Mode-Register mode */
- writel(0xB8001000, ESDCTL0)
- /* Load reg EMR2 */
- writeb(0xda, 0x84000000)
- /* Load reg EMR3 */
- writeb(0xda, 0x86000000)
- /* Load reg EMR1 -- enable DLL */
- writeb(0xda, 0x82000400)
- /* Load reg MR -- reset DLL */
- writeb(0xda, 0x80000333)
-
- /* select Prechare-All mode */
- writel(0x92220000, ESDCTL0)
- /* Prechare-All */
- writel(0x12345678, IMX_SDRAM_CS0 + 0x400)
-
- /* select Manual-Refresh mode */
- writel(0xA2220000, ESDCTL0)
- /* Manual-Refresh 2 times */
- writel(0x87654321, IMX_SDRAM_CS0)
- writel(0x87654321, IMX_SDRAM_CS0)
-
- /* select Load-Mode-Register mode */
- writel(0xB2220000, ESDCTL0)
- /* Load reg MR -- CL3, BL8, end DLL reset */
- writeb(0xda, 0x80000233)
- /* Load reg EMR1 -- OCD default */
- writeb(0xda, 0x82000780)
- /* Load reg EMR1 -- OCD exit */
- writeb(0xda, 0x82000400)
-
- /* select normal-operation mode
- * DSIZ32-bit, BL8, COL10-bit, ROW13-bit
- * disable PWT & PRCT
- * disable Auto-Refresh */
- writel(0x82220080, ESDCTL0)
-
- /* enable Auto-Refresh */
- writel(0x82228080, ESDCTL0)
- /* enable Auto-Refresh */
- writel(0x00002000, ESDCTL1)
-
- mov r0, #IMX_L2CC_BASE
- ldr r1, [r0, #L2X0_AUX_CTRL]
- orr r1, r1, #0x1000
- str r1, [r0, #L2X0_AUX_CTRL]
-
-#ifdef CONFIG_NAND_IMX_BOOT
- ldr sp, =TEXT_BASE - 4 /* Setup a temporary stack in SDRAM */
-
- ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
- ldr r2, =IMX_NFC_BASE + 0x800 /* end of NFC SRAM */
-
- /* skip NAND boot if not running from NFC space */
- cmp pc, r0
- blo ret
- cmp pc, r2
- bhs ret
-
- /* Move ourselves out of NFC SRAM */
- ldr r1, =TEXT_BASE
-
-copy_loop:
- ldmia r0!, {r3-r9} /* copy from source address [r0] */
- stmia r1!, {r3-r9} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-
- ldr pc, =1f /* Jump to SDRAM */
-1:
- bl nand_boot /* Load barebox from NAND Flash */
-
- /* rebase the return address */
- ldr r1, =IMX_NFC_BASE - TEXT_BASE
- sub r10, r10, r1 /* adjust return address from NFC SRAM */
-ret:
-#endif /* CONFIG_NAND_IMX_BOOT */
-
- mov pc, r10
-
diff --git a/board/pcm043/pcm043.c b/board/pcm043/pcm043.c
index d8cd7b8..dd178ed 100644
--- a/board/pcm043/pcm043.c
+++ b/board/pcm043/pcm043.c
@@ -390,20 +390,3 @@ BAREBOX_CMD_START(cpufreq)
BAREBOX_CMD_HELP(cmd_cpufreq_help)
BAREBOX_CMD_END
-#ifdef CONFIG_NAND_IMX_BOOT
-void __bare_init nand_boot(void)
-{
- u32 val;
-
- val = readl(IMX_CCM_BASE + CCM_PDR4);
- val &= ~(0xf << 28);
- val |= 0x1 << 28;
- writel(val, IMX_CCM_BASE + CCM_PDR4);
-
- /*
- * The driver is able to detect NAND's pagesize by CPU internal
- * fuses or external pull ups. But not the blocksize...
- */
- imx_nand_load_image((void *)TEXT_BASE, 256 * 1024);
-}
-#endif
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 16/17] i.MX35: Fix ahbclock calculation
2010-04-29 7:51 patches for next v2 Sascha Hauer
` (14 preceding siblings ...)
2010-04-29 7:52 ` [PATCH 15/17] pcm043: reimplement lowlevel code in C Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
2010-04-29 7:52 ` [PATCH 17/17] pcm038: reimplement lowlevel code in C Sascha Hauer
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/speed-imx35.c | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-imx/speed-imx35.c b/arch/arm/mach-imx/speed-imx35.c
index 1721079..c5a31c7 100644
--- a/arch/arm/mach-imx/speed-imx35.c
+++ b/arch/arm/mach-imx/speed-imx35.c
@@ -74,9 +74,11 @@ unsigned long imx_get_ahbclk(void)
{
unsigned long pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
struct arm_ahb_div *aad;
- unsigned long fref = imx_get_armclk();
+ unsigned long fref = imx_get_mpllclk();
aad = &clk_consumer[(pdr0 >> 16) & 0xf];
+ if (aad->sel)
+ fref = fref * 3 / 4;
return fref / aad->ahb;
}
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 17/17] pcm038: reimplement lowlevel code in C
2010-04-29 7:51 patches for next v2 Sascha Hauer
` (15 preceding siblings ...)
2010-04-29 7:52 ` [PATCH 16/17] i.MX35: Fix ahbclock calculation Sascha Hauer
@ 2010-04-29 7:52 ` Sascha Hauer
16 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2010-04-29 7:52 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
board/pcm038/Makefile | 2 +-
board/pcm038/lowlevel.c | 117 ++++++++++++++++++++++++++++++++++++++++++
board/pcm038/lowlevel_init.S | 116 -----------------------------------------
board/pcm038/pcm038.c | 9 ---
4 files changed, 118 insertions(+), 126 deletions(-)
create mode 100644 board/pcm038/lowlevel.c
delete mode 100644 board/pcm038/lowlevel_init.S
diff --git a/board/pcm038/Makefile b/board/pcm038/Makefile
index d978c77..a681dda 100644
--- a/board/pcm038/Makefile
+++ b/board/pcm038/Makefile
@@ -1,3 +1,3 @@
-obj-y += lowlevel_init.o pll_init.o
+obj-y += lowlevel.o pll_init.o
obj-y += pcm038.o
diff --git a/board/pcm038/lowlevel.c b/board/pcm038/lowlevel.c
new file mode 100644
index 0000000..0c376f2
--- /dev/null
+++ b/board/pcm038/lowlevel.c
@@ -0,0 +1,117 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <init.h>
+#include <mach/imx-regs.h>
+#include <mach/imx-pll.h>
+#include <mach/esdctl.h>
+#include <asm/cache-l2x0.h>
+#include <asm/io.h>
+#include <mach/imx-nand.h>
+#include <asm/barebox-arm.h>
+#include <asm/system.h>
+#include <asm-generic/memory_layout.h>
+
+static void __bare_init __naked insdram(void)
+{
+ uint32_t r;
+
+ PCCR1 |= PCCR1_NFC_BAUDEN;
+
+ /* setup a stack to be able to call imx_nand_load_image() */
+ r = STACK_BASE + STACK_SIZE - 12;
+ __asm__ __volatile__("mov sp, %0" : : "r"(r));
+
+ imx_nand_load_image((void *)TEXT_BASE, 256 * 1024);
+
+ board_init_lowlevel_return();
+}
+
+#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
+
+void __bare_init __naked board_init_lowlevel(void)
+{
+ uint32_t r;
+ int i;
+ unsigned int *trg, *src;
+
+ /* ahb lite ip interface */
+ AIPI1_PSR0 = 0x20040304;
+ AIPI1_PSR1 = 0xDFFBFCFB;
+ AIPI2_PSR0 = 0x00000000;
+ AIPI2_PSR1 = 0xFFFFFFFF;
+
+ /* Skip SDRAM initialization if we run from RAM */
+ r = get_pc();
+ if (r > 0xa0000000 && r < 0xb0000000)
+ board_init_lowlevel_return();
+
+ /*
+ * DDR on CSD0
+ */
+ writel(0x00000008, ESDMISC); /* Enable DDR SDRAM operation */
+
+ DSCR(3) = 0x55555555; /* Set the driving strength */
+ DSCR(5) = 0x55555555;
+ DSCR(6) = 0x55555555;
+ DSCR(7) = 0x00005005;
+ DSCR(8) = 0x15555555;
+
+ writel(0x00000004, ESDMISC); /* Initial reset */
+ writel(0x006ac73a, ESDCFG0);
+
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); /* precharge CSD0 all banks */
+ writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0);
+
+ for (i = 0; i < 8; i++)
+ writel(0, 0xa0000f00);
+
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0);
+
+ writeb(0xda, 0xa0000033);
+ writeb(0xff, 0xa1000000);
+ writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
+ ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0);
+
+#ifdef CONFIG_NAND_IMX_BOOT
+ /* skip NAND boot if not running from NFC space */
+ r = get_pc();
+ if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
+ board_init_lowlevel_return();
+
+ src = (unsigned int *)IMX_NFC_BASE;
+ trg = (unsigned int *)TEXT_BASE;
+
+ /* Move ourselves out of NFC SRAM */
+ for (i = 0; i < 0x800 / sizeof(int); i++)
+ *trg++ = *src++;
+
+ /* Jump to SDRAM */
+ r = (unsigned int)&insdram;
+ __asm__ __volatile__("mov pc, %0" : : "r"(r));
+#else
+ board_init_lowlevel_return();
+#endif
+}
+
diff --git a/board/pcm038/lowlevel_init.S b/board/pcm038/lowlevel_init.S
deleted file mode 100644
index 0001e4f..0000000
--- a/board/pcm038/lowlevel_init.S
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
- * Applications Processor Reference Manual, Rev. 0.2".
- *
- */
-
-#include <config.h>
-#include <mach/imx-regs.h>
-
-#define writel(val, reg) \
- ldr r0, =reg; \
- ldr r1, =val; \
- str r1, [r0];
-
-
-#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
-
-.macro sdram_init
- /*
- * DDR on CSD0
- */
- writel(0x00000008, ESDMISC) /* Enable DDR SDRAM operation */
-
- writel(0x55555555, DSCR(3)) /* Set the driving strength */
- writel(0x55555555, DSCR(5))
- writel(0x55555555, DSCR(6))
- writel(0x00005005, DSCR(7))
- writel(0x15555555, DSCR(8))
-
- writel(0x00000004, ESDMISC) /* Initial reset */
-
- /*
- * tXP=3, tWTR=0, tRP=2, tMRD=2, tWR=1,
- * tRAS=4, tRRD=1, tCAS=3, tRCD=3, tRC=10
- */
- writel(0x006ac73a, ESDCFG0)
-
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */
- writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0)
-
- ldr r0, =0xa0000f00
- mov r1, #0
- mov r2, #8
-1:
- str r1, [r0]
- subs r2, #1
- bne 1b
-
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0)
- ldr r0, =0xA0000033
- mov r1, #0xda
- strb r1, [r0]
- ldr r0, =0xA1000000
- mov r1, #0xff
- strb r1, [r0]
- writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0)
-.endm
-
- .section ".text_bare_init","ax"
-
-.globl board_init_lowlevel
-board_init_lowlevel:
-
- mov r10, lr
-
- /* ahb lite ip interface */
- writel(0x20040304, AIPI1_PSR0)
- writel(0xDFFBFCFB, AIPI1_PSR1)
- writel(0x00000000, AIPI2_PSR0)
- writel(0xFFFFFFFF, AIPI2_PSR1)
-
- /* skip sdram initialization if we run from ram */
- cmp pc, #0xa0000000
- bls 1f
- cmp pc, #0xc0000000
- bhi 1f
-
- mov pc,r10
-1:
- sdram_init
-
-#ifdef CONFIG_NAND_IMX_BOOT
- ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */
-
- ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
- ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */
-
- /* skip NAND boot if not running from NFC space */
- cmp pc, r0
- bls ret
- cmp pc, r2
- bhi ret
-
- /* Move ourselves out of NFC SRAM */
- ldr r1, =TEXT_BASE
-
-copy_loop:
- ldmia r0!, {r3-r9} /* copy from source address [r0] */
- stmia r1!, {r3-r9} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-
- ldr pc, =1f /* Jump to SDRAM */
-1:
- bl nand_boot /* Load barebox from NAND Flash */
-
- ldr r1, =IMX_NFC_BASE - TEXT_BASE
- sub r10, r10, r1 /* adjust return address from NFC SRAM */
- /* to SDRAM */
-
-#endif /* CONFIG_NAND_IMX_BOOT */
-
-ret:
- mov pc,r10
-
diff --git a/board/pcm038/pcm038.c b/board/pcm038/pcm038.c
index 3c17036..fbd53a5 100644
--- a/board/pcm038/pcm038.c
+++ b/board/pcm038/pcm038.c
@@ -420,12 +420,3 @@ static int pcm038_power_init(void)
late_initcall(pcm038_power_init);
-#ifdef CONFIG_NAND_IMX_BOOT
-void __bare_init nand_boot(void)
-{
- PCCR1 |= PCCR1_NFC_BAUDEN; /* FIXME: Really needed? Probably not */
-
- imx_nand_load_image((void *)TEXT_BASE, 256 * 1024);
-}
-#endif
-
--
1.7.0
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^ permalink raw reply [flat|nested] 20+ messages in thread