* [PATCH 01/13] i2c: Add missing defines for omap
2010-08-04 9:59 [PATCH 00/13] OMAP/Beagleboard ehci support Michael Grzeschik
@ 2010-08-04 9:59 ` Michael Grzeschik
2010-08-04 9:59 ` [PATCH 02/13] arm omap: Add I2C driver Michael Grzeschik
` (12 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Michael Grzeschik @ 2010-08-04 9:59 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/i2c/i2c.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/i2c/i2c.h b/include/i2c/i2c.h
index c031bbb..2507d68 100644
--- a/include/i2c/i2c.h
+++ b/include/i2c/i2c.h
@@ -30,6 +30,8 @@ struct i2c_platform_data {
#define I2C_NAME_SIZE 20
#define I2C_M_RD 0x0001 /* read data, from slave to master */
+#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */
+#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */
/**
* struct i2c_msg - an I2C transaction segment beginning with START
--
1.7.1
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^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 02/13] arm omap: Add I2C driver
2010-08-04 9:59 [PATCH 00/13] OMAP/Beagleboard ehci support Michael Grzeschik
2010-08-04 9:59 ` [PATCH 01/13] i2c: Add missing defines for omap Michael Grzeschik
@ 2010-08-04 9:59 ` Michael Grzeschik
2010-08-04 9:59 ` [PATCH 03/13] add twl4030 support Michael Grzeschik
` (11 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Michael Grzeschik @ 2010-08-04 9:59 UTC (permalink / raw)
To: barebox
[-- Attachment #1: Type: text/plain, Size: 25906 bytes --]
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
drivers/i2c/Kconfig | 4 +
drivers/i2c/Makefile | 1 +
drivers/i2c/i2c-omap.c | 803 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 808 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/i2c-omap.c
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index a9ee411..147ea49 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -7,6 +7,10 @@ config DRIVER_I2C_IMX
bool "i.MX I2C Master driver"
depends on ARCH_IMX
+config DRIVER_I2C_OMAP
+ bool "OMAP I2C Master driver"
+ depends on ARCH_OMAP
+
config DRIVER_I2C_MC13892
bool "MC13892 a.k.a. PMIC driver"
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 13e5804..9be8ab2 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -1,6 +1,7 @@
obj-$(CONFIG_I2C) += i2c.o
obj-$(CONFIG_DRIVER_I2C_IMX) += i2c-imx.o
+obj-$(CONFIG_DRIVER_I2C_OMAP) += i2c-omap.o
obj-$(CONFIG_DRIVER_I2C_MC13892) += mc13892.o
obj-$(CONFIG_DRIVER_I2C_MC34704) += mc34704.o
diff --git a/drivers/i2c/i2c-omap.c b/drivers/i2c/i2c-omap.c
new file mode 100644
index 0000000..8e7a8b5
--- /dev/null
+++ b/drivers/i2c/i2c-omap.c
@@ -0,0 +1,803 @@
+/*
+ * TI OMAP I2C master mode driver
+ *
+ * Copyright (C) 2003 MontaVista Software, Inc.
+ * Copyright (C) 2005 Nokia Corporation
+ * Copyright (C) 2004 - 2007 Texas Instruments.
+ *
+ * Originally written by MontaVista Software, Inc.
+ * Additional contributions by:
+ * Tony Lindgren <tony@atomide.com>
+ * Imre Deak <imre.deak@nokia.com>
+ * Juha Yrj��l�� <juha.yrjola@solidboot.com>
+ * Syed Khasim <x0khasim@ti.com>
+ * Nishant Menon <nm@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+
+/* #include <linux/delay.h> */
+
+
+#include <clock.h>
+#include <common.h>
+#include <driver.h>
+#include <gpio.h>
+#include <init.h>
+#include <malloc.h>
+#include <types.h>
+#include <xfuncs.h>
+
+#include <linux/err.h>
+
+#include <asm/io.h>
+#include <i2c/i2c.h>
+#include <mach/generic.h>
+#include <mach/omap3-clock.h>
+
+#define OMAP_I2C_SIZE 0x3f
+#define OMAP1_I2C_BASE 0xfffb3800
+#define OMAP2_I2C_BASE1 0x48070000
+#define OMAP2_I2C_BASE2 0x48072000
+#define OMAP2_I2C_BASE3 0x48060000
+
+/* This will be the driver name */
+#define DRIVER_NAME "i2c-omap"
+
+#define OMAP_I2C_REV_REG 0x00
+#define OMAP_I2C_IE_REG 0x04
+#define OMAP_I2C_STAT_REG 0x08
+#define OMAP_I2C_IV_REG 0x0c
+/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
+#define OMAP_I2C_WE_REG 0x0c
+#define OMAP_I2C_SYSS_REG 0x10
+#define OMAP_I2C_BUF_REG 0x14
+#define OMAP_I2C_CNT_REG 0x18
+#define OMAP_I2C_DATA_REG 0x1c
+#define OMAP_I2C_SYSC_REG 0x20
+#define OMAP_I2C_CON_REG 0x24
+#define OMAP_I2C_OA_REG 0x28
+#define OMAP_I2C_SA_REG 0x2c
+#define OMAP_I2C_PSC_REG 0x30
+#define OMAP_I2C_SCLL_REG 0x34
+#define OMAP_I2C_SCLH_REG 0x38
+#define OMAP_I2C_SYSTEST_REG 0x3c
+#define OMAP_I2C_BUFSTAT_REG 0x40
+
+/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
+#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
+#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
+#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
+#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
+#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
+#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
+#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
+
+/* I2C Status Register (OMAP_I2C_STAT): */
+#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
+#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
+#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
+#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
+#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
+#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
+#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
+#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
+#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
+#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
+#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
+#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
+
+/* I2C WE wakeup enable register */
+#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
+#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
+#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
+#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
+#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
+#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
+#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
+#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
+#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
+#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
+
+#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
+ OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
+ OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
+ OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
+ OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
+
+/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
+#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
+#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
+#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
+#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
+
+/* I2C Configuration Register (OMAP_I2C_CON): */
+#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
+#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
+#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
+#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
+#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
+#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
+#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
+#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
+#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
+#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
+
+/* I2C SCL time value when Master */
+#define OMAP_I2C_SCLL_HSSCLL 8
+#define OMAP_I2C_SCLH_HSSCLH 8
+
+/* I2C System Test Register (OMAP_I2C_SYSTEST): */
+#ifdef DEBUG
+#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
+#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
+#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
+#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
+#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
+#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
+#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
+#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
+#endif
+
+/* OCP_SYSSTATUS bit definitions */
+#define SYSS_RESETDONE_MASK (1 << 0)
+
+/* OCP_SYSCONFIG bit definitions */
+#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
+#define SYSC_SIDLEMODE_MASK (0x3 << 3)
+#define SYSC_ENAWAKEUP_MASK (1 << 2)
+#define SYSC_SOFTRESET_MASK (1 << 1)
+#define SYSC_AUTOIDLE_MASK (1 << 0)
+
+#define SYSC_IDLEMODE_SMART 0x2
+#define SYSC_CLOCKACTIVITY_FCLK 0x2
+
+
+struct omap_i2c_struct {
+ void *base;
+ struct resource *ioarea;
+ u32 speed; /* Speed of bus in Khz */
+ u16 cmd_err;
+ u8 *buf;
+ size_t buf_len;
+ struct i2c_adapter adapter;
+ u8 fifo_size; /* use as flag and value
+ * fifo_size==0 implies no fifo
+ * if set, should be trsh+1
+ */
+ u8 rev;
+ unsigned b_hw:1; /* bad h/w fixes */
+ u16 iestate; /* Saved interrupt register */
+ u16 pscstate;
+ u16 scllstate;
+ u16 sclhstate;
+ u16 bufstate;
+ u16 syscstate;
+ u16 westate;
+};
+#define to_omap_i2c_struct(a) container_of(a, struct omap_i2c_struct, adapter)
+
+
+static inline void omap_i2c_write_reg(struct omap_i2c_struct *i2c_omap,
+ int reg, u16 val)
+{
+ __raw_writew(val, i2c_omap->base + reg);
+}
+
+static inline u16 omap_i2c_read_reg(struct omap_i2c_struct *i2c_omap, int reg)
+{
+ return __raw_readw(i2c_omap->base + reg);
+}
+
+static void omap_i2c_unidle(struct omap_i2c_struct *i2c_omap)
+{
+ if (cpu_is_omap34xx()) {
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, 0);
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_PSC_REG, i2c_omap->pscstate);
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_SCLL_REG, i2c_omap->scllstate);
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_SCLH_REG, i2c_omap->sclhstate);
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_BUF_REG, i2c_omap->bufstate);
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_SYSC_REG, i2c_omap->syscstate);
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_WE_REG, i2c_omap->westate);
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
+ }
+
+ /*
+ * Don't write to this register if the IE state is 0 as it can
+ * cause deadlock.
+ */
+ if (i2c_omap->iestate)
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_IE_REG, i2c_omap->iestate);
+}
+
+static void omap_i2c_idle(struct omap_i2c_struct *i2c_omap)
+{
+ u16 iv;
+
+ i2c_omap->iestate = omap_i2c_read_reg(i2c_omap, OMAP_I2C_IE_REG);
+ /* omap_i2c_write_reg(i2c_omap, OMAP_I2C_IE_REG, 0); */
+ if (i2c_omap->rev < OMAP_I2C_REV_2) {
+ iv = omap_i2c_read_reg(i2c_omap, OMAP_I2C_IV_REG); /* Read clears */
+ } else {
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_STAT_REG, i2c_omap->iestate);
+
+ /* Flush posted write before the i2c_omap->idle store occurs */
+ omap_i2c_read_reg(i2c_omap, OMAP_I2C_STAT_REG);
+ }
+}
+
+static int omap_i2c_init(struct omap_i2c_struct *i2c_omap)
+{
+ u16 psc = 0, scll = 0, sclh = 0, buf = 0;
+ u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
+ uint64_t start;
+
+ unsigned long fclk_rate = 12000000;
+ unsigned long internal_clk = 0;
+
+ if (i2c_omap->rev >= OMAP_I2C_REV_2) {
+ /* Disable I2C controller before soft reset */
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG,
+ omap_i2c_read_reg(i2c_omap, OMAP_I2C_CON_REG) &
+ ~(OMAP_I2C_CON_EN));
+
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
+ /* For some reason we need to set the EN bit before the
+ * reset done bit gets set. */
+ start = get_time_ns();
+
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
+ while (!(omap_i2c_read_reg(i2c_omap, OMAP_I2C_SYSS_REG) &
+ SYSS_RESETDONE_MASK)) {
+ if (is_timeout(start, MSECOND)) {
+ dev_warn(i2c_omap->adapter.dev, "timeout waiting "
+ "for controller reset\n");
+ return -ETIMEDOUT;
+ }
+ mdelay(1);
+ }
+
+ /* SYSC register is cleared by the reset; rewrite it */
+ if (i2c_omap->rev == OMAP_I2C_REV_ON_2430) {
+
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_SYSC_REG,
+ SYSC_AUTOIDLE_MASK);
+
+ } else if (i2c_omap->rev >= OMAP_I2C_REV_ON_3430) {
+ i2c_omap->syscstate = SYSC_AUTOIDLE_MASK;
+ i2c_omap->syscstate |= SYSC_ENAWAKEUP_MASK;
+ i2c_omap->syscstate |= (SYSC_IDLEMODE_SMART <<
+ __ffs(SYSC_SIDLEMODE_MASK));
+ i2c_omap->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
+ __ffs(SYSC_CLOCKACTIVITY_MASK));
+
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_SYSC_REG,
+ i2c_omap->syscstate);
+ /*
+ * Enabling all wakup sources to stop I2C freezing on
+ * WFI instruction.
+ * REVISIT: Some wkup sources might not be needed.
+ */
+ i2c_omap->westate = OMAP_I2C_WE_ALL;
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_WE_REG, i2c_omap->westate);
+ }
+ }
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, 0);
+
+ /* omap1 handling is missing here */
+
+ if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+
+ /*
+ * HSI2C controller internal clk rate should be 19.2 Mhz for
+ * HS and for all modes on 2430. On 34xx we can use lower rate
+ * to get longer filter period for better noise suppression.
+ * The filter is iclk (fclk for HS) period.
+ */
+ if (i2c_omap->speed > 400 || cpu_is_omap2430())
+ internal_clk = 19200;
+ else if (i2c_omap->speed > 100)
+ internal_clk = 9600;
+ else
+ internal_clk = 4000;
+ fclk_rate = 96000000 / 1000;
+
+ /* Compute prescaler divisor */
+ psc = fclk_rate / internal_clk;
+ psc = psc - 1;
+
+ /* If configured for High Speed */
+ if (i2c_omap->speed > 400) {
+ unsigned long scl;
+
+ /* For first phase of HS mode */
+ scl = internal_clk / 400;
+ fsscll = scl - (scl / 3) - 7;
+ fssclh = (scl / 3) - 5;
+
+ /* For second phase of HS mode */
+ scl = fclk_rate / i2c_omap->speed;
+ hsscll = scl - (scl / 3) - 7;
+ hssclh = (scl / 3) - 5;
+ } else if (i2c_omap->speed > 100) {
+ unsigned long scl;
+
+ /* Fast mode */
+ scl = internal_clk / i2c_omap->speed;
+ fsscll = scl - (scl / 3) - 7;
+ fssclh = (scl / 3) - 5;
+ } else {
+ /* Standard mode */
+ fsscll = internal_clk / (i2c_omap->speed * 2) - 7;
+ fssclh = internal_clk / (i2c_omap->speed * 2) - 5;
+ }
+ scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
+ sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
+ } else {
+ /* Program desired operating rate */
+ fclk_rate /= (psc + 1) * 1000;
+ if (psc > 2)
+ psc = 2;
+ scll = fclk_rate / (i2c_omap->speed * 2) - 7 + psc;
+ sclh = fclk_rate / (i2c_omap->speed * 2) - 7 + psc;
+ }
+
+ /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_PSC_REG, psc);
+
+ /* SCL low and high time values */
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_SCLL_REG, scll);
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_SCLH_REG, sclh);
+
+ if (i2c_omap->fifo_size) {
+ /* Note: setup required fifo size - 1. RTRSH and XTRSH */
+ buf = (i2c_omap->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
+ (i2c_omap->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_BUF_REG, buf);
+ }
+
+ /* Take the I2C module out of reset: */
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
+
+ /* Enable interrupts */
+ i2c_omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
+ OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
+ OMAP_I2C_IE_AL) | ((i2c_omap->fifo_size) ?
+ (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_IE_REG, i2c_omap->iestate);
+ if (cpu_is_omap34xx()) {
+ i2c_omap->pscstate = psc;
+ i2c_omap->scllstate = scll;
+ i2c_omap->sclhstate = sclh;
+ i2c_omap->bufstate = buf;
+ }
+ return 0;
+}
+
+/*
+ * Waiting on Bus Busy
+ */
+static int omap_i2c_wait_for_bb(struct i2c_adapter *adapter)
+{
+ uint64_t start;
+ struct omap_i2c_struct *i2c_omap = to_omap_i2c_struct(adapter);
+
+ start = get_time_ns();
+ while (omap_i2c_read_reg(i2c_omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
+ if (is_timeout(start, MSECOND)) {
+ dev_warn(adapter->dev, "timeout waiting for bus ready\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+static inline void
+omap_i2c_ack_stat(struct omap_i2c_struct *i2c_omap, u16 stat)
+{
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_STAT_REG, stat);
+}
+
+static int
+omap_i2c_isr(struct omap_i2c_struct *dev)
+{
+ u16 bits;
+ u16 stat, w;
+ int err, count = 0;
+
+ bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
+ while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
+ dev_dbg(dev->adapter.dev, "IRQ (ISR = 0x%04x)\n", stat);
+ if (count++ == 100) {
+ dev_warn(dev->adapter.dev, "Too much work in one IRQ\n");
+ break;
+ }
+
+ err = 0;
+complete:
+ /*
+ * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
+ * acked after the data operation is complete.
+ * Ref: TRM SWPU114Q Figure 18-31
+ */
+ omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
+ ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
+ OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
+
+ if (stat & OMAP_I2C_STAT_NACK) {
+ err |= OMAP_I2C_STAT_NACK;
+ omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
+ OMAP_I2C_CON_STP);
+ }
+ if (stat & OMAP_I2C_STAT_AL) {
+ dev_err(dev->adapter.dev, "Arbitration lost\n");
+ err |= OMAP_I2C_STAT_AL;
+ }
+ if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
+ OMAP_I2C_STAT_AL)) {
+ omap_i2c_ack_stat(dev, stat &
+ (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
+ OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
+ return 0;
+ }
+ if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
+ u8 num_bytes = 1;
+ if (dev->fifo_size) {
+ if (stat & OMAP_I2C_STAT_RRDY)
+ num_bytes = dev->fifo_size;
+ else /* read RXSTAT on RDR interrupt */
+ num_bytes = (omap_i2c_read_reg(dev,
+ OMAP_I2C_BUFSTAT_REG)
+ >> 8) & 0x3F;
+ }
+ while (num_bytes) {
+ num_bytes--;
+ w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
+ if (dev->buf_len) {
+ *dev->buf++ = w;
+ dev->buf_len--;
+ /* Data reg from 2430 is 8 bit wide */
+ if (!cpu_is_omap2430() &&
+ !cpu_is_omap34xx()) {
+ if (dev->buf_len) {
+ *dev->buf++ = w >> 8;
+ dev->buf_len--;
+ }
+ }
+ } else {
+ if (stat & OMAP_I2C_STAT_RRDY)
+ dev_err(dev->adapter.dev,
+ "RRDY IRQ while no data"
+ " requested\n");
+ if (stat & OMAP_I2C_STAT_RDR)
+ dev_err(dev->adapter.dev,
+ "RDR IRQ while no data"
+ " requested\n");
+ break;
+ }
+ }
+ omap_i2c_ack_stat(dev,
+ stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
+ continue;
+ }
+ if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
+ u8 num_bytes = 1;
+ if (dev->fifo_size) {
+ if (stat & OMAP_I2C_STAT_XRDY)
+ num_bytes = dev->fifo_size;
+ else /* read TXSTAT on XDR interrupt */
+ num_bytes = omap_i2c_read_reg(dev,
+ OMAP_I2C_BUFSTAT_REG)
+ & 0x3F;
+ }
+ while (num_bytes) {
+ num_bytes--;
+ w = 0;
+ if (dev->buf_len) {
+ w = *dev->buf++;
+ dev->buf_len--;
+ /* Data reg from 2430 is 8 bit wide */
+ if (!cpu_is_omap2430() &&
+ !cpu_is_omap34xx()) {
+ if (dev->buf_len) {
+ w |= *dev->buf++ << 8;
+ dev->buf_len--;
+ }
+ }
+ } else {
+ if (stat & OMAP_I2C_STAT_XRDY)
+ dev_err(dev->adapter.dev,
+ "XRDY IRQ while no "
+ "data to send\n");
+ if (stat & OMAP_I2C_STAT_XDR)
+ dev_err(dev->adapter.dev,
+ "XDR IRQ while no "
+ "data to send\n");
+ break;
+ }
+
+ /*
+ * OMAP3430 Errata 1.153: When an XRDY/XDR
+ * is hit, wait for XUDF before writing data
+ * to DATA_REG. Otherwise some data bytes can
+ * be lost while transferring them from the
+ * memory to the I2C interface.
+ */
+
+ if (dev->rev <= OMAP_I2C_REV_ON_3430) {
+ while (!(stat & OMAP_I2C_STAT_XUDF)) {
+ if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
+ omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
+ err |= OMAP_I2C_STAT_XUDF;
+ goto complete;
+ }
+ stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+ }
+ }
+
+ omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
+ }
+ omap_i2c_ack_stat(dev,
+ stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
+ continue;
+ }
+ if (stat & OMAP_I2C_STAT_ROVR) {
+ dev_err(dev->adapter.dev, "Receive overrun\n");
+ dev->cmd_err |= OMAP_I2C_STAT_ROVR;
+ }
+ if (stat & OMAP_I2C_STAT_XUDF) {
+ dev_err(dev->adapter.dev, "Transmit underflow\n");
+ dev->cmd_err |= OMAP_I2C_STAT_XUDF;
+ }
+ }
+
+ return -EBUSY;
+}
+
+
+/*
+ * Low level master read/write transaction.
+ */
+static int omap_i2c_xfer_msg(struct i2c_adapter *adapter,
+ struct i2c_msg *msg, int stop)
+{
+ struct omap_i2c_struct *i2c_omap = to_omap_i2c_struct(adapter);
+ uint64_t start;
+ u16 con;
+ u16 w;
+ int ret = 0;
+
+
+ dev_dbg(adapter->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
+ msg->addr, msg->len, msg->flags, stop);
+
+ if (msg->len == 0)
+ return -EINVAL;
+
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_SA_REG, msg->addr);
+
+ /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
+ i2c_omap->buf = msg->buf;
+ i2c_omap->buf_len = msg->len;
+
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_CNT_REG, i2c_omap->buf_len);
+
+ /* Clear the FIFO Buffers */
+ w = omap_i2c_read_reg(i2c_omap, OMAP_I2C_BUF_REG);
+ w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_BUF_REG, w);
+
+ i2c_omap->cmd_err = 0;
+
+ w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
+
+ /* High speed configuration */
+ if (i2c_omap->speed > 400)
+ w |= OMAP_I2C_CON_OPMODE_HS;
+
+ if (msg->flags & I2C_M_TEN)
+ w |= OMAP_I2C_CON_XA;
+ if (!(msg->flags & I2C_M_RD))
+ w |= OMAP_I2C_CON_TRX;
+
+ if (!i2c_omap->b_hw && stop)
+ w |= OMAP_I2C_CON_STP;
+
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, w);
+
+ /*
+ * Don't write stt and stp together on some hardware.
+ */
+ if (i2c_omap->b_hw && stop) {
+ start = get_time_ns();
+ con = omap_i2c_read_reg(i2c_omap, OMAP_I2C_CON_REG);
+ while (con & OMAP_I2C_CON_STT) {
+ con = omap_i2c_read_reg(i2c_omap, OMAP_I2C_CON_REG);
+
+ /* Let the user know if i2c is in a bad state */
+ if (is_timeout(start, MSECOND)) {
+ dev_err(adapter->dev, "controller timed out "
+ "waiting for start condition to finish\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ w |= OMAP_I2C_CON_STP;
+ w &= ~OMAP_I2C_CON_STT;
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, w);
+ }
+
+ /*
+ * REVISIT: We should abort the transfer on signals, but the bus goes
+ * into arbitration and we're currently unable to recover from it.
+ */
+ start = get_time_ns();
+ ret = omap_i2c_isr(i2c_omap);
+ while (ret){
+ ret = omap_i2c_isr(i2c_omap);
+ if (is_timeout(start, MSECOND)) {
+ dev_err(adapter->dev, "timed out on polling for"
+ "open i2c message handling\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ i2c_omap->buf_len = 0;
+ if (likely(!i2c_omap->cmd_err))
+ return 0;
+
+ /* We have an error */
+ if (i2c_omap->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
+ OMAP_I2C_STAT_XUDF)) {
+ omap_i2c_init(i2c_omap);
+ return -EIO;
+ }
+
+ if (i2c_omap->cmd_err & OMAP_I2C_STAT_NACK) {
+ if (msg->flags & I2C_M_IGNORE_NAK)
+ return 0;
+ if (stop) {
+ w = omap_i2c_read_reg(i2c_omap, OMAP_I2C_CON_REG);
+ w |= OMAP_I2C_CON_STP;
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, w);
+ }
+ return -EREMOTEIO;
+ }
+ return -EIO;
+}
+
+
+/*
+ * Prepare controller for a transaction and call omap_i2c_xfer_msg
+ * to do the work during IRQ processing.
+ */
+static int
+omap_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg msgs[], int num)
+{
+ struct omap_i2c_struct *i2c_omap = to_omap_i2c_struct(adapter);
+ int i;
+ int r;
+
+ omap_i2c_unidle(i2c_omap);
+
+ r = omap_i2c_wait_for_bb(adapter);
+ if (r < 0)
+ goto out;
+
+ for (i = 0; i < num; i++) {
+ r = omap_i2c_xfer_msg(adapter, &msgs[i], (i == (num - 1)));
+ if (r != 0)
+ break;
+ }
+
+ if (r == 0)
+ r = num;
+out:
+ omap_i2c_idle(i2c_omap);
+ return r;
+}
+
+static int __init
+i2c_omap_probe(struct device_d *pdev)
+{
+ struct omap_i2c_struct *i2c_omap;
+ /* struct i2c_platform_data *pdata; */
+ /* unsigned long base = pdev->map_base; */
+ int r;
+ u32 speed = 0;
+
+ i2c_omap = kzalloc(sizeof(struct omap_i2c_struct), GFP_KERNEL);
+ if (!i2c_omap) {
+ r = -ENOMEM;
+ goto err_free_mem;
+ }
+
+ if (pdev->platform_data != NULL)
+ speed = *(u32 *)pdev->platform_data;
+ else
+ speed = 100; /* Defualt speed */
+
+ i2c_omap->speed = speed;
+ i2c_omap->base = (void*)pdev->map_base;
+ printf ("I2C probe\n");
+ omap_i2c_unidle(i2c_omap);
+
+ i2c_omap->rev = omap_i2c_read_reg(i2c_omap, OMAP_I2C_REV_REG) & 0xff;
+ /* i2c_omap->base = OMAP2_I2C_BASE3; */
+
+ if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+ u16 s;
+
+ /* Set up the fifo size - Get total size */
+ s = (omap_i2c_read_reg(i2c_omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
+ i2c_omap->fifo_size = 0x8 << s;
+
+ /*
+ * Set up notification threshold as half the total available
+ * size. This is to ensure that we can handle the status on int
+ * call back latencies.
+ */
+ i2c_omap->fifo_size = (i2c_omap->fifo_size / 2);
+ i2c_omap->b_hw = 1; /* Enable hardware fixes */
+ }
+
+ /* reset ASAP, clearing any IRQs */
+ omap_i2c_init(i2c_omap);
+
+ dev_info(pdev, "bus %d rev%d.%d at %d kHz\n",
+ pdev->id, i2c_omap->rev >> 4, i2c_omap->rev & 0xf, i2c_omap->speed);
+
+ omap_i2c_idle(i2c_omap);
+
+ i2c_omap->adapter.master_xfer = omap_i2c_xfer,
+ i2c_omap->adapter.nr = pdev->id;
+ i2c_omap->adapter.dev = pdev;
+
+ /* i2c device drivers may be active on return from add_adapter() */
+ r = i2c_add_numbered_adapter(&i2c_omap->adapter);
+ if (r) {
+ dev_err(pdev, "failure adding adapter\n");
+ goto err_unuse_clocks;
+ }
+
+ return 0;
+
+err_unuse_clocks:
+ omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, 0);
+ omap_i2c_idle(i2c_omap);
+
+err_free_mem:
+ kfree(i2c_omap);
+
+ return r;
+}
+
+static struct driver_d omap_i2c_driver = {
+ .probe = i2c_omap_probe,
+ .name = DRIVER_NAME,
+};
+
+/* I2C may be needed to bring up other drivers */
+static int __init omap_i2c_init_driver(void)
+{
+ return register_driver(&omap_i2c_driver);
+}
+device_initcall(omap_i2c_init_driver);
+
+MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
+MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
+MODULE_LICENSE("GPL");
--
1.7.1
[-- Attachment #2: Type: text/plain, Size: 149 bytes --]
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^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 03/13] add twl4030 support
2010-08-04 9:59 [PATCH 00/13] OMAP/Beagleboard ehci support Michael Grzeschik
2010-08-04 9:59 ` [PATCH 01/13] i2c: Add missing defines for omap Michael Grzeschik
2010-08-04 9:59 ` [PATCH 02/13] arm omap: Add I2C driver Michael Grzeschik
@ 2010-08-04 9:59 ` Michael Grzeschik
2010-08-04 9:59 ` [PATCH 04/13] arm omap: Add gpio support Michael Grzeschik
` (10 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Michael Grzeschik @ 2010-08-04 9:59 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
drivers/i2c/Kconfig | 4 +
drivers/i2c/Makefile | 1 +
drivers/i2c/twl4030.c | 186 ++++++++++++++++++++
include/i2c/twl4030.h | 461 +++++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 652 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/twl4030.c
create mode 100644 include/i2c/twl4030.h
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 147ea49..66a7cf7 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -23,4 +23,8 @@ config DRIVER_I2C_MC9SDZ60
config DRIVER_I2C_LP3972
bool "LP3972 driver"
+config DRIVER_I2C_TWL4030
+ bool "TWL4030 driver"
+ select GPIO
+
endif
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 9be8ab2..7d07cf0 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_DRIVER_I2C_MC13892) += mc13892.o
obj-$(CONFIG_DRIVER_I2C_MC34704) += mc34704.o
obj-$(CONFIG_DRIVER_I2C_MC9SDZ60) += mc9sdz60.o
obj-$(CONFIG_DRIVER_I2C_LP3972) += lp3972.o
+obj-$(CONFIG_DRIVER_I2C_TWL4030) += twl4030.o
diff --git a/drivers/i2c/twl4030.c b/drivers/i2c/twl4030.c
new file mode 100644
index 0000000..4d47fc8
--- /dev/null
+++ b/drivers/i2c/twl4030.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2010 Michael Grzeschik <mgr@pengutronix.de>
+ *
+ * This file is released under the GPLv2
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <xfuncs.h>
+#include <errno.h>
+
+#include <i2c/i2c.h>
+#include <i2c/twl4030.h>
+
+#define DRIVERNAME "twl4030"
+
+#define to_twl4030(a) container_of(a, struct twl4030, cdev)
+
+static struct twl4030 *twl_dev;
+
+struct twl4030 *twl4030_get(void)
+{
+ if (!twl_dev)
+ return NULL;
+
+ return twl_dev;
+}
+EXPORT_SYMBOL(twl4030_get);
+
+int twl4030_reg_read(struct twl4030 *twl4030, u16 reg, u8 *val)
+{
+ int ret;
+ struct i2c_msg xfer_msg[2];
+ struct i2c_msg *msg;
+ int i2c_addr;
+ unsigned char buf = reg & 0xff;
+
+ i2c_addr = twl4030->client->addr + (reg / 0x100);
+
+ /* [MSG1] fill the register address data */
+ msg = &xfer_msg[0];
+ msg->addr = i2c_addr;
+ msg->len = 1;
+ msg->flags = 0; /* Read the register value */
+ msg->buf = &buf;
+ /* [MSG2] fill the data rx buffer */
+ msg = &xfer_msg[1];
+ msg->addr = i2c_addr;
+ msg->flags = I2C_M_RD; /* Read the register value */
+ msg->len = 1; /* only n bytes */
+ msg->buf = val;
+ ret = i2c_transfer(twl4030->client->adapter, &xfer_msg, 2);
+
+ /* i2c_transfer returns number of messages transferred */
+ if (ret < 0) {
+ pr_err("%s: failed to transfer all messages: %s\n", __func__, strerror(-ret));
+ return ret;
+ }
+ return 0;
+}
+EXPORT_SYMBOL(twl4030_reg_read)
+
+int twl4030_reg_write(struct twl4030 *twl4030, u16 reg, u8 val)
+{
+ int ret;
+ struct i2c_msg xfer_msg[1];
+ struct i2c_msg *msg;
+ int i2c_addr;
+ u8 buf[2];
+
+ buf[0] = reg & 0xff;
+ buf[1] = val;
+
+ i2c_addr = twl4030->client->addr + (reg / 0x100);
+
+ /*
+ * [MSG1]: fill the register address data
+ * fill the data Tx buffer
+ */
+ msg = xfer_msg;
+ msg->addr = i2c_addr;
+ msg->len = 2;
+ msg->flags = 0;
+ msg->buf = buf;
+ /* over write the first byte of buffer with the register address */
+ ret = i2c_transfer(twl4030->client->adapter, xfer_msg, 1);
+
+ /* i2c_transfer returns number of messages transferred */
+ if (ret < 0) {
+ pr_err("%s: failed to transfer all messages: %s\n", __func__, strerror(-ret));
+ return ret;
+ }
+ return 0;
+}
+EXPORT_SYMBOL(twl4030_reg_write)
+
+int twl4030_set_bits(struct twl4030 *twl4030, enum twl4030_reg reg, u32 mask, u32 val)
+{
+ u32 tmp;
+ int err;
+
+ err = twl4030_reg_read(twl4030, reg, &tmp);
+ tmp = (tmp & ~mask) | val;
+
+ if (!err)
+ err = twl4030_reg_write(twl4030, reg, tmp);
+
+ return err;
+}
+EXPORT_SYMBOL(twl4030_set_bits);
+
+static ssize_t twl_read(struct cdev *cdev, void *_buf, size_t count, ulong offset, ulong flags)
+{
+ struct twl4030 *priv = to_twl4030(cdev);
+ u8 *buf = _buf;
+ size_t i = count;
+ int err;
+
+ while (i) {
+ err = twl4030_reg_read(priv, offset, buf);
+ if (err)
+ return (ssize_t)err;
+ buf++;
+ i--;
+ offset++;
+ }
+
+ return count;
+}
+
+static ssize_t twl_write(struct cdev *cdev, const void *_buf, size_t count, ulong offset, ulong flags)
+{
+ struct twl4030 *twl4030 = to_twl4030(cdev);
+ const u8 *buf = _buf;
+ size_t i = count;
+ int err;
+
+ while (i) {
+ err = twl4030_reg_write(twl4030, offset, *buf);
+ if (err)
+ return (ssize_t)err;
+ buf++;
+ i--;
+ offset++;
+ }
+
+ return count;
+}
+
+static struct file_operations twl_fops = {
+ .lseek = dev_lseek_default,
+ .read = twl_read,
+ .write = twl_write,
+};
+
+static int twl_probe(struct device_d *dev)
+{
+ if (twl_dev)
+ return -EBUSY;
+
+ twl_dev = xzalloc(sizeof(struct twl4030));
+ twl_dev->cdev.name = DRIVERNAME;
+ twl_dev->client = to_i2c_client(dev);
+ twl_dev->cdev.size = 1024;
+ twl_dev->cdev.dev = dev;
+ twl_dev->cdev.ops = &twl_fops;
+
+ devfs_create(&twl_dev->cdev);
+
+ return 0;
+}
+
+static struct driver_d twl_driver = {
+ .name = DRIVERNAME,
+ .probe = twl_probe,
+};
+
+static int twl_init(void)
+{
+ register_driver(&twl_driver);
+ return 0;
+}
+
+device_initcall(twl_init);
diff --git a/include/i2c/twl4030.h b/include/i2c/twl4030.h
new file mode 100644
index 0000000..c9fbae0
--- /dev/null
+++ b/include/i2c/twl4030.h
@@ -0,0 +1,461 @@
+/*
+ * Copyright (C) 2010 Michael Grzeschik <mgr@pengutronix.de>
+ * Copyright (C) 2010 Sascha Hauer <sha@pengutronix.de>
+ *
+ * This file is released under the GPLv2
+ *
+ */
+
+#ifndef __I2C_TWL4030_H
+#define __I2C_TWL4030_H
+
+#include <common.h>
+#include <i2c/i2c.h>
+#include <linux/err.h>
+
+/* LED */
+#define TWL4030_LED_LEDEN_LEDAON (1 << 0)
+#define TWL4030_LED_LEDEN_LEDBON (1 << 1)
+#define TWL4030_LED_LEDEN_LEDAPWM (1 << 4)
+#define TWL4030_LED_LEDEN_LEDBPWM (1 << 5)
+
+/* KEYPAD */
+#define TWL4030_KEYPAD_CTRL_KBD_ON (1 << 6)
+#define TWL4030_KEYPAD_CTRL_RP_EN (1 << 5)
+#define TWL4030_KEYPAD_CTRL_TOLE_EN (1 << 4)
+#define TWL4030_KEYPAD_CTRL_TOE_EN (1 << 3)
+#define TWL4030_KEYPAD_CTRL_LK_EN (1 << 2)
+#define TWL4030_KEYPAD_CTRL_SOFTMODEN (1 << 1)
+#define TWL4030_KEYPAD_CTRL_SOFT_NRST (1 << 0)
+
+/* P[1-3]_SW_EVENTS */
+#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON (1 << 6)
+#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN (1 << 5)
+#define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET (1 << 4)
+#define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP (1 << 3)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVACT (1 << 2)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0)
+
+
+enum twl4030_reg {
+ /* Register base addresses */
+ /* USB */
+ TWL4030_BASEADD_USB = 0x0000,
+ /* AUD */
+ TWL4030_BASEADD_AUDIO_VOICE = 0x0100,
+ TWL4030_BASEADD_GPIO = 0x0198,
+ TWL4030_BASEADD_INTBR = 0x0185,
+ TWL4030_BASEADD_PIH = 0x0180,
+ TWL4030_BASEADD_TEST = 0x014C,
+ /* AUX */
+ TWL4030_BASEADD_INTERRUPTS = 0x02B9,
+ TWL4030_BASEADD_LED = 0x02EE,
+ TWL4030_BASEADD_MADC = 0x0200,
+ TWL4030_BASEADD_MAIN_CHARGE = 0x0274,
+ TWL4030_BASEADD_PRECHARGE = 0x02AA,
+ TWL4030_BASEADD_PWM0 = 0x02F8,
+ TWL4030_BASEADD_PWM1 = 0x02FB,
+ TWL4030_BASEADD_PWMA = 0x02EF,
+ TWL4030_BASEADD_PWMB = 0x02F1,
+ TWL4030_BASEADD_KEYPAD = 0x02D2,
+ /* POWER */
+ TWL4030_BASEADD_BACKUP = 0x0314,
+ TWL4030_BASEADD_INT = 0x032E,
+ TWL4030_BASEADD_PM_MASTER = 0x0336,
+ TWL4030_BASEADD_PM_RECIEVER = 0x035B,
+ TWL4030_BASEADD_RTC = 0x031C,
+ TWL4030_BASEADD_SECURED_REG = 0x0300,
+
+ /* LED */
+ TWL4030_LED_LEDEN = 0x02EE,
+
+ /*
+ * Voltage Selection in PM Receiver Module
+ */
+ TWL4030_PM_RECEIVER_VAUX2_VSEL_18 = 0x05,
+ TWL4030_PM_RECEIVER_VAUX3_VSEL_28 = 0x03,
+ TWL4030_PM_RECEIVER_VPLL2_VSEL_18 = 0x05,
+ TWL4030_PM_RECEIVER_VDAC_VSEL_18 = 0x03,
+ TWL4030_PM_RECEIVER_VMMC1_VSEL_30 = 0x02,
+
+ /*
+ * Device Selection in PM Receiver Module
+ */
+ TWL4030_PM_RECEIVER_DEV_GRP_P1 = 0x20,
+ TWL4030_PM_RECEIVER_DEV_GRP_ALL = 0xE0,
+
+ /*
+ * Power Management Master
+ */
+ TWL4030_PM_MASTER_CFG_P1_TRANSITION = 0x0336,
+ TWL4030_PM_MASTER_CFG_P2_TRANSITION = 0x0337,
+ TWL4030_PM_MASTER_CFG_P3_TRANSITION = 0x0338,
+ TWL4030_PM_MASTER_CFG_P123_TRANSITION = 0x0339,
+ TWL4030_PM_MASTER_STS_BOOT = 0x033A,
+ TWL4030_PM_MASTER_CFG_BOOT = 0x033B,
+ TWL4030_PM_MASTER_SHUNDAN = 0x033C,
+ TWL4030_PM_MASTER_BOOT_BCI = 0x033D,
+ TWL4030_PM_MASTER_CFG_PWRANA1 = 0x033E,
+ TWL4030_PM_MASTER_CFG_PWRANA2 = 0x033F,
+ TWL4030_PM_MASTER_BGAP_TRIM = 0x0340,
+ TWL4030_PM_MASTER_BACKUP_MISC_STS = 0x0341,
+ TWL4030_PM_MASTER_BACKUP_MISC_CFG = 0x0342,
+ TWL4030_PM_MASTER_BACKUP_MISC_TST = 0x0343,
+ TWL4030_PM_MASTER_PROTECT_KEY = 0x0344,
+ TWL4030_PM_MASTER_STS_HW_CONDITIONS = 0x0345,
+ TWL4030_PM_MASTER_P1_SW_EVENTS = 0x0346,
+ TWL4030_PM_MASTER_P2_SW_EVENTS = 0x0347,
+ TWL4030_PM_MASTER_P3_SW_EVENTS = 0x0348,
+ TWL4030_PM_MASTER_STS_P123_STATE = 0x0349,
+ TWL4030_PM_MASTER_PB_CFG = 0x034A,
+ TWL4030_PM_MASTER_PB_WORD_MSB = 0x034B,
+ TWL4030_PM_MASTER_PB_WORD_LSB = 0x034C,
+ TWL4030_PM_MASTER_SEQ_ADD_W2P = 0x0352,
+ TWL4030_PM_MASTER_SEQ_ADD_P2A = 0x0353,
+ TWL4030_PM_MASTER_SEQ_ADD_A2W = 0x0354,
+ TWL4030_PM_MASTER_SEQ_ADD_A2S = 0x0355,
+ TWL4030_PM_MASTER_SEQ_ADD_S2A12 = 0x0356,
+ TWL4030_PM_MASTER_SEQ_ADD_S2A3 = 0x0357,
+ TWL4030_PM_MASTER_SEQ_ADD_WARM = 0x0358,
+ TWL4030_PM_MASTER_MEMORY_ADDRESS = 0x0359,
+ TWL4030_PM_MASTER_MEMORY_DATA = 0x035A,
+ TWL4030_PM_MASTER_SC_CONFIG = 0x035B,
+ TWL4030_PM_MASTER_SC_DETECT1 = 0x035C,
+ TWL4030_PM_MASTER_SC_DETECT2 = 0x035D,
+ TWL4030_PM_MASTER_WATCHDOG_CFG = 0x035E,
+ TWL4030_PM_MASTER_IT_CHECK_CFG = 0x035F,
+ TWL4030_PM_MASTER_VIBRATOR_CFG = 0x0360,
+ TWL4030_PM_MASTER_DCDC_GLOBAL_CFG = 0x0361,
+ TWL4030_PM_MASTER_VDD1_TRIM1 = 0x0362,
+ TWL4030_PM_MASTER_VDD1_TRIM2 = 0x0363,
+ TWL4030_PM_MASTER_VDD2_TRIM1 = 0x0364,
+ TWL4030_PM_MASTER_VDD2_TRIM2 = 0x0365,
+ TWL4030_PM_MASTER_VIO_TRIM1 = 0x0366,
+ TWL4030_PM_MASTER_VIO_TRIM2 = 0x0367,
+ TWL4030_PM_MASTER_MISC_CFG = 0x0368,
+ TWL4030_PM_MASTER_LS_TST_A = 0x0369,
+ TWL4030_PM_MASTER_LS_TST_B = 0x036A,
+ TWL4030_PM_MASTER_LS_TST_C = 0x036B,
+ TWL4030_PM_MASTER_LS_TST_D = 0x036C,
+ TWL4030_PM_MASTER_BB_CFG = 0x036D,
+ TWL4030_PM_MASTER_MISC_TST = 0x036E,
+ TWL4030_PM_MASTER_TRIM1 = 0x036F,
+
+ /* Power Managment Receiver */
+ TWL4030_PM_RECEIVER_SC_CONFIG = 0x035B,
+ TWL4030_PM_RECEIVER_SC_DETECT1 = 0x035C,
+ TWL4030_PM_RECEIVER_SC_DETECT2 = 0x035D,
+ TWL4030_PM_RECEIVER_WATCHDOG_CFG = 0x035E,
+ TWL4030_PM_RECEIVER_IT_CHECK_CFG = 0x035F,
+ TWL4030_PM_RECEIVER_VIBRATOR_CFG = 0x035F,
+ TWL4030_PM_RECEIVER_DC_TO_DC_CFG = 0x0361,
+ TWL4030_PM_RECEIVER_VDD1_TRIM1 = 0x0362,
+ TWL4030_PM_RECEIVER_VDD1_TRIM2 = 0x0363,
+ TWL4030_PM_RECEIVER_VDD2_TRIM1 = 0x0364,
+ TWL4030_PM_RECEIVER_VDD2_TRIM2 = 0x0365,
+ TWL4030_PM_RECEIVER_VIO_TRIM1 = 0x0366,
+ TWL4030_PM_RECEIVER_VIO_TRIM2 = 0x0367,
+ TWL4030_PM_RECEIVER_MISC_CFG = 0x0368,
+ TWL4030_PM_RECEIVER_LS_TST_A = 0x0369,
+ TWL4030_PM_RECEIVER_LS_TST_B = 0x036A,
+ TWL4030_PM_RECEIVER_LS_TST_C = 0x036B,
+ TWL4030_PM_RECEIVER_LS_TST_D = 0x036C,
+ TWL4030_PM_RECEIVER_BB_CFG = 0x036D,
+ TWL4030_PM_RECEIVER_MISC_TST = 0x036E,
+ TWL4030_PM_RECEIVER_TRIM1 = 0x036F,
+ TWL4030_PM_RECEIVER_TRIM2 = 0x0370,
+ TWL4030_PM_RECEIVER_DC_DC_TIMEOUT = 0x0371,
+ TWL4030_PM_RECEIVER_VAUX1_DEV_GRP = 0x0372,
+ TWL4030_PM_RECEIVER_VAUX1_TYPE = 0x0373,
+ TWL4030_PM_RECEIVER_VAUX1_REMAP = 0x0374,
+ TWL4030_PM_RECEIVER_VAUX1_DEDICATED = 0x0375,
+ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP = 0x0376,
+ TWL4030_PM_RECEIVER_VAUX2_TYPE = 0x0377,
+ TWL4030_PM_RECEIVER_VAUX2_REMAP = 0x0378,
+ TWL4030_PM_RECEIVER_VAUX2_DEDICATED = 0x0379,
+ TWL4030_PM_RECEIVER_VAUX3_DEV_GRP = 0x037A,
+ TWL4030_PM_RECEIVER_VAUX3_TYPE = 0x037B,
+ TWL4030_PM_RECEIVER_VAUX3_REMAP = 0x037C,
+ TWL4030_PM_RECEIVER_VAUX3_DEDICATED = 0x037D,
+ TWL4030_PM_RECEIVER_VAUX4_DEV_GRP = 0x037E,
+ TWL4030_PM_RECEIVER_VAUX4_TYPE = 0x037F,
+ TWL4030_PM_RECEIVER_VAUX4_REMAP = 0x0380,
+ TWL4030_PM_RECEIVER_VAUX4_DEDICATED = 0x0381,
+ TWL4030_PM_RECEIVER_VMMC1_DEV_GRP = 0x0382,
+ TWL4030_PM_RECEIVER_VMMC1_TYPE = 0x0383,
+ TWL4030_PM_RECEIVER_VMMC1_REMAP = 0x0384,
+ TWL4030_PM_RECEIVER_VMMC1_DEDICATED = 0x0385,
+ TWL4030_PM_RECEIVER_VMMC2_DEV_GRP = 0x0386,
+ TWL4030_PM_RECEIVER_VMMC2_TYPE = 0x0387,
+ TWL4030_PM_RECEIVER_VMMC2_REMAP = 0x0388,
+ TWL4030_PM_RECEIVER_VMMC2_DEDICATED = 0x0389,
+ TWL4030_PM_RECEIVER_VPLL1_DEV_GRP = 0x038A,
+ TWL4030_PM_RECEIVER_VPLL1_TYPE = 0x038B,
+ TWL4030_PM_RECEIVER_VPLL1_REMAP = 0x038C,
+ TWL4030_PM_RECEIVER_VPLL1_DEDICATED = 0x038D,
+ TWL4030_PM_RECEIVER_VPLL2_DEV_GRP = 0x038E,
+ TWL4030_PM_RECEIVER_VPLL2_TYPE = 0x038F,
+ TWL4030_PM_RECEIVER_VPLL2_REMAP = 0x0390,
+ TWL4030_PM_RECEIVER_VPLL2_DEDICATED = 0x0391,
+ TWL4030_PM_RECEIVER_VSIM_DEV_GRP = 0x0392,
+ TWL4030_PM_RECEIVER_VSIM_TYPE = 0x0393,
+ TWL4030_PM_RECEIVER_VSIM_REMAP = 0x0394,
+ TWL4030_PM_RECEIVER_VSIM_DEDICATED = 0x0395,
+ TWL4030_PM_RECEIVER_VDAC_DEV_GRP = 0x0396,
+ TWL4030_PM_RECEIVER_VDAC_TYPE = 0x0397,
+ TWL4030_PM_RECEIVER_VDAC_REMAP = 0x0398,
+ TWL4030_PM_RECEIVER_VDAC_DEDICATED = 0x0399,
+ TWL4030_PM_RECEIVER_VINTANA1_DEV_GRP = 0x039A,
+ TWL4030_PM_RECEIVER_VINTANA1_TYP = 0x039B,
+ TWL4030_PM_RECEIVER_VINTANA1_REMAP = 0x039C,
+ TWL4030_PM_RECEIVER_VINTANA1_DEDICATED = 0x039D,
+ TWL4030_PM_RECEIVER_VINTANA2_DEV_GRP = 0x039E,
+ TWL4030_PM_RECEIVER_VINTANA2_TYPE = 0x039F,
+ TWL4030_PM_RECEIVER_VINTANA2_REMAP = 0x03A0,
+ TWL4030_PM_RECEIVER_VINTANA2_DEDICATED = 0x03A1,
+ TWL4030_PM_RECEIVER_VINTDIG_DEV_GRP = 0x03A2,
+ TWL4030_PM_RECEIVER_VINTDIG_TYPE = 0x03A3,
+ TWL4030_PM_RECEIVER_VINTDIG_REMAP = 0x03A4,
+ TWL4030_PM_RECEIVER_VINTDIG_DEDICATED = 0x03A5,
+ TWL4030_PM_RECEIVER_VIO_DEV_GRP = 0x03A6,
+ TWL4030_PM_RECEIVER_VIO_TYPE = 0x03A7,
+ TWL4030_PM_RECEIVER_VIO_REMAP = 0x03A8,
+ TWL4030_PM_RECEIVER_VIO_CFG = 0x03A9,
+ TWL4030_PM_RECEIVER_VIO_MISC_CFG = 0x03AA,
+ TWL4030_PM_RECEIVER_VIO_TEST1 = 0x03AB,
+ TWL4030_PM_RECEIVER_VIO_TEST2 = 0x03AC,
+ TWL4030_PM_RECEIVER_VIO_OSC = 0x03AD,
+ TWL4030_PM_RECEIVER_VIO_RESERVED = 0x03AE,
+ TWL4030_PM_RECEIVER_VIO_VSEL = 0x03AF,
+ TWL4030_PM_RECEIVER_VDD1_DEV_GRP = 0x03B0,
+ TWL4030_PM_RECEIVER_VDD1_TYPE = 0x03B1,
+ TWL4030_PM_RECEIVER_VDD1_REMAP = 0x03B2,
+ TWL4030_PM_RECEIVER_VDD1_CFG = 0x03B3,
+ TWL4030_PM_RECEIVER_VDD1_MISC_CFG = 0x03B4,
+ TWL4030_PM_RECEIVER_VDD1_TEST1 = 0x03B5,
+ TWL4030_PM_RECEIVER_VDD1_TEST2 = 0x03B6,
+ TWL4030_PM_RECEIVER_VDD1_OSC = 0x03B7,
+ TWL4030_PM_RECEIVER_VDD1_RESERVED = 0x03B8,
+ TWL4030_PM_RECEIVER_VDD1_VSEL = 0x03B9,
+ TWL4030_PM_RECEIVER_VDD1_VMODE_CFG = 0x03BA,
+ TWL4030_PM_RECEIVER_VDD1_VFLOOR = 0x03BB,
+ TWL4030_PM_RECEIVER_VDD1_VROOF = 0x03BC,
+ TWL4030_PM_RECEIVER_VDD1_STEP = 0x03BD,
+ TWL4030_PM_RECEIVER_VDD2_DEV_GRP = 0x03BE,
+ TWL4030_PM_RECEIVER_VDD2_TYPE = 0x03BF,
+ TWL4030_PM_RECEIVER_VDD2_REMAP = 0x03C0,
+ TWL4030_PM_RECEIVER_VDD2_CFG = 0x03C1,
+ TWL4030_PM_RECEIVER_VDD2_MISC_CFG = 0x03C2,
+ TWL4030_PM_RECEIVER_VDD2_TEST1 = 0x03C3,
+ TWL4030_PM_RECEIVER_VDD2_TEST2 = 0x03C4,
+ TWL4030_PM_RECEIVER_VDD2_OSC = 0x03C5,
+ TWL4030_PM_RECEIVER_VDD2_RESERVED = 0x03C6,
+ TWL4030_PM_RECEIVER_VDD2_VSEL = 0x03C7,
+ TWL4030_PM_RECEIVER_VDD2_VMODE_CFG = 0x03C8,
+ TWL4030_PM_RECEIVER_VDD2_VFLOOR = 0x03C9,
+ TWL4030_PM_RECEIVER_VDD2_VROOF = 0x03CA,
+ TWL4030_PM_RECEIVER_VDD2_STEP = 0x03CB,
+ TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP = 0x03CC,
+ TWL4030_PM_RECEIVER_VUSB1V5_TYPE = 0x03CD,
+ TWL4030_PM_RECEIVER_VUSB1V5_REMAP = 0x03CE,
+ TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP = 0x03CF,
+ TWL4030_PM_RECEIVER_VUSB1V8_TYPE = 0x03D0,
+ TWL4030_PM_RECEIVER_VUSB1V8_REMAP = 0x03D1,
+ TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP = 0x03D2,
+ TWL4030_PM_RECEIVER_VUSB3V1_TYPE = 0x03D3,
+ TWL4030_PM_RECEIVER_VUSB3V1_REMAP = 0x03D4,
+ TWL4030_PM_RECEIVER_VUSBCP_DEV_GRP = 0x03D5,
+ TWL4030_PM_RECEIVER_VUSBCP_TYPE = 0x03D6,
+ TWL4030_PM_RECEIVER_VUSBCP_REMAP = 0x03D7,
+ TWL4030_PM_RECEIVER_VUSB_DEDICATED1 = 0x03D8,
+ TWL4030_PM_RECEIVER_VUSB_DEDICATED2 = 0x03D9,
+ TWL4030_PM_RECEIVER_REGEN_DEV_GRP = 0x03DA,
+ TWL4030_PM_RECEIVER_REGEN_TYPE = 0x03DB,
+ TWL4030_PM_RECEIVER_REGEN_REMAP = 0x03DC,
+ TWL4030_PM_RECEIVER_NRESPWRON_DEV_GRP = 0x03DD,
+ TWL4030_PM_RECEIVER_NRESPWRON_TYPE = 0x03DE,
+ TWL4030_PM_RECEIVER_NRESPWRON_REMAP = 0x03DF,
+ TWL4030_PM_RECEIVER_CLKEN_DEV_GRP = 0x03E0,
+ TWL4030_PM_RECEIVER_CLKEN_TYPE = 0x03E1,
+ TWL4030_PM_RECEIVER_CLKEN_REMAP = 0x03E2,
+ TWL4030_PM_RECEIVER_SYSEN_DEV_GRP = 0x03E3,
+ TWL4030_PM_RECEIVER_SYSEN_TYPE = 0x03E4,
+ TWL4030_PM_RECEIVER_SYSEN_REMAP = 0x03E5,
+ TWL4030_PM_RECEIVER_HFCLKOUT_DEV_GRP = 0x03E6,
+ TWL4030_PM_RECEIVER_HFCLKOUT_TYPE = 0x03E7,
+ TWL4030_PM_RECEIVER_HFCLKOUT_REMAP = 0x03E8,
+ TWL4030_PM_RECEIVER_32KCLKOUT_DEV_GRP = 0x03E9,
+ TWL4030_PM_RECEIVER_32KCLKOUT_TYPE = 0x03EA,
+ TWL4030_PM_RECEIVER_32KCLKOUT_REMAP = 0x03EB,
+ TWL4030_PM_RECEIVER_TRITON_RESET_DEV_GR = 0x03EC,
+ TWL4030_PM_RECEIVER_TRITON_RESET_TYPE = 0x03ED,
+ TWL4030_PM_RECEIVER_TRITON_RESET_REMAP = 0x03EE,
+ TWL4030_PM_RECEIVER_MAINREF_DEV_GRP = 0x03EF,
+ TWL4030_PM_RECEIVER_MAINREF_TYPE = 0x03F0,
+ TWL4030_PM_RECEIVER_MAINREF_REMAP = 0x03F1,
+
+ /* Keypad */
+ TWL4030_KEYPAD_KEYP_CTRL_REG = 0x02D2,
+ TWL4030_KEYPAD_KEY_DEB_REG = 0x02D3,
+ TWL4030_KEYPAD_LONG_KEY_REG1 = 0x02D4,
+ TWL4030_KEYPAD_LK_PTV_REG = 0x02D5,
+ TWL4030_KEYPAD_TIME_OUT_REG1 = 0x02D6,
+ TWL4030_KEYPAD_TIME_OUT_REG2 = 0x02D7,
+ TWL4030_KEYPAD_KBC_REG = 0x02D8,
+ TWL4030_KEYPAD_KBR_REG = 0x02D9,
+ TWL4030_KEYPAD_KEYP_SMS = 0x02DA,
+ TWL4030_KEYPAD_FULL_CODE_7_0 = 0x02DB,
+ TWL4030_KEYPAD_FULL_CODE_15_8 = 0x02DC,
+ TWL4030_KEYPAD_FULL_CODE_23_16 = 0x02DD,
+ TWL4030_KEYPAD_FULL_CODE_31_24 = 0x02DE,
+ TWL4030_KEYPAD_FULL_CODE_39_32 = 0x02DF,
+ TWL4030_KEYPAD_FULL_CODE_47_40 = 0x02E0,
+ TWL4030_KEYPAD_FULL_CODE_55_48 = 0x02E1,
+ TWL4030_KEYPAD_FULL_CODE_63_56 = 0x02E2,
+ TWL4030_KEYPAD_KEYP_ISR1 = 0x02E3,
+ TWL4030_KEYPAD_KEYP_IMR1 = 0x02E4,
+ TWL4030_KEYPAD_KEYP_ISR2 = 0x02E5,
+ TWL4030_KEYPAD_KEYP_IMR2 = 0x02E6,
+ TWL4030_KEYPAD_KEYP_SIR = 0x02E7,
+ TWL4030_KEYPAD_KEYP_EDR = 0x02E8,
+ TWL4030_KEYPAD_KEYP_SIH_CTRL = 0x02E9,
+
+ /* USB */
+ TWL4030_USB_VENDOR_ID_LO = 0x0000,
+ TWL4030_USB_VENDOR_ID_HI = 0x0001,
+ TWL4030_USB_PRODUCT_ID_LO = 0x0002,
+ TWL4030_USB_PRODUCT_ID_HI = 0x0003,
+ TWL4030_USB_FUNC_CTRL = 0x0004,
+ TWL4030_USB_FUNC_CTRL_SET = 0x0005,
+ TWL4030_USB_FUNC_CTRL_CLR = 0x0006,
+ TWL4030_USB_IFC_CTRL = 0x0007,
+ TWL4030_USB_IFC_CTRL_SET = 0x0008,
+ TWL4030_USB_IFC_CTRL_CLR = 0x0009,
+ TWL4030_USB_OTG_CTRL = 0x000A,
+ TWL4030_USB_OTG_CTRL_SET = 0x000B,
+ TWL4030_USB_OTG_CTRL_CLR = 0x000C,
+ TWL4030_USB_USB_INT_EN_RISE = 0x000D,
+ TWL4030_USB_USB_INT_EN_RISE_SET = 0x000E,
+ TWL4030_USB_USB_INT_EN_RISE_CLR = 0x000F,
+ TWL4030_USB_USB_INT_EN_FALL = 0x0010,
+ TWL4030_USB_USB_INT_EN_FALL_SET = 0x0011,
+ TWL4030_USB_USB_INT_EN_FALL_CLR = 0x0012,
+ TWL4030_USB_USB_INT_STS = 0x0013,
+ TWL4030_USB_USB_INT_LATCH = 0x0014,
+ TWL4030_USB_DEBUG = 0x0015,
+ TWL4030_USB_SCRATCH_REG = 0x0016,
+ TWL4030_USB_SCRATCH_REG_SET = 0x0017,
+ TWL4030_USB_SCRATCH_REG_CLR = 0x0018,
+ TWL4030_USB_CARKIT_CTRL = 0x0019,
+ TWL4030_USB_CARKIT_CTRL_SET = 0x001A,
+ TWL4030_USB_CARKIT_CTRL_CLR = 0x001B,
+ TWL4030_USB_CARKIT_INT_DELAY = 0x001C,
+ TWL4030_USB_CARKIT_INT_EN = 0x001D,
+ TWL4030_USB_CARKIT_INT_EN_SET = 0x001E,
+ TWL4030_USB_CARKIT_INT_EN_CLR = 0x001F,
+ TWL4030_USB_CARKIT_INT_STS = 0x0020,
+ TWL4030_USB_CARKIT_INT_LATCH = 0x0021,
+ TWL4030_USB_CARKIT_PLS_CTRL = 0x0022,
+ TWL4030_USB_CARKIT_PLS_CTRL_SET = 0x0023,
+ TWL4030_USB_CARKIT_PLS_CTRL_CLR = 0x0024,
+ TWL4030_USB_TRANS_POS_WIDTH = 0x0025,
+ TWL4030_USB_TRANS_NEG_WIDTH = 0x0026,
+ TWL4030_USB_RCV_PLTY_RECOVERY = 0x0027,
+ TWL4030_USB_MCPC_CTRL = 0x0030,
+ TWL4030_USB_MCPC_CTRL_SET = 0x0031,
+ TWL4030_USB_MCPC_CTRL_CLR = 0x0032,
+ TWL4030_USB_MCPC_IO_CTRL = 0x0033,
+ TWL4030_USB_MCPC_IO_CTRL_SET = 0x0034,
+ TWL4030_USB_MCPC_IO_CTRL_CLR = 0x0035,
+ TWL4030_USB_MCPC_CTRL2 = 0x0036,
+ TWL4030_USB_MCPC_CTRL2_SET = 0x0037,
+ TWL4030_USB_MCPC_CTRL2_CLR = 0x0038,
+ TWL4030_USB_OTHER_FUNC_CTRL = 0x0080,
+ TWL4030_USB_OTHER_FUNC_CTRL_SET = 0x0081,
+ TWL4030_USB_OTHER_FUNC_CTRL_CLR = 0x0082,
+ TWL4030_USB_OTHER_IFC_CTRL = 0x0083,
+ TWL4030_USB_OTHER_IFC_CTRL_SET = 0x0084,
+ TWL4030_USB_OTHER_IFC_CTRL_CLR = 0x0085,
+ TWL4030_USB_OTHER_INT_EN_RISE_SET = 0x0087,
+ TWL4030_USB_OTHER_INT_EN_RISE_CLR = 0x0088,
+ TWL4030_USB_OTHER_INT_EN_FALL = 0x0089,
+ TWL4030_USB_OTHER_INT_EN_FALL_SET = 0x008A,
+ TWL4030_USB_OTHER_INT_EN_FALL_CLR = 0x008B,
+ TWL4030_USB_OTHER_INT_STS = 0x008C,
+ TWL4030_USB_OTHER_INT_LATCH = 0x008D,
+ TWL4030_USB_ID_STATUS = 0x0096,
+ TWL4030_USB_CARKIT_SM_1_INT_EN = 0x0097,
+ TWL4030_USB_CARKIT_SM_1_INT_EN_SET = 0x0098,
+ TWL4030_USB_CARKIT_SM_1_INT_EN_CLR = 0x0099,
+ TWL4030_USB_CARKIT_SM_1_INT_STS = 0x009A,
+ TWL4030_USB_CARKIT_SM_1_INT_LATCH = 0x009B,
+ TWL4030_USB_CARKIT_SM_2_INT_EN = 0x009C,
+ TWL4030_USB_CARKIT_SM_2_INT_EN_SET = 0x009D,
+ TWL4030_USB_CARKIT_SM_2_INT_EN_CLR = 0x009E,
+ TWL4030_USB_CARKIT_SM_2_INT_STS = 0x009F,
+ TWL4030_USB_CARKIT_SM_2_INT_LATCH = 0x00A0,
+ TWL4030_USB_CARKIT_SM_CTRL = 0x00A1,
+ TWL4030_USB_CARKIT_SM_CTRL_SET = 0x00A2,
+ TWL4030_USB_CARKIT_SM_CTRL_CLR = 0x00A3,
+ TWL4030_USB_CARKIT_SM_CMD = 0x00A4,
+ TWL4030_USB_CARKIT_SM_CMD_SET = 0x00A5,
+ TWL4030_USB_CARKIT_SM_CMD_CLR = 0x00A6,
+ TWL4030_USB_CARKIT_SM_CMD_STS = 0x00A7,
+ TWL4030_USB_CARKIT_SM_STATUS = 0x00A8,
+ TWL4030_USB_CARKIT_SM_ERR_STATUS = 0x00AA,
+ TWL4030_USB_CARKIT_SM_CTRL_STATE = 0x00AB,
+ TWL4030_USB_POWER_CTRL = 0x00AC,
+ TWL4030_USB_POWER_CTRL_SET = 0x00AD,
+ TWL4030_USB_POWER_CTRL_CLR = 0x00AE,
+ TWL4030_USB_OTHER_IFC_CTRL2 = 0x00AF,
+ TWL4030_USB_OTHER_IFC_CTRL2_SET = 0x00B0,
+ TWL4030_USB_OTHER_IFC_CTRL2_CLR = 0x00B1,
+ TWL4030_USB_REG_CTRL_EN = 0x00B2,
+ TWL4030_USB_REG_CTRL_EN_SET = 0x00B3,
+ TWL4030_USB_REG_CTRL_EN_CLR = 0x00B4,
+ TWL4030_USB_REG_CTRL_ERROR = 0x00B5,
+ TWL4030_USB_OTHER_FUNC_CTRL2 = 0x00B8,
+ TWL4030_USB_OTHER_FUNC_CTRL2_SET = 0x00B9,
+ TWL4030_USB_OTHER_FUNC_CTRL2_CLR = 0x00BA,
+ TWL4030_USB_CARKIT_ANA_CTRL = 0x00BB,
+ TWL4030_USB_CARKIT_ANA_CTRL_SET = 0x00BC,
+ TWL4030_USB_CARKIT_ANA_CTRL_CLR = 0x00BD,
+ TWL4030_USB_VBUS_DEBOUNCE = 0x00C0,
+ TWL4030_USB_ID_DEBOUNCE = 0x00C1,
+ TWL4030_USB_TPH_DP_CON_MIN = 0x00C2,
+ TWL4030_USB_TPH_DP_CON_MAX = 0x00C3,
+ TWL4030_USB_TCR_DP_CON_MIN = 0x00C4,
+ TWL4030_USB_TCR_DP_CON_MAX = 0x00C5,
+ TWL4030_USB_TPH_DP_PD_SHORT = 0x00C6,
+ TWL4030_USB_TPH_CMD_DLY = 0x00C7,
+ TWL4030_USB_TPH_DET_RST = 0x00C8,
+ TWL4030_USB_TPH_AUD_BIAS = 0x00C9,
+ TWL4030_USB_TCR_UART_DET_MIN = 0x00CA,
+ TWL4030_USB_TCR_UART_DET_MAX = 0x00CB,
+ TWL4030_USB_TPH_ID_INT_PW = 0x00CD,
+ TWL4030_USB_TACC_ID_INT_WAIT = 0x00CE,
+ TWL4030_USB_TACC_ID_INT_PW = 0x00CF,
+ TWL4030_USB_TPH_CMD_WAIT = 0x00D0,
+ TWL4030_USB_TPH_ACK_WAIT = 0x00D1,
+ TWL4030_USB_TPH_DP_DISC_DET = 0x00D2,
+ TWL4030_USB_VBAT_TIMER = 0x00D3,
+ TWL4030_USB_CARKIT_4W_DEBUG = 0x00E0,
+ TWL4030_USB_CARKIT_5W_DEBUG = 0x00E1,
+ TWL4030_USB_PHY_PWR_CTRL = 0x00FD,
+ TWL4030_USB_PHY_CLK_CTRL = 0x00FE,
+ TWL4030_USB_PHY_CLK_CTRL_STS = 0x00FF,
+};
+
+struct twl4030 {
+ struct cdev cdev;
+ struct i2c_client *client;
+};
+
+extern struct twl4030 *twl4030_get(void);
+
+extern int twl4030_reg_read(struct twl4030 *twl4030, u16 reg, u8 *val);
+extern int twl4030_reg_write(struct twl4030 *twl4030, u16 reg, u8 val);
+extern int twl4030_set_bits(struct twl4030 *twl4030, enum twl4030_reg reg, u32 mask, u32 val);
+
+#endif /* __I2C_TWL4030_H */
--
1.7.1
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^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 04/13] arm omap: Add gpio support
2010-08-04 9:59 [PATCH 00/13] OMAP/Beagleboard ehci support Michael Grzeschik
` (2 preceding siblings ...)
2010-08-04 9:59 ` [PATCH 03/13] add twl4030 support Michael Grzeschik
@ 2010-08-04 9:59 ` Michael Grzeschik
2010-08-04 9:59 ` [PATCH 05/13] arm omap: Add cpu_is_ macros Michael Grzeschik
` (9 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Michael Grzeschik @ 2010-08-04 9:59 UTC (permalink / raw)
To: barebox
[-- Attachment #1: Type: text/plain, Size: 10038 bytes --]
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/Kconfig | 15 ++-
arch/arm/mach-omap/Makefile | 1 +
arch/arm/mach-omap/gpio.c | 206 ++++++++++++++++++++++++++++++++
arch/arm/mach-omap/include/mach/gpio.h | 92 ++++++++++++++
4 files changed, 311 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-omap/gpio.c
create mode 100644 arch/arm/mach-omap/include/mach/gpio.h
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index 158639e..630405b 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -78,9 +78,18 @@ config GPMC
depends on (ARCH_OMAP2 || ARCH_OMAP3)
default y
help
- Enable this if you use Texas Instrument's General purpose Memory
- Controller(GPMC). GPMC allows you to configure devices such as NOR,
- NAND, OneNAND etc.
+ Enable this if you use Texas Instrument's General purpose Memory
+ Controller(GPMC). GPMC allows you to configure devices such as NOR,
+ NAND, OneNAND etc.
+
+config GPIO
+ prompt "Support for GPIO configuration"
+ bool
+ select GENERIC_GPIO
+ depends on (ARCH_OMAP2 || ARCH_OMAP3)
+ default y
+ help
+ Enable this if you use Texas Instrument's General Purpose IO
# Get the board specific configurations
source arch/arm/boards/omap/Kconfig
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index f672dce..57bab99 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o
obj-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o
obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock_core.o omap3_clock.o
obj-$(CONFIG_GPMC) += gpmc.o
+obj-$(CONFIG_GPIO) += gpio.o
diff --git a/arch/arm/mach-omap/gpio.c b/arch/arm/mach-omap/gpio.c
new file mode 100644
index 0000000..240ac8e
--- /dev/null
+++ b/arch/arm/mach-omap/gpio.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ * linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrj��l�� <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+#include <mach/gpio.h>
+#include <asm/io.h>
+#include <errno.h>
+
+static struct gpio_bank gpio_bank_34xx[6] = {
+ { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+static struct gpio_bank *gpio_bank = &gpio_bank_34xx[0];
+
+static inline struct gpio_bank *get_gpio_bank(int gpio)
+{
+ return &gpio_bank[gpio >> 5];
+}
+
+static inline int get_gpio_index(int gpio)
+{
+ return gpio & 0x1f;
+}
+
+static inline int gpio_valid(int gpio)
+{
+ if (gpio < 0)
+ return -1;
+ if (gpio < 192)
+ return 0;
+ return -1;
+}
+
+static int check_gpio(int gpio)
+{
+ if (gpio_valid(gpio) < 0) {
+ printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
+ return -1;
+ }
+ return 0;
+}
+
+void gpio_set_value(unsigned gpio, int value)
+{
+ struct gpio_bank *bank;
+ void *reg;
+ u32 l = 0;
+
+ if (check_gpio(gpio) < 0)
+ return;
+ bank = get_gpio_bank(gpio);
+ reg = bank->base;
+
+ switch (bank->method) {
+ case METHOD_GPIO_24XX:
+ if (value)
+ reg += OMAP24XX_GPIO_SETDATAOUT;
+ else
+ reg += OMAP24XX_GPIO_CLEARDATAOUT;
+ l = 1 << get_gpio_index(gpio);
+ break;
+ default:
+ printf("omap3-gpio unknown bank method %s %d\n",
+ __FILE__, __LINE__);
+ return;
+ }
+ __raw_writel(l, reg);
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ struct gpio_bank *bank;
+ void *reg;
+ u32 val;
+
+ if (check_gpio(gpio) < 0)
+ return -EINVAL;
+ bank = get_gpio_bank(gpio);
+
+ reg = bank->base;
+
+ switch (bank->method) {
+ case METHOD_GPIO_24XX:
+ reg += OMAP24XX_GPIO_OE;
+ break;
+ default:
+ return -EINVAL;
+ }
+ val = __raw_readl(reg);
+ val |= 1 << get_gpio_index(gpio);
+ __raw_writel(val, reg);
+
+ return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ struct gpio_bank *bank;
+ void *reg;
+ u32 val;
+
+ if (check_gpio(gpio) < 0)
+ return -EINVAL;
+ bank = get_gpio_bank(gpio);
+
+ reg = bank->base;
+
+ gpio_set_value(gpio, value);
+
+ switch (bank->method) {
+ case METHOD_GPIO_24XX:
+ reg += OMAP24XX_GPIO_OE;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ val = __raw_readl(reg);
+ val &= ~(1 << get_gpio_index(gpio));
+ __raw_writel(val, reg);
+
+ return 0;
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ struct gpio_bank *bank;
+ void *reg;
+
+ if (check_gpio(gpio) < 0)
+ return -EINVAL;
+ bank = get_gpio_bank(gpio);
+ reg = bank->base;
+ switch (bank->method) {
+ case METHOD_GPIO_24XX:
+ reg += OMAP24XX_GPIO_DATAIN;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return (__raw_readl(reg)
+ & (1 << get_gpio_index(gpio))) != 0;
+}
+
+static void _reset_gpio(int gpio)
+{
+ gpio_direction_input(gpio);
+}
+
+int omap_request_gpio(int gpio)
+{
+ if (check_gpio(gpio) < 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+void omap_free_gpio(int gpio)
+{
+ struct gpio_bank *bank;
+
+ if (check_gpio(gpio) < 0)
+ return;
+ bank = get_gpio_bank(gpio);
+
+ _reset_gpio(gpio);
+}
diff --git a/arch/arm/mach-omap/include/mach/gpio.h b/arch/arm/mach-omap/include/mach/gpio.h
new file mode 100644
index 0000000..9840b6e
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/gpio.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ * linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrj��l�� <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _GPIO_H
+#define _GPIO_H
+
+#define OMAP24XX_GPIO_REVISION 0x0000
+#define OMAP24XX_GPIO_SYSCONFIG 0x0010
+#define OMAP24XX_GPIO_SYSSTATUS 0x0014
+#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
+#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
+#define OMAP24XX_GPIO_IRQENABLE2 0x002c
+#define OMAP24XX_GPIO_IRQENABLE1 0x001c
+#define OMAP24XX_GPIO_WAKE_EN 0x0020
+#define OMAP24XX_GPIO_CTRL 0x0030
+#define OMAP24XX_GPIO_OE 0x0034
+#define OMAP24XX_GPIO_DATAIN 0x0038
+#define OMAP24XX_GPIO_DATAOUT 0x003c
+#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
+#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
+#define OMAP24XX_GPIO_RISINGDETECT 0x0048
+#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
+#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
+#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
+#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
+#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
+#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
+#define OMAP24XX_GPIO_SETWKUENA 0x0084
+#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
+#define OMAP24XX_GPIO_SETDATAOUT 0x0094
+
+struct gpio_bank {
+ void *base;
+ int method;
+};
+
+/* OMAP3 GPIO registers */
+#define OMAP34XX_GPIO1_BASE 0x48310000
+#define OMAP34XX_GPIO2_BASE 0x49050000
+#define OMAP34XX_GPIO3_BASE 0x49052000
+#define OMAP34XX_GPIO4_BASE 0x49054000
+#define OMAP34XX_GPIO5_BASE 0x49056000
+#define OMAP34XX_GPIO6_BASE 0x49058000
+
+#define METHOD_GPIO_24XX 4
+
+/* This is the interface */
+
+/* Request a gpio before using it */
+int omap_request_gpio(int gpio);
+/* Reset and free a gpio after using it */
+void omap_free_gpio(int gpio);
+void gpio_set_value(unsigned gpio, int value);
+int gpio_get_value(unsigned gpio);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_direction_input(unsigned gpio);
+
+#endif /* _GPIO_H_ */
--
1.7.1
[-- Attachment #2: Type: text/plain, Size: 149 bytes --]
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^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 05/13] arm omap: Add cpu_is_ macros
2010-08-04 9:59 [PATCH 00/13] OMAP/Beagleboard ehci support Michael Grzeschik
` (3 preceding siblings ...)
2010-08-04 9:59 ` [PATCH 04/13] arm omap: Add gpio support Michael Grzeschik
@ 2010-08-04 9:59 ` Michael Grzeschik
2010-08-04 9:59 ` [PATCH 06/13] beagle: Add missing pinmux for usb Michael Grzeschik
` (8 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Michael Grzeschik @ 2010-08-04 9:59 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/include/mach/generic.h | 19 +++++++++++++++++++
1 files changed, 19 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap/include/mach/generic.h
diff --git a/arch/arm/mach-omap/include/mach/generic.h b/arch/arm/mach-omap/include/mach/generic.h
new file mode 100644
index 0000000..a2dd229
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/generic.h
@@ -0,0 +1,19 @@
+
+/* I2C controller revisions */
+#define OMAP_I2C_REV_2 0x20
+
+/* I2C controller revisions present on specific hardware */
+#define OMAP_I2C_REV_ON_2430 0x36
+#define OMAP_I2C_REV_ON_3430 0x3C
+
+#ifdef CONFIG_ARCH_OMAP
+#define cpu_is_omap2430() (1)
+#else
+#define cpu_is_omap2430() (0)
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+#define cpu_is_omap34xx() (1)
+#else
+#define cpu_is_omap34xx() (0)
+#endif
--
1.7.1
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^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 06/13] beagle: Add missing pinmux for usb
2010-08-04 9:59 [PATCH 00/13] OMAP/Beagleboard ehci support Michael Grzeschik
` (4 preceding siblings ...)
2010-08-04 9:59 ` [PATCH 05/13] arm omap: Add cpu_is_ macros Michael Grzeschik
@ 2010-08-04 9:59 ` Michael Grzeschik
2010-08-04 9:59 ` [PATCH 07/13] ehci: Make has_tt configurable via platform data Michael Grzeschik
` (7 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Michael Grzeschik @ 2010-08-04 9:59 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/omap/board-beagle.c | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boards/omap/board-beagle.c b/arch/arm/boards/omap/board-beagle.c
index 5daad86..01c6cd2 100644
--- a/arch/arm/boards/omap/board-beagle.c
+++ b/arch/arm/boards/omap/board-beagle.c
@@ -189,6 +189,20 @@ static void mux_config(void)
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
/* I2C1_SCL default mux mode is mode0 */
/* I2C1_SDA default mux mode is mode0 */
+ /* USB EHCI (port 2) */
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3));
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3));
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3));
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3));
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3));
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3));
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3));
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3));
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3));
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3));
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3));
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3));
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/;
}
/**
--
1.7.1
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^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 07/13] ehci: Make has_tt configurable via platform data
2010-08-04 9:59 [PATCH 00/13] OMAP/Beagleboard ehci support Michael Grzeschik
` (5 preceding siblings ...)
2010-08-04 9:59 ` [PATCH 06/13] beagle: Add missing pinmux for usb Michael Grzeschik
@ 2010-08-04 9:59 ` Michael Grzeschik
2010-08-04 9:59 ` [PATCH 08/13] ehci: set CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS to 16 Michael Grzeschik
` (6 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Michael Grzeschik @ 2010-08-04 9:59 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
drivers/usb/host/ehci-hcd.c | 13 ++++++++-----
include/usb/ehci.h | 2 ++
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 8995fa3..1c266f3 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -899,22 +899,25 @@ static int ehci_probe(struct device_d *dev)
ehci = xmalloc(sizeof(struct ehci_priv));
host = &ehci->host;
- if (pdata)
+ if (pdata) {
ehci->flags = pdata->flags;
- else
+ ehci->hccr = (void *)(dev->map_base + pdata->hccr_offset);
+ ehci->hcor = (void *)(dev->map_base + pdata->hcor_offset);
+ }
+ else {
/* default to EHCI_HAS_TT to not change behaviour of boards
* with platform_data
*/
ehci->flags = EHCI_HAS_TT;
+ ehci->hccr = (void *)(dev->map_base + 0x100);
+ ehci->hcor = (void *)(dev->map_base + 0x140);
+ }
host->init = ehci_init;
host->submit_int_msg = submit_int_msg;
host->submit_control_msg = submit_control_msg;
host->submit_bulk_msg = submit_bulk_msg;
- ehci->hccr = (void *)(dev->map_base + 0x100);
- ehci->hcor = (void *)(dev->map_base + 0x140);
-
usb_register_host(host);
reg = HC_VERSION(ehci_readl(&ehci->hccr->cr_capbase));
diff --git a/include/usb/ehci.h b/include/usb/ehci.h
index 3304b60..2ec862c 100644
--- a/include/usb/ehci.h
+++ b/include/usb/ehci.h
@@ -5,6 +5,8 @@
struct ehci_platform_data {
unsigned long flags;
+ unsigned long hccr_offset;
+ unsigned long hcor_offset;
};
#endif /* __USB_EHCI_H */
--
1.7.1
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^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 08/13] ehci: set CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS to 16
2010-08-04 9:59 [PATCH 00/13] OMAP/Beagleboard ehci support Michael Grzeschik
` (6 preceding siblings ...)
2010-08-04 9:59 ` [PATCH 07/13] ehci: Make has_tt configurable via platform data Michael Grzeschik
@ 2010-08-04 9:59 ` Michael Grzeschik
2010-08-04 9:59 ` [PATCH 09/13] ehci: add remove function Michael Grzeschik
` (5 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Michael Grzeschik @ 2010-08-04 9:59 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
drivers/usb/host/ehci.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index af49249..07a1768 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -23,7 +23,7 @@
#define USB_EHCI_H
#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 16
#endif
/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
--
1.7.1
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^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 09/13] ehci: add remove function
2010-08-04 9:59 [PATCH 00/13] OMAP/Beagleboard ehci support Michael Grzeschik
` (7 preceding siblings ...)
2010-08-04 9:59 ` [PATCH 08/13] ehci: set CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS to 16 Michael Grzeschik
@ 2010-08-04 9:59 ` Michael Grzeschik
2010-08-04 9:59 ` [PATCH 10/13] usb: add twl4030 phy support Michael Grzeschik
` (4 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Michael Grzeschik @ 2010-08-04 9:59 UTC (permalink / raw)
To: barebox
and stop the ehci controller before the kernel is trying to restart it.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
drivers/usb/host/ehci-hcd.c | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 1c266f3..802c548 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -898,6 +898,7 @@ static int ehci_probe(struct device_d *dev)
ehci = xmalloc(sizeof(struct ehci_priv));
host = &ehci->host;
+ dev->priv = ehci;
if (pdata) {
ehci->flags = pdata->flags;
@@ -926,9 +927,16 @@ static int ehci_probe(struct device_d *dev)
return 0;
}
+static void ehci_remove(struct device_d *dev)
+{
+ struct ehci_priv *ehci = dev->priv;
+ ehci_halt(ehci);
+}
+
static struct driver_d ehci_driver = {
.name = "ehci",
.probe = ehci_probe,
+ .remove = ehci_remove,
};
static int ehcil_init(void)
--
1.7.1
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^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 10/13] usb: add twl4030 phy support
2010-08-04 9:59 [PATCH 00/13] OMAP/Beagleboard ehci support Michael Grzeschik
` (8 preceding siblings ...)
2010-08-04 9:59 ` [PATCH 09/13] ehci: add remove function Michael Grzeschik
@ 2010-08-04 9:59 ` Michael Grzeschik
2010-08-04 9:59 ` [PATCH 11/13] ehci: add omap support Michael Grzeschik
` (3 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Michael Grzeschik @ 2010-08-04 9:59 UTC (permalink / raw)
To: barebox
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
drivers/usb/otg/Kconfig | 3 +
drivers/usb/otg/Makefile | 2 +
drivers/usb/otg/twl4030.c | 199 +++++++++++++++++++++++++++++++++++++++++++++
include/usb/twl4030.h | 28 +++++++
4 files changed, 232 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/otg/twl4030.c
create mode 100644 include/usb/twl4030.h
diff --git a/drivers/usb/otg/Kconfig b/drivers/usb/otg/Kconfig
index 0191c87..de09cf3 100644
--- a/drivers/usb/otg/Kconfig
+++ b/drivers/usb/otg/Kconfig
@@ -4,3 +4,6 @@ config USB_ULPI
config USB_ISP1504
select USB_ULPI
bool "ISP1504 Tranceiver support"
+
+config USB_TWL4030
+ bool "TWL4030 Tranceiver support"
diff --git a/drivers/usb/otg/Makefile b/drivers/usb/otg/Makefile
index 785f922..aa95cc9 100644
--- a/drivers/usb/otg/Makefile
+++ b/drivers/usb/otg/Makefile
@@ -1,2 +1,4 @@
obj-$(CONFIG_USB_ULPI) += ulpi.o
obj-$(CONFIG_USB_ISP1504) += isp1504.o
+obj-$(CONFIG_USB_TWL4030) += twl4030.o
+
diff --git a/drivers/usb/otg/twl4030.c b/drivers/usb/otg/twl4030.c
new file mode 100644
index 0000000..72edf25
--- /dev/null
+++ b/drivers/usb/otg/twl4030.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This is file is based on
+ * repository git.gitorious.org/u-boot-omap3/mainline.git,
+ * branch omap3-dev-usb, file drivers/usb/gadget/twl4030_usb.c
+ *
+ * This is the unique part of its copyright :
+ *
+ * ------------------------------------------------------------------------
+ *
+ * * (C) Copyright 2009 Atin Malaviya (atin.malaviya@gmail.com)
+ *
+ * Based on: twl4030_usb.c in linux 2.6 (drivers/i2c/chips/twl4030_usb.c)
+ * Copyright (C) 2004-2007 Texas Instruments
+ * Copyright (C) 2008 Nokia Corporation
+ * Contact: Felipe Balbi <felipe.balbi@nokia.com>
+ *
+ * Author: Atin Malaviya (atin.malaviya@gmail.com)
+ *
+ * ------------------------------------------------------------------------
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <i2c/twl4030.h>
+#include <usb/twl4030.h>
+#include <clock.h>
+
+static int twl4030_usb_write(u8 address, u8 data)
+{
+ int ret;
+ struct twl4030 *twl4030 = twl4030_get();
+
+ ret = twl4030_reg_write(twl4030, address, data);
+ if (ret != 0)
+ printf("TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
+
+ return ret;
+}
+
+static int twl4030_usb_read(u8 address)
+{
+ u8 data;
+ int ret;
+ struct twl4030 *twl4030 = twl4030_get();
+
+ ret = twl4030_reg_read(twl4030, address, &data);
+ if (ret == 0)
+ ret = data;
+ else
+ printf("TWL4030:USB:Read[0x%x] Error %d\n", address, ret);
+
+ return ret;
+}
+
+void twl4030_power_init(void)
+{
+ unsigned char byte;
+ struct twl4030 *twl4030 = twl4030_get();
+
+ /* set VAUX3 to 2.8V */
+ byte = TWL4030_PM_RECEIVER_DEV_GRP_P1;
+ twl4030_reg_write(twl4030, TWL4030_PM_RECEIVER_VAUX3_DEV_GRP, byte);
+ byte = TWL4030_PM_RECEIVER_VAUX3_VSEL_28;
+ twl4030_reg_write(twl4030, TWL4030_PM_RECEIVER_VAUX3_DEDICATED, byte);
+
+ /* set VPLL2 to 1.8V */
+ byte = TWL4030_PM_RECEIVER_DEV_GRP_ALL;
+ twl4030_reg_write(twl4030, TWL4030_PM_RECEIVER_VPLL2_DEV_GRP, byte);
+ byte = TWL4030_PM_RECEIVER_VPLL2_VSEL_18;
+ twl4030_reg_write(twl4030, TWL4030_PM_RECEIVER_VPLL2_DEDICATED, byte);
+
+ /* set VDAC to 1.8V */
+ byte = TWL4030_PM_RECEIVER_DEV_GRP_P1;
+ twl4030_reg_write(twl4030, TWL4030_PM_RECEIVER_VDAC_DEV_GRP, byte);
+ byte = TWL4030_PM_RECEIVER_VDAC_VSEL_18;
+ twl4030_reg_write(twl4030, TWL4030_PM_RECEIVER_VDAC_DEDICATED, byte);
+}
+
+static void twl4030_usb_ldo_init(void)
+{
+ struct twl4030 *twl4030 = twl4030_get();
+ /* Enable writing to power configuration registers */
+ twl4030_reg_write(twl4030, TWL4030_PM_MASTER_PROTECT_KEY, 0xC0);
+ twl4030_reg_write(twl4030, TWL4030_PM_MASTER_PROTECT_KEY, 0x0C);
+
+ /* put VUSB3V1 LDO in active state */
+ twl4030_reg_write(twl4030, TWL4030_PM_RECEIVER_VUSB_DEDICATED2, 0x00);
+
+ /* input to VUSB3V1 LDO is from VBAT, not VBUS */
+ twl4030_reg_write(twl4030, TWL4030_PM_RECEIVER_VUSB_DEDICATED1, 0x14);
+
+ /* turn on 3.1V regulator */
+ twl4030_reg_write(twl4030, TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP, 0x20);
+ twl4030_reg_write(twl4030, TWL4030_PM_RECEIVER_VUSB3V1_TYPE, 0x00);
+
+ /* turn on 1.5V regulator */
+ twl4030_reg_write(twl4030, TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP, 0x20);
+ twl4030_reg_write(twl4030, TWL4030_PM_RECEIVER_VUSB1V5_TYPE, 0x00);
+
+ /* turn on 1.8V regulator */
+ twl4030_reg_write(twl4030, TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP, 0x20);
+ twl4030_reg_write(twl4030, TWL4030_PM_RECEIVER_VUSB1V8_TYPE, 0x00);
+
+ /* disable access to power configuration registers */
+ twl4030_reg_write(twl4030, TWL4030_PM_MASTER_PROTECT_KEY, 0x0 );
+
+ twl4030_reg_write(twl4030, TWL4030_BASEADD_LED, 0x33); /* FIXME *need to enable LED to get USB power? */
+
+}
+
+static void twl4030_phy_power(void)
+{
+ u8 pwr, clk;
+ /* Power the PHY */
+ pwr = twl4030_usb_read(TWL4030_USB_PHY_PWR_CTRL);
+ pwr &= ~PHYPWD;
+ twl4030_usb_write(TWL4030_USB_PHY_PWR_CTRL, pwr);
+ /* Enable clocks */
+ clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL);
+ clk |= CLOCKGATING_EN | CLK32K_EN;
+ twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk);
+}
+
+/*
+ * Initiaze the ULPI interface
+ * ULPI : Universal Transceiver Macrocell Low Pin Interface
+ * An interface between the USB link controller like musb and the
+ * the PHY or transceiver that drives the actual bus.
+ */
+int twl4030_usb_ulpi_init(void)
+{
+ u8 clk, sts, pwr;
+ uint64_t start;
+ long timeout = 1000 * 1000; /* 1 sec */;
+
+ /* power up the twl4030 */
+ twl4030_power_init();
+
+ /* twl4030 ldo init */
+ twl4030_usb_ldo_init();
+
+ /* Enable the twl4030 phy */
+ twl4030_phy_power();
+
+ /* Enable DPLL to access PHY registers over I2C */
+ clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL);
+ clk |= REQ_PHY_DPLL_CLK;
+ twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk);
+
+ /* Check if the PHY DPLL is locked */
+ sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS);
+ start = get_time_ns();
+ while (!(sts & PHY_DPLL_CLK)) {
+ udelay(10);
+ sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS);
+ printf("Error:TWL4030:USB Timeout setting PHY DPLL clock\n");
+ if (is_timeout(start, timeout * USECOND)) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /*
+ * There are two circuit blocks attached to the PHY,
+ * Carkit and USB OTG. Disable Carkit and enable USB OTG
+ */
+ twl4030_usb_write(TWL4030_USB_IFC_CTRL_CLR, CARKITMODE);
+ pwr = twl4030_usb_read(TWL4030_USB_POWER_CTRL);
+ pwr |= OTG_ENAB;
+ twl4030_usb_write(TWL4030_USB_POWER_CTRL_SET, pwr);
+
+ /* Clear the opmode bits to ensure normal encode */
+ twl4030_usb_write(TWL4030_USB_FUNC_CTRL_CLR, OPMODE_MASK);
+
+ /* Clear the xcvrselect bits to enable the high speed transeiver */
+ twl4030_usb_write(TWL4030_USB_FUNC_CTRL_CLR, XCVRSELECT_MASK);
+
+ /* Let ULPI control the DPLL clock */
+ clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL);
+ clk &= ~REQ_PHY_DPLL_CLK;
+ twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk);
+
+ return 0;
+}
diff --git a/include/usb/twl4030.h b/include/usb/twl4030.h
new file mode 100644
index 0000000..66f5156
--- /dev/null
+++ b/include/usb/twl4030.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2010 Michael Grzeschik <mgr@pengutronix.de>
+ * Copyright (C) 2010 Sascha Hauer <sha@pengutronix.de>
+ *
+ * This file is released under the GPLv2
+ *
+ */
+
+#ifndef __USB_TWL4030_H
+#define __USB_TWL4030_H
+
+/* Defines for bits in registers */
+#define OPMODE_MASK (3 << 3)
+#define XCVRSELECT_MASK (3 << 0)
+#define CARKITMODE (1 << 2)
+#define OTG_ENAB (1 << 5)
+#define PHYPWD (1 << 0)
+#define CLOCKGATING_EN (1 << 2)
+#define CLK32K_EN (1 << 1)
+#define REQ_PHY_DPLL_CLK (1 << 0)
+#define PHY_DPLL_CLK (1 << 0)
+
+/*
+ * USB
+ */
+int twl4030_usb_ulpi_init(void);
+
+#endif /* __USB_TWL4030_H */
--
1.7.1
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^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 11/13] ehci: add omap support
2010-08-04 9:59 [PATCH 00/13] OMAP/Beagleboard ehci support Michael Grzeschik
` (9 preceding siblings ...)
2010-08-04 9:59 ` [PATCH 10/13] usb: add twl4030 phy support Michael Grzeschik
@ 2010-08-04 9:59 ` Michael Grzeschik
2010-08-04 9:59 ` [PATCH 12/13] beagle: add usb support Michael Grzeschik
` (2 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Michael Grzeschik @ 2010-08-04 9:59 UTC (permalink / raw)
To: barebox
with cm-regbits-34xx.h and codebase from linux kernel
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
arch/arm/mach-omap/include/mach/cm-regbits-34xx.h | 799 +++++++++++++++++++++
arch/arm/mach-omap/include/mach/ehci.h | 109 +++
arch/arm/mach-omap/include/mach/omap3-clock.h | 11 +
arch/arm/mach-omap/include/mach/omap3-silicon.h | 6 +
drivers/usb/host/Kconfig | 4 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-omap.c | 260 +++++++
7 files changed, 1190 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap/include/mach/cm-regbits-34xx.h
create mode 100644 arch/arm/mach-omap/include/mach/ehci.h
create mode 100644 drivers/usb/host/ehci-omap.c
diff --git a/arch/arm/mach-omap/include/mach/cm-regbits-34xx.h b/arch/arm/mach-omap/include/mach/cm-regbits-34xx.h
new file mode 100644
index 0000000..16a0201
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/cm-regbits-34xx.h
@@ -0,0 +1,799 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
+
+/*
+ * OMAP3430 Clock Management register bits
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* Bits shared between registers */
+
+/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
+#define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
+#define OMAP3430ES2_EN_MMC3_SHIFT 30
+#define OMAP3430_EN_MSPRO_MASK (1 << 23)
+#define OMAP3430_EN_MSPRO_SHIFT 23
+#define OMAP3430_EN_HDQ_MASK (1 << 22)
+#define OMAP3430_EN_HDQ_SHIFT 22
+#define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5)
+#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
+#define OMAP3430ES1_EN_D2D_MASK (1 << 3)
+#define OMAP3430ES1_EN_D2D_SHIFT 3
+#define OMAP3430_EN_SSI_MASK (1 << 0)
+#define OMAP3430_EN_SSI_SHIFT 0
+
+/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
+#define OMAP3430ES2_EN_USBTLL_SHIFT 2
+#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)
+
+/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
+#define OMAP3430_EN_WDT2_MASK (1 << 5)
+#define OMAP3430_EN_WDT2_SHIFT 5
+
+/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
+#define OMAP3430_EN_CAM_MASK (1 << 0)
+#define OMAP3430_EN_CAM_SHIFT 0
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
+#define OMAP3430_EN_WDT3_MASK (1 << 12)
+#define OMAP3430_EN_WDT3_SHIFT 12
+
+/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
+#define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19)
+
+
+/* Bits specific to each register */
+
+/* CM_FCLKEN_IVA2 */
+#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)
+#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
+
+/* CM_CLKEN_PLL_IVA2 */
+#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
+#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)
+#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
+#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
+#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
+#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)
+#define OMAP3430_EN_IVA2_DPLL_SHIFT 0
+#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
+
+/* CM_IDLEST_IVA2 */
+#define OMAP3430_ST_IVA2_MASK (1 << 0)
+
+/* CM_IDLEST_PLL_IVA2 */
+#define OMAP3430_ST_IVA2_CLK_SHIFT 0
+#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
+
+/* CM_AUTOIDLE_PLL_IVA2 */
+#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
+#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
+
+/* CM_CLKSEL1_PLL_IVA2 */
+#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
+#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19)
+#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
+#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
+#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
+#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
+
+/* CM_CLKSEL2_PLL_IVA2 */
+#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
+#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
+
+/* CM_CLKSTCTRL_IVA2 */
+#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
+#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
+
+/* CM_CLKSTST_IVA2 */
+#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0
+#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
+
+/* CM_REVISION specific bits */
+
+/* CM_SYSCONFIG specific bits */
+
+/* CM_CLKEN_PLL_MPU */
+#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8
+#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)
+#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4
+#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
+#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
+#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)
+#define OMAP3430_EN_MPU_DPLL_SHIFT 0
+#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
+
+/* CM_IDLEST_MPU */
+#define OMAP3430_ST_MPU_MASK (1 << 0)
+
+/* CM_IDLEST_PLL_MPU */
+#define OMAP3430_ST_MPU_CLK_SHIFT 0
+#define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
+
+/* CM_AUTOIDLE_PLL_MPU */
+#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
+#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
+
+/* CM_CLKSEL1_PLL_MPU */
+#define OMAP3430_MPU_CLK_SRC_SHIFT 19
+#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19)
+#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
+#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
+#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
+#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
+
+/* CM_CLKSEL2_PLL_MPU */
+#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
+#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
+
+/* CM_CLKSTCTRL_MPU */
+#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
+#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
+
+/* CM_CLKSTST_MPU */
+#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0
+#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)
+
+/* CM_FCLKEN1_CORE specific bits */
+#define OMAP3430_EN_MODEM_MASK (1 << 31)
+#define OMAP3430_EN_MODEM_SHIFT 31
+
+/* CM_ICLKEN1_CORE specific bits */
+#define OMAP3430_EN_ICR_MASK (1 << 29)
+#define OMAP3430_EN_ICR_SHIFT 29
+#define OMAP3430_EN_AES2_MASK (1 << 28)
+#define OMAP3430_EN_AES2_SHIFT 28
+#define OMAP3430_EN_SHA12_MASK (1 << 27)
+#define OMAP3430_EN_SHA12_SHIFT 27
+#define OMAP3430_EN_DES2_MASK (1 << 26)
+#define OMAP3430_EN_DES2_SHIFT 26
+#define OMAP3430ES1_EN_FAC_MASK (1 << 8)
+#define OMAP3430ES1_EN_FAC_SHIFT 8
+#define OMAP3430_EN_MAILBOXES_MASK (1 << 7)
+#define OMAP3430_EN_MAILBOXES_SHIFT 7
+#define OMAP3430_EN_OMAPCTRL_MASK (1 << 6)
+#define OMAP3430_EN_OMAPCTRL_SHIFT 6
+#define OMAP3430_EN_SAD2D_MASK (1 << 3)
+#define OMAP3430_EN_SAD2D_SHIFT 3
+#define OMAP3430_EN_SDRC_MASK (1 << 1)
+#define OMAP3430_EN_SDRC_SHIFT 1
+
+/* AM35XX specific CM_ICLKEN1_CORE bits */
+#define AM35XX_EN_IPSS_MASK (1 << 4)
+#define AM35XX_EN_IPSS_SHIFT 4
+#define AM35XX_EN_UART4_MASK (1 << 23)
+#define AM35XX_EN_UART4_SHIFT 23
+
+/* CM_ICLKEN2_CORE */
+#define OMAP3430_EN_PKA_MASK (1 << 4)
+#define OMAP3430_EN_PKA_SHIFT 4
+#define OMAP3430_EN_AES1_MASK (1 << 3)
+#define OMAP3430_EN_AES1_SHIFT 3
+#define OMAP3430_EN_RNG_MASK (1 << 2)
+#define OMAP3430_EN_RNG_SHIFT 2
+#define OMAP3430_EN_SHA11_MASK (1 << 1)
+#define OMAP3430_EN_SHA11_SHIFT 1
+#define OMAP3430_EN_DES1_MASK (1 << 0)
+#define OMAP3430_EN_DES1_SHIFT 0
+
+/* CM_ICLKEN3_CORE */
+#define OMAP3430_EN_MAD2D_SHIFT 3
+#define OMAP3430_EN_MAD2D_MASK (1 << 3)
+
+/* CM_FCLKEN3_CORE specific bits */
+#define OMAP3430ES2_EN_TS_SHIFT 1
+#define OMAP3430ES2_EN_TS_MASK (1 << 1)
+#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
+#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
+
+/* CM_IDLEST1_CORE specific bits */
+#define OMAP3430ES2_ST_MMC3_SHIFT 30
+#define OMAP3430ES2_ST_MMC3_MASK (1 << 30)
+#define OMAP3430_ST_ICR_SHIFT 29
+#define OMAP3430_ST_ICR_MASK (1 << 29)
+#define OMAP3430_ST_AES2_SHIFT 28
+#define OMAP3430_ST_AES2_MASK (1 << 28)
+#define OMAP3430_ST_SHA12_SHIFT 27
+#define OMAP3430_ST_SHA12_MASK (1 << 27)
+#define OMAP3430_ST_DES2_SHIFT 26
+#define OMAP3430_ST_DES2_MASK (1 << 26)
+#define OMAP3430_ST_MSPRO_SHIFT 23
+#define OMAP3430_ST_MSPRO_MASK (1 << 23)
+#define OMAP3430_ST_HDQ_SHIFT 22
+#define OMAP3430_ST_HDQ_MASK (1 << 22)
+#define OMAP3430ES1_ST_FAC_SHIFT 8
+#define OMAP3430ES1_ST_FAC_MASK (1 << 8)
+#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8
+#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8)
+#define OMAP3430_ST_MAILBOXES_SHIFT 7
+#define OMAP3430_ST_MAILBOXES_MASK (1 << 7)
+#define OMAP3430_ST_OMAPCTRL_SHIFT 6
+#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6)
+#define OMAP3430_ST_SDMA_SHIFT 2
+#define OMAP3430_ST_SDMA_MASK (1 << 2)
+#define OMAP3430_ST_SDRC_SHIFT 1
+#define OMAP3430_ST_SDRC_MASK (1 << 1)
+#define OMAP3430_ST_SSI_STDBY_SHIFT 0
+#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0)
+
+/* AM35xx specific CM_IDLEST1_CORE bits */
+#define AM35XX_ST_IPSS_SHIFT 5
+#define AM35XX_ST_IPSS_MASK (1 << 5)
+
+/* CM_IDLEST2_CORE */
+#define OMAP3430_ST_PKA_SHIFT 4
+#define OMAP3430_ST_PKA_MASK (1 << 4)
+#define OMAP3430_ST_AES1_SHIFT 3
+#define OMAP3430_ST_AES1_MASK (1 << 3)
+#define OMAP3430_ST_RNG_SHIFT 2
+#define OMAP3430_ST_RNG_MASK (1 << 2)
+#define OMAP3430_ST_SHA11_SHIFT 1
+#define OMAP3430_ST_SHA11_MASK (1 << 1)
+#define OMAP3430_ST_DES1_SHIFT 0
+#define OMAP3430_ST_DES1_MASK (1 << 0)
+
+/* CM_IDLEST3_CORE */
+#define OMAP3430ES2_ST_USBTLL_SHIFT 2
+#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)
+#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0
+#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0)
+
+/* CM_AUTOIDLE1_CORE */
+#define OMAP3430_AUTO_MODEM_MASK (1 << 31)
+#define OMAP3430_AUTO_MODEM_SHIFT 31
+#define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30)
+#define OMAP3430ES2_AUTO_MMC3_SHIFT 30
+#define OMAP3430ES2_AUTO_ICR_MASK (1 << 29)
+#define OMAP3430ES2_AUTO_ICR_SHIFT 29
+#define OMAP3430_AUTO_AES2_MASK (1 << 28)
+#define OMAP3430_AUTO_AES2_SHIFT 28
+#define OMAP3430_AUTO_SHA12_MASK (1 << 27)
+#define OMAP3430_AUTO_SHA12_SHIFT 27
+#define OMAP3430_AUTO_DES2_MASK (1 << 26)
+#define OMAP3430_AUTO_DES2_SHIFT 26
+#define OMAP3430_AUTO_MMC2_MASK (1 << 25)
+#define OMAP3430_AUTO_MMC2_SHIFT 25
+#define OMAP3430_AUTO_MMC1_MASK (1 << 24)
+#define OMAP3430_AUTO_MMC1_SHIFT 24
+#define OMAP3430_AUTO_MSPRO_MASK (1 << 23)
+#define OMAP3430_AUTO_MSPRO_SHIFT 23
+#define OMAP3430_AUTO_HDQ_MASK (1 << 22)
+#define OMAP3430_AUTO_HDQ_SHIFT 22
+#define OMAP3430_AUTO_MCSPI4_MASK (1 << 21)
+#define OMAP3430_AUTO_MCSPI4_SHIFT 21
+#define OMAP3430_AUTO_MCSPI3_MASK (1 << 20)
+#define OMAP3430_AUTO_MCSPI3_SHIFT 20
+#define OMAP3430_AUTO_MCSPI2_MASK (1 << 19)
+#define OMAP3430_AUTO_MCSPI2_SHIFT 19
+#define OMAP3430_AUTO_MCSPI1_MASK (1 << 18)
+#define OMAP3430_AUTO_MCSPI1_SHIFT 18
+#define OMAP3430_AUTO_I2C3_MASK (1 << 17)
+#define OMAP3430_AUTO_I2C3_SHIFT 17
+#define OMAP3430_AUTO_I2C2_MASK (1 << 16)
+#define OMAP3430_AUTO_I2C2_SHIFT 16
+#define OMAP3430_AUTO_I2C1_MASK (1 << 15)
+#define OMAP3430_AUTO_I2C1_SHIFT 15
+#define OMAP3430_AUTO_UART2_MASK (1 << 14)
+#define OMAP3430_AUTO_UART2_SHIFT 14
+#define OMAP3430_AUTO_UART1_MASK (1 << 13)
+#define OMAP3430_AUTO_UART1_SHIFT 13
+#define OMAP3430_AUTO_GPT11_MASK (1 << 12)
+#define OMAP3430_AUTO_GPT11_SHIFT 12
+#define OMAP3430_AUTO_GPT10_MASK (1 << 11)
+#define OMAP3430_AUTO_GPT10_SHIFT 11
+#define OMAP3430_AUTO_MCBSP5_MASK (1 << 10)
+#define OMAP3430_AUTO_MCBSP5_SHIFT 10
+#define OMAP3430_AUTO_MCBSP1_MASK (1 << 9)
+#define OMAP3430_AUTO_MCBSP1_SHIFT 9
+#define OMAP3430ES1_AUTO_FAC_MASK (1 << 8)
+#define OMAP3430ES1_AUTO_FAC_SHIFT 8
+#define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7)
+#define OMAP3430_AUTO_MAILBOXES_SHIFT 7
+#define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6)
+#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
+#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5)
+#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
+#define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4)
+#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
+#define OMAP3430ES1_AUTO_D2D_MASK (1 << 3)
+#define OMAP3430ES1_AUTO_D2D_SHIFT 3
+#define OMAP3430_AUTO_SAD2D_MASK (1 << 3)
+#define OMAP3430_AUTO_SAD2D_SHIFT 3
+#define OMAP3430_AUTO_SSI_MASK (1 << 0)
+#define OMAP3430_AUTO_SSI_SHIFT 0
+
+/* CM_AUTOIDLE2_CORE */
+#define OMAP3430_AUTO_PKA_MASK (1 << 4)
+#define OMAP3430_AUTO_PKA_SHIFT 4
+#define OMAP3430_AUTO_AES1_MASK (1 << 3)
+#define OMAP3430_AUTO_AES1_SHIFT 3
+#define OMAP3430_AUTO_RNG_MASK (1 << 2)
+#define OMAP3430_AUTO_RNG_SHIFT 2
+#define OMAP3430_AUTO_SHA11_MASK (1 << 1)
+#define OMAP3430_AUTO_SHA11_SHIFT 1
+#define OMAP3430_AUTO_DES1_MASK (1 << 0)
+#define OMAP3430_AUTO_DES1_SHIFT 0
+
+/* CM_AUTOIDLE3_CORE */
+#define OMAP3430ES2_AUTO_USBHOST (1 << 0)
+#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
+#define OMAP3430ES2_AUTO_USBTLL (1 << 2)
+#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2
+#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)
+#define OMAP3430_AUTO_MAD2D_SHIFT 3
+#define OMAP3430_AUTO_MAD2D_MASK (1 << 3)
+
+/* CM_CLKSEL_CORE */
+#define OMAP3430_CLKSEL_SSI_SHIFT 8
+#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
+#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
+#define OMAP3430_CLKSEL_GPT11_SHIFT 7
+#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
+#define OMAP3430_CLKSEL_GPT10_SHIFT 6
+#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4
+#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
+#define OMAP3430_CLKSEL_L4_SHIFT 2
+#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
+#define OMAP3430_CLKSEL_L3_SHIFT 0
+#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
+#define OMAP3630_CLKSEL_96M_SHIFT 12
+#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12)
+
+/* CM_CLKSTCTRL_CORE */
+#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
+#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
+#define OMAP3430_CLKTRCTRL_L4_SHIFT 2
+#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
+#define OMAP3430_CLKTRCTRL_L3_SHIFT 0
+#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
+
+/* CM_CLKSTST_CORE */
+#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2
+#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)
+#define OMAP3430_CLKACTIVITY_L4_SHIFT 1
+#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)
+#define OMAP3430_CLKACTIVITY_L3_SHIFT 0
+#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)
+
+/* CM_FCLKEN_GFX */
+#define OMAP3430ES1_EN_3D_MASK (1 << 2)
+#define OMAP3430ES1_EN_3D_SHIFT 2
+#define OMAP3430ES1_EN_2D_MASK (1 << 1)
+#define OMAP3430ES1_EN_2D_SHIFT 1
+
+/* CM_ICLKEN_GFX specific bits */
+
+/* CM_IDLEST_GFX specific bits */
+
+/* CM_CLKSEL_GFX specific bits */
+
+/* CM_SLEEPDEP_GFX specific bits */
+
+/* CM_CLKSTCTRL_GFX */
+#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0
+#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
+
+/* CM_CLKSTST_GFX */
+#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0
+#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)
+
+/* CM_FCLKEN_SGX */
+#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1
+#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1)
+
+/* CM_IDLEST_SGX */
+#define OMAP3430ES2_ST_SGX_SHIFT 1
+#define OMAP3430ES2_ST_SGX_MASK (1 << 1)
+
+/* CM_ICLKEN_SGX */
+#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0
+#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0)
+
+/* CM_CLKSEL_SGX */
+#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
+#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
+
+/* CM_CLKSTCTRL_SGX */
+#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0
+#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
+
+/* CM_CLKSTST_SGX */
+#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0
+#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)
+
+/* CM_FCLKEN_WKUP specific bits */
+#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
+#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9)
+
+/* CM_ICLKEN_WKUP specific bits */
+#define OMAP3430_EN_WDT1_MASK (1 << 4)
+#define OMAP3430_EN_WDT1_SHIFT 4
+#define OMAP3430_EN_32KSYNC_MASK (1 << 2)
+#define OMAP3430_EN_32KSYNC_SHIFT 2
+
+/* CM_IDLEST_WKUP specific bits */
+#define OMAP3430ES2_ST_USIMOCP_SHIFT 9
+#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9)
+#define OMAP3430_ST_WDT2_SHIFT 5
+#define OMAP3430_ST_WDT2_MASK (1 << 5)
+#define OMAP3430_ST_WDT1_SHIFT 4
+#define OMAP3430_ST_WDT1_MASK (1 << 4)
+#define OMAP3430_ST_32KSYNC_SHIFT 2
+#define OMAP3430_ST_32KSYNC_MASK (1 << 2)
+
+/* CM_AUTOIDLE_WKUP */
+#define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9)
+#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9
+#define OMAP3430_AUTO_WDT2_MASK (1 << 5)
+#define OMAP3430_AUTO_WDT2_SHIFT 5
+#define OMAP3430_AUTO_WDT1_MASK (1 << 4)
+#define OMAP3430_AUTO_WDT1_SHIFT 4
+#define OMAP3430_AUTO_GPIO1_MASK (1 << 3)
+#define OMAP3430_AUTO_GPIO1_SHIFT 3
+#define OMAP3430_AUTO_32KSYNC_MASK (1 << 2)
+#define OMAP3430_AUTO_32KSYNC_SHIFT 2
+#define OMAP3430_AUTO_GPT12_MASK (1 << 1)
+#define OMAP3430_AUTO_GPT12_SHIFT 1
+#define OMAP3430_AUTO_GPT1_MASK (1 << 0)
+#define OMAP3430_AUTO_GPT1_SHIFT 0
+
+/* CM_CLKSEL_WKUP */
+#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
+#define OMAP3430_CLKSEL_RM_SHIFT 1
+#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
+#define OMAP3430_CLKSEL_GPT1_SHIFT 0
+#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
+
+/* CM_CLKEN_PLL */
+#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
+#define OMAP3430_PWRDN_CAM_SHIFT 30
+#define OMAP3430_PWRDN_DSS1_SHIFT 29
+#define OMAP3430_PWRDN_TV_SHIFT 28
+#define OMAP3430_PWRDN_96M_SHIFT 27
+#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24
+#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)
+#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20
+#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
+#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
+#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)
+#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16
+#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
+#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
+#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8
+#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)
+#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4
+#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
+#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
+#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)
+#define OMAP3430_EN_CORE_DPLL_SHIFT 0
+#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
+
+/* CM_CLKEN2_PLL */
+#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10
+#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)
+#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4
+#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
+#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
+#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0
+#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
+
+/* CM_IDLEST_CKGEN */
+#define OMAP3430_ST_54M_CLK_MASK (1 << 5)
+#define OMAP3430_ST_12M_CLK_MASK (1 << 4)
+#define OMAP3430_ST_48M_CLK_MASK (1 << 3)
+#define OMAP3430_ST_96M_CLK_MASK (1 << 2)
+#define OMAP3430_ST_PERIPH_CLK_SHIFT 1
+#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)
+#define OMAP3430_ST_CORE_CLK_SHIFT 0
+#define OMAP3430_ST_CORE_CLK_MASK (1 << 0)
+
+/* CM_IDLEST2_CKGEN */
+#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2
+#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2)
+#define OMAP3430ES2_ST_120M_CLK_SHIFT 1
+#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)
+#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0
+#define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)
+
+/* CM_AUTOIDLE_PLL */
+#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3
+#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
+#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0
+#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
+
+/* CM_AUTOIDLE2_PLL */
+#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0
+#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0)
+
+/* CM_CLKSEL1_PLL */
+/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
+#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
+#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
+#define OMAP3430_CORE_DPLL_MULT_SHIFT 16
+#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
+#define OMAP3430_CORE_DPLL_DIV_SHIFT 8
+#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
+#define OMAP3430_SOURCE_96M_SHIFT 6
+#define OMAP3430_SOURCE_96M_MASK (1 << 6)
+#define OMAP3430_SOURCE_54M_SHIFT 5
+#define OMAP3430_SOURCE_54M_MASK (1 << 5)
+#define OMAP3430_SOURCE_48M_SHIFT 3
+#define OMAP3430_SOURCE_48M_MASK (1 << 3)
+
+/* CM_CLKSEL2_PLL */
+#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
+#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
+#define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8)
+#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0
+#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
+#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21
+#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21)
+#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24
+#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24)
+
+/* CM_CLKSEL3_PLL */
+#define OMAP3430_DIV_96M_SHIFT 0
+#define OMAP3430_DIV_96M_MASK (0x1f << 0)
+#define OMAP3630_DIV_96M_MASK (0x3f << 0)
+
+/* CM_CLKSEL4_PLL */
+#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
+#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
+#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0
+#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
+
+/* CM_CLKSEL5_PLL */
+#define OMAP3430ES2_DIV_120M_SHIFT 0
+#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
+
+/* CM_CLKOUT_CTRL */
+#define OMAP3430_CLKOUT2_EN_SHIFT 7
+#define OMAP3430_CLKOUT2_EN_MASK (1 << 7)
+#define OMAP3430_CLKOUT2_DIV_SHIFT 3
+#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
+#define OMAP3430_CLKOUT2SOURCE_SHIFT 0
+#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
+
+/* CM_FCLKEN_DSS */
+#define OMAP3430_EN_TV_MASK (1 << 2)
+#define OMAP3430_EN_TV_SHIFT 2
+#define OMAP3430_EN_DSS2_MASK (1 << 1)
+#define OMAP3430_EN_DSS2_SHIFT 1
+#define OMAP3430_EN_DSS1_MASK (1 << 0)
+#define OMAP3430_EN_DSS1_SHIFT 0
+
+/* CM_ICLKEN_DSS */
+#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0)
+#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
+
+/* CM_IDLEST_DSS */
+#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1
+#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1)
+#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0
+#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0)
+#define OMAP3430ES1_ST_DSS_SHIFT 0
+#define OMAP3430ES1_ST_DSS_MASK (1 << 0)
+
+/* CM_AUTOIDLE_DSS */
+#define OMAP3430_AUTO_DSS_MASK (1 << 0)
+#define OMAP3430_AUTO_DSS_SHIFT 0
+
+/* CM_CLKSEL_DSS */
+#define OMAP3430_CLKSEL_TV_SHIFT 8
+#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
+#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8)
+#define OMAP3430_CLKSEL_DSS1_SHIFT 0
+#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
+#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0)
+
+/* CM_SLEEPDEP_DSS specific bits */
+
+/* CM_CLKSTCTRL_DSS */
+#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0
+#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
+
+/* CM_CLKSTST_DSS */
+#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0
+#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
+
+/* CM_FCLKEN_CAM specific bits */
+#define OMAP3430_EN_CSI2_MASK (1 << 1)
+#define OMAP3430_EN_CSI2_SHIFT 1
+
+/* CM_ICLKEN_CAM specific bits */
+
+/* CM_IDLEST_CAM */
+#define OMAP3430_ST_CAM_MASK (1 << 0)
+
+/* CM_AUTOIDLE_CAM */
+#define OMAP3430_AUTO_CAM_MASK (1 << 0)
+#define OMAP3430_AUTO_CAM_SHIFT 0
+
+/* CM_CLKSEL_CAM */
+#define OMAP3430_CLKSEL_CAM_SHIFT 0
+#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
+#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0)
+
+/* CM_SLEEPDEP_CAM specific bits */
+
+/* CM_CLKSTCTRL_CAM */
+#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0
+#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
+
+/* CM_CLKSTST_CAM */
+#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0
+#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)
+
+/* CM_FCLKEN_PER specific bits */
+
+/* CM_ICLKEN_PER specific bits */
+
+/* CM_IDLEST_PER */
+#define OMAP3430_ST_WDT3_SHIFT 12
+#define OMAP3430_ST_WDT3_MASK (1 << 12)
+#define OMAP3430_ST_MCBSP4_SHIFT 2
+#define OMAP3430_ST_MCBSP4_MASK (1 << 2)
+#define OMAP3430_ST_MCBSP3_SHIFT 1
+#define OMAP3430_ST_MCBSP3_MASK (1 << 1)
+#define OMAP3430_ST_MCBSP2_SHIFT 0
+#define OMAP3430_ST_MCBSP2_MASK (1 << 0)
+
+/* CM_AUTOIDLE_PER */
+#define OMAP3430_AUTO_GPIO6_MASK (1 << 17)
+#define OMAP3430_AUTO_GPIO6_SHIFT 17
+#define OMAP3430_AUTO_GPIO5_MASK (1 << 16)
+#define OMAP3430_AUTO_GPIO5_SHIFT 16
+#define OMAP3430_AUTO_GPIO4_MASK (1 << 15)
+#define OMAP3430_AUTO_GPIO4_SHIFT 15
+#define OMAP3430_AUTO_GPIO3_MASK (1 << 14)
+#define OMAP3430_AUTO_GPIO3_SHIFT 14
+#define OMAP3430_AUTO_GPIO2_MASK (1 << 13)
+#define OMAP3430_AUTO_GPIO2_SHIFT 13
+#define OMAP3430_AUTO_WDT3_MASK (1 << 12)
+#define OMAP3430_AUTO_WDT3_SHIFT 12
+#define OMAP3430_AUTO_UART3_MASK (1 << 11)
+#define OMAP3430_AUTO_UART3_SHIFT 11
+#define OMAP3430_AUTO_GPT9_MASK (1 << 10)
+#define OMAP3430_AUTO_GPT9_SHIFT 10
+#define OMAP3430_AUTO_GPT8_MASK (1 << 9)
+#define OMAP3430_AUTO_GPT8_SHIFT 9
+#define OMAP3430_AUTO_GPT7_MASK (1 << 8)
+#define OMAP3430_AUTO_GPT7_SHIFT 8
+#define OMAP3430_AUTO_GPT6_MASK (1 << 7)
+#define OMAP3430_AUTO_GPT6_SHIFT 7
+#define OMAP3430_AUTO_GPT5_MASK (1 << 6)
+#define OMAP3430_AUTO_GPT5_SHIFT 6
+#define OMAP3430_AUTO_GPT4_MASK (1 << 5)
+#define OMAP3430_AUTO_GPT4_SHIFT 5
+#define OMAP3430_AUTO_GPT3_MASK (1 << 4)
+#define OMAP3430_AUTO_GPT3_SHIFT 4
+#define OMAP3430_AUTO_GPT2_MASK (1 << 3)
+#define OMAP3430_AUTO_GPT2_SHIFT 3
+#define OMAP3430_AUTO_MCBSP4_MASK (1 << 2)
+#define OMAP3430_AUTO_MCBSP4_SHIFT 2
+#define OMAP3430_AUTO_MCBSP3_MASK (1 << 1)
+#define OMAP3430_AUTO_MCBSP3_SHIFT 1
+#define OMAP3430_AUTO_MCBSP2_MASK (1 << 0)
+#define OMAP3430_AUTO_MCBSP2_SHIFT 0
+
+/* CM_CLKSEL_PER */
+#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
+#define OMAP3430_CLKSEL_GPT9_SHIFT 7
+#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
+#define OMAP3430_CLKSEL_GPT8_SHIFT 6
+#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
+#define OMAP3430_CLKSEL_GPT7_SHIFT 5
+#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
+#define OMAP3430_CLKSEL_GPT6_SHIFT 4
+#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
+#define OMAP3430_CLKSEL_GPT5_SHIFT 3
+#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
+#define OMAP3430_CLKSEL_GPT4_SHIFT 2
+#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
+#define OMAP3430_CLKSEL_GPT3_SHIFT 1
+#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
+#define OMAP3430_CLKSEL_GPT2_SHIFT 0
+
+/* CM_SLEEPDEP_PER specific bits */
+#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2)
+
+/* CM_CLKSTCTRL_PER */
+#define OMAP3430_CLKTRCTRL_PER_SHIFT 0
+#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
+
+/* CM_CLKSTST_PER */
+#define OMAP3430_CLKACTIVITY_PER_SHIFT 0
+#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)
+
+/* CM_CLKSEL1_EMU */
+#define OMAP3430_DIV_DPLL4_SHIFT 24
+#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
+#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24)
+#define OMAP3430_DIV_DPLL3_SHIFT 16
+#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
+#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
+#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
+#define OMAP3430_CLKSEL_PCLK_SHIFT 8
+#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
+#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
+#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
+#define OMAP3430_CLKSEL_ATCLK_SHIFT 4
+#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
+#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
+#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
+#define OMAP3430_MUX_CTRL_SHIFT 0
+#define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
+
+/* CM_CLKSTCTRL_EMU */
+#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
+#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
+
+/* CM_CLKSTST_EMU */
+#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0
+#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)
+
+/* CM_CLKSEL2_EMU specific bits */
+#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
+#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
+#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0
+#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
+
+/* CM_CLKSEL3_EMU specific bits */
+#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8
+#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)
+#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0
+#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)
+
+/* CM_POLCTRL */
+#define OMAP3430_CLKOUT2_POL_MASK (1 << 0)
+
+/* CM_IDLEST_NEON */
+#define OMAP3430_ST_NEON_MASK (1 << 0)
+
+/* CM_CLKSTCTRL_NEON */
+#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0
+#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
+
+/* CM_FCLKEN_USBHOST */
+#define OMAP3430ES2_EN_USBHOST2_SHIFT 1
+#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)
+#define OMAP3430ES2_EN_USBHOST1_SHIFT 0
+#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)
+
+/* CM_ICLKEN_USBHOST */
+#define OMAP3430ES2_EN_USBHOST_SHIFT 0
+#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
+
+/* CM_IDLEST_USBHOST */
+#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1
+#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1)
+#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0
+#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0)
+
+/* CM_AUTOIDLE_USBHOST */
+#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
+#define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0)
+
+/* CM_SLEEPDEP_USBHOST */
+#define OMAP3430ES2_EN_MPU_SHIFT 1
+#define OMAP3430ES2_EN_MPU_MASK (1 << 1)
+#define OMAP3430ES2_EN_IVA2_SHIFT 2
+#define OMAP3430ES2_EN_IVA2_MASK (1 << 2)
+
+/* CM_CLKSTCTRL_USBHOST */
+#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
+#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
+
+/* CM_CLKSTST_USBHOST */
+#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0
+#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)
+
+#endif
diff --git a/arch/arm/mach-omap/include/mach/ehci.h b/arch/arm/mach-omap/include/mach/ehci.h
new file mode 100644
index 0000000..cccb9ad
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/ehci.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2010 Michael Grzeschik <mgr@pengutronix.de>
+ *
+ * This file is released under the GPLv2
+ *
+ */
+
+#ifndef __OMAP_EHCI_H
+#define __OMAP_EHCI_H
+
+/* TLL Register Set */
+#define OMAP_USBTLL_REVISION (0x00)
+#define OMAP_USBTLL_SYSCONFIG (0x10)
+#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
+#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
+#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
+#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
+#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
+
+#define OMAP_USBTLL_SYSSTATUS (0x14)
+#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
+
+#define OMAP_USBTLL_IRQSTATUS (0x18)
+#define OMAP_USBTLL_IRQENABLE (0x1C)
+
+#define OMAP_TLL_SHARED_CONF (0x30)
+#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
+#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
+#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
+#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
+#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
+
+#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
+#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
+#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
+#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
+#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
+#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
+
+#define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
+#define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
+#define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
+#define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
+#define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
+#define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
+#define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
+#define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
+#define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
+
+#define OMAP_TLL_CHANNEL_COUNT 3
+#define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 1)
+#define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 2)
+#define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 4)
+
+/* UHH Register Set */
+#define OMAP_UHH_REVISION (0x00)
+#define OMAP_UHH_SYSCONFIG (0x10)
+#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
+#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
+#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
+#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
+#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
+#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
+
+#define OMAP_UHH_SYSSTATUS (0x14)
+#define OMAP_UHH_HOSTCONFIG (0x40)
+#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
+#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
+#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
+#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
+#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
+#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
+#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
+#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
+#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
+#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
+#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
+
+#define OMAP_UHH_DEBUG_CSR (0x44)
+
+/* EHCI Register Set */
+#define EHCI_INSNREG05_ULPI (0xA4)
+#define EHCI_INSNREG05_ULPI_CONTROL_SHIFT 31
+#define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT 24
+#define EHCI_INSNREG05_ULPI_OPSEL_SHIFT 22
+#define EHCI_INSNREG05_ULPI_REGADD_SHIFT 16
+#define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT 8
+#define EHCI_INSNREG05_ULPI_WRDATA_SHIFT 0
+
+#define OMAP3_HS_USB_PORTS 3
+
+enum ehci_hcd_omap_mode {
+ EHCI_HCD_OMAP_MODE_UNKNOWN,
+ EHCI_HCD_OMAP_MODE_PHY,
+ EHCI_HCD_OMAP_MODE_TLL,
+};
+
+struct omap_hcd {
+ enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
+ unsigned phy_reset:1;
+
+ /* have to be valid if phy_reset is true and portx is in phy mode */
+ int reset_gpio_port[OMAP3_HS_USB_PORTS];
+};
+
+void omap_usb_utmi_init(struct omap_hcd *omap, u8 tll_channel_mask);
+int ehci_omap_init(struct omap_hcd *omap);
+
+#endif /* __OMAP_EHCI_H */
diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h
index 22694f2..b655fe3 100644
--- a/arch/arm/mach-omap/include/mach/omap3-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap3-clock.h
@@ -43,8 +43,11 @@
#define CM_CLKSEL1_PLL_MPU 0X0940
#define CM_CLKSEL2_PLL_MPU 0X0944
#define CM_FCLKEN1_CORE 0X0A00
+#define CM_FCLKEN3_CORE 0X0A08
#define CM_ICLKEN1_CORE 0X0A10
#define CM_ICLKEN2_CORE 0X0A14
+#define CM_ICLKEN3_CORE 0X0A18
+#define CM_AIDLE3_CORE 0X0A38
#define CM_CLKSEL_CORE 0X0A40
#define CM_FCLKEN_GFX 0X0B00
#define CM_ICLKEN_GFX 0X0B10
@@ -54,10 +57,13 @@
#define CM_CLKSEL_WKUP 0X0C40
#define CM_IDLEST_WKUP 0X0C20
#define CM_CLKEN_PLL 0X0D00
+#define CM_CLKEN2_PLL 0X0D04
#define CM_IDLEST_CKGEN 0X0D20
#define CM_CLKSEL1_PLL 0X0D40
#define CM_CLKSEL2_PLL 0X0D44
#define CM_CLKSEL3_PLL 0X0D48
+#define CM_CLKSEL4_PLL 0X0D4C
+#define CM_CLKSEL5_PLL 0X0D50
#define CM_FCLKEN_DSS 0X0E00
#define CM_ICLKEN_DSS 0X0E10
#define CM_CLKSEL_DSS 0X0E40
@@ -68,6 +74,11 @@
#define CM_ICLKEN_PER 0X1010
#define CM_CLKSEL_PER 0X1040
#define CM_CLKSEL1_EMU 0X1140
+#define CM_FCLKEN_USBH 0x1400
+#define CM_ICLKEN_USBH 0x1410
+#define CM_AIDLE_USBH 0x1430
+#define CM_SLEEPD_USBH 0x1444
+#define CM_CLKSTCTRL_USBH 0x1448
/** PRM Clock Regs */
#define PRM_REG(REGNAME) (OMAP_PRM_BASE + PRM_##REGNAME)
diff --git a/arch/arm/mach-omap/include/mach/omap3-silicon.h b/arch/arm/mach-omap/include/mach/omap3-silicon.h
index dde2412..62e612b 100644
--- a/arch/arm/mach-omap/include/mach/omap3-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap3-silicon.h
@@ -100,6 +100,12 @@
/** MPU WDT Definition */
#define OMAP_MPU_WDTIMER_BASE OMAP_WDTIMER2_BASE
+#define OMAP_HSUSB_OTG_BASE (OMAP_L4_CORE_BASE + 0xAB000)
+#define OMAP_USBTLL_BASE (OMAP_L4_CORE_BASE + 0x62000)
+#define OMAP_UHH_CONFIG_BASE (OMAP_L4_CORE_BASE + 0x64000)
+#define OMAP_OHCI_BASE (OMAP_L4_CORE_BASE + 0x64400)
+#define OMAP_EHCI_BASE (OMAP_L4_CORE_BASE + 0x64800)
+
/** Interrupt Vector base address */
#define OMAP_SRAM_INTVECT 0x4020F800
#define OMAP_SRAM_INTVECT_COPYSIZE 0x64
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index e1549e8..145f7d1 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -1,2 +1,6 @@
config USB_EHCI
bool "EHCI driver"
+
+config USB_EHCI_OMAP
+ depends on ARCH_OMAP3
+ bool "OMAP EHCI driver"
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 6c48e3a..a334b08 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_USB_EHCI) += ehci-hcd.o
+obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
new file mode 100644
index 0000000..0c30c52
--- /dev/null
+++ b/drivers/usb/host/ehci-omap.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2010 Michael Grzeschik <mgr@pengutronix.de>
+ *
+ * This file is released under the GPLv2
+ *
+ */
+
+/*
+ * OMAP USBHOST Register addresses: VIRTUAL ADDRESSES
+ */
+
+/*-------------------------------------------------------------------------*/
+
+#include <i2c/twl4030.h>
+#include <usb/twl4030.h>
+#include <mach/ehci.h>
+#include <common.h>
+#include <asm/io.h>
+#include <clock.h>
+#include <gpio.h>
+#include <mach/omap3-silicon.h>
+#include <mach/omap3-clock.h>
+#include <mach/cm-regbits-34xx.h>
+#include <mach/sys_info.h>
+
+void omap_usb_utmi_init(struct omap_hcd *omap, u8 tll_channel_mask)
+{
+ unsigned reg;
+ int i;
+
+ /* Program the 3 TLL channels upfront */
+ for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
+ reg = __raw_readl(OMAP_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
+
+ /* Disable AutoIdle, BitStuffing and use SDR Mode */
+ reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
+ | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
+ | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
+ __raw_writel(reg, OMAP_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
+ }
+
+ /* Program Common TLL register */
+ reg = __raw_readl(OMAP_USBTLL_BASE + OMAP_TLL_SHARED_CONF);
+ reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
+ | OMAP_TLL_SHARED_CONF_USB_DIVRATION
+ | OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN);
+ reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
+
+ __raw_writel(reg, OMAP_USBTLL_BASE + OMAP_TLL_SHARED_CONF);
+
+ /* Enable channels now */
+ for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
+ reg = __raw_readl(OMAP_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
+
+ /* Enable only the reg that is needed */
+ if (!(tll_channel_mask & 1<<i))
+ continue;
+
+ reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
+ __raw_writel(reg, OMAP_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
+
+ __raw_writeb(0xbe,
+ OMAP_USBTLL_BASE + OMAP_TLL_ULPI_SCRATCH_REGISTER(i));
+ }
+}
+
+int ehci_omap_init(struct omap_hcd *omap)
+{
+ uint64_t start;
+ int timeout = 1000;
+ u8 tll_ch_mask = 0;
+ u32 v = 0;
+
+ if (twl4030_usb_ulpi_init()) {
+ printf("ERROR: %s Could not initialize PHY\n",
+ __PRETTY_FUNCTION__);
+ return -EINVAL;
+ }
+
+
+ v = __raw_readl(CM_REG(CLKSEL4_PLL));
+ v |= (12 << OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT);
+ v |= (120 << OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT);
+ __raw_writel(v, CM_REG(CLKSEL4_PLL));
+
+ v = __raw_readl(CM_REG(CLKSEL5_PLL));
+ v |= (1 << OMAP3430ES2_DIV_120M_SHIFT);
+ __raw_writel(v, CM_REG(CLKSEL5_PLL));
+
+ v = __raw_readl(CM_REG(CLKEN2_PLL));
+ v |= (7 << OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT);
+ v |= (7 << OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT);
+ __raw_writel(v, CM_REG(CLKEN2_PLL));
+
+ /* PRCM settings for USBHOST:
+ * Interface clk un-related to domain transition
+ */
+
+ v = __raw_readl(CM_REG(AIDLE_USBH));
+ v |= (0 << OMAP3430ES2_AUTO_USBHOST_SHIFT);
+ __raw_writel(v, CM_REG(AIDLE_USBH));
+
+ /* Disable sleep dependency with MPU and IVA */
+
+ v = __raw_readl(CM_REG(SLEEPD_USBH));
+ v |= (0 << OMAP3430ES2_EN_MPU_SHIFT);
+ v |= (0 << OMAP3430ES2_EN_IVA2_SHIFT);
+ __raw_writel(v, CM_REG(SLEEPD_USBH));
+
+ /* Disable Automatic transition of clock */
+ v = __raw_readl(CM_REG(CLKSTCTRL_USBH));
+ v |= (0 << OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT);
+ __raw_writel(v, CM_REG(CLKSTCTRL_USBH));
+
+ /* Enable Clocks for USBHOST */
+
+ /* enable usbhost_ick */
+ v = __raw_readl(CM_REG(ICLKEN_USBH));
+ v |= (1 << OMAP3430ES2_EN_USBHOST_SHIFT);
+ __raw_writel(v, CM_REG(ICLKEN_USBH));
+
+ /* enable usbhost_120m_fck */
+ v = __raw_readl(CM_REG(FCLKEN_USBH));
+ v |= (1 << OMAP3430ES2_EN_USBHOST2_SHIFT);
+ __raw_writel(v, CM_REG(FCLKEN_USBH));
+
+ /* enable usbhost_48m_fck */
+ v = __raw_readl(CM_REG(FCLKEN_USBH));
+ v |= (1 << OMAP3430ES2_EN_USBHOST1_SHIFT);
+ __raw_writel(v, CM_REG(FCLKEN_USBH));
+
+ if (omap->phy_reset) {
+ /* Refer: ISSUE1 */
+ if (omap->reset_gpio_port[0] != -EINVAL) {
+ gpio_direction_output(omap->reset_gpio_port[0], 0);
+ }
+
+ if (omap->reset_gpio_port[1] != -EINVAL) {
+ gpio_direction_output(omap->reset_gpio_port[1], 0);
+ }
+
+ /* Hold the PHY in RESET for enough time till DIR is high */
+ mdelay(10);
+ }
+
+ /* enable usbtll_fck */
+ v = __raw_readl(CM_REG(FCLKEN3_CORE));
+ v |= (1 << OMAP3430ES2_EN_USBTLL_SHIFT);
+ __raw_writel(v, CM_REG(FCLKEN3_CORE));
+
+ /* Configure TLL for 60Mhz clk for ULPI */
+ /* enable usbtll_ick */
+ v = __raw_readl(CM_REG(ICLKEN3_CORE));
+ v |= (1 << OMAP3430ES2_EN_USBTLL_SHIFT);
+ __raw_writel(v, CM_REG(ICLKEN3_CORE));
+
+ v = __raw_readl(CM_REG(AIDLE3_CORE));
+ v |= (0 << OMAP3430ES2_AUTO_USBTLL_SHIFT);
+ __raw_writel(v, CM_REG(AIDLE3_CORE));
+
+ /* perform TLL soft reset, and wait until reset is complete */
+ __raw_writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,
+ OMAP_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
+
+ /* Wait for TLL reset to complete */
+ start = get_time_ns();
+
+ while (!(__raw_readl(OMAP_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)
+ & OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
+ if (is_timeout(start, timeout * USECOND)) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* (1<<3) = no idle mode only for initial debugging */
+ __raw_writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
+ OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
+ OMAP_USBTLL_SYSCONFIG_CACTIVITY, OMAP_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
+
+ /* Put UHH in NoIdle/NoStandby mode */
+ v = __raw_readl(OMAP_UHH_CONFIG_BASE + OMAP_UHH_SYSCONFIG);
+ v |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
+ | OMAP_UHH_SYSCONFIG_SIDLEMODE
+ | OMAP_UHH_SYSCONFIG_CACTIVITY
+ | OMAP_UHH_SYSCONFIG_MIDLEMODE);
+ v &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
+ __raw_writel(v, OMAP_UHH_CONFIG_BASE + OMAP_UHH_SYSCONFIG);
+
+ v = __raw_readl(OMAP_UHH_CONFIG_BASE + OMAP_UHH_HOSTCONFIG);
+ /* setup ULPI bypass and burst configurations */
+ v |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
+ | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
+ | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
+ v &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
+
+ if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
+ v &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
+ if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
+ v &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
+ if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
+ v &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
+
+ /* Bypass the TLL module for PHY mode operation */
+ if (get_cpu_rev() <= CPU_ES2P1) {
+ if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) ||
+ (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) ||
+ (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY))
+ v &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
+ else
+ v |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
+ } else {
+ if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY)
+ v &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
+ else if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
+ v |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
+
+ if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY)
+ v &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
+ else if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
+ v |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
+
+ if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY)
+ v &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
+ else if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
+ v |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
+
+ }
+ __raw_writel(v, OMAP_UHH_CONFIG_BASE + OMAP_UHH_HOSTCONFIG);
+
+ if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) ||
+ (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) ||
+ (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) {
+
+ if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
+ tll_ch_mask |= OMAP_TLL_CHANNEL_1_EN_MASK;
+ if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
+ tll_ch_mask |= OMAP_TLL_CHANNEL_2_EN_MASK;
+ if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
+ tll_ch_mask |= OMAP_TLL_CHANNEL_3_EN_MASK;
+
+ /* Enable UTMI mode for required TLL channels */
+ omap_usb_utmi_init(omap, tll_ch_mask);
+ }
+
+ if (omap->phy_reset) {
+ /* Refer ISSUE1:
+ * Hold the PHY in RESET for enough time till
+ * PHY is settled and ready
+ */
+ udelay(10);
+
+ if (omap->reset_gpio_port[0] != -EINVAL)
+ gpio_direction_output(omap->reset_gpio_port[0], 1);
+
+ if (omap->reset_gpio_port[1] != -EINVAL)
+ gpio_direction_output(omap->reset_gpio_port[1], 1);
+ }
+
+ return 0;
+}
--
1.7.1
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^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 12/13] beagle: add usb support
2010-08-04 9:59 [PATCH 00/13] OMAP/Beagleboard ehci support Michael Grzeschik
` (10 preceding siblings ...)
2010-08-04 9:59 ` [PATCH 11/13] ehci: add omap support Michael Grzeschik
@ 2010-08-04 9:59 ` Michael Grzeschik
2010-08-17 8:40 ` [PATCH] beagle: fix usb dependencies Michael Grzeschik
2010-08-04 9:59 ` [PATCH 13/13] add beagle board defconfig Michael Grzeschik
2010-10-10 8:37 ` [PATCH 00/13] OMAP/Beagleboard ehci support Anand Gadiyar
13 siblings, 1 reply; 18+ messages in thread
From: Michael Grzeschik @ 2010-08-04 9:59 UTC (permalink / raw)
To: barebox
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
arch/arm/boards/omap/Kconfig | 2 +
arch/arm/boards/omap/board-beagle.c | 44 +++++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boards/omap/Kconfig b/arch/arm/boards/omap/Kconfig
index d612064..6012227 100644
--- a/arch/arm/boards/omap/Kconfig
+++ b/arch/arm/boards/omap/Kconfig
@@ -48,6 +48,8 @@ config MACH_BEAGLE
select MACH_HAS_LOWLEVEL_INIT
select OMAP_CLOCK_ALL
select HAS_OMAP_NAND
+ select USB_EHCI_OMAP
+ select USB_TWL4030
help
Say Y here if you are using Beagle Board
diff --git a/arch/arm/boards/omap/board-beagle.c b/arch/arm/boards/omap/board-beagle.c
index 01c6cd2..c0b6b43 100644
--- a/arch/arm/boards/omap/board-beagle.c
+++ b/arch/arm/boards/omap/board-beagle.c
@@ -59,6 +59,7 @@
#include <asm/io.h>
#include <ns16550.h>
#include <asm/armlinux.h>
+#include <asm/mach-types.h>
#include <mach/silicon.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
@@ -67,6 +68,10 @@
#include <mach/omap3-mux.h>
#include <mach/gpmc.h>
#include <mach/gpmc_nand.h>
+#include <mach/ehci.h>
+#include <i2c/i2c.h>
+#include <linux/err.h>
+#include <usb/ehci.h>
#include "board.h"
/******************** Board Boot Time *******************/
@@ -268,6 +273,40 @@ static struct device_d sdram_dev = {
.platform_data = &sram_pdata,
};
+static struct omap_hcd omap_ehci_pdata = {
+ .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
+ .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+ .phy_reset = 1,
+ .reset_gpio_port[0] = -EINVAL,
+ .reset_gpio_port[1] = 147,
+ .reset_gpio_port[2] = -EINVAL
+};
+
+static struct ehci_platform_data ehci_pdata = {
+ .flags = 0,
+ .hccr_offset = 0x100,
+ .hcor_offset = 0x110,
+};
+
+static struct device_d usbh_dev = {
+ .name = "ehci",
+ .map_base = 0x48064700,
+ .size = 4 * 1024,
+ .platform_data = &ehci_pdata,
+};
+
+static struct device_d i2c_dev = {
+ .name = "i2c-omap",
+ .map_base = OMAP_I2C1_BASE,
+};
+
+static struct i2c_board_info i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("twl4030", 0x48),
+ },
+};
+
static int beagle_devices_init(void)
{
int ret;
@@ -276,6 +315,11 @@ static int beagle_devices_init(void)
if (ret)
goto failed;
+ i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
+ register_device(&i2c_dev);
+
+ if (ehci_omap_init(&omap_ehci_pdata) >= 0)
+ register_device(&usbh_dev);
#ifdef CONFIG_GPMC
/* WP is made high and WAIT1 active Low */
gpmc_generic_init(0x10);
--
1.7.1
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^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH] beagle: fix usb dependencies
2010-08-04 9:59 ` [PATCH 12/13] beagle: add usb support Michael Grzeschik
@ 2010-08-17 8:40 ` Michael Grzeschik
2010-08-17 10:09 ` Nishanth Menon
0 siblings, 1 reply; 18+ messages in thread
From: Michael Grzeschik @ 2010-08-17 8:40 UTC (permalink / raw)
To: barebox
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
arch/arm/boards/omap/Kconfig | 2 --
arch/arm/boards/omap/board-beagle.c | 4 ++++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boards/omap/Kconfig b/arch/arm/boards/omap/Kconfig
index 6012227..d612064 100644
--- a/arch/arm/boards/omap/Kconfig
+++ b/arch/arm/boards/omap/Kconfig
@@ -48,8 +48,6 @@ config MACH_BEAGLE
select MACH_HAS_LOWLEVEL_INIT
select OMAP_CLOCK_ALL
select HAS_OMAP_NAND
- select USB_EHCI_OMAP
- select USB_TWL4030
help
Say Y here if you are using Beagle Board
diff --git a/arch/arm/boards/omap/board-beagle.c b/arch/arm/boards/omap/board-beagle.c
index c0b6b43..e9d3072 100644
--- a/arch/arm/boards/omap/board-beagle.c
+++ b/arch/arm/boards/omap/board-beagle.c
@@ -273,6 +273,7 @@ static struct device_d sdram_dev = {
.platform_data = &sram_pdata,
};
+#ifdef CONFIG_USB_EHCI_OMAP
static struct omap_hcd omap_ehci_pdata = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
@@ -295,6 +296,7 @@ static struct device_d usbh_dev = {
.size = 4 * 1024,
.platform_data = &ehci_pdata,
};
+#endif /* CONFIG_USB_EHCI_OMAP */
static struct device_d i2c_dev = {
.name = "i2c-omap",
@@ -318,8 +320,10 @@ static int beagle_devices_init(void)
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
register_device(&i2c_dev);
+#ifdef CONFIG_USB_EHCI_OMAP
if (ehci_omap_init(&omap_ehci_pdata) >= 0)
register_device(&usbh_dev);
+#endif /* CONFIG_USB_EHCI_OMAP */
#ifdef CONFIG_GPMC
/* WP is made high and WAIT1 active Low */
gpmc_generic_init(0x10);
--
1.7.1
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^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH] beagle: fix usb dependencies
2010-08-17 8:40 ` [PATCH] beagle: fix usb dependencies Michael Grzeschik
@ 2010-08-17 10:09 ` Nishanth Menon
0 siblings, 0 replies; 18+ messages in thread
From: Nishanth Menon @ 2010-08-17 10:09 UTC (permalink / raw)
To: Michael Grzeschik; +Cc: barebox
On 08/17/2010 03:40 AM, Michael Grzeschik wrote:
> Signed-off-by: Michael Grzeschik<m.grzeschik@pengutronix.de>
Acked-by: Nishanth Menon <nm@ti.com>
> ---
> arch/arm/boards/omap/Kconfig | 2 --
> arch/arm/boards/omap/board-beagle.c | 4 ++++
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boards/omap/Kconfig b/arch/arm/boards/omap/Kconfig
> index 6012227..d612064 100644
> --- a/arch/arm/boards/omap/Kconfig
> +++ b/arch/arm/boards/omap/Kconfig
> @@ -48,8 +48,6 @@ config MACH_BEAGLE
> select MACH_HAS_LOWLEVEL_INIT
> select OMAP_CLOCK_ALL
> select HAS_OMAP_NAND
> - select USB_EHCI_OMAP
> - select USB_TWL4030
> help
> Say Y here if you are using Beagle Board
>
> diff --git a/arch/arm/boards/omap/board-beagle.c b/arch/arm/boards/omap/board-beagle.c
> index c0b6b43..e9d3072 100644
> --- a/arch/arm/boards/omap/board-beagle.c
> +++ b/arch/arm/boards/omap/board-beagle.c
> @@ -273,6 +273,7 @@ static struct device_d sdram_dev = {
> .platform_data =&sram_pdata,
> };
>
> +#ifdef CONFIG_USB_EHCI_OMAP
> static struct omap_hcd omap_ehci_pdata = {
> .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
> .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
> @@ -295,6 +296,7 @@ static struct device_d usbh_dev = {
> .size = 4 * 1024,
> .platform_data =&ehci_pdata,
> };
> +#endif /* CONFIG_USB_EHCI_OMAP */
>
> static struct device_d i2c_dev = {
> .name = "i2c-omap",
> @@ -318,8 +320,10 @@ static int beagle_devices_init(void)
> i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
> register_device(&i2c_dev);
>
> +#ifdef CONFIG_USB_EHCI_OMAP
> if (ehci_omap_init(&omap_ehci_pdata)>= 0)
> register_device(&usbh_dev);
> +#endif /* CONFIG_USB_EHCI_OMAP */
> #ifdef CONFIG_GPMC
> /* WP is made high and WAIT1 active Low */
> gpmc_generic_init(0x10);
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 13/13] add beagle board defconfig
2010-08-04 9:59 [PATCH 00/13] OMAP/Beagleboard ehci support Michael Grzeschik
` (11 preceding siblings ...)
2010-08-04 9:59 ` [PATCH 12/13] beagle: add usb support Michael Grzeschik
@ 2010-08-04 9:59 ` Michael Grzeschik
2010-08-17 8:42 ` [PATCH] beagle: defconfig cleanup for v2010.08.0 Michael Grzeschik
2010-10-10 8:37 ` [PATCH 00/13] OMAP/Beagleboard ehci support Anand Gadiyar
13 siblings, 1 reply; 18+ messages in thread
From: Michael Grzeschik @ 2010-08-04 9:59 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/configs/omap3530_beagle_defconfig | 257 ++++++++++++++++++++++++++++
1 files changed, 257 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/configs/omap3530_beagle_defconfig
diff --git a/arch/arm/configs/omap3530_beagle_defconfig b/arch/arm/configs/omap3530_beagle_defconfig
new file mode 100644
index 0000000..9f9a875
--- /dev/null
+++ b/arch/arm/configs/omap3530_beagle_defconfig
@@ -0,0 +1,257 @@
+#
+# Automatically generated make config: don't edit
+# barebox version: 2010.06.0
+# Wed Jun 23 14:18:59 2010
+#
+# CONFIG_BOARD_LINKER_SCRIPT is not set
+CONFIG_GENERIC_LINKER_SCRIPT=y
+CONFIG_ARM=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_NETX is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_S3C24xx is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+
+#
+# processor features
+#
+CONFIG_ARCH_TEXT_BASE=0x80e80000
+CONFIG_BOARDINFO="Texas Instrument's Beagle"
+
+#
+# OMAP Features
+#
+CONFIG_ARCH_OMAP3=y
+CONFIG_OMAP_CONFIG_STACKSIZE=0x00008000
+CONFIG_OMAP_MALLOC_LEN=0x00008000
+CONFIG_OMAP_CLOCK_ALL=y
+CONFIG_OMAP_CLOCK_SOURCE_S32K=y
+CONFIG_OMAP3_CLOCK_CONFIG=y
+# CONFIG_OMAP3_COPY_CLOCK_SRAM is not set
+CONFIG_GPMC=y
+CONFIG_GPIO=y
+
+#
+# OMAP Platform Features
+#
+# CONFIG_MACH_OMAP343xSDP is not set
+CONFIG_MACH_BEAGLE=y
+# CONFIG_MACH_OMAP3EVM is not set
+CONFIG_HAS_OMAP_NAND=y
+CONFIG_MACH_OMAP_GPMC_NAND=y
+CONFIG_MACH_OMAP_GPMC_GENERICNAND=y
+# CONFIG_MACH_OMAP_GPMC_GENERICNAND_LP_X8 is not set
+CONFIG_MACH_OMAP_GPMC_GENERICNAND_LP_X16=y
+# CONFIG_MACH_OMAP_GPMC_GENERICNAND_SP_X8 is not set
+# CONFIG_MACH_OMAP_GPMC_GENERICNAND_SP_X16 is not set
+CONFIG_MACH_OMAP_CS=0x0
+CONFIG_AEABI=y
+
+#
+# Arm specific settings
+#
+CONFIG_CMD_ARM_CPUINFO=y
+# CONFIG_CPU_V7_DCACHE_SKIP is not set
+# CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS is not set
+CONFIG_HAS_KALLSYMS=y
+CONFIG_HAS_MODULES=y
+CONFIG_CMD_MEMORY=y
+CONFIG_ENV_HANDLING=y
+
+#
+# General Settings
+#
+CONFIG_LOCALVERSION_AUTO=y
+
+#
+# memory layout
+#
+CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y
+CONFIG_TEXT_BASE=0x81000000
+CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y
+CONFIG_MEMORY_LAYOUT_DEFAULT=y
+# CONFIG_MEMORY_LAYOUT_FIXED is not set
+CONFIG_STACK_SIZE=0x8000
+CONFIG_MALLOC_SIZE=0x400000
+# CONFIG_BROKEN is not set
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_MACH_HAS_LOWLEVEL_INIT=y
+CONFIG_MACH_DO_LOWLEVEL_INIT=y
+CONFIG_ARCH_HAS_LOWLEVEL_INIT=y
+CONFIG_PROMPT="barebox> "
+CONFIG_BAUDRATE=115200
+CONFIG_LONGHELP=y
+CONFIG_CBSIZE=1024
+CONFIG_MAXARGS=16
+CONFIG_SHELL_HUSH=y
+# CONFIG_SHELL_SIMPLE is not set
+CONFIG_GLOB=y
+CONFIG_PROMPT_HUSH_PS2="> "
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_DYNAMIC_CRC_TABLE=y
+CONFIG_ERRNO_MESSAGES=y
+# CONFIG_TIMESTAMP is not set
+CONFIG_CONSOLE_FULL=y
+CONFIG_CONSOLE_ACTIVATE_FIRST=y
+# CONFIG_OF_FLAT_TREE is not set
+CONFIG_PARTITION=y
+# CONFIG_DEFAULT_ENVIRONMENT is not set
+
+#
+# Debugging
+#
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_ENABLE_FLASH_NOISE is not set
+# CONFIG_ENABLE_PARTITION_NOISE is not set
+# CONFIG_ENABLE_DEVICE_NOISE is not set
+
+#
+# Commands
+#
+
+#
+# scripting
+#
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TRUE=y
+CONFIG_CMD_FALSE=y
+
+#
+# file commands
+#
+CONFIG_CMD_LS=y
+CONFIG_CMD_RM=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_MKDIR=y
+CONFIG_CMD_RMDIR=y
+CONFIG_CMD_CP=y
+CONFIG_CMD_PWD=y
+CONFIG_CMD_CD=y
+CONFIG_CMD_MOUNT=y
+CONFIG_CMD_UMOUNT=y
+
+#
+# console
+#
+CONFIG_CMD_CLEAR=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ECHO_E=y
+
+#
+# memory
+#
+CONFIG_CMD_LOADB=y
+# CONFIG_CMD_MEMINFO is not set
+# CONFIG_CMD_CRC is not set
+# CONFIG_CMD_MTEST is not set
+
+#
+# flash
+#
+CONFIG_CMD_FLASH=y
+
+#
+# booting
+#
+# CONFIG_CMD_BOOTM is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_BOOTU=y
+# CONFIG_CMD_LINUX16 is not set
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_TEST=y
+CONFIG_CMD_VERSION=y
+CONFIG_CMD_HELP=y
+CONFIG_CMD_DEVINFO=y
+CONFIG_CMD_UNLZO=y
+CONFIG_CMD_I2C=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_RARP=y
+CONFIG_NET_NFS=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+
+#
+# Drivers
+#
+
+#
+# serial drivers
+#
+# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
+CONFIG_MIIPHY=y
+
+#
+# Network drivers
+#
+# CONFIG_DRIVER_NET_SMC911X is not set
+# CONFIG_DRIVER_NET_SMC91111 is not set
+CONFIG_NET_USB=y
+CONFIG_NET_USB_ASIX=y
+
+#
+# SPI drivers
+#
+# CONFIG_SPI is not set
+CONFIG_I2C=y
+CONFIG_DRIVER_I2C_OMAP=y
+# CONFIG_DRIVER_I2C_MC13892 is not set
+# CONFIG_DRIVER_I2C_MC9SDZ60 is not set
+# CONFIG_DRIVER_I2C_LP3972 is not set
+CONFIG_DRIVER_I2C_TWL4030=y
+
+#
+# flash drivers
+#
+# CONFIG_DRIVER_CFI is not set
+CONFIG_NAND=y
+CONFIG_NAND_OMAP_GPMC=y
+# CONFIG_NAND_OMAP_GPMC_HWECC is not set
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_ATA is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+# CONFIG_USB_ISP1504 is not set
+CONFIG_USB_TWL4030=y
+# CONFIG_USB_GADGET is not set
+# CONFIG_VIDEO is not set
+
+#
+# Filesystem support
+#
+# CONFIG_FS_CRAMFS is not set
+CONFIG_FS_RAMFS=y
+CONFIG_FS_DEVFS=y
+CONFIG_CRC32=y
+CONFIG_CRC16=y
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_PROCESS_ESCAPE_SEQUENCE=y
+CONFIG_LZO_DECOMPRESS=y
--
1.7.1
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^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH] beagle: defconfig cleanup for v2010.08.0
2010-08-04 9:59 ` [PATCH 13/13] add beagle board defconfig Michael Grzeschik
@ 2010-08-17 8:42 ` Michael Grzeschik
0 siblings, 0 replies; 18+ messages in thread
From: Michael Grzeschik @ 2010-08-17 8:42 UTC (permalink / raw)
To: barebox
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
arch/arm/configs/omap3530_beagle_defconfig | 26 +++++++++++++-------------
1 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm/configs/omap3530_beagle_defconfig b/arch/arm/configs/omap3530_beagle_defconfig
index 9f9a875..2383c63 100644
--- a/arch/arm/configs/omap3530_beagle_defconfig
+++ b/arch/arm/configs/omap3530_beagle_defconfig
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
-# barebox version: 2010.06.0
-# Wed Jun 23 14:18:59 2010
+# barebox version: 2010.08.0
+# Tue Aug 10 18:52:24 2010
#
# CONFIG_BOARD_LINKER_SCRIPT is not set
CONFIG_GENERIC_LINKER_SCRIPT=y
@@ -15,6 +15,7 @@ CONFIG_ARM=y
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_NOMADIK is not set
CONFIG_ARCH_OMAP=y
# CONFIG_ARCH_S3C24xx is not set
@@ -35,8 +36,6 @@ CONFIG_BOARDINFO="Texas Instrument's Beagle"
# OMAP Features
#
CONFIG_ARCH_OMAP3=y
-CONFIG_OMAP_CONFIG_STACKSIZE=0x00008000
-CONFIG_OMAP_MALLOC_LEN=0x00008000
CONFIG_OMAP_CLOCK_ALL=y
CONFIG_OMAP_CLOCK_SOURCE_S32K=y
CONFIG_OMAP3_CLOCK_CONFIG=y
@@ -51,13 +50,6 @@ CONFIG_GPIO=y
CONFIG_MACH_BEAGLE=y
# CONFIG_MACH_OMAP3EVM is not set
CONFIG_HAS_OMAP_NAND=y
-CONFIG_MACH_OMAP_GPMC_NAND=y
-CONFIG_MACH_OMAP_GPMC_GENERICNAND=y
-# CONFIG_MACH_OMAP_GPMC_GENERICNAND_LP_X8 is not set
-CONFIG_MACH_OMAP_GPMC_GENERICNAND_LP_X16=y
-# CONFIG_MACH_OMAP_GPMC_GENERICNAND_SP_X8 is not set
-# CONFIG_MACH_OMAP_GPMC_GENERICNAND_SP_X16 is not set
-CONFIG_MACH_OMAP_CS=0x0
CONFIG_AEABI=y
#
@@ -70,6 +62,7 @@ CONFIG_HAS_KALLSYMS=y
CONFIG_HAS_MODULES=y
CONFIG_CMD_MEMORY=y
CONFIG_ENV_HANDLING=y
+CONFIG_GENERIC_GPIO=y
#
# General Settings
@@ -170,6 +163,7 @@ CONFIG_CMD_LOADB=y
# flash
#
CONFIG_CMD_FLASH=y
+# CONFIG_CMD_UBI is not set
#
# booting
@@ -186,14 +180,17 @@ CONFIG_CMD_TEST=y
CONFIG_CMD_VERSION=y
CONFIG_CMD_HELP=y
CONFIG_CMD_DEVINFO=y
+# CONFIG_CMD_GPIO is not set
CONFIG_CMD_UNLZO=y
CONFIG_CMD_I2C=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
-CONFIG_NET_RARP=y
CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
+# CONFIG_NET_TFTP_PUSH is not set
+# CONFIG_NET_NETCONSOLE is not set
+# CONFIG_NET_RESOLV is not set
#
# Drivers
@@ -222,6 +219,7 @@ CONFIG_NET_USB_ASIX=y
CONFIG_I2C=y
CONFIG_DRIVER_I2C_OMAP=y
# CONFIG_DRIVER_I2C_MC13892 is not set
+# CONFIG_DRIVER_I2C_MC34704 is not set
# CONFIG_DRIVER_I2C_MC9SDZ60 is not set
# CONFIG_DRIVER_I2C_LP3972 is not set
CONFIG_DRIVER_I2C_TWL4030=y
@@ -230,15 +228,17 @@ CONFIG_DRIVER_I2C_TWL4030=y
# flash drivers
#
# CONFIG_DRIVER_CFI is not set
+CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_OMAP_GPMC=y
-# CONFIG_NAND_OMAP_GPMC_HWECC is not set
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
# CONFIG_MTD_NAND_ECC_SMC is not set
CONFIG_MTD_NAND_IDS=y
+# CONFIG_UBI is not set
# CONFIG_ATA is not set
CONFIG_USB=y
CONFIG_USB_EHCI=y
+CONFIG_USB_EHCI_OMAP=y
# CONFIG_USB_ISP1504 is not set
CONFIG_USB_TWL4030=y
# CONFIG_USB_GADGET is not set
--
1.7.1
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 00/13] OMAP/Beagleboard ehci support
2010-08-04 9:59 [PATCH 00/13] OMAP/Beagleboard ehci support Michael Grzeschik
` (12 preceding siblings ...)
2010-08-04 9:59 ` [PATCH 13/13] add beagle board defconfig Michael Grzeschik
@ 2010-10-10 8:37 ` Anand Gadiyar
13 siblings, 0 replies; 18+ messages in thread
From: Anand Gadiyar @ 2010-10-10 8:37 UTC (permalink / raw)
To: Michael Grzeschik; +Cc: barebox
On Wed, Aug 4, 2010 at 3:29 PM, Michael Grzeschik
<m.grzeschik@pengutronix.de> wrote:
> Hi all,
>
> this patchseries adds ehci support for the beagleboard, which includes
> i2c-omap, twl4030 phy and ehci-omap support.
>
Small comment - there shouldn't be any need for i2c-omap
and twl4030 phy support to get EHCI working on the beagleboard.
The EHCI ports are wired up through an SMSC332x PHY, while
the PHY in the TWL4030 is connected to the OTG port.
So this series likely ends up enabling the OTG port as well - or
brings us closer to that!
Thanks for the series - I'll try and test on my beagle.
- Anand
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^ permalink raw reply [flat|nested] 18+ messages in thread