[PATCH 0/8] omap36x: Add basic support

[PATCH 0/8] omap36x: Add basic support

[Sanjeev Premi]

This series enables basic support of OMAP36XX in the
barebox sources.

First few commits are directly related to automatic
detection of the silicon, it's revisions and clock
configuration.

The last two patches are more of bugfixes, but relate
to/ manifest when adding support of OMAP36XX. Hence,
they were included in this series.

Sanjeev Premi (8):
  omap36x: Add support for dynamic detection
  omap36x: Detect silicon revisions
  omap36x: Define structure for PER DPLL
  omap36x: Add DPLL tables and functions to access them
  omap36x: Define per domain functions for DPLL configuration
  omap36x: Perform basic clock initialization
  omap3: Avoid sudden change to SYS_CLK divider
  omap3: Define GFX_DIV values for OMAP34xx and OMAP36xx

 arch/arm/mach-omap/include/mach/omap3-clock.h |   25 +++-
 arch/arm/mach-omap/include/mach/sys_info.h    |   14 +-
 arch/arm/mach-omap/omap3_clock.c              |  246 +++++++++++++++++++++++-
 arch/arm/mach-omap/omap3_clock_core.S         |   90 +++++++++-
 arch/arm/mach-omap/omap3_generic.c            |   65 +++++--
 5 files changed, 404 insertions(+), 36 deletions(-)

-- 
1.7.2.2


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[PATCH 1/8] omap36x: Add support for dynamic detection

[Sanjeev Premi]

This patch adds the support to detect OMAP3630.

It also re-organizes the CPU_xxxx definitions in sys_info.h
to ascending order so that newer silicons can be added at
bottom.

Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 arch/arm/mach-omap/include/mach/sys_info.h |   10 ++++++----
 arch/arm/mach-omap/omap3_generic.c         |    5 ++++-
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h
index 8b8d332..37a4a71 100644
--- a/arch/arm/mach-omap/include/mach/sys_info.h
+++ b/arch/arm/mach-omap/include/mach/sys_info.h
@@ -44,11 +44,12 @@
 #define DDR_133		133    /* most combo, some mem d-boards */
 #define DDR_165		165    /* future parts */
 
-#define CPU_3430	0x3430
-#define CPU_2430	0x2430
-#define CPU_2420	0x2420
-#define CPU_1710	0x1710
 #define CPU_1610	0x1610
+#define CPU_1710	0x1710
+#define CPU_2420	0x2420
+#define CPU_2430	0x2430
+#define CPU_3430	0x3430
+#define CPU_3630	0x3630
 
 /**
  * Define CPU revisions
@@ -80,6 +81,7 @@
  * Hawkeye definitions to identify silicon families
  */
 #define OMAP_HAWKEYE_34XX	0xB7AE
+#define OMAP_HAWKEYE_36XX	0xB891
 
 /** These are implemented by the System specific code in omapX-generic.c */
 u32 get_cpu_type(void);
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index e146780..e9083bc 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -66,7 +66,7 @@ EXPORT_SYMBOL(reset_cpu);
 /**
  * @brief Low level CPU type
  *
- * @return CPU_3430
+ * @return Detected CPU type
  */
 u32 get_cpu_type(void)
 {
@@ -80,6 +80,9 @@ u32 get_cpu_type(void)
 	if (hawkeye == OMAP_HAWKEYE_34XX)
 		return CPU_3430;
 
+	if (hawkeye == OMAP_HAWKEYE_36XX)
+		return CPU_3630;
+
 	/*
 	 * Fallback to OMAP3430 as default.
 	 */
-- 
1.7.2.2


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[PATCH 2/8] omap36x: Detect silicon revisions

[Sanjeev Premi]

This patch adds support to detect the different
OMAP36XX silicon revisions.

Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 arch/arm/mach-omap/include/mach/sys_info.h |    4 ++
 arch/arm/mach-omap/omap3_generic.c         |   60 +++++++++++++++++++--------
 2 files changed, 46 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h
index 37a4a71..f557068 100644
--- a/arch/arm/mach-omap/include/mach/sys_info.h
+++ b/arch/arm/mach-omap/include/mach/sys_info.h
@@ -62,6 +62,10 @@
 #define OMAP34XX_ES3		cpu_revision(CPU_3430, 3)
 #define OMAP34XX_ES3_1		cpu_revision(CPU_3430, 4)
 
+#define OMAP36XX_ES1		cpu_revision(CPU_3630, 0)
+#define OMAP36XX_ES1_1		cpu_revision(CPU_3630, 1)
+#define OMAP36XX_ES1_2		cpu_revision(CPU_3630, 2)
+
 #define GPMC_MUXED		1
 #define GPMC_NONMUXED		0
 
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index e9083bc..843143b 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -92,6 +92,7 @@ u32 get_cpu_type(void)
 /**
  * @brief Extract the OMAP ES revision
  *
+ * The significance of the CPU revision depends upon the cpu type.
  * Latest known revision is considered default.
  *
  * @return silicon version
@@ -105,31 +106,54 @@ u32 get_cpu_rev(void)
 
 	version = get_version(idcode_val);
 
-	/*
-	 * On OMAP3430 ES1.0 the IDCODE register is not exposed on L4.
-	 * Use CPU ID to check for the same.
-	 */
-	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(retval));
-	if ((retval & 0xf) == 0x0) {
-		retval = OMAP34XX_ES1;
-	} else {
+	switch (get_cpu_type()) {
+	case CPU_3630:
 		switch (version) {
-		case 0: /* This field was not set in early samples */
+		case 0:
+			retval = OMAP36XX_ES1;
+			break;
 		case 1:
-			retval = OMAP34XX_ES2;
+			retval = OMAP36XX_ES1_1;
 			break;
 		case 2:
-			retval = OMAP34XX_ES2_1;
-			break;
-		case 3:
-			retval = OMAP34XX_ES3;
-			break;
-		case 4:
 			/*
-			 * Same as default case
+			 * Fall through the default case.
 			 */
 		default:
-			retval = OMAP34XX_ES3_1;
+			retval = OMAP36XX_ES1_2;
+		}
+		break;
+	case CPU_3430:
+		/*
+		 * Same as default case
+		 */
+	default:
+		/*
+		 * On OMAP3430 ES1.0 the IDCODE register is not exposed on L4.
+		 * Use CPU ID to check for the same.
+		 */
+		__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(retval));
+		if ((retval & 0xf) == 0x0) {
+			retval = OMAP34XX_ES1;
+		} else {
+			switch (version) {
+			case 0: /* This field was not set in early samples */
+			case 1:
+				retval = OMAP34XX_ES2;
+				break;
+			case 2:
+				retval = OMAP34XX_ES2_1;
+				break;
+			case 3:
+				retval = OMAP34XX_ES3;
+				break;
+			case 4:
+				/*
+				 * Same as default case
+				 */
+			default:
+				retval = OMAP34XX_ES3_1;
+			}
 		}
 	}
 
-- 
1.7.2.2


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[PATCH 3/8] omap36x: Define structure for PER DPLL

[Sanjeev Premi]

The PER domain dpll significantly differs from 34x.
This patch defines struct to collate related info.

Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 arch/arm/mach-omap/include/mach/omap3-clock.h |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h
index 6613645..aa420f8 100644
--- a/arch/arm/mach-omap/include/mach/omap3-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap3-clock.h
@@ -124,6 +124,18 @@ struct dpll_param {
 	unsigned int fsel;
 	unsigned int m2;
 };
+
+struct dpll_param_per_36x {
+	unsigned int m;
+	unsigned int n;
+	unsigned int m2;
+	unsigned int m3;
+	unsigned int m4;
+	unsigned int m5;
+	unsigned int m6;
+	unsigned int m2div;
+};
+
 /* External functions see omap3_clock_core.S */
 extern struct dpll_param *get_mpu_dpll_param_34x(u32);
 extern struct dpll_param *get_iva_dpll_param_34x(u32);
-- 
1.7.2.2


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[PATCH 4/8] omap36x: Add DPLL tables and functions to access them

[Sanjeev Premi]

This patch adds the DPLL tables for OMAP36XX and the
necessary functions to access these tables.

Both definitions follow the conventions used for
OMAP34XX.

All tables, currently, correspond to SYSCLK at 26MHz.

Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 arch/arm/mach-omap/include/mach/omap3-clock.h |    4 +
 arch/arm/mach-omap/omap3_clock_core.S         |   88 +++++++++++++++++++++++++
 2 files changed, 92 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h
index aa420f8..b9e2714 100644
--- a/arch/arm/mach-omap/include/mach/omap3-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap3-clock.h
@@ -142,6 +142,10 @@ extern struct dpll_param *get_iva_dpll_param_34x(u32);
 extern struct dpll_param *get_core_dpll_param_34x(u32);
 extern struct dpll_param *get_per_dpll_param_34x(u32);
 
+extern struct dpll_param *get_mpu_dpll_param_36x(u32);
+extern struct dpll_param *get_iva_dpll_param_36x(u32);
+extern struct dpll_param *get_core_dpll_param_36x(u32);
+extern struct dpll_param_per_36x *get_per_dpll_param_36x(u32);
 #endif /* __ASSEMBLY__ */
 
 #endif  /* endif _OMAP343X_CLOCKS_H_ */
diff --git a/arch/arm/mach-omap/omap3_clock_core.S b/arch/arm/mach-omap/omap3_clock_core.S
index 5a1f068..eb13c2f 100644
--- a/arch/arm/mach-omap/omap3_clock_core.S
+++ b/arch/arm/mach-omap/omap3_clock_core.S
@@ -336,3 +336,91 @@ per_dpll_param_34x:
 get_per_dpll_param_34x:
 	adr r0, per_dpll_param_34x
 	mov pc, lr
+
+.globl mpu_dpll_param_36x
+mpu_dpll_param_36x:
+/* FIXME: All values correspond to 26MHz only */
+/*    	M	N	FREQSEL	M2	*/
+.word	0x12C,	0x0C,	0x00,	0x01		/* 12   MHz	*/
+.word	0x12C,	0x0C,	0x00,	0x01		/* 13   MHz	*/
+.word	0x12C,	0x0C,	0x00,	0x01		/* 19.2 MHz	*/
+.word	0x12C,	0x0C,	0x00,	0x01		/* 26   MHz	*/
+.word	0x12C,	0x0C,	0x00,	0x01		/* 38.4 MHz	*/
+
+/**
+ * @brief Get address of MPU DPLL param table (OMAP36XX).
+ *
+ * @param rev Silicon revision.
+ *
+ * @return Address of the param table
+ */
+.globl get_mpu_dpll_param_36x
+get_mpu_dpll_param_36x:
+	adr r0, mpu_dpll_param_36x
+	mov pc, lr
+
+.globl iva_dpll_param_36x
+iva_dpll_param_36x:
+/* FIXME: All values correspond to 26MHz only */
+/*    	M	N	FREQSEL	M2	*/
+.word	0x00A,	0x00,	0x00,	0x01		/* 12   MHz	*/
+.word	0x00A,	0x00,	0x00,	0x01		/* 13   MHz	*/
+.word	0x00A,	0x00,	0x00,	0x01		/* 19.2 MHz	*/
+.word	0x00A,	0x00,	0x00,	0x01		/* 26   MHz	*/
+.word	0x00A,	0x00,	0x00,	0x01		/* 38.4 MHz	*/
+
+/**
+ * @brief Get address of IVA DPLL param table (OMAP36XX).
+ *
+ * @param rev Silicon revision.
+ *
+ * @return Address of the param table
+ */
+.globl get_iva_dpll_param_36x
+get_iva_dpll_param_36x:
+	adr r0, iva_dpll_param_36x
+	mov pc, lr
+
+.globl core_dpll_param_36x
+core_dpll_param_36x:
+/* FIXME: All values correspond to 26MHz only */
+/*    	M	N	FREQSEL	M2	*/
+.word	0x0C8,	0x0C,	0x00,	0x01		/* 12   MHz	*/
+.word	0x0C8,	0x0C,	0x00,	0x01		/* 13   MHz	*/
+.word	0x0C8,	0x0C,	0x00,	0x01		/* 19.2 MHz	*/
+.word	0x0C8,	0x0C,	0x00,	0x01		/* 26   MHz	*/
+.word	0x0C8,	0x0C,	0x00,	0x01		/* 38.4 MHz	*/
+
+/**
+ * @brief Get address of IVA DPLL param table (OMAP36XX).
+ *
+ * @param rev Silicon revision.
+ *
+ * @return Address of the param table
+ */
+.globl get_core_dpll_param_36x
+get_core_dpll_param_36x:
+	adr r0, core_dpll_param_36x
+	mov pc, lr
+
+.globl per_dpll_param_36x
+per_dpll_param_36x:
+/* FIXME: All values correspond to 26MHz only */
+/*	M	N	M2	M3	M4	M5	M6	m2DIV */
+.word	0x1B0,	0x0C,	9,	0x10,	9,	4,	3,	1 /* 12   MHz */
+.word	0x1B0,	0x0C,	9,	0x10,	9,	4,	3,	1 /* 13   MHz */
+.word	0x1B0,	0x0C,	9,	0x10,	9,	4,	3,	1 /* 19.2 MHz */
+.word	0x1B0,	0x0C,	9,	0x10,	9,	4,	3,	1 /* 26   MHz */
+.word	0x1B0,	0x0C,	9,	0x10,	9,	4,	3,	1 /* 38.4 MHz */
+
+/**
+ * @brief Get address of PER DPLL param table (OMAP36XX).
+ *
+ * @param rev Silicon revision.
+ *
+ * @return Address of the param table
+ */
+.globl get_per_dpll_param_36x
+get_per_dpll_param_36x:
+	adr r0, per_dpll_param_36x
+	mov pc, lr
-- 
1.7.2.2


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[PATCH 5/8] omap36x: Define per domain functions for DPLL configuration

[Sanjeev Premi]

This patch defines functions that contain steps to configure
DPLL for each clock domain.

Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 arch/arm/mach-omap/omap3_clock.c |  193 ++++++++++++++++++++++++++++++++++++++
 1 files changed, 193 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index c5a32e9..492e309 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -351,6 +351,199 @@ static void init_iva_dpll_34x(u32 cpu_rev, u32 clk_sel)
 }
 
 /**
+ * @brief Initialize CORE DPLL for OMAP36x
+ *
+ * @param[in] cpu_rev - Silicon revision
+ * @param[in] clk_sel - Clock selection used as index into the dpll table
+ */
+static void init_core_dpll_36x(u32 cpu_rev, u32 clk_sel)
+{
+	struct dpll_param *dp = get_core_dpll_param_36x(cpu_rev);
+#ifdef CONFIG_OMAP3_COPY_CLOCK_SRAM
+	int p0, p1, p2, p3;
+#endif
+
+	dp += clk_sel;
+
+	if (running_in_sram()) {
+		sr32(CM_REG(CLKEN_PLL), 0, 3, PLL_FAST_RELOCK_BYPASS);
+		wait_on_value((0x1 << 0), 0, CM_REG(IDLEST_CKGEN), LDELAY);
+
+		/* CM_CLKSEL1_EMU[DIV_DPLL3] */
+		sr32(CM_REG(CLKSEL1_EMU), 16, 5, CORE_M3X2);
+
+		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+		sr32(CM_REG(CLKSEL1_PLL), 27, 5, dp->m2);
+
+		/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+		sr32(CM_REG(CLKSEL1_PLL), 16, 11, dp->m);
+
+		/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+		sr32(CM_REG(CLKSEL1_PLL), 8, 7, dp->n);
+
+		/* Set source CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+		sr32(CM_REG(CLKSEL1_PLL), 6, 1, 0);
+
+		sr32(CM_REG(CLKSEL_CORE), 8, 4, CORE_SSI_DIV);
+		sr32(CM_REG(CLKSEL_CORE), 4, 2, CORE_FUSB_DIV);
+		sr32(CM_REG(CLKSEL_CORE), 2, 2, CORE_L4_DIV);
+		sr32(CM_REG(CLKSEL_CORE), 0, 2, CORE_L3_DIV);
+		sr32(CM_REG(CLKSEL_GFX),  0, 3, GFX_DIV_36X);
+		sr32(CM_REG(CLKSEL_WKUP), 1, 2, WKUP_RSM);
+
+		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+		sr32(CM_REG(CLKEN_PLL), 4, 4, dp->fsel);
+
+		/* Lock Mode */
+		sr32(CM_REG(CLKEN_PLL), 0, 3, PLL_LOCK);
+		wait_on_value((0x1 << 0), 1, CM_REG(IDLEST_CKGEN), LDELAY);
+	} else if (running_in_flash()) {
+#ifdef CONFIG_OMAP3_COPY_CLOCK_SRAM
+		f_lock_pll = (void *)(OMAP_SRAM_INTVECT +
+					OMAP_SRAM_INTVECT_COPYSIZE);
+
+		/*
+		 * Jump to small relocated code area in SRAM.
+		 */
+		p0 = readl(CM_REG(CLKEN_PLL));
+		sr32((u32) &p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
+
+		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+		sr32((u32) &p0, 4, 4, dp->fsel);
+
+		p1 = readl(CM_REG(CLKSEL1_PLL));
+
+		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+		sr32((u32) &p1, 27, 5, dp->m2);
+
+		/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+		sr32((u32) &p1, 16, 11, dp->m);
+
+		/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+		sr32((u32) &p1, 8, 7, dp->n);
+
+		/* Set source CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+		sr32((u32) &p1, 6, 1, 0);
+
+		p2 = readl(CM_REG(CLKSEL_CORE));
+		sr32((u32) &p2, 8, 4, CORE_SSI_DIV);
+		sr32((u32) &p2, 4, 2, CORE_FUSB_DIV);
+		sr32((u32) &p2, 2, 2, CORE_L4_DIV);
+		sr32((u32) &p2, 0, 2, CORE_L3_DIV);
+
+		p3 = CM_REG(IDLEST_CKGEN);
+
+		(*f_lock_pll) (p0, p1, p2, p3);
+#else
+		/***Oopps.. Wrong .config!! *****/
+		hang();
+#endif
+	}
+}
+
+/**
+ * @brief Initialize PER DPLL for OMAP36x
+ *
+ * @param[in] cpu_rev - Silicon revision
+ * @param[in] clk_sel - Clock selection used as index into the dpll table
+ */
+static void init_per_dpll_36x(u32 cpu_rev, u32 clk_sel)
+{
+	struct dpll_param_per_36x *dp = get_per_dpll_param_36x(cpu_rev);
+
+	dp += clk_sel;
+
+	sr32(CM_REG(CLKEN_PLL), 16, 3, PLL_STOP);
+	wait_on_value((0x1 << 1), 0, CM_REG(IDLEST_CKGEN), LDELAY);
+
+	/* Set M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
+	sr32(CM_REG(CLKSEL1_EMU), 24, 6, dp->m6);
+
+	/* Set M5 (CLKSEL_CAM): CM_CLKSEL_CAM[0:5] */
+	sr32(CM_REG(CLKSEL_CAM), 0, 6, dp->m5);
+
+	/* Set M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
+	sr32(CM_REG(CLKSEL_DSS), 0, 6, dp->m4);
+
+	/* Set M3 (CLKSEL_DSS2): CM_CLKSEL_DSS[8:13] */
+	sr32(CM_REG(CLKSEL_DSS), 8, 6, dp->m3);
+
+	/* Set M2: CM_CLKSEL3_PLL[0:4] */
+	sr32(CM_REG(CLKSEL3_PLL), 0, 5, dp->m2);
+
+	/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
+	sr32(CM_REG(CLKSEL2_PLL), 8, 12, dp->m);
+
+	/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
+	sr32(CM_REG(CLKSEL2_PLL), 0, 7, dp->n);
+
+	/* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
+	sr32(CM_REG(CLKSEL_CORE), 12, 2, dp->m2div);
+
+	/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
+	sr32(CM_REG(CLKEN_PLL), 16, 3, PLL_LOCK);
+	wait_on_value((0x1 << 1), 2, CM_REG(IDLEST_CKGEN), LDELAY);
+}
+
+/**
+ * @brief Initialize MPU DPLL for OMAP36x
+ *
+ * @param[in] cpu_rev - Silicon revision
+ * @param[in] clk_sel - Clock selection used as index into the dpll table
+ */
+static void init_mpu_dpll_36x(u32 cpu_rev, u32 clk_sel)
+{
+	struct dpll_param *dp = get_mpu_dpll_param_36x(cpu_rev);
+
+	dp += clk_sel;
+
+	/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
+	sr32(CM_REG(CLKSEL2_PLL_MPU), 0, 5, dp->m2);
+
+	/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
+	sr32(CM_REG(CLKSEL1_PLL_MPU), 8, 11, dp->m);
+
+	/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
+	sr32(CM_REG(CLKSEL1_PLL_MPU), 0, 7, dp->n);
+
+	/* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
+	sr32(CM_REG(CLKEN_PLL_MPU), 4, 4, dp->fsel);
+}
+
+/**
+ * @brief Initialize IVA DPLL for OMAP36x
+ *
+ * @param[in] cpu_rev - Silicon revision
+ * @param[in] clk_sel - Clock selection used as index into the dpll table
+ */
+static void init_iva_dpll_36x(u32 cpu_rev, u32 clk_sel)
+{
+	struct dpll_param *dp = get_iva_dpll_param_36x(cpu_rev);
+
+	dp += clk_sel;
+
+	/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
+	sr32(CM_REG(CLKEN_PLL_IVA2), 0, 3, PLL_STOP);
+	wait_on_value((0x1 << 0), 0, CM_REG(IDLEST_PLL_IVA2), LDELAY);
+
+	/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
+	sr32(CM_REG(CLKSEL2_PLL_IVA2), 0, 5, dp->m2);
+
+	/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
+	sr32(CM_REG(CLKSEL1_PLL_IVA2), 8, 11, dp->m);
+
+	/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
+	sr32(CM_REG(CLKSEL1_PLL_IVA2), 0, 7, dp->n);
+
+	/* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
+	sr32(CM_REG(CLKEN_PLL_IVA2), 4, 4, dp->fsel);
+
+	/* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+	sr32(CM_REG(CLKEN_PLL_IVA2), 0, 3, PLL_LOCK);
+	wait_on_value((0x1 << 0), 1, CM_REG(IDLEST_PLL_IVA2), LDELAY);
+}
+
+/**
  * @brief Inits clocks for PRCM
  *
  * This is called from SRAM, or Flash (using temp SRAM stack).
-- 
1.7.2.2


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[PATCH 6/8] omap36x: Perform basic clock initialization

[Sanjeev Premi]

This patch adds the basic clock initizlization for OMAP36XX.

Portion of this patch is based on commit:
    29587220909e639cda4fb5a35cb5bf33aba242b9
    at http://arago-project.org/git/projects/?p=x-load-omap3.git

Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 arch/arm/mach-omap/omap3_clock.c |   32 ++++++++++++++++++++++++++------
 1 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 492e309..1668369 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -554,6 +554,7 @@ static void init_iva_dpll_36x(u32 cpu_rev, u32 clk_sel)
 void prcm_init(void)
 {
 	u32 osc_clk = 0, sys_clkin_sel = 0;
+	u32 cpu_type = get_cpu_type();
 	u32 cpu_rev = get_cpu_rev();
 	u32 clk_index;
 
@@ -565,8 +566,15 @@ void prcm_init(void)
 	/* set input crystal speed */
 	sr32(PRM_REG(CLKSEL), 0, 3, sys_clkin_sel);
 
-	/* If the input clock is greater than 19.2M always divide/2 */
-	if (sys_clkin_sel > 2) {
+	/*
+	 * OMAP3430:
+	 *	If the input clock is greater than 19.2M always divide/2
+	 * OMAP3630:
+	 *	DDR corruption was observed on exit from OFF mode, when
+	 *	sys clock is lower than 26M. As workaround, it is maintained
+	 *	at 26M.
+	 */
+	if ((cpu_type != CPU_3630) && (sys_clkin_sel > 2)) {
 		/* input clock divider */
 		sr32(PRM_REG(CLKSRC_CTRL), 6, 2, 2);
 		clk_index = sys_clkin_sel / 2;
@@ -582,10 +590,22 @@ void prcm_init(void)
 	sr32(CM_REG(CLKEN_PLL_MPU), 0, 3, PLL_LOW_POWER_BYPASS);
 	wait_on_value((0x1 << 0), 0, CM_REG(IDLEST_PLL_MPU), LDELAY);
 
-	init_core_dpll_34x(cpu_rev, clk_index);
-	init_per_dpll_34x(cpu_rev, clk_index);
-	init_mpu_dpll_34x(cpu_rev, clk_index);
-	init_iva_dpll_34x(cpu_rev, clk_index);
+	if (cpu_type == CPU_3430) {
+		init_core_dpll_34x(cpu_rev, clk_index);
+		init_per_dpll_34x(cpu_rev, clk_index);
+		init_mpu_dpll_34x(cpu_rev, clk_index);
+		init_iva_dpll_34x(cpu_rev, clk_index);
+	}
+	else if (cpu_type == CPU_3630) {
+		init_core_dpll_36x(cpu_rev, clk_index);
+		init_per_dpll_36x(cpu_rev, clk_index);
+		init_mpu_dpll_36x(cpu_rev, clk_index);
+		init_iva_dpll_36x(cpu_rev, clk_index);
+	}
+	else {
+		/* Unknown CPU */
+		hang();
+	}
 
 	/*
 	 * Clock configuration complete. Lock MPU PLL.
-- 
1.7.2.2


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[PATCH 7/8] omap3: Avoid sudden change to SYS_CLK divider

[Sanjeev Premi]

In function get_osc_clk_speed(), the SYS_CLK divider
was being changed 'suddenly'.

This change has cascading effect on the derived clocks,
leading to inconsistent behavior - often a crash.

Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 arch/arm/mach-omap/include/mach/omap3-clock.h |    6 ++++++
 arch/arm/mach-omap/omap3_clock.c              |   19 +++++++++++++++----
 2 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h
index b9e2714..cccb0da 100644
--- a/arch/arm/mach-omap/include/mach/omap3-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap3-clock.h
@@ -92,6 +92,12 @@
 #define PLL_FAST_RELOCK_BYPASS	6	/* CORE */
 #define PLL_LOCK		7	/* MPU, IVA, CORE & PER */
 
+/*
+ * Bit positions indicating current SYSCLK divider
+ */
+#define SYSCLK_DIV_1		(1 << 6)
+#define SYSCLK_DIV_2		(1 << 7)
+
 /* The following configurations are OPP and SysClk value independant
  * and hence are defined here.
  */
diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 1668369..16cbae9 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -65,12 +65,20 @@ static void per_clocks_enable(void);
  */
 static u32 get_osc_clk_speed(void)
 {
-	u32 start, cstart, cend, cdiff, val;
+	u32 start, cstart, cend, cdiff, cdiv, val;
 
 	val = readl(PRM_REG(CLKSRC_CTRL));
-	/* If SYS_CLK is being divided by 2, remove for now */
-	val = (val & (~(0x1 << 7))) | (0x1 << 6);
-	writel(val, PRM_REG(CLKSRC_CTRL));
+
+	if (val & SYSCLK_DIV_2)
+		cdiv = 2;
+	else if (val & SYSCLK_DIV_1)
+		cdiv = 1;
+	else
+		/*
+		 * Should never reach here!
+		 * To proceed, assume divider as 1.
+		 */
+		cdiv = 1;
 
 	/* enable timer2 */
 	val = readl(CM_REG(CLKSEL_WKUP)) | (0x1 << 0);
@@ -97,6 +105,9 @@ static u32 get_osc_clk_speed(void)
 	cend = readl(OMAP_GPTIMER1_BASE + TCRR);
 	cdiff = cend - cstart;	/* get elapsed ticks */
 
+	if (cdiv == 2)
+		cdiff *= 2;
+
 	/* based on number of ticks assign speed */
 	if (cdiff > 19000)
 		return S38_4M;
-- 
1.7.2.2


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[PATCH 8/8] omap3: Define GFX_DIV values for OMAP34xx and OMAP36xx

[Sanjeev Premi]

This patch updates the clock dividers for the graphics
processor.

It is based on commit:
    c4e1d9b718b65436e30422506f43fa4eb21069d3
    at http://arago-project.org/git/projects/?p=u-boot-omap3.git

Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 arch/arm/mach-omap/include/mach/omap3-clock.h |    3 ++-
 arch/arm/mach-omap/omap3_clock.c              |    2 +-
 arch/arm/mach-omap/omap3_clock_core.S         |    2 +-
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h
index cccb0da..10566e1 100644
--- a/arch/arm/mach-omap/include/mach/omap3-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap3-clock.h
@@ -108,7 +108,8 @@
 #define CORE_FUSB_DIV		2        /* 41.5MHz: */
 #define CORE_L4_DIV		2        /*  83MHz : L4 */
 #define CORE_L3_DIV		2        /* 166MHz : L3 {DDR} */
-#define GFX_DIV			2        /*  83MHz : CM_CLKSEL_GFX */
+#define GFX_DIV_34X		3        /*  96MHz : CM_CLKSEL_GFX (OMAP34XX) */
+#define GFX_DIV_36X		5        /* 200MHz : CM_CLKSEL_GFX (OMAP36XX) */
 #define WKUP_RSM		2        /* 41.5MHz: CM_CLKSEL_WKUP */
 
 /* PER DPLL */
diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 16cbae9..3a0ab24 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -192,7 +192,7 @@ static void init_core_dpll_34x(u32 cpu_rev, u32 clk_sel)
 		sr32(CM_REG(CLKSEL_CORE), 4, 2, CORE_FUSB_DIV);
 		sr32(CM_REG(CLKSEL_CORE), 2, 2, CORE_L4_DIV);
 		sr32(CM_REG(CLKSEL_CORE), 0, 2, CORE_L3_DIV);
-		sr32(CM_REG(CLKSEL_GFX), 0, 3, GFX_DIV);
+		sr32(CM_REG(CLKSEL_GFX), 0, 3, GFX_DIV_34X);
 		sr32(CM_REG(CLKSEL_WKUP), 1, 2, WKUP_RSM);
 
 		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
diff --git a/arch/arm/mach-omap/omap3_clock_core.S b/arch/arm/mach-omap/omap3_clock_core.S
index eb13c2f..c8d04bb 100644
--- a/arch/arm/mach-omap/omap3_clock_core.S
+++ b/arch/arm/mach-omap/omap3_clock_core.S
@@ -194,7 +194,7 @@ pll_div_val3:
 pll_div_add4:
     .word CM_CLKSEL_GFX
 pll_div_val4:
-    .word (GFX_DIV << 0)
+    .word GFX_DIV_34X
 pll_div_add5:
     .word CM_CLKSEL1_EMU
 pll_div_val5:
-- 
1.7.2.2


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