[PATCH] S3C24xx: NAND management changes to support booting from NAND

[PATCH] S3C24xx: NAND management changes to support booting from NAND

[Juergen Beisert]

It seems there are more variants of the mini2440 in the wild than I ever
thought.

In order to support booting from NAND some important settings like NAND's page
size and address cycle count must be known. These settings are provided by
four external pins and can be read back from an register of the NFC. This
patch set makes the S3C24xx NFC driver using these bits.

Hopefully now all mini2440 variants can be booted from NAND without the need
for special configurations.

Juergen


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[PATCH 1/2] mini2440: Add more info about possible SDRAM and flash devices

[Juergen Beisert]

From: Juergen Beisert <juergen@kreuzholzen.de>

It seems there are various variants of the mini2440 in the wild. Not only
the SDRAMs differ, but more important the NANDs also differ.

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
---
 arch/arm/boards/mini2440/mini2440.c |   50 +++++++++++++++++++++++-----------
 1 files changed, 34 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index ab309a0..1e5813a 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -316,23 +316,41 @@ This system is based on a Samsung S3C2440 CPU. The card is shipped with:
 - 12 MHz crystal reference
 - 32.768 kHz crystal reference
 - SDRAM 64 MiB (one bank only)
-   - HY57V561620 (two devices for 64 MiB to form a 32 bit bus)
-     - 4M x 16bit x 4 Banks Mobile SDRAM
-     - 8192 refresh cycles / 64 ms
-     - CL2\@100 MHz
-     - 133 MHz max
-     - collumn address size is 9 bits
-     - row address size is 13 bits
-   - MT48LC16M16 (two devices for 64 MiB to form a 32 bit bus)
-     - 4M x 16bit x 4 Banks Mobile SDRAM
-     - commercial & industrial type
-     - 8192 refresh cycles / 64 ms
-     - CL2\@100 MHz
-     - 133 MHz max
-     - collumn address size is 9 bits
-     - row address size is 13 bits
+   - Hynix SDRAM
+    - HY57V561620FTP-H (two devices for 64 MiB to form a 32 bit bus)
+      - 4M x 16bit x 4 Banks Mobile SDRAM
+      - 8192 refresh cycles / 64 ms
+      - CL2\@100 MHz
+      - 133 MHz max
+      - collumn address size is 9 bits
+      - row address size is 13 bits
+   - Micron SDRAM
+    - MT48LC16M16A2-75IT (two devices for 64 MiB to form a 32 bit bus)
+    - MT48LC16M16A2-7E (two devices for 64 MiB to form a 32 bit bus)
+      - 4M x 16bit x 4 Banks Mobile SDRAM
+      - commercial & industrial type
+      - 8192 refresh cycles / 64 ms
+      - CL2\@100 MHz
+      - 133 MHz max
+      - collumn address size is 9 bits
+      - row address size is 13 bits
 - NAND Flash 128MiB...1GiB
-   - K9Fxx08
+   - K9F1208U0C
+      - VID: 0xec, DID: 0x76
+      - Samsung/64MiB 3,3V 8-bit
+      - 512 + 8 bytes per page, 16 kiB block size, 4 address cycles
+   - K9F1G08UOB
+      - VID: 0xec, DID: 0xf1
+      - Samsung/128MiB 3,3V 8-bit
+      - 2048 + 64 bytes per page, 128 kiB block size, 4 address cycles
+   - K9F2G08UOB
+      - VID: 0xec, DID: 0xda
+      - Samsung/256MiB 3,3V 8-bit
+      - 2048 + 64 bytes per page, 128 kiB block size, 5 address cycles
+   - K9K8G08U0A
+      - VID: 0xec, DID: 0xd3
+      - Samsung/1GiB 3,3V 8-bit
+      - 2048 + 64 bytes per page, 128 kiB block size, 5 address cycles
 - NOR Flash (up to 22 address lines available)
    - AM29LV160DB, 2 MiB
    - SST39VF1601, 2 MiB
-- 
1.7.2.3


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[PATCH 2/2] mini2440: Consider correct NAND page size for boot.

[Juergen Beisert]

From: Juergen Beisert <juergen@kreuzholzen.de>

When booting from NAND, its important to know the correct page size. When
the NAND is used as the boot source, four dedicated pins are used to configure
the correct page size and address cycles. These pins can be read back in one
of the NFC registers to parametrize the load function.

This patch also extends the read routine to support more than four address
cycles on demand.

BTW: At least some mini2440s are misconfigured to use five address cycles for
a NAND device that is known to need only four address cycles. In this case the
vendor is at our side: This NAND simply ignores any additional address cycles
than required.

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
---
 arch/arm/boards/a9m2410/a9m2410.c                 |    2 +-
 arch/arm/boards/a9m2440/a9m2440.c                 |    2 +-
 arch/arm/boards/mini2440/mini2440.c               |    2 +-
 arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h |    2 +-
 drivers/mtd/nand/nand_s3c2410.c                   |   60 +++++++++++++++------
 5 files changed, 48 insertions(+), 20 deletions(-)

diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index 57d8fa3..8cbaec5 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -176,7 +176,7 @@ device_initcall(a9m2410_devices_init);
 #ifdef CONFIG_S3C24XX_NAND_BOOT
 void __bare_init nand_boot(void)
 {
-	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512);
+	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
 }
 #endif
 
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 764cd65..39b5276 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -182,7 +182,7 @@ device_initcall(a9m2440_devices_init);
 #ifdef CONFIG_S3C24XX_NAND_BOOT
 void __bare_init nand_boot(void)
 {
-	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512);
+	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
 }
 #endif
 
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 1e5813a..fe60d3b 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -281,7 +281,7 @@ device_initcall(mini2440_devices_init);
 #ifdef CONFIG_S3C24XX_NAND_BOOT
 void __bare_init nand_boot(void)
 {
-	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512);
+	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
 }
 #endif
 
diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h b/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h
index d06287e..7610b4e 100644
--- a/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h
+++ b/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h
@@ -19,7 +19,7 @@
  */
 
 #ifdef CONFIG_S3C24XX_NAND_BOOT
-extern void s3c24x0_nand_load_image(void*, int, int, int);
+extern void s3c24x0_nand_load_image(void*, int, int);
 #endif
 
 /**
diff --git a/drivers/mtd/nand/nand_s3c2410.c b/drivers/mtd/nand/nand_s3c2410.c
index df0b7c1..374a6fa 100644
--- a/drivers/mtd/nand/nand_s3c2410.c
+++ b/drivers/mtd/nand/nand_s3c2410.c
@@ -497,12 +497,23 @@ static void __nand_boot_init wait_for_completion(void __iomem *host)
 		;
 }
 
-static void __nand_boot_init nfc_addr(void __iomem *host, uint32_t offs)
+static void __nand_boot_init nfc_addr(void __iomem *host, uint32_t offs,
+					int ps, int c)
 {
 	send_addr(host, offs & 0xff);
-	send_addr(host, (offs >> 9) & 0xff);
-	send_addr(host, (offs >> 17) & 0xff);
-	send_addr(host, (offs >> 25) & 0xff);
+
+	if (ps == 512) {
+		send_addr(host, (offs >> 9) & 0xff);
+		send_addr(host, (offs >> 17) & 0xff);
+		if (c > 3)
+			send_addr(host, (offs >> 25) & 0xff);
+	} else {
+		send_addr(host, (offs >> 8) & 0xf0);
+		send_addr(host, (offs >> 12) & 0xff);
+		send_addr(host, (offs >> 20) & 0xff);
+		if (c > 4)
+			send_addr(host, (offs >> 28) & 0xff);
+	}
 }
 
 /**
@@ -510,24 +521,42 @@ static void __nand_boot_init nfc_addr(void __iomem *host, uint32_t offs)
  * @param[out] dest Pointer to target area (in SDRAM)
  * @param[in] size Bytes to read from NAND device
  * @param[in] page Start page to read from
- * @param[in] pagesize Size of each page in the NAND
  *
  * This function must be located in the first 4kiB of the barebox image
- * (guess why). When this routine is running the SDRAM is up and running
- * and it runs from the correct address (physical=linked address).
- * TODO Could we access the platform data from the boardfile?
- * Due to it makes no sense this function does not return in case of failure.
+ * (guess why).
  */
-void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page, int pagesize)
+void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page)
 {
 	void __iomem *host = (void __iomem *)S3C24X0_NAND_BASE;
-	int i;
+	unsigned pagesize;
+	int i, cycle;
 
 	/*
 	 * Reenable the NFC and use the default (but slow) access
 	 * timing or the board specific setting if provided.
 	 */
 	enable_nand_controller(host, BOARD_DEFAULT_NAND_TIMING);
+
+	/* use the current NAND hardware configuration */
+	switch (readl(S3C24X0_NAND_BASE) & 0xf) {
+	case 0x6:	/* 8 bit, 4 addr cycles, 512 bpp, normal NAND */
+		pagesize = 512;
+		cycle = 4;
+		break;
+	case 0xc:	/* 8 bit, 4 addr cycles, 2048 bpp, advanced NAND */
+		pagesize = 2048;
+		cycle = 4;
+		break;
+	case 0xe:	/* 8 bit, 5 addr cycles, 2048 bpp, advanced NAND */
+		pagesize = 2048;
+		cycle = 5;
+		break;
+	default:
+		/* we cannot output an error message here :-( */
+		disable_nand_controller(host);
+		return;
+	}
+
 	enable_cs(host);
 
 	/* Reset the NAND device */
@@ -538,7 +567,7 @@ void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page, in
 	do {
 		enable_cs(host);
 		send_cmd(host, NAND_CMD_READ0);
-		nfc_addr(host, page * pagesize);
+		nfc_addr(host, page * pagesize, pagesize, cycle);
 		wait_for_completion(host);
 		/* copy one page (do *not* use readsb() here!)*/
 		for (i = 0; i < pagesize; i++)
@@ -560,22 +589,21 @@ void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page, in
 static int do_nand_boot_test(struct command *cmdtp, int argc, char *argv[])
 {
 	void *dest;
-	int size, pagesize;
+	int size;
 
 	if (argc < 3)
 		return COMMAND_ERROR_USAGE;
 
 	dest = (void *)strtoul_suffix(argv[1], NULL, 0);
 	size = strtoul_suffix(argv[2], NULL, 0);
-	pagesize = strtoul_suffix(argv[3], NULL, 0);
 
-	s3c24x0_nand_load_image(dest, size, 0, pagesize);
+	s3c24x0_nand_load_image(dest, size, 0);
 
 	return 0;
 }
 
 static const __maybe_unused char cmd_nand_boot_test_help[] =
-"Usage: nand_boot_test <dest> <size> <pagesize>\n";
+"Usage: nand_boot_test <dest> <size>\n";
 
 BAREBOX_CMD_START(nand_boot_test)
 	.cmd		= do_nand_boot_test,
-- 
1.7.2.3


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Re: [PATCH] S3C24xx: NAND management changes to support booting from NAND

[Belisko Marek]

Hi Juergen,

On Thu, Feb 24, 2011 at 10:10 PM, Juergen Beisert <jbe@pengutronix.de> wrote:
> It seems there are more variants of the mini2440 in the wild than I ever
> thought.
>
> In order to support booting from NAND some important settings like NAND's page
> size and address cycle count must be known. These settings are provided by
> four external pins and can be read back from an register of the NFC. This
> patch set makes the S3C24xx NFC driver using these bits.
>
> Hopefully now all mini2440 variants can be booted from NAND without the need
> for special configurations.
Seems my board is somehow cursed. I apply those 2 patche up to the
next tree (also add slo wdown sdram timing)
but nothing helps. Board still doesn't boot from flash :(.
>
> Juergen
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>

thanks,

marek

-- 
as simple and primitive as possible
-------------------------------------------------
Marek Belisko - OPEN-NANDRA
Freelance Developer

Ruska Nova Ves 219 | Presov, 08005 Slovak Republic
Tel: +421 915 052 184
skype: marekwhite
icq: 290551086
web: http://open-nandra.com

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Re: [PATCH 2/2] mini2440: Consider correct NAND page size for boot.

[Zoltán Kócsi]

On Wed, 23 Feb 2011 23:08:14 +0100
Juergen Beisert <jbe@pengutronix.de> wrote:

> Hi Zoltan,
> 
> > [..]
> 
> do you mean something like that?
> 
> From: Juergen Beisert <juergen@kreuzholzen.de>
> Subject: mini2440: Consider correct NAND page size for boot.
> 
> When booting from NAND, its important to know the correct page size.
> When the NAND is used as the boot source, four dedicated pins are
> used to configure the correct page size and address cycle count.
> These pins can be read back in one of the NFC registers to
> parametrize the load function.
> [...]

Yes, *exactly* like that!

Best Regards,

Zoltan

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Re: [PATCH 2/2] mini2440: Consider correct NAND page size for boot.

[Juergen Beisert]

Hi Zoltan,

> Isn't that info available as soon as SteppingStone sucked in the first 4K
> into the internal SRAM?
>
> As far as I can follow the s3c2440 manual, bit 0 and the read-only bits 1
> to 3 of the NFCONF register convey that information and these bits are set
> by sampling a few GPIO (NCON and GPG13-GPG15) pins at reset. Supposedly
> these pins are pulled up/low during reset so that SteppingStone itself can
> read the boot code from the NAND

do you mean something like that?

From: Juergen Beisert <juergen@kreuzholzen.de>
Subject: mini2440: Consider correct NAND page size for boot.

When booting from NAND, its important to know the correct page size. When
the NAND is used as the boot source, four dedicated pins are used to configure
the correct page size and address cycle count. These pins can be read back in
one of the NFC registers to parametrize the load function.

This patch also extends the read routine to support more than four address
cycles on demand.

BTW: At least some mini2440s are misconfigured to use five address cycles for
a NAND device that is known to need only four address cycles. In this case the
vendor is at our side: This NAND simply ignores any additional address cycles
than required.

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>

---
 arch/arm/boards/a9m2410/a9m2410.c                 |    2 
 arch/arm/boards/a9m2440/a9m2440.c                 |    2 
 arch/arm/boards/mini2440/mini2440.c               |    2 
 arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h |    2 
 drivers/mtd/nand/nand_s3c2410.c                   |   60 ++++++++++++++++------
 5 files changed, 48 insertions(+), 20 deletions(-)

Index: barebox-2011.01.0/drivers/mtd/nand/nand_s3c2410.c
===================================================================
--- barebox-2011.01.0.orig/drivers/mtd/nand/nand_s3c2410.c
+++ barebox-2011.01.0/drivers/mtd/nand/nand_s3c2410.c
@@ -497,12 +497,23 @@ static void __nand_boot_init wait_for_co
 		;
 }
 
-static void __nand_boot_init nfc_addr(void __iomem *host, uint32_t offs)
+static void __nand_boot_init nfc_addr(void __iomem *host, uint32_t offs,
+					int ps, int c)
 {
 	send_addr(host, offs & 0xff);
-	send_addr(host, (offs >> 9) & 0xff);
-	send_addr(host, (offs >> 17) & 0xff);
-	send_addr(host, (offs >> 25) & 0xff);
+
+	if (ps == 512) {
+		send_addr(host, (offs >> 9) & 0xff);
+		send_addr(host, (offs >> 17) & 0xff);
+		if (c > 3)
+			send_addr(host, (offs >> 25) & 0xff);
+	} else {
+		send_addr(host, (offs >> 8) & 0xf0);
+		send_addr(host, (offs >> 12) & 0xff);
+		send_addr(host, (offs >> 20) & 0xff);
+		if (c > 4)
+			send_addr(host, (offs >> 28) & 0xff);
+	}
 }
 
 /**
@@ -510,24 +521,42 @@ static void __nand_boot_init nfc_addr(vo
  * @param[out] dest Pointer to target area (in SDRAM)
  * @param[in] size Bytes to read from NAND device
  * @param[in] page Start page to read from
- * @param[in] pagesize Size of each page in the NAND
  *
  * This function must be located in the first 4kiB of the barebox image
- * (guess why). When this routine is running the SDRAM is up and running
- * and it runs from the correct address (physical=linked address).
- * TODO Could we access the platform data from the boardfile?
- * Due to it makes no sense this function does not return in case of failure.
+ * (guess why).
  */
-void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page, int pagesize)
+void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page)
 {
 	void __iomem *host = (void __iomem *)S3C24X0_NAND_BASE;
-	int i;
+	unsigned pagesize;
+	int i, cycle;
 
 	/*
 	 * Reenable the NFC and use the default (but slow) access
 	 * timing or the board specific setting if provided.
 	 */
 	enable_nand_controller(host, BOARD_DEFAULT_NAND_TIMING);
+
+	/* use the current NAND hardware configuration */
+	switch (readl(S3C24X0_NAND_BASE) & 0xf) {
+	case 0x6:	/* 8 bit, 4 addr cycles, 512 bpp, normal NAND */
+		pagesize = 512;
+		cycle = 4;
+		break;
+	case 0xc:	/* 8 bit, 4 addr cycles, 2048 bpp, advanced NAND */
+		pagesize = 2048;
+		cycle = 4;
+		break;
+	case 0xe:	/* 8 bit, 5 addr cycles, 2048 bpp, advanced NAND */
+		pagesize = 2048;
+		cycle = 5;
+		break;
+	default:
+		/* we cannot output an error message here :-( */
+		disable_nand_controller(host);
+		return;
+	}
+
 	enable_cs(host);
 
 	/* Reset the NAND device */
@@ -538,7 +567,7 @@ void __nand_boot_init s3c24x0_nand_load_
 	do {
 		enable_cs(host);
 		send_cmd(host, NAND_CMD_READ0);
-		nfc_addr(host, page * pagesize);
+		nfc_addr(host, page * pagesize, pagesize, cycle);
 		wait_for_completion(host);
 		/* copy one page (do *not* use readsb() here!)*/
 		for (i = 0; i < pagesize; i++)
@@ -560,22 +589,21 @@ void __nand_boot_init s3c24x0_nand_load_
 static int do_nand_boot_test(struct command *cmdtp, int argc, char *argv[])
 {
 	void *dest;
-	int size, pagesize;
+	int size;
 
 	if (argc < 3)
 		return COMMAND_ERROR_USAGE;
 
 	dest = (void *)strtoul_suffix(argv[1], NULL, 0);
 	size = strtoul_suffix(argv[2], NULL, 0);
-	pagesize = strtoul_suffix(argv[3], NULL, 0);
 
-	s3c24x0_nand_load_image(dest, size, 0, pagesize);
+	s3c24x0_nand_load_image(dest, size, 0);
 
 	return 0;
 }
 
 static const __maybe_unused char cmd_nand_boot_test_help[] =
-"Usage: nand_boot_test <dest> <size> <pagesize>\n";
+"Usage: nand_boot_test <dest> <size>\n";
 
 BAREBOX_CMD_START(nand_boot_test)
 	.cmd		= do_nand_boot_test,
Index: barebox-2011.01.0/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h
===================================================================
--- barebox-2011.01.0.orig/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h
+++ barebox-2011.01.0/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h
@@ -19,7 +19,7 @@
  */
 
 #ifdef CONFIG_S3C24XX_NAND_BOOT
-extern void s3c24x0_nand_load_image(void*, int, int, int);
+extern void s3c24x0_nand_load_image(void*, int, int);
 #endif
 
 /**
Index: barebox-2011.01.0/arch/arm/boards/a9m2410/a9m2410.c
===================================================================
--- barebox-2011.01.0.orig/arch/arm/boards/a9m2410/a9m2410.c
+++ barebox-2011.01.0/arch/arm/boards/a9m2410/a9m2410.c
@@ -176,7 +176,7 @@ device_initcall(a9m2410_devices_init);
 #ifdef CONFIG_S3C24XX_NAND_BOOT
 void __bare_init nand_boot(void)
 {
-	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512);
+	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
 }
 #endif
 
Index: barebox-2011.01.0/arch/arm/boards/a9m2440/a9m2440.c
===================================================================
--- barebox-2011.01.0.orig/arch/arm/boards/a9m2440/a9m2440.c
+++ barebox-2011.01.0/arch/arm/boards/a9m2440/a9m2440.c
@@ -182,7 +182,7 @@ device_initcall(a9m2440_devices_init);
 #ifdef CONFIG_S3C24XX_NAND_BOOT
 void __bare_init nand_boot(void)
 {
-	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512);
+	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
 }
 #endif
 
Index: barebox-2011.01.0/arch/arm/boards/mini2440/mini2440.c
===================================================================
--- barebox-2011.01.0.orig/arch/arm/boards/mini2440/mini2440.c
+++ barebox-2011.01.0/arch/arm/boards/mini2440/mini2440.c
@@ -281,7 +281,7 @@ device_initcall(mini2440_devices_init);
 #ifdef CONFIG_S3C24XX_NAND_BOOT
 void __bare_init nand_boot(void)
 {
-	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512);
+	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
 }
 #endif
 

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | Phone: +49-8766-939 228     |
Vertretung Sued/Muenchen, Germany             | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686              | http://www.pengutronix.de/  |

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Re: [PATCH 2/2] mini2440: Consider correct NAND page size for boot.

[Juergen Beisert]

zoltan@bendor.com.au wrote:
> On Tue, 22 Feb 2011, Juergen Beisert wrote:
> > From: Juergen Beisert <juergen@kreuzholzen.de>
> >
> > When booting from NAND, its important to know the correct page size.
>
> Isn't that info available as soon as SteppingStone sucked in the first 4K
> into the internal SRAM?
>
> As far as I can follow the s3c2440 manual, bit 0 and the read-only bits 1
> to 3 of the NFCONF register convey that information and these bits are set
> by sampling a few GPIO (NCON and GPG13-GPG15) pins at reset. Supposedly
> these pins are pulled up/low during reset so that SteppingStone itself can
> read the boot code from the NAND.
>
> What am I missing?

I did a look at it. On my board this register states "0110" which means:
 - 8 bit NAND
 - 512 bytes per page (e.g. "normal" NAND)
 - 4 address cycles
And this setting is all right, my flash is a K9F1208U0A.

But Marek's board states "1110" which means:
 - 8 bit NAND
 - 2048 bytes per page (e.g. "advanced" NAND)
 - 5 address cycles
And this setting is bad, because his K9F1G08U0B uses 4 address cycles only.
Maybe it works because the NAND ignores the 5th address cycle?

Others here around with a mini2440? Can you send me your NAND device type and 
the content of register 0x4e000000?

jbe

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | Phone: +49-8766-939 228     |
Vertretung Sued/Muenchen, Germany             | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686              | http://www.pengutronix.de/  |

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Re: [PATCH 2/2] mini2440: Consider correct NAND page size for boot.

[Juergen Beisert]

zoltan@bendor.com.au wrote:
> On Tue, 22 Feb 2011, Juergen Beisert wrote:
> > From: Juergen Beisert <juergen@kreuzholzen.de>
> >
> > When booting from NAND, its important to know the correct page size.
>
> Isn't that info available as soon as SteppingStone sucked in the first 4K
> into the internal SRAM?
>
> As far as I can follow the s3c2440 manual, bit 0 and the read-only bits 1
> to 3 of the NFCONF register convey that information and these bits are set
> by sampling a few GPIO (NCON and GPG13-GPG15) pins at reset. Supposedly
> these pins are pulled up/low during reset so that SteppingStone itself can
> read the boot code from the NAND.
>
> What am I missing?

Hmm, good idea. I will try it. Thanks for the hint.

jbe

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | Phone: +49-8766-939 228     |
Vertretung Sued/Muenchen, Germany             | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686              | http://www.pengutronix.de/  |

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Re: [PATCH 2/2] mini2440: Consider correct NAND page size for boot.

[zoltan]

On Tue, 22 Feb 2011, Juergen Beisert wrote:

> From: Juergen Beisert <juergen@kreuzholzen.de>
>
> When booting from NAND, its important to know the correct page size.

Isn't that info available as soon as SteppingStone sucked in the first 4K
into the internal SRAM?

As far as I can follow the s3c2440 manual, bit 0 and the read-only bits 1
to 3 of the NFCONF register convey that information and these bits are set
by sampling a few GPIO (NCON and GPG13-GPG15) pins at reset. Supposedly
these pins are pulled up/low during reset so that SteppingStone itself can
read the boot code from the NAND.

What am I missing?

Zoltan


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[PATCH 2/2] mini2440: Consider correct NAND page size for boot.

[Juergen Beisert]

From: Juergen Beisert <juergen@kreuzholzen.de>

When booting from NAND, its important to know the correct page size.

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
---
 arch/arm/boards/mini2440/mini2440.c |   22 +++++++++++++++++++++-
 arch/arm/mach-s3c24xx/Kconfig       |   25 +++++++++++++++++++++++++
 2 files changed, 46 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 6842a79..d710e6d 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -279,9 +279,20 @@ static int mini2440_devices_init(void)
 device_initcall(mini2440_devices_init);
 
 #ifdef CONFIG_S3C24XX_NAND_BOOT
+/*
+ * To make barebox booting from NAND the page size must be known, as
+ * there is no way to autodetect it at this early point of boot time.
+ */
+#ifdef CONFIG_MACH_MINI2440_NAND_512B_PAGE_SIZE
+# define NAND_PAGE_SIZE 512
+#endif
+#ifdef CONFIG_MACH_MINI2440_NAND_2048B_PAGE_SIZE
+# define NAND_PAGE_SIZE 2048
+#endif
+
 void __bare_init nand_boot(void)
 {
-	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512);
+	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, NAND_PAGE_SIZE);
 }
 #endif
 
@@ -388,6 +399,15 @@ Using the default configuration:
 make ARCH=arm mini2440_defconfig
 @endcode
 
+To make barebox booting from NAND you must define the page size of the NAND
+in use on your mini2440. Run the menuconfig
+
+@code
+make ARCH=arm menuconfig
+@endcode
+
+and select the corresponding NAND device in the 'Board specific settings' menu.
+
 Build the binary image:
 
 @code
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 33d230c..eaa955f 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -67,6 +67,31 @@ config MACH_A9M2410DEV
 
 endchoice
 
+choice
+	prompt "NAND flash size"
+	depends on MACH_MINI2440
+
+config MACH_MINI2440_NAND_512B_PAGE_SIZE
+	bool
+	prompt "is 64 MiB or less"
+	help
+	  Select this if your mini2440 is shipped with a NAND flash with 64 MiB
+	  or less in size. This is true for the Samsung 'K9F1208U0C' device.
+	  Or select this entry, if you are sure, your NAND comes with a page
+	  size of 512 bytes.
+
+config MACH_MINI2440_NAND_2048B_PAGE_SIZE
+	bool
+	prompt "is 128 MiB or more"
+	help
+	  Select this if your mini2440 is shipped with a NAND flash with
+	  128 MiB or more in size. This is true for the Samsung 'K9F1G08UOB',
+	  'K9F2G08UOB' or 'K9K8G08U0A' devices.
+	  Or select this entry, if you are sure, your NAND comes with a page
+	  size of 2048 bytes.
+
+endchoice
+
 endmenu
 
 menu "S3C24X0 Features              "
-- 
1.7.2.3


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