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From: Juergen Beisert <jbe@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Juergen Beisert <juergen@kreuzholzen.de>
Subject: [PATCH 1/5] mini2440: Add more info about possible SDRAM and flash devices
Date: Sun,  6 Mar 2011 22:53:14 +0100	[thread overview]
Message-ID: <1299448398-5672-2-git-send-email-jbe@pengutronix.de> (raw)
In-Reply-To: <1299448398-5672-1-git-send-email-jbe@pengutronix.de>

From: Juergen Beisert <juergen@kreuzholzen.de>

It seems there are various combinations of the mini2440 in the wild. Not only
the SDRAM differ, but more important the NAND also differs.

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
---
 arch/arm/boards/mini2440/mini2440.c |   54 ++++++++++++++++++++++++----------
 1 files changed, 38 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index ab309a0..6842a79 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -316,23 +316,45 @@ This system is based on a Samsung S3C2440 CPU. The card is shipped with:
 - 12 MHz crystal reference
 - 32.768 kHz crystal reference
 - SDRAM 64 MiB (one bank only)
-   - HY57V561620 (two devices for 64 MiB to form a 32 bit bus)
-     - 4M x 16bit x 4 Banks Mobile SDRAM
-     - 8192 refresh cycles / 64 ms
-     - CL2\@100 MHz
-     - 133 MHz max
-     - collumn address size is 9 bits
-     - row address size is 13 bits
-   - MT48LC16M16 (two devices for 64 MiB to form a 32 bit bus)
-     - 4M x 16bit x 4 Banks Mobile SDRAM
-     - commercial & industrial type
-     - 8192 refresh cycles / 64 ms
-     - CL2\@100 MHz
-     - 133 MHz max
-     - collumn address size is 9 bits
-     - row address size is 13 bits
+   - Hynix SDRAM
+    - HY57V561620FTP-H (two devices for 64 MiB to form a 32 bit bus)
+      - 4M x 16bit x 4 Banks Mobile SDRAM
+      - 8192 refresh cycles / 64 ms
+      - CL2\@100 MHz
+      - 133 MHz max
+      - collumn address size is 9 bits
+      - row address size is 13 bits
+   - Micron SDRAM
+    - MT48LC16M16A2-75IT (two devices for 64 MiB to form a 32 bit bus)
+    - MT48LC16M16A2-7E (two devices for 64 MiB to form a 32 bit bus)
+      - 4M x 16bit x 4 Banks Mobile SDRAM
+      - commercial & industrial type
+      - 8192 refresh cycles / 64 ms
+      - CL2\@100 MHz
+      - 133 MHz max
+      - collumn address size is 9 bits
+      - row address size is 13 bits
 - NAND Flash 128MiB...1GiB
-   - K9Fxx08
+   - K9F1208U0C
+      - VID: 0xec, DID: 0x76
+      - Samsung/64MiB 3,3V 8-bit
+      - 512 + 8 bytes per page
+      - 16 kiB block size
+   - K9F1G08UOB
+      - VID: 0xec, DID: 0xf1
+      - Samsung/128MiB 3,3V 8-bit
+      - 2048 + 64 bytes per page
+      - 128 kiB block size
+   - K9F2G08UOB
+      - VID: 0xec, DID: 0xda
+      - Samsung/256MiB 3,3V 8-bit
+      - 2048 + 64 bytes per page
+      - 128 kiB block size
+   - K9K8G08U0A
+      - VID: 0xec, DID: 0xd3
+      - Samsung/1GiB 3,3V 8-bit
+      - 2048 + 64 bytes per page
+      - 128 kiB block size
 - NOR Flash (up to 22 address lines available)
    - AM29LV160DB, 2 MiB
    - SST39VF1601, 2 MiB
-- 
1.7.2.3


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  reply	other threads:[~2011-03-06 21:53 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-03-06 21:53 [RFC/PATCH v2] S3C24xx: NAND management changes to support booting from NAND Juergen Beisert
2011-03-06 21:53 ` Juergen Beisert [this message]
2011-03-06 21:53 ` [PATCH 2/5] mini2440: Consider correct NAND page size for boot Juergen Beisert
2011-03-06 21:53 ` [PATCH 3/5] S3C2440/NAND: Fix page address generation Juergen Beisert
2011-03-06 21:53 ` [PATCH 4/5] S3C2440/NAND: Re-enable the controller after NAND boot test Juergen Beisert
2011-03-06 21:53 ` [PATCH 5/5] S3C2440/NAND: Fix typo Juergen Beisert
2011-03-07  9:18 ` [RFC/PATCH v2] S3C24xx: NAND management changes to support booting from NAND Juergen Beisert
2011-03-07  9:40   ` Baruch Siach
2011-03-07 10:37     ` Juergen Beisert

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