[RFC/PATCH v2] S3C24xx: NAND management changes to support booting from NAND

[RFC/PATCH v2] S3C24xx: NAND management changes to support booting from NAND

[Juergen Beisert]

This is revision two of my patch series to make the mini2440 booting from NAND.
This seems somehow tricky: The mini2440 with a 64 MiB NAND works fine here,
but the one with 128 MiB does currently boot only.
In the first patch series where some errors in page address calculation, so
they cannot work. This patch series might do it in a correct manner, but now
only tested on 64 MiB and 128 MiB NAND. At least booting from NAND is now
working also from 128 MiB. But the ECC handling fails, and I have no idea
whats wrong now: Reading the environment fails with 'err: -74'...

Comments and ideas are welcome.

Juergen


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[PATCH 1/5] mini2440: Add more info about possible SDRAM and flash devices

[Juergen Beisert]

From: Juergen Beisert <juergen@kreuzholzen.de>

It seems there are various combinations of the mini2440 in the wild. Not only
the SDRAM differ, but more important the NAND also differs.

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
---
 arch/arm/boards/mini2440/mini2440.c |   54 ++++++++++++++++++++++++----------
 1 files changed, 38 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index ab309a0..6842a79 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -316,23 +316,45 @@ This system is based on a Samsung S3C2440 CPU. The card is shipped with:
 - 12 MHz crystal reference
 - 32.768 kHz crystal reference
 - SDRAM 64 MiB (one bank only)
-   - HY57V561620 (two devices for 64 MiB to form a 32 bit bus)
-     - 4M x 16bit x 4 Banks Mobile SDRAM
-     - 8192 refresh cycles / 64 ms
-     - CL2\@100 MHz
-     - 133 MHz max
-     - collumn address size is 9 bits
-     - row address size is 13 bits
-   - MT48LC16M16 (two devices for 64 MiB to form a 32 bit bus)
-     - 4M x 16bit x 4 Banks Mobile SDRAM
-     - commercial & industrial type
-     - 8192 refresh cycles / 64 ms
-     - CL2\@100 MHz
-     - 133 MHz max
-     - collumn address size is 9 bits
-     - row address size is 13 bits
+   - Hynix SDRAM
+    - HY57V561620FTP-H (two devices for 64 MiB to form a 32 bit bus)
+      - 4M x 16bit x 4 Banks Mobile SDRAM
+      - 8192 refresh cycles / 64 ms
+      - CL2\@100 MHz
+      - 133 MHz max
+      - collumn address size is 9 bits
+      - row address size is 13 bits
+   - Micron SDRAM
+    - MT48LC16M16A2-75IT (two devices for 64 MiB to form a 32 bit bus)
+    - MT48LC16M16A2-7E (two devices for 64 MiB to form a 32 bit bus)
+      - 4M x 16bit x 4 Banks Mobile SDRAM
+      - commercial & industrial type
+      - 8192 refresh cycles / 64 ms
+      - CL2\@100 MHz
+      - 133 MHz max
+      - collumn address size is 9 bits
+      - row address size is 13 bits
 - NAND Flash 128MiB...1GiB
-   - K9Fxx08
+   - K9F1208U0C
+      - VID: 0xec, DID: 0x76
+      - Samsung/64MiB 3,3V 8-bit
+      - 512 + 8 bytes per page
+      - 16 kiB block size
+   - K9F1G08UOB
+      - VID: 0xec, DID: 0xf1
+      - Samsung/128MiB 3,3V 8-bit
+      - 2048 + 64 bytes per page
+      - 128 kiB block size
+   - K9F2G08UOB
+      - VID: 0xec, DID: 0xda
+      - Samsung/256MiB 3,3V 8-bit
+      - 2048 + 64 bytes per page
+      - 128 kiB block size
+   - K9K8G08U0A
+      - VID: 0xec, DID: 0xd3
+      - Samsung/1GiB 3,3V 8-bit
+      - 2048 + 64 bytes per page
+      - 128 kiB block size
 - NOR Flash (up to 22 address lines available)
    - AM29LV160DB, 2 MiB
    - SST39VF1601, 2 MiB
-- 
1.7.2.3


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[PATCH 2/5] mini2440: Consider correct NAND page size for boot.

[Juergen Beisert]

From: Juergen Beisert <juergen@kreuzholzen.de>

When booting from NAND, its important to know the correct page size. When
the NAND is used as the boot source, four dedicated pins are used to configure
the correct page size and address cycles. These pins can be read back in one
of the NFC registers to parametrize the load function.

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
---
 arch/arm/boards/a9m2410/a9m2410.c                 |    2 +-
 arch/arm/boards/a9m2440/a9m2440.c                 |    2 +-
 arch/arm/boards/mini2440/mini2440.c               |    2 +-
 arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h |    2 +-
 drivers/mtd/nand/nand_s3c2410.c                   |   44 ++++++++++++++------
 5 files changed, 35 insertions(+), 17 deletions(-)

diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index 57d8fa3..8cbaec5 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -176,7 +176,7 @@ device_initcall(a9m2410_devices_init);
 #ifdef CONFIG_S3C24XX_NAND_BOOT
 void __bare_init nand_boot(void)
 {
-	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512);
+	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
 }
 #endif
 
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 764cd65..39b5276 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -182,7 +182,7 @@ device_initcall(a9m2440_devices_init);
 #ifdef CONFIG_S3C24XX_NAND_BOOT
 void __bare_init nand_boot(void)
 {
-	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512);
+	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
 }
 #endif
 
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 6842a79..9a7fe68 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -281,7 +281,7 @@ device_initcall(mini2440_devices_init);
 #ifdef CONFIG_S3C24XX_NAND_BOOT
 void __bare_init nand_boot(void)
 {
-	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512);
+	s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
 }
 #endif
 
diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h b/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h
index d06287e..7610b4e 100644
--- a/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h
+++ b/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h
@@ -19,7 +19,7 @@
  */
 
 #ifdef CONFIG_S3C24XX_NAND_BOOT
-extern void s3c24x0_nand_load_image(void*, int, int, int);
+extern void s3c24x0_nand_load_image(void*, int, int);
 #endif
 
 /**
diff --git a/drivers/mtd/nand/nand_s3c2410.c b/drivers/mtd/nand/nand_s3c2410.c
index df0b7c1..08330ed 100644
--- a/drivers/mtd/nand/nand_s3c2410.c
+++ b/drivers/mtd/nand/nand_s3c2410.c
@@ -497,7 +497,8 @@ static void __nand_boot_init wait_for_completion(void __iomem *host)
 		;
 }
 
-static void __nand_boot_init nfc_addr(void __iomem *host, uint32_t offs)
+static void __nand_boot_init nfc_addr(void __iomem *host, uint32_t offs,
+					int ps, int c)
 {
 	send_addr(host, offs & 0xff);
 	send_addr(host, (offs >> 9) & 0xff);
@@ -510,24 +511,42 @@ static void __nand_boot_init nfc_addr(void __iomem *host, uint32_t offs)
  * @param[out] dest Pointer to target area (in SDRAM)
  * @param[in] size Bytes to read from NAND device
  * @param[in] page Start page to read from
- * @param[in] pagesize Size of each page in the NAND
  *
  * This function must be located in the first 4kiB of the barebox image
- * (guess why). When this routine is running the SDRAM is up and running
- * and it runs from the correct address (physical=linked address).
- * TODO Could we access the platform data from the boardfile?
- * Due to it makes no sense this function does not return in case of failure.
+ * (guess why).
  */
-void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page, int pagesize)
+void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page)
 {
 	void __iomem *host = (void __iomem *)S3C24X0_NAND_BASE;
-	int i;
+	unsigned pagesize;
+	int i, cycle;
 
 	/*
 	 * Reenable the NFC and use the default (but slow) access
 	 * timing or the board specific setting if provided.
 	 */
 	enable_nand_controller(host, BOARD_DEFAULT_NAND_TIMING);
+
+	/* use the current NAND hardware configuration */
+	switch (readl(S3C24X0_NAND_BASE) & 0xf) {
+	case 0x6:	/* 8 bit, 4 addr cycles, 512 bpp, normal NAND */
+		pagesize = 512;
+		cycle = 4;
+		break;
+	case 0xc:	/* 8 bit, 4 addr cycles, 2048 bpp, advanced NAND */
+		pagesize = 2048;
+		cycle = 4;
+		break;
+	case 0xe:	/* 8 bit, 5 addr cycles, 2048 bpp, advanced NAND */
+		pagesize = 2048;
+		cycle = 5;
+		break;
+	default:
+		/* we cannot output an error message here :-( */
+		disable_nand_controller(host);
+		return;
+	}
+
 	enable_cs(host);
 
 	/* Reset the NAND device */
@@ -538,7 +557,7 @@ void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page, in
 	do {
 		enable_cs(host);
 		send_cmd(host, NAND_CMD_READ0);
-		nfc_addr(host, page * pagesize);
+		nfc_addr(host, page * pagesize, pagesize, cycle);
 		wait_for_completion(host);
 		/* copy one page (do *not* use readsb() here!)*/
 		for (i = 0; i < pagesize; i++)
@@ -560,22 +579,21 @@ void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page, in
 static int do_nand_boot_test(struct command *cmdtp, int argc, char *argv[])
 {
 	void *dest;
-	int size, pagesize;
+	int size;
 
 	if (argc < 3)
 		return COMMAND_ERROR_USAGE;
 
 	dest = (void *)strtoul_suffix(argv[1], NULL, 0);
 	size = strtoul_suffix(argv[2], NULL, 0);
-	pagesize = strtoul_suffix(argv[3], NULL, 0);
 
-	s3c24x0_nand_load_image(dest, size, 0, pagesize);
+	s3c24x0_nand_load_image(dest, size, 0);
 
 	return 0;
 }
 
 static const __maybe_unused char cmd_nand_boot_test_help[] =
-"Usage: nand_boot_test <dest> <size> <pagesize>\n";
+"Usage: nand_boot_test <dest> <size>\n";
 
 BAREBOX_CMD_START(nand_boot_test)
 	.cmd		= do_nand_boot_test,
-- 
1.7.2.3


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[PATCH 3/5] S3C2440/NAND: Fix page address generation

[Juergen Beisert]

From: Juergen Beisert <juergen@kreuzholzen.de>

A NAND page address consist of a collumn and row part. It depends on the NAND
type, how to handle both parts correctly. This patch tries to generate the
page address from a given page offset correctly. It also forces the collumn
part to '0', as the NAND boot routine reads full pages only.

Note: Page offset to page address conversion does only work for 512 or 2048
bytes per page NAND types.

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
---
 drivers/mtd/nand/nand_s3c2410.c |   30 ++++++++++++++++++++++++++----
 1 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/nand_s3c2410.c b/drivers/mtd/nand/nand_s3c2410.c
index 08330ed..e298771 100644
--- a/drivers/mtd/nand/nand_s3c2410.c
+++ b/drivers/mtd/nand/nand_s3c2410.c
@@ -497,13 +497,35 @@ static void __nand_boot_init wait_for_completion(void __iomem *host)
 		;
 }
 
+/**
+ * Convert a page offset into a page address for the NAND
+ * @param host Where to write the address to
+ * @param offs Page's offset in the NAND
+ * @param ps Page size (512 or 2048)
+ * @param c Address cycle count (3, 4 or 5)
+ *
+ * Uses the offset of the page to generate a page address into the NAND. This
+ * differs when using a 512 byte or 2048 bytes per page NAND.
+ * The collumn part of the page address to be generated is always forced to '0'.
+ */
 static void __nand_boot_init nfc_addr(void __iomem *host, uint32_t offs,
 					int ps, int c)
 {
-	send_addr(host, offs & 0xff);
-	send_addr(host, (offs >> 9) & 0xff);
-	send_addr(host, (offs >> 17) & 0xff);
-	send_addr(host, (offs >> 25) & 0xff);
+	send_addr(host, 0); /* collumn part 1 */
+
+	if (ps == 512) {
+		send_addr(host, offs >> 9);
+		send_addr(host, offs >> 17);
+		if (c > 3)
+			send_addr(host, offs >> 25);
+	} else {
+		send_addr(host, 0); /* collumn part 2 */
+		send_addr(host, offs >> 11);
+		send_addr(host, offs >> 19);
+		if (c > 4)
+			send_addr(host, offs >> 27);
+		send_cmd(host, NAND_CMD_READSTART);
+	}
 }
 
 /**
-- 
1.7.2.3


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[PATCH 4/5] S3C2440/NAND: Re-enable the controller after NAND boot test

[Juergen Beisert]

From: Juergen Beisert <juergen@kreuzholzen.de>

After running the 'nand_boot_test' command, any usage of the NAND fails with
an IO error. This happens due to the load routine disables the NAND controller
after loading the image.

This patch re-enables the NAND controller again after running the test.

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
---
 drivers/mtd/nand/nand_s3c2410.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/nand_s3c2410.c b/drivers/mtd/nand/nand_s3c2410.c
index e298771..7d7ff46 100644
--- a/drivers/mtd/nand/nand_s3c2410.c
+++ b/drivers/mtd/nand/nand_s3c2410.c
@@ -611,6 +611,10 @@ static int do_nand_boot_test(struct command *cmdtp, int argc, char *argv[])
 
 	s3c24x0_nand_load_image(dest, size, 0);
 
+	/* re-enable the controller again, as this was a test only */
+	enable_nand_controller((void *)S3C24X0_NAND_BASE,
+				BOARD_DEFAULT_NAND_TIMING);
+
 	return 0;
 }
 
-- 
1.7.2.3


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[PATCH 5/5] S3C2440/NAND: Fix typo

[Juergen Beisert]

From: Juergen Beisert <juergen@kreuzholzen.de>

This routine loops over 'pages', not 'blocks'.

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
---
 drivers/mtd/nand/nand_s3c2410.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/nand/nand_s3c2410.c b/drivers/mtd/nand/nand_s3c2410.c
index 7d7ff46..5a607b4 100644
--- a/drivers/mtd/nand/nand_s3c2410.c
+++ b/drivers/mtd/nand/nand_s3c2410.c
@@ -529,7 +529,7 @@ static void __nand_boot_init nfc_addr(void __iomem *host, uint32_t offs,
 }
 
 /**
- * Load a sequential count of blocks from the NAND into memory
+ * Load a sequential count of pages from the NAND into memory
  * @param[out] dest Pointer to target area (in SDRAM)
  * @param[in] size Bytes to read from NAND device
  * @param[in] page Start page to read from
-- 
1.7.2.3


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Re: [RFC/PATCH v2] S3C24xx: NAND management changes to support booting from NAND

[Juergen Beisert]

Juergen Beisert wrote:
> This is revision two of my patch series to make the mini2440 booting from
> NAND. This seems somehow tricky: The mini2440 with a 64 MiB NAND works fine
> here, but the one with 128 MiB does currently boot only.
> In the first patch series where some errors in page address calculation, so
> they cannot work. This patch series might do it in a correct manner, but
> now only tested on 64 MiB and 128 MiB NAND. At least booting from NAND is
> now working also from 128 MiB. But the ECC handling fails, and I have no
> idea whats wrong now: Reading the environment fails with 'err: -74'...

Here the main question:
- what is the difference in ECC handling in the S3C2440 CPU when using
  a "small page" or a "large page" NAND?
  "Small page" ECC seems to work, but "large page" ECC fails. Anyone here with
  more experience with S3C2440/NAND? The Linux driver works well on the large
  page NANDs, but not the barebox's one.

jbe

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | Phone: +49-8766-939 228     |
Vertretung Sued/Muenchen, Germany             | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686              | http://www.pengutronix.de/  |

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Re: [RFC/PATCH v2] S3C24xx: NAND management changes to support booting from NAND

[Baruch Siach]

Hi Juergen,

On Mon, Mar 07, 2011 at 10:18:00AM +0100, Juergen Beisert wrote:
> Juergen Beisert wrote:
> > This is revision two of my patch series to make the mini2440 booting from
> > NAND. This seems somehow tricky: The mini2440 with a 64 MiB NAND works fine
> > here, but the one with 128 MiB does currently boot only.
> > In the first patch series where some errors in page address calculation, so
> > they cannot work. This patch series might do it in a correct manner, but
> > now only tested on 64 MiB and 128 MiB NAND. At least booting from NAND is
> > now working also from 128 MiB. But the ECC handling fails, and I have no
> > idea whats wrong now: Reading the environment fails with 'err: -74'...
> 
> Here the main question:
> - what is the difference in ECC handling in the S3C2440 CPU when using
>   a "small page" or a "large page" NAND?
>   "Small page" ECC seems to work, but "large page" ECC fails. Anyone here with
>   more experience with S3C2440/NAND? The Linux driver works well on the large
>   page NANDs, but not the barebox's one.

I don't have experience with the S3C2440 NAND controller, but I'm working on a 
similar problem in the i.MX NAND controller Linux driver. NAND chips with 2k 
page size work fine, but 4k devices fail in the kernel. The cause for this is 
the wrong nand_ecclayout. In the i.MX case, the .eccpos table was too small 
for the larger ECC table of the 4k devices. This caused a corruption of the 
OOB data at the higher level of the NAND stack. Fixing this requires upgrade 
to a newer kernel (I currently use 2.6.36).

As the nand_s3c2410 Barebox driver (like the kernel one) has only one 
nand_ecclayout struct for the 512 bytes page size, this may be the cause of 
your problem.

I hope this helps.

baruch

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch@tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -

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Re: [RFC/PATCH v2] S3C24xx: NAND management changes to support booting from NAND

[Juergen Beisert]

Baruch Siach wrote:
> On Mon, Mar 07, 2011 at 10:18:00AM +0100, Juergen Beisert wrote:
> > Juergen Beisert wrote:
> > > This is revision two of my patch series to make the mini2440 booting
> > > from NAND. This seems somehow tricky: The mini2440 with a 64 MiB NAND
> > > works fine here, but the one with 128 MiB does currently boot only.
> > > In the first patch series where some errors in page address
> > > calculation, so they cannot work. This patch series might do it in a
> > > correct manner, but now only tested on 64 MiB and 128 MiB NAND. At
> > > least booting from NAND is now working also from 128 MiB. But the ECC
> > > handling fails, and I have no idea whats wrong now: Reading the
> > > environment fails with 'err: -74'...
> >
> > Here the main question:
> > - what is the difference in ECC handling in the S3C2440 CPU when using
> >   a "small page" or a "large page" NAND?
> >   "Small page" ECC seems to work, but "large page" ECC fails. Anyone here
> > with more experience with S3C2440/NAND? The Linux driver works well on
> > the large page NANDs, but not the barebox's one.
>
> I don't have experience with the S3C2440 NAND controller, but I'm working
> on a similar problem in the i.MX NAND controller Linux driver. NAND chips
> with 2k page size work fine, but 4k devices fail in the kernel. The cause
> for this is the wrong nand_ecclayout. In the i.MX case, the .eccpos table
> was too small for the larger ECC table of the 4k devices. This caused a
> corruption of the OOB data at the higher level of the NAND stack. Fixing
> this requires upgrade to a newer kernel (I currently use 2.6.36).
>
> As the nand_s3c2410 Barebox driver (like the kernel one) has only one
> nand_ecclayout struct for the 512 bytes page size, this may be the cause of
> your problem.
>
> I hope this helps.

\o/ The S3C2440 is using a 4 bytes ECC for 2048 sized page NANDs. After 
changing it, barebox is now able to write and read the environment.

Thanks,
jbe

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | Phone: +49-8766-939 228     |
Vertretung Sued/Muenchen, Germany             | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686              | http://www.pengutronix.de/  |

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