* [PATCH] ARM mmu fixes
@ 2011-03-07 18:01 Sascha Hauer
2011-03-07 18:01 ` [PATCH 1/3] ARM v7: Fix broken mmu initialization Sascha Hauer
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Sascha Hauer @ 2011-03-07 18:01 UTC (permalink / raw)
To: barebox
Hi,
Here are some ARM mmu fixes. Patch 1/3 fixes a brown paper bag bug and
is an urgent fix for all armv7 users using the mmu. We still have this
lzo issue in the latest release requiring a stable release, this patch
will be part of it also.
Sascha Hauer (3):
ARM v7: Fix broken mmu initialization
ARM v7: Fix typos in cache-armv7.S
ARM: use memalign to allocate page table
arch/arm/cpu/cache-armv7.S | 5 ++---
arch/arm/cpu/mmu.c | 3 +--
2 files changed, 3 insertions(+), 5 deletions(-)
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/3] ARM v7: Fix broken mmu initialization
2011-03-07 18:01 [PATCH] ARM mmu fixes Sascha Hauer
@ 2011-03-07 18:01 ` Sascha Hauer
2011-03-07 18:03 ` Sascha Hauer
2011-03-07 18:01 ` [PATCH 2/3] ARM v7: Fix typos in cache-armv7.S Sascha Hauer
2011-03-07 18:01 ` [PATCH 3/3] ARM: use memalign to allocate page table Sascha Hauer
2 siblings, 1 reply; 5+ messages in thread
From: Sascha Hauer @ 2011-03-07 18:01 UTC (permalink / raw)
To: barebox
The armv7 specific __mmu_cache_on function accidently sets
the page table pointer with the unitialized value of r3. It seems
that often enough r3 still held the correct value from a previous
call to mmu_init allowing this bug to remain uncovered for longer.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/cache-armv7.S | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index 79bc243..538ab28 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -20,7 +20,6 @@ ENTRY(__mmu_cache_on)
#endif
orrne r0, r0, #1 @ MMU enabled
movne r1, #-1
- mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
#endif
mcr p15, 0, r0, c1, c0, 0 @ load control register
--
1.7.2.3
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/3] ARM v7: Fix typos in cache-armv7.S
2011-03-07 18:01 [PATCH] ARM mmu fixes Sascha Hauer
2011-03-07 18:01 ` [PATCH 1/3] ARM v7: Fix broken mmu initialization Sascha Hauer
@ 2011-03-07 18:01 ` Sascha Hauer
2011-03-07 18:01 ` [PATCH 3/3] ARM: use memalign to allocate page table Sascha Hauer
2 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2011-03-07 18:01 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/cache-armv7.S | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index 538ab28..5b8491e 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -47,7 +47,7 @@ ENTRY(__mmu_cache_off)
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
mov pc, r12
-ENDPROC(__mmu_cache_on)
+ENDPROC(__mmu_cache_off)
__BARE_INIT
ENTRY(__mmu_cache_flush)
@@ -97,7 +97,7 @@ skip:
bgt loop1
finished:
ldmfd sp!, {r0-r7, r9-r11}
- mov r10, #0 @ swith back to cache level 0
+ mov r10, #0 @ switch back to cache level 0
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
iflush:
mcr p15, 0, r10, c7, c10, 4 @ DSB
--
1.7.2.3
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 3/3] ARM: use memalign to allocate page table
2011-03-07 18:01 [PATCH] ARM mmu fixes Sascha Hauer
2011-03-07 18:01 ` [PATCH 1/3] ARM v7: Fix broken mmu initialization Sascha Hauer
2011-03-07 18:01 ` [PATCH 2/3] ARM v7: Fix typos in cache-armv7.S Sascha Hauer
@ 2011-03-07 18:01 ` Sascha Hauer
2 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2011-03-07 18:01 UTC (permalink / raw)
To: barebox
We have the proper function for getting aligned memory, so use it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/mmu.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index df664f6..7b5686b 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -31,8 +31,7 @@ void mmu_init(void)
{
int i;
- ttb = xzalloc(0x8000);
- ttb = (void *)(((unsigned long)ttb + 0x4000) & ~0x3fff);
+ ttb = memalign(0x10000, 0x4000);
/* Set the ttb register */
asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb) /*:*/);
--
1.7.2.3
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] ARM v7: Fix broken mmu initialization
2011-03-07 18:01 ` [PATCH 1/3] ARM v7: Fix broken mmu initialization Sascha Hauer
@ 2011-03-07 18:03 ` Sascha Hauer
0 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2011-03-07 18:03 UTC (permalink / raw)
To: barebox; +Cc: Eric BENARD
Eric,
This could well be the cause of your i.MX51 mmu trouble.
Sascha
On Mon, Mar 07, 2011 at 07:01:06PM +0100, Sascha Hauer wrote:
> The armv7 specific __mmu_cache_on function accidently sets
> the page table pointer with the unitialized value of r3. It seems
> that often enough r3 still held the correct value from a previous
> call to mmu_init allowing this bug to remain uncovered for longer.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/cpu/cache-armv7.S | 1 -
> 1 files changed, 0 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
> index 79bc243..538ab28 100644
> --- a/arch/arm/cpu/cache-armv7.S
> +++ b/arch/arm/cpu/cache-armv7.S
> @@ -20,7 +20,6 @@ ENTRY(__mmu_cache_on)
> #endif
> orrne r0, r0, #1 @ MMU enabled
> movne r1, #-1
> - mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
> mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
> #endif
> mcr p15, 0, r0, c1, c0, 0 @ load control register
> --
> 1.7.2.3
>
>
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2011-03-07 18:01 [PATCH] ARM mmu fixes Sascha Hauer
2011-03-07 18:01 ` [PATCH 1/3] ARM v7: Fix broken mmu initialization Sascha Hauer
2011-03-07 18:03 ` Sascha Hauer
2011-03-07 18:01 ` [PATCH 2/3] ARM v7: Fix typos in cache-armv7.S Sascha Hauer
2011-03-07 18:01 ` [PATCH 3/3] ARM: use memalign to allocate page table Sascha Hauer
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