updates for imx-esdhc controller

updates for imx-esdhc controller

[Sascha Hauer]

The following patches contain some fixes for the i.MX esdhc controller.
The first one i'd like to put into the upcoming release, the others
can wait some time for the upcoming i.MX53 support.

Sascha

Sascha Hauer (3):
      MCI imx-esdhc: Fix cache flush/inval for multi block support
      MCI imx-esdhc: Fix multiblock transfers on i.MX53
      MCI imx-esdhc: remove unnecessary large delay

 drivers/mci/imx-esdhc.c |   33 +++++++++++++++++----------------
 1 files changed, 17 insertions(+), 16 deletions(-)


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[PATCH 1/3] MCI imx-esdhc: Fix cache flush/inval for multi block support

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/imx-esdhc.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index 2937156..7595a93 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -257,10 +257,10 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
 			return err;
 		if (data->flags & MMC_DATA_WRITE) {
 			dma_flush_range((unsigned long)data->src,
-				(unsigned long)(data->src + 512));
+				(unsigned long)(data->src + data->blocks * 512));
 		} else
 			dma_clean_range((unsigned long)data->src,
-				(unsigned long)(data->src + 512));
+				(unsigned long)(data->src + data->blocks * 512));
 
 	}
 
@@ -317,7 +317,7 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
 
 		if (data->flags & MMC_DATA_READ) {
 			dma_inv_range((unsigned long)data->dest,
-					(unsigned long)(data->dest + 512));
+					(unsigned long)(data->dest + data->blocks * 512));
 		}
 #endif
 	}
-- 
1.7.5.3


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[PATCH 2/3] MCI imx-esdhc: Fix multiblock transfers on i.MX53

[Sascha Hauer]

In the Kernel this bug is described like this:

> The CMDTYPE of the CMD register (offset 0xE) should be set to
> "11" when the STOP CMD12 is issued on imx53 to abort one
> open ended multi-blk IO. Otherwise the TC INT wouldn't
> be generated.
> In exact block transfer, the controller doesn't complete the
> operations automatically as required at the end of the
> transfer and remains on hold if the abort command is not sent.
> As a result, the TC flag is not asserted and SW  received timeout
> exeception. Bit1 of Vendor Spec registor is used to fix it.

We do not use exact block transfers in barebox, so we only need
the first part of this fix.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/imx-esdhc.c |   21 +++++++++++++--------
 1 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index 7595a93..27ec4ed 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -35,6 +35,7 @@
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <mach/clock.h>
+#include <mach/generic.h>
 
 #include "imx-esdhc.h"
 
@@ -75,6 +76,8 @@ struct fsl_esdhc_host {
 
 #define to_fsl_esdhc(mci)	container_of(mci, struct fsl_esdhc_host, mci)
 
+#define  SDHCI_CMD_ABORTCMD (0xC0 << 16)
+
 /* Return the XFERTYP flags for a given command and data packet */
 u32 esdhc_xfertyp(struct mci_cmd *cmd, struct mci_data *data)
 {
@@ -104,6 +107,8 @@ u32 esdhc_xfertyp(struct mci_cmd *cmd, struct mci_data *data)
 		xfertyp |= XFERTYP_RSPTYP_48_BUSY;
 	else if (cmd->resp_type & MMC_RSP_PRESENT)
 		xfertyp |= XFERTYP_RSPTYP_48;
+	if (cpu_is_mx53() && cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+		xfertyp |= SDHCI_CMD_ABORTCMD;
 
 	return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 }
@@ -233,14 +238,6 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
 
 	esdhc_write32(&regs->irqstat, -1);
 
-	/* Wait for the bus to be idle */
-	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
-			(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
-		;
-
-	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
-		;
-
 	/* Wait at least 8 SD clock cycles before the next command */
 	/*
 	 * Note: This is way more than 8 cycles, but 1ms seems to
@@ -324,6 +321,14 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
 
 	esdhc_write32(&regs->irqstat, -1);
 
+	/* Wait for the bus to be idle */
+	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
+			(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
+		;
+
+	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
+		;
+
 	return 0;
 }
 
-- 
1.7.5.3


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[PATCH 3/3] MCI imx-esdhc: remove unnecessary large delay

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/imx-esdhc.c |    6 +-----
 1 files changed, 1 insertions(+), 5 deletions(-)

diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index 27ec4ed..f592e1e 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -239,11 +239,7 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
 	esdhc_write32(&regs->irqstat, -1);
 
 	/* Wait at least 8 SD clock cycles before the next command */
-	/*
-	 * Note: This is way more than 8 cycles, but 1ms seems to
-	 * resolve timing issues with some cards
-	 */
-	udelay(1000);
+	udelay(1);
 
 	/* Set up for a data transfer if we have one */
 	if (data) {
-- 
1.7.5.3


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