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* [PATCH 1/2] mach-imx: iim: clarify documentation
@ 2011-09-28  9:16 Paul Fertser
  2011-09-28  9:16 ` [PATCH 2/2] mach-imx: iim: cosmetic changes to the code to make it easier to follow Paul Fertser
  0 siblings, 1 reply; 2+ messages in thread
From: Paul Fertser @ 2011-09-28  9:16 UTC (permalink / raw)
  To: barebox; +Cc: Paul Fertser

This adds additional Kconfig help to clarify the way to use barebox
for eFuses handling.

Signed-off-by: Paul Fertser <fercerpav@gmail.com>
---
 arch/arm/mach-imx/Kconfig |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 8dc6a24..8d5bd74 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -497,6 +497,12 @@ config IMX_IIM
 	  Device driver for the IC Identification Module (IIM) fusebox. Use the 
 	  regular md/mw commands to program and read the fusebox.
 
+	  Fuses are grouped in "rows", 8 bits per row. When using md/mw commands,
+	  employ the -b switch and consider the region to be specifying the "Fuse
+	  Row Index" rather than "Fuse Row Offset" (which is FRI * 4). You should
+	  consult the documentation for your chip for more elaborate description,
+	  including the eFuse map, e.g. see AN3682 for i.MX25.
+
 config IMX_IIM_FUSE_BLOW
 	bool "IIM fuses blow support"
 	depends on IMX_IIM
@@ -507,6 +513,10 @@ config IMX_IIM_FUSE_BLOW
 	  Warning: blown fuses can not be unblown. Using this option may damage
 	  your CPU, or make it unbootalbe. Use with care.
 
+	  Before being actually able to blow the fuses, you need to explicitely
+	  enable it:
+	  	 imx_iim0.permanent_write_enable=1
+
 endmenu
 
 endif
-- 
1.7.3.4


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^ permalink raw reply	[flat|nested] 2+ messages in thread

* [PATCH 2/2] mach-imx: iim: cosmetic changes to the code to make it easier to follow
  2011-09-28  9:16 [PATCH 1/2] mach-imx: iim: clarify documentation Paul Fertser
@ 2011-09-28  9:16 ` Paul Fertser
  0 siblings, 0 replies; 2+ messages in thread
From: Paul Fertser @ 2011-09-28  9:16 UTC (permalink / raw)
  To: barebox; +Cc: Paul Fertser

This brings consistency to the way variables are named and used
according to the Freescale documentation. Also, since user is
supplying row indicies, and not offsets, it's reasonable to amend the
error message accordingly.

Signed-off-by: Paul Fertser <fercerpav@gmail.com>
---
 arch/arm/mach-imx/iim.c |   20 ++++++++++----------
 1 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-imx/iim.c b/arch/arm/mach-imx/iim.c
index ca89710..85bcfdb 100644
--- a/arch/arm/mach-imx/iim.c
+++ b/arch/arm/mach-imx/iim.c
@@ -51,8 +51,8 @@ static int do_fuse_sense(void __iomem *reg_base, unsigned int bank,
 		return -EINVAL;
 	}
 
-	if (row > 0x3ff) {
-		printf("%s: invalid row offset\n", __func__);
+	if (row > 255) {
+		printf("%s: invalid row index\n", __func__);
 		return -EINVAL;
 	}
 
@@ -61,8 +61,8 @@ static int do_fuse_sense(void __iomem *reg_base, unsigned int bank,
 	writeb(0xfe, reg_base + IIM_ERR);
 
 	/* upper and lower address halves */
-	writeb((bank << 3) | (row >> 7), reg_base + IIM_UA);
-	writeb((row << 1) & 0xf8, reg_base + IIM_LA);
+	writeb((bank << 3) | (row >> 5), reg_base + IIM_UA);
+	writeb((row << 3) & 0xf8, reg_base + IIM_LA);
 
 	/* start fuse sensing */
 	writeb(0x08, reg_base + IIM_FCTL);
@@ -100,7 +100,7 @@ static ssize_t imx_iim_cdev_read(struct cdev *cdev, void *buf, size_t count,
 			int row_val;
 
 			row_val = do_fuse_sense(priv->base,
-				priv->bank, (offset + i) * 4);
+						priv->bank, offset + i);
 			if (row_val < 0)
 				return row_val;
 			((u8 *)buf)[i] = (u8)row_val;
@@ -125,8 +125,8 @@ static int do_fuse_blow(void __iomem *reg_base, unsigned int bank,
 		return -EINVAL;
 	}
 
-	if (row > 0x3ff) {
-		printf("%s: invalid row offset\n", __func__);
+	if (row > 255) {
+		printf("%s: invalid row index\n", __func__);
 		return -EINVAL;
 	}
 
@@ -138,14 +138,14 @@ static int do_fuse_blow(void __iomem *reg_base, unsigned int bank,
 	writeb(0xaa, reg_base + IIM_PREG_P);
 
 	/* upper half address register */
-	writeb((bank << 3) | (row >> 7), reg_base + IIM_UA);
+	writeb((bank << 3) | (row >> 5), reg_base + IIM_UA);
 
 	for (bit = 0; bit < 8; bit++) {
 		if (((value >> bit) & 1) == 0)
 			continue;
 
 		/* lower half address register */
-		writeb(((row << 1) | bit), reg_base + IIM_LA);
+		writeb(((row << 3) | bit), reg_base + IIM_LA);
 
 		/* start fuse programing */
 		writeb(0x71, reg_base + IIM_FCTL);
@@ -193,7 +193,7 @@ static ssize_t imx_iim_cdev_write(struct cdev *cdev, const void *buf, size_t cou
 			int ret;
 
 			ret = do_fuse_blow(priv->base, priv->bank,
-					(offset + i) * 4, ((u8 *)buf)[i]);
+					   offset + i, ((u8 *)buf)[i]);
 			if (ret < 0)
 				return ret;
 		}
-- 
1.7.3.4


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