* [PATCH 2/6] CPUIMX35: enable the watchdog clock asap
2011-12-12 21:19 [PATCH 1/6] i.MX25: fix LD16 & LD17 iomux Eric Bénard
@ 2011-12-12 21:19 ` Eric Bénard
2011-12-12 21:19 ` [PATCH 3/6] CPUIMX51: add ARM errata and enable L2 cache Eric Bénard
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Eric Bénard @ 2011-12-12 21:19 UTC (permalink / raw)
To: barebox
Signed-off-by: Eric Bénard <eric@eukrea.com>
---
arch/arm/boards/eukrea_cpuimx35/lowlevel.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
index a909a87..969c813 100644
--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
@@ -123,6 +123,11 @@ void __bare_init __naked board_init_lowlevel(void)
r |= 0x00000003;
writel(r, ccm_base + CCM_CGR1);
+ /* enable watchdog asap */
+ r = readl(ccm_base + CCM_CGR2);
+ r |= 0x03000000;
+ writel(r, ccm_base + CCM_CGR2);
+
r = readl(IMX_L2CC_BASE + L2X0_AUX_CTRL);
r |= 0x1000;
writel(r, IMX_L2CC_BASE + L2X0_AUX_CTRL);
--
1.7.6.4
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^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 3/6] CPUIMX51: add ARM errata and enable L2 cache
2011-12-12 21:19 [PATCH 1/6] i.MX25: fix LD16 & LD17 iomux Eric Bénard
2011-12-12 21:19 ` [PATCH 2/6] CPUIMX35: enable the watchdog clock asap Eric Bénard
@ 2011-12-12 21:19 ` Eric Bénard
2011-12-13 9:42 ` Sascha Hauer
2011-12-12 21:19 ` [PATCH 4/6] CPUIMX51: fix environement Eric Bénard
` (3 subsequent siblings)
5 siblings, 1 reply; 8+ messages in thread
From: Eric Bénard @ 2011-12-12 21:19 UTC (permalink / raw)
To: barebox
- add ARM errata ID #468414
- enable L2 cache to get better performances
Signed-off-by: Eric Bénard <eric@eukrea.com>
---
arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
index 0b3726f..ee3b0fc 100644
--- a/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
+++ b/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
@@ -57,6 +57,11 @@
board_init_lowlevel:
mov r10, lr
+ /* ARM errata ID #468414 */
+ mrc 15, 0, r1, c1, c0, 1
+ orr r1, r1, #(1 << 5) /* enable L1NEON bit */
+ mcr 15, 0, r1, c1, c0, 1
+
/* explicitly disable L2 cache */
mrc 15, 0, r0, c1, c0, 1
bic r0, r0, #0x2
@@ -76,6 +81,11 @@ board_init_lowlevel:
mcr 15, 1, r0, c9, c0, 2
+ /* enable L2 cache */
+ mrc 15, 0, r0, c1, c0, 1
+ orr r0, r0, #2
+ mcr 15, 0, r0, c1, c0, 1
+
ldr r0, =MX51_CCM_BASE_ADDR
/* Gate of clocks to the peripherals first */
--
1.7.6.4
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^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 3/6] CPUIMX51: add ARM errata and enable L2 cache
2011-12-12 21:19 ` [PATCH 3/6] CPUIMX51: add ARM errata and enable L2 cache Eric Bénard
@ 2011-12-13 9:42 ` Sascha Hauer
0 siblings, 0 replies; 8+ messages in thread
From: Sascha Hauer @ 2011-12-13 9:42 UTC (permalink / raw)
To: Eric Bénard; +Cc: barebox
Hi Eric,
On Mon, Dec 12, 2011 at 10:19:36PM +0100, Eric Bénard wrote:
> - add ARM errata ID #468414
> - enable L2 cache to get better performances
>
> Signed-off-by: Eric Bénard <eric@eukrea.com>
> ---
> arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S | 10 ++++++++++
> 1 files changed, 10 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
> index 0b3726f..ee3b0fc 100644
> --- a/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
> +++ b/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
At the moment arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S and
./arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S are exact copies.
What is being done first in board_init_lowlevel is
- workaround the errata
- configure aux control reg
- dis/enable L2 cache
This is basically the same as being done in mx53_init_lowlevel().
Can we instead add a mx5_init_lowlevel which contains the L2 cache
setting and is called from both mx51_init_lowlevel and mx53_lowlevel?
Sascha
> @@ -57,6 +57,11 @@
> board_init_lowlevel:
> mov r10, lr
>
> + /* ARM errata ID #468414 */
> + mrc 15, 0, r1, c1, c0, 1
> + orr r1, r1, #(1 << 5) /* enable L1NEON bit */
> + mcr 15, 0, r1, c1, c0, 1
> +
> /* explicitly disable L2 cache */
> mrc 15, 0, r0, c1, c0, 1
> bic r0, r0, #0x2
> @@ -76,6 +81,11 @@ board_init_lowlevel:
>
> mcr 15, 1, r0, c9, c0, 2
>
> + /* enable L2 cache */
> + mrc 15, 0, r0, c1, c0, 1
> + orr r0, r0, #2
> + mcr 15, 0, r0, c1, c0, 1
> +
> ldr r0, =MX51_CCM_BASE_ADDR
>
> /* Gate of clocks to the peripherals first */
> --
> 1.7.6.4
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 4/6] CPUIMX51: fix environement
2011-12-12 21:19 [PATCH 1/6] i.MX25: fix LD16 & LD17 iomux Eric Bénard
2011-12-12 21:19 ` [PATCH 2/6] CPUIMX35: enable the watchdog clock asap Eric Bénard
2011-12-12 21:19 ` [PATCH 3/6] CPUIMX51: add ARM errata and enable L2 cache Eric Bénard
@ 2011-12-12 21:19 ` Eric Bénard
2011-12-12 21:19 ` [PATCH 5/6] CPUIMX51: configure SD1 iomux when ESDHC is enabled Eric Bénard
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Eric Bénard @ 2011-12-12 21:19 UTC (permalink / raw)
To: barebox
a temporary setting was inserted in the default env by error
Signed-off-by: Eric Bénard <eric@eukrea.com>
---
arch/arm/boards/eukrea_cpuimx51/env/config | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boards/eukrea_cpuimx51/env/config b/arch/arm/boards/eukrea_cpuimx51/env/config
index 737f8e3..91a2671 100644
--- a/arch/arm/boards/eukrea_cpuimx51/env/config
+++ b/arch/arm/boards/eukrea_cpuimx51/env/config
@@ -30,7 +30,6 @@ rootfsimage=$machine/rootfs.$rootfs_type
# kernel
kernelimage_type=uimage
kernelimage=$machine/uImage-${machine}.bin
-kernelimage=uImage
# barebox and it's env
bareboximage=$machine/barebox-${machine}.bin
--
1.7.6.4
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^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 5/6] CPUIMX51: configure SD1 iomux when ESDHC is enabled
2011-12-12 21:19 [PATCH 1/6] i.MX25: fix LD16 & LD17 iomux Eric Bénard
` (2 preceding siblings ...)
2011-12-12 21:19 ` [PATCH 4/6] CPUIMX51: fix environement Eric Bénard
@ 2011-12-12 21:19 ` Eric Bénard
2011-12-12 21:19 ` [PATCH 6/6] CPUIMX51: update defconfig Eric Bénard
2011-12-13 9:44 ` [PATCH 1/6] i.MX25: fix LD16 & LD17 iomux Sascha Hauer
5 siblings, 0 replies; 8+ messages in thread
From: Eric Bénard @ 2011-12-12 21:19 UTC (permalink / raw)
To: barebox
Signed-off-by: Eric Bénard <eric@eukrea.com>
---
arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
index a128d50..a2db6d9 100644
--- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
+++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
@@ -88,6 +88,15 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
MX51_PAD_NANDF_CS1__NANDF_CS1,
/* LCD BL */
MX51_PAD_DI1_D1_CS__GPIO3_4,
+#ifdef CONFIG_MCI_IMX_ESDHC
+ /* SD 1 */
+ MX51_PAD_SD1_CMD__SD1_CMD,
+ MX51_PAD_SD1_CLK__SD1_CLK,
+ MX51_PAD_SD1_DATA0__SD1_DATA0,
+ MX51_PAD_SD1_DATA1__SD1_DATA1,
+ MX51_PAD_SD1_DATA2__SD1_DATA2,
+ MX51_PAD_SD1_DATA3__SD1_DATA3,
+#endif
};
#define GPIO_LAN8700_RESET (1 * 32 + 31)
--
1.7.6.4
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^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 6/6] CPUIMX51: update defconfig
2011-12-12 21:19 [PATCH 1/6] i.MX25: fix LD16 & LD17 iomux Eric Bénard
` (3 preceding siblings ...)
2011-12-12 21:19 ` [PATCH 5/6] CPUIMX51: configure SD1 iomux when ESDHC is enabled Eric Bénard
@ 2011-12-12 21:19 ` Eric Bénard
2011-12-13 9:44 ` [PATCH 1/6] i.MX25: fix LD16 & LD17 iomux Sascha Hauer
5 siblings, 0 replies; 8+ messages in thread
From: Eric Bénard @ 2011-12-12 21:19 UTC (permalink / raw)
To: barebox
Signed-off-by: Eric Bénard <eric@eukrea.com>
---
arch/arm/configs/eukrea_cpuimx51_defconfig | 24 ++++++++++++++++++++----
1 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/arch/arm/configs/eukrea_cpuimx51_defconfig b/arch/arm/configs/eukrea_cpuimx51_defconfig
index 39fe962..7a746cc 100644
--- a/arch/arm/configs/eukrea_cpuimx51_defconfig
+++ b/arch/arm/configs/eukrea_cpuimx51_defconfig
@@ -1,16 +1,15 @@
CONFIG_ARCH_IMX=y
-CONFIG_ARCH_IMX_INTERNAL_BOOT=y
CONFIG_ARCH_IMX51=y
CONFIG_MACH_EUKREA_CPUIMX51SD=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_MMU=y
CONFIG_MALLOC_SIZE=0x2000000
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
-CONFIG_PARTITION=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/eukrea_cpuimx51/env"
CONFIG_CMD_EDIT=y
@@ -21,16 +20,20 @@ CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_FLASH=y
-CONFIG_CMD_BOOTM_ZLIB=y
-CONFIG_CMD_BOOTM_BZLIB=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_IMINFO=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
@@ -39,7 +42,20 @@ CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
+CONFIG_I2C=y
+CONFIG_I2C_IMX=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_IMX=y
CONFIG_UBI=y
+CONFIG_MCI=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_ZLIB=y
+CONFIG_BZLIB=y
+CONFIG_LZO_DECOMPRESS=y
--
1.7.6.4
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^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/6] i.MX25: fix LD16 & LD17 iomux
2011-12-12 21:19 [PATCH 1/6] i.MX25: fix LD16 & LD17 iomux Eric Bénard
` (4 preceding siblings ...)
2011-12-12 21:19 ` [PATCH 6/6] CPUIMX51: update defconfig Eric Bénard
@ 2011-12-13 9:44 ` Sascha Hauer
5 siblings, 0 replies; 8+ messages in thread
From: Sascha Hauer @ 2011-12-13 9:44 UTC (permalink / raw)
To: Eric Bénard; +Cc: barebox
On Mon, Dec 12, 2011 at 10:19:34PM +0100, Eric Bénard wrote:
> without this, the pins seems to be opendrain and thus the LCD signals
> are not properly driven leading to wrong colors on the screen.
I applied all patches except the one I commented on to master.
Sascha
>
> Signed-off-by: Eric Bénard <eric@eukrea.com>
> ---
> arch/arm/mach-imx/include/mach/iomux-mx25.h | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-imx/include/mach/iomux-mx25.h b/arch/arm/mach-imx/include/mach/iomux-mx25.h
> index ae29323..58761b5 100644
> --- a/arch/arm/mach-imx/include/mach/iomux-mx25.h
> +++ b/arch/arm/mach-imx/include/mach/iomux-mx25.h
> @@ -473,14 +473,14 @@
> #define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
>
> #define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL)
> -#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, NO_PAD_CTRL)
> #define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
>
> #define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL)
> -#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_PUS_100K_UP)
> #define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL)
>
> #define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_PUS_100K_UP)
> #define MX25_PAD_GPIO_F__AUD7_TXC IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL)
>
> #define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL)
> --
> 1.7.6.4
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 8+ messages in thread