Re: [PATCH] ARM: add board support for Phytec phyCARD-M aka pca101

[Teresa Gamez <T.Gamez@phytec.de>]

Hello Sascha,

we want to use a different name convention for all the phyCARDs since it
is quite chaotic atm. Christian is working on patches for the phyCARD-M1
with the new name convention. But he probably won't send them to the
list until the beginning of next year. 

Same with phyCARD-L1, Jürgen Kilb will send patches in the next days.

Regards
Teresa

Am Mittwoch, den 21.12.2011, 12:36 +0100 schrieb Sascha Hauer:
> From: Teresa Gámez <t.gamez@phytec.de>
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Teresa Gamez <t.gamez@phytec.de>
> ---
>  arch/arm/Makefile                    |    1 +
>  arch/arm/boards/phyCARD-M/Makefile   |    2 +
>  arch/arm/boards/phyCARD-M/config.h   |    6 +
>  arch/arm/boards/phyCARD-M/env/config |   59 +++++++
>  arch/arm/boards/phyCARD-M/lowlevel.c |  248 ++++++++++++++++++++++++++++++
>  arch/arm/boards/phyCARD-M/pca101.c   |  276 ++++++++++++++++++++++++++++++++++
>  arch/arm/configs/pca101_defconfig    |   67 ++++++++
>  arch/arm/mach-imx/Kconfig            |   14 ++
>  8 files changed, 673 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boards/phyCARD-M/Makefile
>  create mode 100644 arch/arm/boards/phyCARD-M/config.h
>  create mode 100644 arch/arm/boards/phyCARD-M/env/config
>  create mode 100644 arch/arm/boards/phyCARD-M/lowlevel.c
>  create mode 100644 arch/arm/boards/phyCARD-M/pca101.c
>  create mode 100644 arch/arm/configs/pca101_defconfig
> 
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index a3e12e6..fcb2f1a 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -97,6 +97,7 @@ board-$(CONFIG_MACH_PCM037)			:= pcm037
>  board-$(CONFIG_MACH_PCM038)			:= pcm038
>  board-$(CONFIG_MACH_PCM043)			:= pcm043
>  board-$(CONFIG_MACH_PM9261)			:= pm9261
> +board-$(CONFIG_MACH_PCA101)        		:= phyCARD-M
>  board-$(CONFIG_MACH_PM9263)			:= pm9263
>  board-$(CONFIG_MACH_PM9G45)			:= pm9g45
>  board-$(CONFIG_MACH_SCB9328)			:= scb9328
> diff --git a/arch/arm/boards/phyCARD-M/Makefile b/arch/arm/boards/phyCARD-M/Makefile
> new file mode 100644
> index 0000000..4b983e7
> --- /dev/null
> +++ b/arch/arm/boards/phyCARD-M/Makefile
> @@ -0,0 +1,2 @@
> +obj-y += lowlevel.o
> +obj-y += pca101.o
> diff --git a/arch/arm/boards/phyCARD-M/config.h b/arch/arm/boards/phyCARD-M/config.h
> new file mode 100644
> index 0000000..5ede823
> --- /dev/null
> +++ b/arch/arm/boards/phyCARD-M/config.h
> @@ -0,0 +1,6 @@
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_MX35_HCLK_FREQ	24000000
> +
> +#endif
> diff --git a/arch/arm/boards/phyCARD-M/env/config b/arch/arm/boards/phyCARD-M/env/config
> new file mode 100644
> index 0000000..1f00347
> --- /dev/null
> +++ b/arch/arm/boards/phyCARD-M/env/config
> @@ -0,0 +1,59 @@
> +#!/bin/sh
> +
> +machine=pca101
> +user=
> +
> +# use 'dhcp' to do dhcp in barebox and in kernel
> +# use 'none' if you want to skip kernel ip autoconfiguration
> +ip=dhcp
> +
> +# or set your networking parameters here
> +#eth0.ipaddr=192.168.3.11
> +#eth0.netmask=255.255.255.0
> +#eth0.gateway=192.168.3.10
> +#eth0.serverip=192.168.3.10
> +
> +# can be either 'net' or 'nand'
> +kernel_loc=nand
> +# can be either 'net' or 'nand'
> +rootfs_loc=nand
> +
> +# can be either 'jffs2' or 'ubifs'
> +rootfs_type=ubifs
> +rootfsimage=root-$machine.$rootfs_type
> +
> +kernelimage=uImage-$machine
> +
> +if [ -n $user ]; then
> +	kernelimage="$user"-"$kernelimage"
> +	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
> +	rootfsimage="$user"-"$rootfsimage"
> +else
> +	nfsroot="$eth0.serverip:/path/to/nfs/root"
> +fi
> +
> +autoboot_timeout=3
> +
> +bootargs="console=ttymxc0,115200"
> +
> +#Displays
> +bootargs="$bootargs video=mx3fb:Primeview-PD050VL1"
> +#bootargs="$bootargs video=mx3fb:Primeview-PD035VL1"
> +#bootargs="$bootargs video=mx3fb:Primeview-PD104SLF"
> +#bootargs="$bootargs video=mx3fb:Primeview-PM070WL4"
> +
> +# safetytest display
> +#bootargs="$bootargs video=mx3fb:ETM070001DH6 quiet"
> +
> +#USB OTG - Comment this out if you want to use USB OTG as host
> +#bootargs="$bootargs pca101_otg_mode=host"
> +
> +bootargs="$bootargs lpj=2654208 quiet"
> +
> +nand_parts="512k(barebox)ro,512k(bareboxenv),5M(kernel),-(root)"
> +rootfs_mtdblock_nand=3
> +
> +nand_device=mxc_nand
> +
> +# set a fancy prompt (if support is compiled in)
> +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
> diff --git a/arch/arm/boards/phyCARD-M/lowlevel.c b/arch/arm/boards/phyCARD-M/lowlevel.c
> new file mode 100644
> index 0000000..1d2cd97
> --- /dev/null
> +++ b/arch/arm/boards/phyCARD-M/lowlevel.c
> @@ -0,0 +1,248 @@
> +/*
> + *
> + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <init.h>
> +#include <io.h>
> +
> +#include <asm/barebox-arm.h>
> +#include <asm-generic/memory_layout.h>
> +#include <asm/system.h>
> +#include <asm/cache-l2x0.h>
> +
> +#include <mach/imx-nand.h>
> +#include <mach/imx-regs.h>
> +#include <mach/imx-pll.h>
> +#include <mach/esdctl.h>
> +
> +/* Assuming 24MHz input clock */
> +#define MPCTL_PARAM_399     (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
> +#define MPCTL_PARAM_532     ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
> +#define PPCTL_PARAM_300     (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
> +
> +#define IMX35_CHIP_REVISION_2_1		0x11
> +
> +#define CCM_PDR0_399	0x00011000
> +#define CCM_PDR0_532	0x00001000
> +
> +#ifdef CONFIG_NAND_IMX_BOOT
> +static void __bare_init __naked insdram(void)
> +{
> +	uint32_t r;
> +
> +	/* Speed up NAND controller by adjusting the NFC divider */
> +	r = readl(IMX_CCM_BASE + CCM_PDR4);
> +	r &= ~(0xf << 28);
> +	r |= 0x1 << 28;
> +	writel(r, IMX_CCM_BASE + CCM_PDR4);
> +
> +	/* setup a stack to be able to call imx_nand_load_image() */
> +	r = STACK_BASE + STACK_SIZE - 12;
> +	__asm__ __volatile__("mov sp, %0" : : "r"(r));
> +
> +	imx_nand_load_image((void *)TEXT_BASE, 256 * 1024);
> +
> +	board_init_lowlevel_return();
> +}
> +#endif
> +
> +#define ESDCTLVAL	(ESDCTL0_ROW13 | ESDCTL0_COL10 | ESDCTL0_DSIZ_31_0 | \
> +			 ESDCTL0_REF8 | ESDCTL0_BL)
> +#define ESDCFGVAL	(ESDCFGx_tXP_2 | ESDCFGx_tRP_2 | ESDCFGx_tMRD_2 | ESDCFGx_tRAS_6 | \
> +			 ESDCFGx_tRRD_2 | ESDCFGx_tRCD_2 | \
> +			 ESDCFGx_tRC_16)
> +
> +static inline void phycard_setup_sdram(uint32_t base, uint32_t esdctl,
> +               uint32_t esdcfg)
> +{
> +	uint32_t esdctlreg = ESDCTL0;
> +	uint32_t esdcfgreg = ESDCFG0;
> +
> +	if (base != IMX_SDRAM_CS0) {
> +		esdctlreg += 8;
> +		esdcfgreg += 8;
> +	}
> +
> +	esdctl |= ESDCTL0_SDE;
> +
> +	/* set timing paramters */
> +	writel(esdcfg, esdcfgreg);
> +	/* select Prechare-All mode */
> +	writel(ESDCTL0_SMODE_PRECHARGE | esdctl, esdctlreg);
> +	/* Prechare-All */
> +	writel(0x12345678, base + 0x400);
> +
> +	/* select Load-Mode-Register mode */
> +	writel(ESDCTL0_SMODE_LOAD_MODE | esdctl, esdctlreg);
> +	/* Load reg EMR2 */
> +	writeb(0xda, base + 0x04000000);
> +	/* Load reg EMR3 */
> +	writeb(0xda, base + 0x06000000);
> +	/* Load reg EMR1 -- enable DLL */
> +	writeb(0xda, base + 0x02000400);
> +	/* Load reg MR -- reset DLL */
> +	writeb(0xda, base + 0x00000333);
> +
> +	/* select Prechare-All mode */
> +	writel(ESDCTL0_SMODE_PRECHARGE | esdctl, esdctlreg);
> +	/* Prechare-All */
> +	writel(0x12345678, base + 0x400);
> +
> +	/* select Manual-Refresh mode */
> +	writel(ESDCTL0_SMODE_AUTO_REFRESH | esdctl, esdctlreg);
> +	/* Manual-Refresh 2 times */
> +	writel(0x87654321, base);
> +	writel(0x87654321, base);
> +
> +	/* select Load-Mode-Register mode */
> +	writel(ESDCTL0_SMODE_LOAD_MODE | esdctl, esdctlreg);
> +	/* Load reg MR -- CL3, BL8, end DLL reset */
> +	writeb(0xda, base + 0x233);
> +	/* Load reg EMR1 -- OCD default */
> +	writeb(0xda, base + 0x02000780);
> +	writeb(0xda, base + 0x020007C0);
> +	/* Load reg EMR1 -- OCD exit */
> +	writeb(0xda, base + 0x02000400);
> +	writeb(0xda, base + 0x02000440);
> +
> +	writel(esdctl, esdctlreg);
> +}
> +
> +void __bare_init __naked board_init_lowlevel(void)
> +{
> +	uint32_t r, s;
> +	unsigned long ccm_base = IMX_CCM_BASE;
> +	unsigned long iomuxc_base = IMX_IOMUXC_BASE;
> +#ifdef CONFIG_NAND_IMX_BOOT
> +	unsigned int *trg, *src;
> +	int i;
> +#endif
> +	r = get_cr();
> +	r |= CR_Z; /* Flow prediction (Z) */
> +	r |= CR_U; /* unaligned accesses  */
> +	r |= CR_FI; /* Low Int Latency     */
> +
> +	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(s));
> +	s |= 0x7;
> +	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s));
> +
> +	set_cr(r);
> +
> +	r = 0;
> +	__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
> +
> +	/*
> +	 * Branch predicition is now enabled.  Flush the BTAC to ensure a valid
> +	 * starting point.  Don't flush BTAC while it is disabled to avoid
> +	 * ARM1136 erratum 408023.
> +	 */
> +	__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r));
> +
> +	/* invalidate I cache and D cache */
> +	__asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r));
> +
> +	/* invalidate TLBs */
> +	__asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r));
> +
> +	/* Drain the write buffer */
> +	__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r));
> +
> +	/* Also setup the Peripheral Port Remap register inside the core */
> +	r = 0x40000015; /* start from AIPS 2GB region */
> +	__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
> +
> +	/*
> +	 * End of ARM1136 init
> +	 */
> +
> +	writel(0x003F4208, ccm_base + CCM_CCMR);
> +
> +	/* Set MPLL , arm clock and ahb clock*/
> +	writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL);
> +
> +	writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL);
> +
> +	/* Check silicon revision and use 532MHz if >=2.1 */
> +	r = readl(IMX_IIM_BASE + 0x24);
> +	if (r >= IMX35_CHIP_REVISION_2_1)
> +		writel(CCM_PDR0_532, ccm_base + CCM_PDR0);
> +	else
> +		writel(CCM_PDR0_399, ccm_base + CCM_PDR0);
> +
> +	r = readl(ccm_base + CCM_CGR0);
> +	r |= 0x00300000;
> +	writel(r, ccm_base + CCM_CGR0);
> +
> +	r = readl(ccm_base + CCM_CGR1);
> +	r |= 0x00000C00;
> +	r |= 0x00000003;
> +	writel(r, ccm_base + CCM_CGR1);
> +
> +	r = readl(IMX_L2CC_BASE + L2X0_AUX_CTRL);
> +	r |= 0x1000;
> +	writel(r, IMX_L2CC_BASE + L2X0_AUX_CTRL);
> +
> +	/* Skip SDRAM initialization if we run from RAM */
> +	r = get_pc();
> +	if (r > 0x80000000 && r < 0x90000000)
> +		board_init_lowlevel_return();
> +
> +	/* Set DDR Type to SDRAM, drive strength workaround	*
> +	 * 0x00000000	MDDR					*
> +	 * 0x00000800	3,3V SDRAM				*/
> +
> +	r = 0x00000800;
> +	writel(r, iomuxc_base + 0x794);
> +	writel(r, iomuxc_base + 0x798);
> +	writel(r, iomuxc_base + 0x79c);
> +	writel(r, iomuxc_base + 0x7a0);
> +	writel(r, iomuxc_base + 0x7a4);
> +
> +	/* MDDR init, enable mDDR*/
> +	writel(0x00000304, ESDMISC);
> +
> +	phycard_setup_sdram(0x80000000, ESDCTLVAL, ESDCFGVAL);
> +#ifdef CONFIG_PCA101_RAM_2BANKS
> +	phycard_setup_sdram(0x90000000, ESDCTLVAL, ESDCFGVAL);
> +#endif
> +
> +#ifdef CONFIG_NAND_IMX_BOOT
> +	/* skip NAND boot if not running from NFC space */
> +	r = get_pc();
> +	if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
> +		board_init_lowlevel_return();
> +
> +	src = (unsigned int *)IMX_NFC_BASE;
> +	trg = (unsigned int *)TEXT_BASE;
> +
> +	/* Move ourselves out of NFC SRAM */
> +	for (i = 0; i < 0x800 / sizeof(int); i++)
> +		*trg++ = *src++;
> +
> +	/* Jump to SDRAM */
> +	r = (unsigned int)&insdram;
> +	__asm__ __volatile__("mov pc, %0" : : "r"(r));
> +#else
> +	board_init_lowlevel_return();
> +#endif
> +}
> +
> diff --git a/arch/arm/boards/phyCARD-M/pca101.c b/arch/arm/boards/phyCARD-M/pca101.c
> new file mode 100644
> index 0000000..b4aeb10
> --- /dev/null
> +++ b/arch/arm/boards/phyCARD-M/pca101.c
> @@ -0,0 +1,276 @@
> +/*
> + * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
> + * (C) 2009 Pengutronix, Juergen Beisert <kernel@pengutronix.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + *
> + * Board support for Phytec's, i.MX35 based CPU card, called: PCA101
> + */
> +
> +#include <environment.h>
> +#include <command.h>
> +#include <driver.h>
> +#include <partition.h>
> +#include <common.h>
> +#include <nand.h>
> +#include <init.h>
> +#include <fec.h>
> +#include <io.h>
> +#include <fs.h>
> +
> +#include <asm/mach-types.h>
> +#include <asm/armlinux.h>
> +#include <asm/mmu.h>
> +
> +#include <mach/iomux-mx35.h>
> +#include <mach/imx-regs.h>
> +#include <mach/devices-imx35.h>
> +#include <mach/imx-nand.h>
> +#include <mach/esdctl.h>
> +#include <mach/imx-pll.h>
> +
> +static struct fec_platform_data fec_info = {
> +	.xcv_type = MII100,
> +};
> +
> +struct imx_nand_platform_data nand_info = {
> +	.width	= 1,
> +	.hw_ecc	= 1,
> +	.flash_bbt = 1,
> +};
> +
> +static int pca101_mmu_init(void)
> +{
> +	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
> +
> +	return 0;
> +}
> +postmmu_initcall(pca101_mmu_init);
> +
> +static int pca101_mem_init(void)
> +{
> +	arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
> +#ifdef CONFIG_PCA101_RAM_2BANKS
> +	arm_add_mem_device("ram1", IMX_SDRAM_CS1, 128 * 1024 * 1024);
> +#endif
> +	return 0;
> +}
> +mem_initcall(pca101_mem_init);
> +
> +static int pca101_devices_init(void)
> +{
> +	uint32_t reg;
> +
> +	reg = readl(IMX_CCM_BASE + CCM_RCSR);
> +	/* some fuses provide us vital information about connected hardware */
> +	if (reg & 0x20000000)
> +		nand_info.width = 2;    /* 16 bit */
> +	else
> +		nand_info.width = 1;    /* 8 bit */
> +
> +	imx35_add_fec(&fec_info);
> +	imx35_add_nand(&nand_info);
> +
> +	if ((reg & 0xc00) == 0x800 && ( (reg >> 25) & 0x3) == 0x01 ) {   /* reset mode: external boot */
> +		devfs_add_partition("nand0", 0x00000, 0x80000, PARTITION_FIXED, "self_raw");
> +		dev_add_bb_dev("self_raw", "self0");
> +		devfs_add_partition("nand0", 0x80000, 0x80000, PARTITION_FIXED, "env_raw");
> +		dev_add_bb_dev("env_raw", "env0");
> +	}
> +
> +	armlinux_set_bootparams((void *)0x80000100);
> +	armlinux_set_architecture(2595);
> +
> +	return 0;
> +}
> +
> +device_initcall(pca101_devices_init);
> +
> +static struct pad_desc pca101_pads[] = {
> +	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
> +	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
> +	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
> +	MX35_PAD_FEC_COL__FEC_COL,
> +	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
> +	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
> +	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
> +	MX35_PAD_FEC_MDC__FEC_MDC,
> +	MX35_PAD_FEC_MDIO__FEC_MDIO,
> +	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
> +	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
> +	MX35_PAD_FEC_CRS__FEC_CRS,
> +	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
> +	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
> +	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
> +	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
> +	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
> +	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
> +	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
> +	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
> +	MX35_PAD_RXD1__UART1_RXD_MUX,
> +	MX35_PAD_TXD1__UART1_TXD_MUX,
> +	MX35_PAD_RTS1__UART1_RTS,
> +	MX35_PAD_CTS1__UART1_CTS,
> +	MX35_PAD_I2C1_CLK__I2C1_SCL,
> +	MX35_PAD_I2C1_DAT__I2C1_SDA
> +};
> +
> +static int pca101_console_init(void)
> +{
> +	mxc_iomux_v3_setup_multiple_pads(pca101_pads, ARRAY_SIZE(pca101_pads));
> +
> +	imx35_add_uart0();
> +
> +	return 0;
> +}
> +
> +console_initcall(pca101_console_init);
> +
> +static int pca101_core_setup(void)
> +{
> +	u32 tmp;
> +
> +	/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
> +	/*
> +	 * Set all MPROTx to be non-bufferable, trusted for R/W,
> +	 * not forced to user-mode.
> +	 */
> +	writel(0x77777777, IMX_AIPS1_BASE);
> +	writel(0x77777777, IMX_AIPS1_BASE + 0x4);
> +	writel(0x77777777, IMX_AIPS2_BASE);
> +	writel(0x77777777, IMX_AIPS2_BASE + 0x4);
> +
> +	/*
> +	 * Clear the on and off peripheral modules Supervisor Protect bit
> +	 * for SDMA to access them. Did not change the AIPS control registers
> +	 * (offset 0x20) access type
> +	 */
> +	writel(0x0, IMX_AIPS1_BASE + 0x40);
> +	writel(0x0, IMX_AIPS1_BASE + 0x44);
> +	writel(0x0, IMX_AIPS1_BASE + 0x48);
> +	writel(0x0, IMX_AIPS1_BASE + 0x4C);
> +	tmp = readl(IMX_AIPS1_BASE + 0x50);
> +	tmp &= 0x00FFFFFF;
> +	writel(tmp, IMX_AIPS1_BASE + 0x50);
> +
> +	writel(0x0, IMX_AIPS2_BASE + 0x40);
> +	writel(0x0, IMX_AIPS2_BASE + 0x44);
> +	writel(0x0, IMX_AIPS2_BASE + 0x48);
> +	writel(0x0, IMX_AIPS2_BASE + 0x4C);
> +	tmp = readl(IMX_AIPS2_BASE + 0x50);
> +	tmp &= 0x00FFFFFF;
> +	writel(tmp, IMX_AIPS2_BASE + 0x50);
> +
> +	/* MAX (Multi-Layer AHB Crossbar Switch) setup */
> +
> +	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
> +#define MAX_PARAM1 0x00302154
> +	writel(MAX_PARAM1, IMX_MAX_BASE + 0x0);   /* for S0 */
> +	writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
> +	writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
> +	writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
> +	writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
> +
> +	/* SGPCR - always park on last master */
> +	writel(0x10, IMX_MAX_BASE + 0x10);	/* for S0 */
> +	writel(0x10, IMX_MAX_BASE + 0x110);	/* for S1 */
> +	writel(0x10, IMX_MAX_BASE + 0x210);	/* for S2 */
> +	writel(0x10, IMX_MAX_BASE + 0x310);	/* for S3 */
> +	writel(0x10, IMX_MAX_BASE + 0x410);	/* for S4 */
> +
> +	/* MGPCR - restore default values */
> +	writel(0x0, IMX_MAX_BASE + 0x800);	/* for M0 */
> +	writel(0x0, IMX_MAX_BASE + 0x900);	/* for M1 */
> +	writel(0x0, IMX_MAX_BASE + 0xa00);	/* for M2 */
> +	writel(0x0, IMX_MAX_BASE + 0xb00);	/* for M3 */
> +	writel(0x0, IMX_MAX_BASE + 0xc00);	/* for M4 */
> +	writel(0x0, IMX_MAX_BASE + 0xd00);	/* for M5 */
> +
> +	/*
> +	 * M3IF Control Register (M3IFCTL)
> +	 * MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
> +	 * MRRP[1] = MAX1 not on priority list (0 << 0)		= 0x00000000
> +	 * MRRP[2] = L2CC1 not on priority list (0 << 0)	= 0x00000000
> +	 * MRRP[3] = USB  not on priority list (0 << 0)		= 0x00000000
> +	 * MRRP[4] = SDMA not on priority list (0 << 0)		= 0x00000000
> +	 * MRRP[5] = GPU not on priority list (0 << 0)		= 0x00000000
> +	 * MRRP[6] = IPU1 on priority list (1 << 6)		= 0x00000040
> +	 * MRRP[7] = IPU2 not on priority list (0 << 0)		= 0x00000000
> +	 *                                                       ------------
> +	 *                                                        0x00000040
> +	 */
> +	writel(0x40, IMX_M3IF_BASE);
> +
> +	return 0;
> +}
> +
> +core_initcall(pca101_core_setup);
> +
> +#define CCM_PDR0_PARAM_399	0x00011000
> +#define CCM_PDR0_PARAM_532	0x00001000
> +
> +static int do_cpufreq(struct command *cmdtp, int argc, char *argv[])
> +{
> +	unsigned long freq;
> +
> +	if (argc != 2) {
> +		barebox_cmd_usage(cmdtp);
> +		return 1;
> +	}
> +
> +	freq = simple_strtoul(argv[1], NULL, 0);
> +
> +	switch (freq) {
> +	case 399:
> +		writel(CCM_PDR0_PARAM_399, IMX_CCM_BASE + CCM_PDR0);
> +		break;
> +	case 532:
> +		writel(CCM_PDR0_PARAM_532, IMX_CCM_BASE + CCM_PDR0);
> +		break;
> +	default:
> +		barebox_cmd_usage(cmdtp);
> +		return 1;
> +	}
> +
> +	printf("Switched CPU frequency to %ldMHz\n", freq);
> +
> +	return 0;
> +}
> +
> +static const __maybe_unused char cmd_cpufreq_help[] =
> +"Usage: cpufreq 399|532\n"
> +"\n"
> +"Set CPU frequency to <freq> MHz\n";
> +
> +BAREBOX_CMD_START(cpufreq)
> +	.cmd            = do_cpufreq,
> +	.usage          = "adjust CPU frequency",
> +	BAREBOX_CMD_HELP(cmd_cpufreq_help)
> +BAREBOX_CMD_END
> +
> +#ifdef CONFIG_NAND_IMX_BOOT
> +void __bare_init nand_boot(void)
> +{
> +	/*
> +	 * The driver is able to detect NAND's pagesize by CPU internal
> +	 * fuses or external pull ups. But not the blocksize...
> +	 */
> +	imx_nand_load_image((void *)TEXT_BASE, 256 * 1024);
> +}
> +#endif
> diff --git a/arch/arm/configs/pca101_defconfig b/arch/arm/configs/pca101_defconfig
> new file mode 100644
> index 0000000..67e3024
> --- /dev/null
> +++ b/arch/arm/configs/pca101_defconfig
> @@ -0,0 +1,67 @@
> +CONFIG_ARCH_IMX=y
> +CONFIG_CACHE_L2X0=y
> +CONFIG_ARCH_IMX_EXTERNAL_BOOT=y
> +CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
> +CONFIG_NAND_IMX_BOOT_2K=y
> +CONFIG_ARCH_IMX35=y
> +CONFIG_MACH_PCA101=y
> +CONFIG_IMX_CLKO=y
> +CONFIG_AEABI=y
> +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
> +CONFIG_ARM_UNWIND=y
> +CONFIG_MMU=y
> +CONFIG_MALLOC_SIZE=0x2000000
> +CONFIG_KALLSYMS=y
> +CONFIG_LONGHELP=y
> +CONFIG_GLOB=y
> +CONFIG_HUSH_FANCY_PROMPT=y
> +CONFIG_CMDLINE_EDITING=y
> +CONFIG_AUTO_COMPLETE=y
> +CONFIG_PARTITION=y
> +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
> +CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/phyCARD-M/env"
> +CONFIG_DEBUG_INFO=y
> +CONFIG_CMD_EDIT=y
> +CONFIG_CMD_SLEEP=y
> +CONFIG_CMD_SAVEENV=y
> +CONFIG_CMD_LOADENV=y
> +CONFIG_CMD_EXPORT=y
> +CONFIG_CMD_PRINTENV=y
> +CONFIG_CMD_READLINE=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_ECHO_E=y
> +CONFIG_CMD_MEMINFO=y
> +CONFIG_CMD_IOMEM=y
> +CONFIG_CMD_MTEST=y
> +CONFIG_CMD_FLASH=y
> +CONFIG_CMD_BOOTM_SHOW_TYPE=y
> +CONFIG_CMD_BOOTM_VERBOSE=y
> +CONFIG_CMD_BOOTM_INITRD=y
> +CONFIG_CMD_BOOTM_OFTREE=y
> +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
> +CONFIG_CMD_UIMAGE=y
> +CONFIG_CMD_RESET=y
> +CONFIG_CMD_GO=y
> +CONFIG_CMD_OFTREE=y
> +CONFIG_CMD_TIMEOUT=y
> +CONFIG_CMD_PARTITION=y
> +CONFIG_CMD_MAGICVAR=y
> +CONFIG_CMD_MAGICVAR_HELP=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_UNCOMPRESS=y
> +CONFIG_NET=y
> +CONFIG_NET_DHCP=y
> +CONFIG_NET_NFS=y
> +CONFIG_NET_PING=y
> +CONFIG_NET_TFTP=y
> +CONFIG_NET_TFTP_PUSH=y
> +CONFIG_DRIVER_NET_FEC_IMX=y
> +CONFIG_I2C=y
> +CONFIG_MTD=y
> +CONFIG_NAND=y
> +# CONFIG_NAND_ECC_SOFT is not set
> +# CONFIG_NAND_ECC_HW_SYNDROME is not set
> +CONFIG_NAND_IMX=y
> +CONFIG_UBI=y
> +CONFIG_ZLIB=y
> +CONFIG_LZO_DECOMPRESS=y
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 27bf386..817d0a2 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -12,6 +12,7 @@ config ARCH_TEXT_BASE
>  	default 0x83f00000 if MACH_FREESCALE_MX25_3STACK && FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2
>  	default 0x87f00000 if MACH_FREESCALE_MX25_3STACK && FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR
>  	default 0x87f00000 if MACH_FREESCALE_MX35_3STACK
> +	default 0x87f00000 if MACH_PCA101
>  	default 0xa7f00000 if MACH_PCA100
>  	default 0xa0000000 if MACH_PCM038
>  	default 0x87f00000 if MACH_PCM037
> @@ -34,6 +35,7 @@ config BOARDINFO
>  	default "Freescale MX35 3Stack" if MACH_FREESCALE_MX35_3STACK
>  	default "Freescale MX25 3Stack" if MACH_FREESCALE_MX25_3STACK
>  	default "Phytec phyCard-i.MX27" if MACH_PCA100
> +	default "Phytec phyCARD-M" if MACH_PCA101
>  	default "Phytec phyCORE-i.MX27" if MACH_PCM038
>  	default "Phytec phyCORE-i.MX31" if MACH_PCM037
>  	default "Phytec phyCORE-i.MX35" if MACH_PCM043
> @@ -358,6 +360,14 @@ config MACH_GUF_CUPID
>  	  Say Y here if you are using the Garz+Fricke Neso board equipped
>  	  with a Freescale i.MX35 Processor
>  
> +config MACH_PCA101
> +	bool "phyCARD-M"
> +	select MACH_HAS_LOWLEVEL_INIT
> +	select ARCH_HAS_L2X0
> +	help
> +	   Say Y here if you are using Phytec's phyCARD-M (pca101) equipped
> +	   with a Freescale i.MX35 Processor
> +
>  endchoice
>  
>  endif
> @@ -474,6 +484,10 @@ config FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR
>  	bool "128 MB (mDDR)"
>  endchoice
>  endif
> +
> +config PCA101_RAM_2BANKS
> +	depends on MACH_PCA101
> +	bool "two sdram banks equipped on phyCARD"
>  endmenu
>  
>  menu "i.MX specific settings        "



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