* [PATCH 01/14] MACH SAMSUNG: Rename the whole mach to add more CPUs in future
2012-01-02 11:43 [PATCH v2] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
@ 2012-01-02 11:43 ` Juergen Beisert
2012-01-02 11:43 ` [PATCH 02/14] MACH SAMSUNG/S3C: Do not compile S3C24xx's GPIO support unconditionally Juergen Beisert
` (12 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2012-01-02 11:43 UTC (permalink / raw)
To: barebox
The S3Cxxxx family consists of ARMv4, ARMv5 and ARMv6 types of CPU cores. The
S3C24xx sub family is only one of it. To be able to handle all CPUs in one mach
directory, use a more generic name for it.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/Kconfig | 3 ++-
arch/arm/Makefile | 2 +-
arch/arm/{mach-s3c24xx => mach-samsung}/Kconfig | 15 ++++++++++++---
arch/arm/{mach-s3c24xx => mach-samsung}/Makefile | 0
arch/arm/{mach-s3c24xx => mach-samsung}/generic.c | 0
.../{mach-s3c24xx => mach-samsung}/gpio-s3c24x0.c | 0
.../include/mach/fb.h | 0
.../include/mach/gpio.h | 0
.../include/mach/iomux-s3c24x0.h | 0
.../include/mach/mci.h | 0
.../include/mach/s3c24x0-iomap.h | 0
.../include/mach/s3c24x0-nand.h | 0
.../include/mach/s3c24xx-generic.h | 0
.../{mach-s3c24xx => mach-samsung}/lowlevel-init.S | 0
14 files changed, 15 insertions(+), 5 deletions(-)
rename arch/arm/{mach-s3c24xx => mach-samsung}/Kconfig (91%)
rename arch/arm/{mach-s3c24xx => mach-samsung}/Makefile (100%)
rename arch/arm/{mach-s3c24xx => mach-samsung}/generic.c (100%)
rename arch/arm/{mach-s3c24xx => mach-samsung}/gpio-s3c24x0.c (100%)
rename arch/arm/{mach-s3c24xx => mach-samsung}/include/mach/fb.h (100%)
rename arch/arm/{mach-s3c24xx => mach-samsung}/include/mach/gpio.h (100%)
rename arch/arm/{mach-s3c24xx => mach-samsung}/include/mach/iomux-s3c24x0.h (100%)
rename arch/arm/{mach-s3c24xx => mach-samsung}/include/mach/mci.h (100%)
rename arch/arm/{mach-s3c24xx => mach-samsung}/include/mach/s3c24x0-iomap.h (100%)
rename arch/arm/{mach-s3c24xx => mach-samsung}/include/mach/s3c24x0-nand.h (100%)
rename arch/arm/{mach-s3c24xx => mach-samsung}/include/mach/s3c24xx-generic.h (100%)
rename arch/arm/{mach-s3c24xx => mach-samsung}/lowlevel-init.S (100%)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 40677a3..b600179 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -68,6 +68,7 @@ config ARCH_PXA
config ARCH_S3C24xx
bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
+ select ARCH_SAMSUNG
select CPU_ARM920T
select GENERIC_GPIO
@@ -86,7 +87,7 @@ source arch/arm/mach-netx/Kconfig
source arch/arm/mach-nomadik/Kconfig
source arch/arm/mach-omap/Kconfig
source arch/arm/mach-pxa/Kconfig
-source arch/arm/mach-s3c24xx/Kconfig
+source arch/arm/mach-samsung/Kconfig
source arch/arm/mach-versatile/Kconfig
config ARM_ASM_UNIFIED
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index b14934c..6c91c22 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -52,7 +52,7 @@ machine-$(CONFIG_ARCH_NOMADIK) := nomadik
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_OMAP) := omap
machine-$(CONFIG_ARCH_PXA) := pxa
-machine-$(CONFIG_ARCH_S3C24xx) := s3c24xx
+machine-$(CONFIG_ARCH_SAMSUNG) := samsung
machine-$(CONFIG_ARCH_VERSATILE) := versatile
# Board directory name. This list is sorted alphanumerically
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-samsung/Kconfig
similarity index 91%
rename from arch/arm/mach-s3c24xx/Kconfig
rename to arch/arm/mach-samsung/Kconfig
index 80b65fb..a800cb8 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-samsung/Kconfig
@@ -1,14 +1,21 @@
-if ARCH_S3C24xx
+config ARCH_SAMSUNG
+ bool
+
+if ARCH_SAMSUNG
config ARCH_TEXT_BASE
hex
- default 0x31fc0000
+ default 0x31fc0000 if MACH_MINI2440
+ default 0x31fc0000 if MACH_A9M2440
+ default 0x31fc0000 if MACH_A9M2410
config BOARDINFO
default "Mini 2440" if MACH_MINI2440
default "Digi A9M2440" if MACH_A9M2440
default "Digi A9M2410" if MACH_A9M2410
+if ARCH_S3C24xx
+
config CPU_S3C2410
bool
@@ -67,7 +74,7 @@ config MACH_A9M2410DEV
endchoice
-source arch/arm/boards/mini2440/Kconfig
+source arch/arm/boards/mini2440/Kconfig
endmenu
@@ -106,3 +113,5 @@ config S3C24XX_NAND_BOOT
endmenu
endif
+
+endif
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-samsung/Makefile
similarity index 100%
rename from arch/arm/mach-s3c24xx/Makefile
rename to arch/arm/mach-samsung/Makefile
diff --git a/arch/arm/mach-s3c24xx/generic.c b/arch/arm/mach-samsung/generic.c
similarity index 100%
rename from arch/arm/mach-s3c24xx/generic.c
rename to arch/arm/mach-samsung/generic.c
diff --git a/arch/arm/mach-s3c24xx/gpio-s3c24x0.c b/arch/arm/mach-samsung/gpio-s3c24x0.c
similarity index 100%
rename from arch/arm/mach-s3c24xx/gpio-s3c24x0.c
rename to arch/arm/mach-samsung/gpio-s3c24x0.c
diff --git a/arch/arm/mach-s3c24xx/include/mach/fb.h b/arch/arm/mach-samsung/include/mach/fb.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/include/mach/fb.h
rename to arch/arm/mach-samsung/include/mach/fb.h
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio.h b/arch/arm/mach-samsung/include/mach/gpio.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/include/mach/gpio.h
rename to arch/arm/mach-samsung/include/mach/gpio.h
diff --git a/arch/arm/mach-s3c24xx/include/mach/iomux-s3c24x0.h b/arch/arm/mach-samsung/include/mach/iomux-s3c24x0.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/include/mach/iomux-s3c24x0.h
rename to arch/arm/mach-samsung/include/mach/iomux-s3c24x0.h
diff --git a/arch/arm/mach-s3c24xx/include/mach/mci.h b/arch/arm/mach-samsung/include/mach/mci.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/include/mach/mci.h
rename to arch/arm/mach-samsung/include/mach/mci.h
diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c24x0-iomap.h b/arch/arm/mach-samsung/include/mach/s3c24x0-iomap.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/include/mach/s3c24x0-iomap.h
rename to arch/arm/mach-samsung/include/mach/s3c24x0-iomap.h
diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h b/arch/arm/mach-samsung/include/mach/s3c24x0-nand.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h
rename to arch/arm/mach-samsung/include/mach/s3c24x0-nand.h
diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c24xx-generic.h b/arch/arm/mach-samsung/include/mach/s3c24xx-generic.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/include/mach/s3c24xx-generic.h
rename to arch/arm/mach-samsung/include/mach/s3c24xx-generic.h
diff --git a/arch/arm/mach-s3c24xx/lowlevel-init.S b/arch/arm/mach-samsung/lowlevel-init.S
similarity index 100%
rename from arch/arm/mach-s3c24xx/lowlevel-init.S
rename to arch/arm/mach-samsung/lowlevel-init.S
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 02/14] MACH SAMSUNG/S3C: Do not compile S3C24xx's GPIO support unconditionally
2012-01-02 11:43 [PATCH v2] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
2012-01-02 11:43 ` [PATCH 01/14] MACH SAMSUNG: Rename the whole mach to add more CPUs in future Juergen Beisert
@ 2012-01-02 11:43 ` Juergen Beisert
2012-01-02 11:43 ` [PATCH 03/14] MACH SAMSUNG/S3C: Make it more generic for future updates Juergen Beisert
` (11 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2012-01-02 11:43 UTC (permalink / raw)
To: barebox
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/mach-samsung/Makefile | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index 88d45fe..f329cdb 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -1,2 +1,3 @@
-obj-y += generic.o gpio-s3c24x0.o
+obj-y += generic.o
+obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o
obj-$(CONFIG_S3C24XX_LOW_LEVEL_INIT) += lowlevel-init.o
--
1.7.7.3
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 03/14] MACH SAMSUNG/S3C: Make it more generic for future updates
2012-01-02 11:43 [PATCH v2] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
2012-01-02 11:43 ` [PATCH 01/14] MACH SAMSUNG: Rename the whole mach to add more CPUs in future Juergen Beisert
2012-01-02 11:43 ` [PATCH 02/14] MACH SAMSUNG/S3C: Do not compile S3C24xx's GPIO support unconditionally Juergen Beisert
@ 2012-01-02 11:43 ` Juergen Beisert
2012-01-02 11:43 ` [PATCH 04/14] MACH SAMSUNG/S3C: Use the correct CPU family name to reflect NAND driver's usage Juergen Beisert
` (10 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2012-01-02 11:43 UTC (permalink / raw)
To: barebox
Start with renaming files to share them in the S3C CPU family,
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/a9m2410/a9m2410.c | 2 +-
arch/arm/boards/a9m2410/lowlevel_init.S | 2 +-
arch/arm/boards/a9m2440/a9m2410dev.c | 2 +-
arch/arm/boards/a9m2440/a9m2440.c | 4 ++--
arch/arm/boards/a9m2440/lowlevel_init.S | 2 +-
arch/arm/boards/mini2440/lowlevel_init.S | 2 +-
arch/arm/boards/mini2440/mini2440.c | 4 ++--
arch/arm/mach-samsung/generic.c | 2 +-
arch/arm/mach-samsung/gpio-s3c24x0.c | 2 +-
arch/arm/mach-samsung/include/mach/gpio.h | 7 +------
.../mach/{s3c24xx-generic.h => s3c-generic.h} | 0
.../include/mach/{s3c24x0-iomap.h => s3c-iomap.h} | 0
arch/arm/mach-samsung/lowlevel-init.S | 2 +-
drivers/mci/s3c.c | 4 ++--
drivers/mtd/nand/nand_s3c2410.c | 4 ++--
drivers/serial/serial_s3c24x0.c | 4 ++--
drivers/video/s3c.c | 2 +-
17 files changed, 20 insertions(+), 25 deletions(-)
rename arch/arm/mach-samsung/include/mach/{s3c24xx-generic.h => s3c-generic.h} (100%)
rename arch/arm/mach-samsung/include/mach/{s3c24x0-iomap.h => s3c-iomap.h} (100%)
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index bbe1604..14eaa1b 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -32,7 +32,7 @@
#include <partition.h>
#include <nand.h>
#include <io.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
#include <mach/s3c24x0-nand.h>
// {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
diff --git a/arch/arm/boards/a9m2410/lowlevel_init.S b/arch/arm/boards/a9m2410/lowlevel_init.S
index 461b93c..752c668 100644
--- a/arch/arm/boards/a9m2410/lowlevel_init.S
+++ b/arch/arm/boards/a9m2410/lowlevel_init.S
@@ -3,7 +3,7 @@
*/
#include <config.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
.section ".text_bare_init.board_init_lowlevel","ax"
diff --git a/arch/arm/boards/a9m2440/a9m2410dev.c b/arch/arm/boards/a9m2440/a9m2410dev.c
index 5f7c53b..aa5da88 100644
--- a/arch/arm/boards/a9m2440/a9m2410dev.c
+++ b/arch/arm/boards/a9m2440/a9m2410dev.c
@@ -28,7 +28,7 @@
#include <driver.h>
#include <init.h>
#include <io.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
/**
* Initialize the CPU to be able to work with the a9m2410dev evaluation board
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 964d376..9002052 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -32,9 +32,9 @@
#include <partition.h>
#include <nand.h>
#include <io.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
#include <mach/s3c24x0-nand.h>
-#include <mach/s3c24xx-generic.h>
+#include <mach/s3c-generic.h>
#include "baseboards.h"
diff --git a/arch/arm/boards/a9m2440/lowlevel_init.S b/arch/arm/boards/a9m2440/lowlevel_init.S
index 4b5c596..bfdd7f0 100644
--- a/arch/arm/boards/a9m2440/lowlevel_init.S
+++ b/arch/arm/boards/a9m2440/lowlevel_init.S
@@ -3,7 +3,7 @@
*/
#include <config.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
.section ".text_bare_init.board_init_lowlevel","ax"
diff --git a/arch/arm/boards/mini2440/lowlevel_init.S b/arch/arm/boards/mini2440/lowlevel_init.S
index 41f50cb..f114bb7 100644
--- a/arch/arm/boards/mini2440/lowlevel_init.S
+++ b/arch/arm/boards/mini2440/lowlevel_init.S
@@ -3,7 +3,7 @@
*/
#include <config.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
.section ".text_bare_init.board_init_lowlevel","ax"
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index b4cc0f8..5e6910b 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -38,9 +38,9 @@
#include <asm/armlinux.h>
#include <io.h>
#include <mach/gpio.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
#include <mach/s3c24x0-nand.h>
-#include <mach/s3c24xx-generic.h>
+#include <mach/s3c-generic.h>
#include <mach/mci.h>
#include <mach/fb.h>
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
index d2f2ac7..3c24b1a 100644
--- a/arch/arm/mach-samsung/generic.c
+++ b/arch/arm/mach-samsung/generic.c
@@ -27,7 +27,7 @@
#include <init.h>
#include <clock.h>
#include <io.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
/**
* Calculate the current M-PLL clock.
diff --git a/arch/arm/mach-samsung/gpio-s3c24x0.c b/arch/arm/mach-samsung/gpio-s3c24x0.c
index 946ec33..23b2609 100644
--- a/arch/arm/mach-samsung/gpio-s3c24x0.c
+++ b/arch/arm/mach-samsung/gpio-s3c24x0.c
@@ -18,7 +18,7 @@
#include <common.h>
#include <errno.h>
#include <io.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
#include <mach/gpio.h>
static const unsigned char group_offset[] =
diff --git a/arch/arm/mach-samsung/include/mach/gpio.h b/arch/arm/mach-samsung/include/mach/gpio.h
index 37db4f5..3723394 100644
--- a/arch/arm/mach-samsung/include/mach/gpio.h
+++ b/arch/arm/mach-samsung/include/mach/gpio.h
@@ -8,17 +8,12 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
*/
#ifndef __ASM_MACH_GPIO_H
#define __ASM_MACH_GPIO_H
-#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2410)
+#ifdef CONFIG_ARCH_S3C24xx
# include <mach/iomux-s3c24x0.h>
#endif
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-generic.h b/arch/arm/mach-samsung/include/mach/s3c-generic.h
similarity index 100%
rename from arch/arm/mach-samsung/include/mach/s3c24xx-generic.h
rename to arch/arm/mach-samsung/include/mach/s3c-generic.h
diff --git a/arch/arm/mach-samsung/include/mach/s3c24x0-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
similarity index 100%
rename from arch/arm/mach-samsung/include/mach/s3c24x0-iomap.h
rename to arch/arm/mach-samsung/include/mach/s3c-iomap.h
diff --git a/arch/arm/mach-samsung/lowlevel-init.S b/arch/arm/mach-samsung/lowlevel-init.S
index e8004e5..8529283 100644
--- a/arch/arm/mach-samsung/lowlevel-init.S
+++ b/arch/arm/mach-samsung/lowlevel-init.S
@@ -19,7 +19,7 @@
*/
#include <config.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
.section ".text_bare_init.s3c24x0_disable_wd","ax"
diff --git a/drivers/mci/s3c.c b/drivers/mci/s3c.c
index 89c8168..c877e09 100644
--- a/drivers/mci/s3c.c
+++ b/drivers/mci/s3c.c
@@ -41,8 +41,8 @@
#include <clock.h>
#include <io.h>
#include <mach/mci.h>
-#include <mach/s3c24xx-generic.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-iomap.h>
#define SDICON 0x0
# define SDICON_SDRESET (1 << 8)
diff --git a/drivers/mtd/nand/nand_s3c2410.c b/drivers/mtd/nand/nand_s3c2410.c
index ed45788..3117614 100644
--- a/drivers/mtd/nand/nand_s3c2410.c
+++ b/drivers/mtd/nand/nand_s3c2410.c
@@ -30,8 +30,8 @@
#include <init.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
-#include <mach/s3c24xx-generic.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-iomap.h>
#include <mach/s3c24x0-nand.h>
#include <io.h>
#include <asm-generic/errno.h>
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
index 1e27d48..4e95e5c 100644
--- a/drivers/serial/serial_s3c24x0.c
+++ b/drivers/serial/serial_s3c24x0.c
@@ -25,8 +25,8 @@
#include <init.h>
#include <malloc.h>
#include <io.h>
-#include <mach/s3c24xx-generic.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-iomap.h>
/* Note: Offsets are for little endian access */
#define ULCON 0x00 /* line control */
diff --git a/drivers/video/s3c.c b/drivers/video/s3c.c
index b17aeb6..a03ec3d 100644
--- a/drivers/video/s3c.c
+++ b/drivers/video/s3c.c
@@ -31,7 +31,7 @@
#include <errno.h>
#include <io.h>
#include <mach/gpio.h>
-#include <mach/s3c24xx-generic.h>
+#include <mach/s3c-generic.h>
#include <mach/fb.h>
#define LCDCON1 0x00
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 04/14] MACH SAMSUNG/S3C: Use the correct CPU family name to reflect NAND driver's usage
2012-01-02 11:43 [PATCH v2] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (2 preceding siblings ...)
2012-01-02 11:43 ` [PATCH 03/14] MACH SAMSUNG/S3C: Make it more generic for future updates Juergen Beisert
@ 2012-01-02 11:43 ` Juergen Beisert
2012-01-02 11:43 ` [PATCH 05/14] MACH SAMSUNG/S3C: Parts of the SDHC driver can be shared in the S3C CPU family Juergen Beisert
` (9 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2012-01-02 11:43 UTC (permalink / raw)
To: barebox
The aready existing NAND controller driver in Barebox is for the S3C24XX family
only. Change the name of the file to reflect this fact (and free the way to add
more recent Samsung NAND controllers)
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/a9m2410/a9m2410.c | 2 +-
arch/arm/boards/a9m2440/a9m2440.c | 2 +-
arch/arm/boards/mini2440/mini2440.c | 2 +-
arch/arm/mach-samsung/Kconfig | 2 +-
.../mach/{s3c24x0-nand.h => s3c24xx-nand.h} | 0
drivers/mtd/nand/Kconfig | 4 ++--
drivers/mtd/nand/Makefile | 2 +-
.../mtd/nand/{nand_s3c2410.c => nand_s3c24xx.c} | 6 +++---
8 files changed, 10 insertions(+), 10 deletions(-)
rename arch/arm/mach-samsung/include/mach/{s3c24x0-nand.h => s3c24xx-nand.h} (100%)
rename drivers/mtd/nand/{nand_s3c2410.c => nand_s3c24xx.c} (99%)
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index 14eaa1b..989dcf7 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -33,7 +33,7 @@
#include <nand.h>
#include <io.h>
#include <mach/s3c-iomap.h>
-#include <mach/s3c24x0-nand.h>
+#include <mach/s3c24xx-nand.h>
// {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
static struct s3c24x0_nand_platform_data nand_info = {
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 9002052..1986efb 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -33,7 +33,7 @@
#include <nand.h>
#include <io.h>
#include <mach/s3c-iomap.h>
-#include <mach/s3c24x0-nand.h>
+#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
#include "baseboards.h"
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 5e6910b..dca9083 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -39,7 +39,7 @@
#include <io.h>
#include <mach/gpio.h>
#include <mach/s3c-iomap.h>
-#include <mach/s3c24x0-nand.h>
+#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
#include <mach/mci.h>
#include <mach/fb.h>
diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig
index a800cb8..bc283dc 100644
--- a/arch/arm/mach-samsung/Kconfig
+++ b/arch/arm/mach-samsung/Kconfig
@@ -105,7 +105,7 @@ config S3C24XX_NAND_BOOT
prompt "Booting from NAND"
select MTD
select NAND
- select NAND_S3C24X0
+ select NAND_S3C24XX
help
Add generic support to boot from NAND flash. Image loading will be
skipped if the code is running from NOR or already from SDRAM.
diff --git a/arch/arm/mach-samsung/include/mach/s3c24x0-nand.h b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
similarity index 100%
rename from arch/arm/mach-samsung/include/mach/s3c24x0-nand.h
rename to arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index bda0529..926a64b 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -65,9 +65,9 @@ config NAND_ATMEL
prompt "Atmel (AT91SAM9xxx) NAND driver"
depends on ARCH_AT91
-config NAND_S3C24X0
+config NAND_S3C24XX
bool
- prompt "Samsung S3C24X0 NAND driver"
+ prompt "Samsung S3C24XX NAND driver"
depends on ARCH_S3C24xx
help
Add support for processor's NAND device controller.
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 00b7b27..5c6d8b3 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -14,4 +14,4 @@ obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o
obj-$(CONFIG_NAND_IMX) += nand_imx.o
obj-$(CONFIG_NAND_OMAP_GPMC) += nand_omap_gpmc.o nand_omap_bch_decoder.o
obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
-obj-$(CONFIG_NAND_S3C24X0) += nand_s3c2410.o
+obj-$(CONFIG_NAND_S3C24XX) += nand_s3c24xx.o
diff --git a/drivers/mtd/nand/nand_s3c2410.c b/drivers/mtd/nand/nand_s3c24xx.c
similarity index 99%
rename from drivers/mtd/nand/nand_s3c2410.c
rename to drivers/mtd/nand/nand_s3c24xx.c
index 3117614..c4fd13e 100644
--- a/drivers/mtd/nand/nand_s3c2410.c
+++ b/drivers/mtd/nand/nand_s3c24xx.c
@@ -32,7 +32,7 @@
#include <linux/mtd/nand.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-iomap.h>
-#include <mach/s3c24x0-nand.h>
+#include <mach/s3c24xx-nand.h>
#include <io.h>
#include <asm-generic/errno.h>
@@ -485,8 +485,8 @@ static int s3c24x0_nand_probe(struct device_d *dev)
goto on_error;
}
- return add_mtd_device(mtd, "nand");
-
+ return add_mtd_device(mtd);
+
on_error:
free(host);
return ret;
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 05/14] MACH SAMSUNG/S3C: Parts of the SDHC driver can be shared in the S3C CPU family
2012-01-02 11:43 [PATCH v2] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (3 preceding siblings ...)
2012-01-02 11:43 ` [PATCH 04/14] MACH SAMSUNG/S3C: Use the correct CPU family name to reflect NAND driver's usage Juergen Beisert
@ 2012-01-02 11:43 ` Juergen Beisert
2012-01-02 11:43 ` [PATCH 06/14] MACH SAMSUNG/S3C: Reflect the CPU name the LCD driver is for Juergen Beisert
` (8 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2012-01-02 11:43 UTC (permalink / raw)
To: barebox
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/mini2440/mini2440.c | 2 +-
.../mach-samsung/include/mach/{mci.h => s3c-mci.h} | 0
drivers/mci/s3c.c | 2 +-
3 files changed, 2 insertions(+), 2 deletions(-)
rename arch/arm/mach-samsung/include/mach/{mci.h => s3c-mci.h} (100%)
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index dca9083..233f337 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -41,7 +41,7 @@
#include <mach/s3c-iomap.h>
#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
-#include <mach/mci.h>
+#include <mach/s3c-mci.h>
#include <mach/fb.h>
static struct s3c24x0_nand_platform_data nand_info = {
diff --git a/arch/arm/mach-samsung/include/mach/mci.h b/arch/arm/mach-samsung/include/mach/s3c-mci.h
similarity index 100%
rename from arch/arm/mach-samsung/include/mach/mci.h
rename to arch/arm/mach-samsung/include/mach/s3c-mci.h
diff --git a/drivers/mci/s3c.c b/drivers/mci/s3c.c
index c877e09..12d2c03 100644
--- a/drivers/mci/s3c.c
+++ b/drivers/mci/s3c.c
@@ -40,7 +40,7 @@
#include <errno.h>
#include <clock.h>
#include <io.h>
-#include <mach/mci.h>
+#include <mach/s3c-mci.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-iomap.h>
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 06/14] MACH SAMSUNG/S3C: Reflect the CPU name the LCD driver is for
2012-01-02 11:43 [PATCH v2] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (4 preceding siblings ...)
2012-01-02 11:43 ` [PATCH 05/14] MACH SAMSUNG/S3C: Parts of the SDHC driver can be shared in the S3C CPU family Juergen Beisert
@ 2012-01-02 11:43 ` Juergen Beisert
2012-01-02 11:43 ` [PATCH 07/14] MACH SAMSUNG/S3C: Separate S3C24XX clock management Juergen Beisert
` (7 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2012-01-02 11:43 UTC (permalink / raw)
To: barebox
This LCD driver is for the LCD controller in the S3C2410/S3C2440 CPUs only.
Change its name to reflect its usage and free the way to add LCD controller
drivers for more recent Samsung CPUs.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/mini2440/mini2440.c | 2 +-
.../include/mach/{fb.h => s3c24xx-fb.h} | 0
drivers/video/Kconfig | 2 +-
drivers/video/Makefile | 2 +-
drivers/video/{s3c.c => s3c24xx.c} | 4 ++--
5 files changed, 5 insertions(+), 5 deletions(-)
rename arch/arm/mach-samsung/include/mach/{fb.h => s3c24xx-fb.h} (100%)
rename drivers/video/{s3c.c => s3c24xx.c} (99%)
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 233f337..0186465 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -42,7 +42,7 @@
#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-mci.h>
-#include <mach/fb.h>
+#include <mach/s3c24xx-fb.h>
static struct s3c24x0_nand_platform_data nand_info = {
.nand_timing = CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0,
diff --git a/arch/arm/mach-samsung/include/mach/fb.h b/arch/arm/mach-samsung/include/mach/s3c24xx-fb.h
similarity index 100%
rename from arch/arm/mach-samsung/include/mach/fb.h
rename to arch/arm/mach-samsung/include/mach/s3c24xx-fb.h
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index df2157e..4a05af9 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -27,7 +27,7 @@ config DRIVER_VIDEO_STM
Say 'Y' here to enable framebuffer and splash screen support for
i.MX23 and i.MX28 based systems.
-config DRIVER_VIDEO_S3C
+config DRIVER_VIDEO_S3C24XX
bool "S3C244x framebuffer driver"
depends on ARCH_S3C24xx
help
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 123c46f..913c78d 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -3,5 +3,5 @@ obj-$(CONFIG_VIDEO) += fb.o
obj-$(CONFIG_DRIVER_VIDEO_STM) += stm.o
obj-$(CONFIG_DRIVER_VIDEO_IMX) += imx.o
obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
-obj-$(CONFIG_DRIVER_VIDEO_S3C) += s3c.o
+obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
diff --git a/drivers/video/s3c.c b/drivers/video/s3c24xx.c
similarity index 99%
rename from drivers/video/s3c.c
rename to drivers/video/s3c24xx.c
index a03ec3d..75677c3 100644
--- a/drivers/video/s3c.c
+++ b/drivers/video/s3c24xx.c
@@ -30,9 +30,9 @@
#include <malloc.h>
#include <errno.h>
#include <io.h>
-#include <mach/gpio.h>
+#include <mach/s3c-gpio.h>
#include <mach/s3c-generic.h>
-#include <mach/fb.h>
+#include <mach/s3c24xx-fb.h>
#define LCDCON1 0x00
# define PNRMODE(x) (((x) & 3) << 5)
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 07/14] MACH SAMSUNG/S3C: Separate S3C24XX clock management
2012-01-02 11:43 [PATCH v2] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (5 preceding siblings ...)
2012-01-02 11:43 ` [PATCH 06/14] MACH SAMSUNG/S3C: Reflect the CPU name the LCD driver is for Juergen Beisert
@ 2012-01-02 11:43 ` Juergen Beisert
2012-01-02 11:43 ` [PATCH 08/14] MACH SAMSUNG/S3C: Separate the clocksource for the S3C family Juergen Beisert
` (6 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2012-01-02 11:43 UTC (permalink / raw)
To: barebox
There are major differences in the clock tree of the S3C24xx family and the
more recent CPUs of the S3C family. Keep the S3C24XX clock routines separate to
avoid an ifdef hell. But also use generic function names to be able to
share drivers among the S3C family.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/mach-samsung/Makefile | 2 +-
arch/arm/mach-samsung/generic.c | 117 +------------------
arch/arm/mach-samsung/include/mach/s3c-clocks.h | 31 +++++
arch/arm/mach-samsung/include/mach/s3c-generic.h | 12 +-
arch/arm/mach-samsung/include/mach/s3c-iomap.h | 11 +--
arch/arm/mach-samsung/lowlevel-init.S | 2 +-
arch/arm/mach-samsung/s3c24xx-clocks.c | 137 ++++++++++++++++++++++
drivers/mci/s3c.c | 10 +-
drivers/serial/serial_s3c24x0.c | 2 +-
drivers/video/s3c24xx.c | 4 +-
10 files changed, 187 insertions(+), 141 deletions(-)
create mode 100644 arch/arm/mach-samsung/include/mach/s3c-clocks.h
create mode 100644 arch/arm/mach-samsung/s3c24xx-clocks.c
diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index f329cdb..c590180 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -1,3 +1,3 @@
obj-y += generic.o
-obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o
+obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o
obj-$(CONFIG_S3C24XX_LOW_LEVEL_INIT) += lowlevel-init.o
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
index 3c24b1a..3f6e801 100644
--- a/arch/arm/mach-samsung/generic.c
+++ b/arch/arm/mach-samsung/generic.c
@@ -28,100 +28,7 @@
#include <clock.h>
#include <io.h>
#include <mach/s3c-iomap.h>
-
-/**
- * Calculate the current M-PLL clock.
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_mpllclk(void)
-{
- uint32_t m, p, s, reg_val;
-
- reg_val = readl(MPLLCON);
- m = ((reg_val & 0xFF000) >> 12) + 8;
- p = ((reg_val & 0x003F0) >> 4) + 2;
- s = reg_val & 0x3;
-#ifdef CONFIG_CPU_S3C2410
- return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
-#endif
-#ifdef CONFIG_CPU_S3C2440
- return 2 * m * (S3C24XX_CLOCK_REFERENCE / (p << s));
-#endif
-}
-
-/**
- * Calculate the current U-PLL clock
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_upllclk(void)
-{
- uint32_t m, p, s, reg_val;
-
- reg_val = readl(UPLLCON);
- m = ((reg_val & 0xFF000) >> 12) + 8;
- p = ((reg_val & 0x003F0) >> 4) + 2;
- s = reg_val & 0x3;
-
- return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
-}
-
-/**
- * Calculate the FCLK frequency used for the ARM CPU core
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_fclk(void)
-{
- return s3c24xx_get_mpllclk();
-}
-
-/**
- * Calculate the HCLK frequency used for the AHB bus (CPU to main peripheral)
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_hclk(void)
-{
- uint32_t f_clk;
-
- f_clk = s3c24xx_get_fclk();
-#ifdef CONFIG_CPU_S3C2410
- if (readl(CLKDIVN) & 0x02)
- return f_clk >> 1;
-#endif
-#ifdef CONFIG_CPU_S3C2440
- switch(readl(CLKDIVN) & 0x06) {
- case 2:
- return f_clk >> 1;
- case 4:
- return f_clk >> 2; /* TODO consider CAMDIVN */
- case 6:
- return f_clk / 3; /* TODO consider CAMDIVN */
- }
-#endif
- return f_clk;
-}
-
-/**
- * Calculate the PCLK frequency used for the slower peripherals
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_pclk(void)
-{
- uint32_t p_clk;
-
- p_clk = s3c24xx_get_hclk();
- if (readl(CLKDIVN) & 0x01)
- return p_clk >> 1;
- return p_clk;
-}
-
-/**
- * Calculate the UCLK frequency used by the USB host device
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_uclk(void)
-{
- return s3c24xx_get_upllclk();
-}
+#include <mach/s3c-generic.h>
/**
* Calculate the amount of connected and available memory
@@ -169,26 +76,6 @@ uint32_t s3c24x0_get_memory_size(void)
return size;
}
-/**
- * Show the user the current clock settings
- */
-int s3c24xx_dump_clocks(void)
-{
- printf("refclk: %7d kHz\n", S3C24XX_CLOCK_REFERENCE / 1000);
- printf("mpll: %7d kHz\n", s3c24xx_get_mpllclk() / 1000);
- printf("upll: %7d kHz\n", s3c24xx_get_upllclk() / 1000);
- printf("fclk: %7d kHz\n", s3c24xx_get_fclk() / 1000);
- printf("hclk: %7d kHz\n", s3c24xx_get_hclk() / 1000);
- printf("pclk: %7d kHz\n", s3c24xx_get_pclk() / 1000);
- printf("SDRAM1: CL%d@%dMHz\n", ((readl(BANKCON6) & 0xc) >> 2) + 2, s3c24xx_get_hclk() / 1000000);
- if ((readl(BANKCON7) & (0x3 << 15)) == (0x3 << 15))
- printf("SDRAM2: CL%d@%dMHz\n", ((readl(BANKCON7) & 0xc) >> 2) + 2,
- s3c24xx_get_hclk() / 1000000);
- return 0;
-}
-
-late_initcall(s3c24xx_dump_clocks);
-
static uint64_t s3c24xx_clocksource_read(void)
{
/* note: its a down counter */
@@ -203,7 +90,7 @@ static struct clocksource cs = {
static int clocksource_init (void)
{
- uint32_t p_clk = s3c24xx_get_pclk();
+ uint32_t p_clk = s3c_get_pclk();
writel(0x00000000, TCON); /* stop all timers */
writel(0x00ffffff, TCFG0); /* PCLK / (255 + 1) for timer 4 */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-clocks.h b/arch/arm/mach-samsung/include/mach/s3c-clocks.h
new file mode 100644
index 0000000..44b2a6c
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c-clocks.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2011 Juergen Beisert, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_S3C_CLOCKS_H
+# define __MACH_S3C_CLOCKS_H
+
+#ifdef CONFIG_ARCH_S3C24xx
+# define S3C_LOCKTIME (S3C_CLOCK_POWER_BASE)
+# define S3C_MPLLCON (S3C_CLOCK_POWER_BASE + 0x4)
+# define S3C_UPLLCON (S3C_CLOCK_POWER_BASE + 0x8)
+# define S3C_CLKCON (S3C_CLOCK_POWER_BASE + 0xc)
+# define S3C_CLKSLOW (S3C_CLOCK_POWER_BASE + 0x10)
+# define S3C_CLKDIVN (S3C_CLOCK_POWER_BASE + 0x14)
+
+# define S3C_MPLLCON_GET_MDIV(x) ((((x) >> 12) & 0xff) + 8)
+# define S3C_MPLLCON_GET_PDIV(x) ((((x) >> 4) & 0x3f) + 2)
+# define S3C_MPLLCON_GET_SDIV(x) ((x) & 0x3)
+#endif
+
+#endif /* __MACH_S3C_CLOCKS_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-generic.h b/arch/arm/mach-samsung/include/mach/s3c-generic.h
index b8abcf1..33f025d 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-generic.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-generic.h
@@ -24,10 +24,10 @@
* MA 02111-1307 USA
*/
-uint32_t s3c24xx_get_mpllclk(void);
-uint32_t s3c24xx_get_upllclk(void);
-uint32_t s3c24xx_get_fclk(void);
-uint32_t s3c24xx_get_hclk(void);
-uint32_t s3c24xx_get_pclk(void);
-uint32_t s3c24xx_get_uclk(void);
+uint32_t s3c_get_mpllclk(void);
+uint32_t s3c_get_upllclk(void);
+uint32_t s3c_get_fclk(void);
+uint32_t s3c_get_hclk(void);
+uint32_t s3c_get_pclk(void);
+uint32_t s3c_get_uclk(void);
uint32_t s3c24x0_get_memory_size(void);
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index a990d80..7cedf6a 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -25,7 +25,7 @@
#define S3C2410_USB_HOST_BASE 0x49000000
#define S3C2410_INTERRUPT_BASE 0x4A000000
#define S3C2410_DMA_BASE 0x4B000000
-#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
+#define S3C_CLOCK_POWER_BASE 0x4C000000
#define S3C2410_LCD_BASE 0x4D000000
#define S3C24X0_NAND_BASE 0x4E000000
#define S3C24X0_UART_BASE 0x50000000
@@ -40,15 +40,6 @@
#define S3C2410_SPI_BASE 0x59000000
#define S3C2410_SDI_BASE 0x5A000000
-/* Clock control (direct access) */
-
-#define LOCKTIME (S3C24X0_CLOCK_POWER_BASE)
-#define MPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x4)
-#define UPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x8)
-#define CLKCON (S3C24X0_CLOCK_POWER_BASE + 0xc)
-#define CLKSLOW (S3C24X0_CLOCK_POWER_BASE + 0x10)
-#define CLKDIVN (S3C24X0_CLOCK_POWER_BASE + 0x14)
-
/* Timer (direct access) */
#define TCFG0 (S3C24X0_TIMER_BASE + 0x00)
#define TCFG1 (S3C24X0_TIMER_BASE + 0x04)
diff --git a/arch/arm/mach-samsung/lowlevel-init.S b/arch/arm/mach-samsung/lowlevel-init.S
index 8529283..e2e3fc0 100644
--- a/arch/arm/mach-samsung/lowlevel-init.S
+++ b/arch/arm/mach-samsung/lowlevel-init.S
@@ -77,7 +77,7 @@ routine very early in your board_init_lowlevel routine.
.globl s3c24x0_pll_init
s3c24x0_pll_init:
- mov r0, #S3C24X0_CLOCK_POWER_BASE
+ mov r0, #S3C_CLOCK_POWER_BASE
/* configure internal clock ratio */
mov r1, #BOARD_SPECIFIC_CLKDIVN
diff --git a/arch/arm/mach-samsung/s3c24xx-clocks.c b/arch/arm/mach-samsung/s3c24xx-clocks.c
new file mode 100644
index 0000000..beacc76
--- /dev/null
+++ b/arch/arm/mach-samsung/s3c24xx-clocks.c
@@ -0,0 +1,137 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+#include <io.h>
+#include <mach/s3c-iomap.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-clocks.h>
+
+/**
+ * Calculate the current M-PLL clock.
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_mpllclk(void)
+{
+ uint32_t m, p, s, reg_val;
+
+ reg_val = readl(S3C_MPLLCON);
+ m = ((reg_val & 0xFF000) >> 12) + 8;
+ p = ((reg_val & 0x003F0) >> 4) + 2;
+ s = reg_val & 0x3;
+#ifdef CONFIG_CPU_S3C2410
+ return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
+#endif
+#ifdef CONFIG_CPU_S3C2440
+ return 2 * m * (S3C24XX_CLOCK_REFERENCE / (p << s));
+#endif
+}
+
+/**
+ * Calculate the current U-PLL clock
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_upllclk(void)
+{
+ uint32_t m, p, s, reg_val;
+
+ reg_val = readl(S3C_UPLLCON);
+ m = ((reg_val & 0xFF000) >> 12) + 8;
+ p = ((reg_val & 0x003F0) >> 4) + 2;
+ s = reg_val & 0x3;
+
+ return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
+}
+
+/**
+ * Calculate the FCLK frequency used for the ARM CPU core
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_fclk(void)
+{
+ return s3c_get_mpllclk();
+}
+
+/**
+ * Calculate the HCLK frequency used for the AHB bus (CPU to main peripheral)
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_hclk(void)
+{
+ uint32_t f_clk;
+
+ f_clk = s3c_get_fclk();
+#ifdef CONFIG_CPU_S3C2410
+ if (readl(S3C_CLKDIVN) & 0x02)
+ return f_clk >> 1;
+#endif
+#ifdef CONFIG_CPU_S3C2440
+ switch(readl(S3C_CLKDIVN) & 0x06) {
+ case 2:
+ return f_clk >> 1;
+ case 4:
+ return f_clk >> 2; /* TODO consider CAMDIVN */
+ case 6:
+ return f_clk / 3; /* TODO consider CAMDIVN */
+ }
+#endif
+ return f_clk;
+}
+
+/**
+ * Calculate the PCLK frequency used for the slower peripherals
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_pclk(void)
+{
+ uint32_t p_clk;
+
+ p_clk = s3c_get_hclk();
+ if (readl(S3C_CLKDIVN) & 0x01)
+ return p_clk >> 1;
+ return p_clk;
+}
+
+/**
+ * Calculate the UCLK frequency used by the USB host device
+ * @return Current frequency in Hz
+ */
+uint32_t s3c24_get_uclk(void)
+{
+ return s3c_get_upllclk();
+}
+
+/**
+ * Show the user the current clock settings
+ */
+int s3c24xx_dump_clocks(void)
+{
+ printf("refclk: %7d kHz\n", S3C24XX_CLOCK_REFERENCE / 1000);
+ printf("mpll: %7d kHz\n", s3c_get_mpllclk() / 1000);
+ printf("upll: %7d kHz\n", s3c_get_upllclk() / 1000);
+ printf("fclk: %7d kHz\n", s3c_get_fclk() / 1000);
+ printf("hclk: %7d kHz\n", s3c_get_hclk() / 1000);
+ printf("pclk: %7d kHz\n", s3c_get_pclk() / 1000);
+ printf("SDRAM1: CL%d@%dMHz\n", ((readl(BANKCON6) & 0xc) >> 2) + 2, s3c_get_hclk() / 1000000);
+ if ((readl(BANKCON7) & (0x3 << 15)) == (0x3 << 15))
+ printf("SDRAM2: CL%d@%dMHz\n", ((readl(BANKCON7) & 0xc) >> 2) + 2,
+ s3c_get_hclk() / 1000000);
+ return 0;
+}
+
+late_initcall(s3c24xx_dump_clocks);
diff --git a/drivers/mci/s3c.c b/drivers/mci/s3c.c
index 12d2c03..7babab4 100644
--- a/drivers/mci/s3c.c
+++ b/drivers/mci/s3c.c
@@ -191,7 +191,7 @@ static unsigned s3c_setup_clock_speed(struct device_d *hw_dev, unsigned nc)
if (nc == 0)
return 0;
- clock = s3c24xx_get_pclk();
+ clock = s3c_get_pclk();
/* Calculate the required prescaler value to get the requested frequency */
mci_psc = (clock + (nc >> 2)) / nc;
@@ -760,8 +760,8 @@ static int s3c_mci_probe(struct device_d *hw_dev)
struct s3c_mci_platform_data *pd = hw_dev->platform_data;
/* TODO replace by the global func: enable the SDI unit clock */
- writel(readl(S3C24X0_CLOCK_POWER_BASE + 0x0c) | 0x200,
- S3C24X0_CLOCK_POWER_BASE + 0x0c);
+ writel(readl(S3C_CLOCK_POWER_BASE + 0x0c) | 0x200,
+ S3C_CLOCK_POWER_BASE + 0x0c);
if (pd == NULL) {
pr_err("Missing platform data\n");
@@ -775,8 +775,8 @@ static int s3c_mci_probe(struct device_d *hw_dev)
/* feed forward the platform specific values */
mci_pdata.voltages = pd->voltages;
mci_pdata.host_caps = pd->caps;
- mci_pdata.f_min = pd->f_min == 0 ? s3c24xx_get_pclk() / 256 : pd->f_min;
- mci_pdata.f_max = pd->f_max == 0 ? s3c24xx_get_pclk() / 2 : pd->f_max;
+ mci_pdata.f_min = pd->f_min == 0 ? s3c_get_pclk() / 256 : pd->f_min;
+ mci_pdata.f_max = pd->f_max == 0 ? s3c_get_pclk() / 2 : pd->f_max;
/*
* Start the clock to let the engine and the card finishes its startup
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
index 4e95e5c..4191a49 100644
--- a/drivers/serial/serial_s3c24x0.c
+++ b/drivers/serial/serial_s3c24x0.c
@@ -48,7 +48,7 @@ static int s3c24x0_serial_setbaudrate(struct console_device *cdev, int baudrate)
unsigned val;
/* value is calculated so : PCLK / (16 * baudrate) -1 */
- val = s3c24xx_get_pclk() / (16 * baudrate) - 1;
+ val = s3c_get_pclk() / (16 * baudrate) - 1;
writew(val, base + UBRDIV);
return 0;
diff --git a/drivers/video/s3c24xx.c b/drivers/video/s3c24xx.c
index 75677c3..f6af773 100644
--- a/drivers/video/s3c24xx.c
+++ b/drivers/video/s3c24xx.c
@@ -227,7 +227,7 @@ static int s3cfb_activate_var(struct fb_info *fb_info)
/* ensure video output is _off_ */
writel(0x00000000, fbi->base + LCDCON1);
- hclk = s3c24xx_get_hclk() / 1000U; /* hclk in kHz */
+ hclk = s3c_get_hclk() / 1000U; /* hclk in kHz */
div = hclk / PICOS2KHZ(mode->pixclock);
if (div < 3)
div = 3;
@@ -339,7 +339,7 @@ static void s3cfb_info(struct device_d *hw_dev)
addr3 = readl(fbi->base + LCDSADDR3);
printf(" Video hardware info:\n");
- printf(" Video clock is running at %u Hz\n", s3c24xx_get_hclk() / ((GET_CLKVAL(con1) + 1) * 2));
+ printf(" Video clock is running at %u Hz\n", s3c_get_hclk() / ((GET_CLKVAL(con1) + 1) * 2));
printf(" Video memory bank starts at 0x%08X\n", GET_LCDBANK(addr1) << 22);
printf(" Video memory bank offset: 0x%08X\n", GET_LCDBASEU(addr1));
printf(" Video memory end: 0x%08X\n", GET_LCDBASEU(addr2));
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 08/14] MACH SAMSUNG/S3C: Separate the clocksource for the S3C family
2012-01-02 11:43 [PATCH v2] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (6 preceding siblings ...)
2012-01-02 11:43 ` [PATCH 07/14] MACH SAMSUNG/S3C: Separate S3C24XX clock management Juergen Beisert
@ 2012-01-02 11:43 ` Juergen Beisert
2012-01-02 11:43 ` [PATCH 09/14] MACH SAMSUNG/S3C: Rename register macros to reflect the MACH they are valid for Juergen Beisert
` (5 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2012-01-02 11:43 UTC (permalink / raw)
To: barebox
This patch just move the clocksource functions out of the generic.c source file
to handle it on a per CPU base later on.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/mach-samsung/Makefile | 2 +-
arch/arm/mach-samsung/generic.c | 33 ----------------------
arch/arm/mach-samsung/s3c-timer.c | 55 +++++++++++++++++++++++++++++++++++++
3 files changed, 56 insertions(+), 34 deletions(-)
create mode 100644 arch/arm/mach-samsung/s3c-timer.c
diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index c590180..2ba5c3f 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -1,3 +1,3 @@
-obj-y += generic.o
+obj-y += s3c-timer.o generic.o
obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o
obj-$(CONFIG_S3C24XX_LOW_LEVEL_INIT) += lowlevel-init.o
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
index 3f6e801..83222e1 100644
--- a/arch/arm/mach-samsung/generic.c
+++ b/arch/arm/mach-samsung/generic.c
@@ -76,39 +76,6 @@ uint32_t s3c24x0_get_memory_size(void)
return size;
}
-static uint64_t s3c24xx_clocksource_read(void)
-{
- /* note: its a down counter */
- return 0xFFFF - readw(TCNTO4);
-}
-
-static struct clocksource cs = {
- .read = s3c24xx_clocksource_read,
- .mask = CLOCKSOURCE_MASK(16),
- .shift = 10,
-};
-
-static int clocksource_init (void)
-{
- uint32_t p_clk = s3c_get_pclk();
-
- writel(0x00000000, TCON); /* stop all timers */
- writel(0x00ffffff, TCFG0); /* PCLK / (255 + 1) for timer 4 */
- writel(0x00030000, TCFG1); /* /16 */
-
- writew(0xffff, TCNTB4); /* reload value is TOP */
-
- writel(0x00600000, TCON); /* force a first reload */
- writel(0x00400000, TCON);
- writel(0x00500000, TCON); /* enable timer 4 with auto reload */
-
- cs.mult = clocksource_hz2mult(p_clk / ((255 + 1) * 16), cs.shift);
- init_clock(&cs);
-
- return 0;
-}
-core_initcall(clocksource_init);
-
void __noreturn reset_cpu(unsigned long addr)
{
/* Disable watchdog */
diff --git a/arch/arm/mach-samsung/s3c-timer.c b/arch/arm/mach-samsung/s3c-timer.c
new file mode 100644
index 0000000..2b0b38a
--- /dev/null
+++ b/arch/arm/mach-samsung/s3c-timer.c
@@ -0,0 +1,55 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+#include <io.h>
+#include <mach/s3c-iomap.h>
+#include <mach/s3c-generic.h>
+
+static uint64_t s3c24xx_clocksource_read(void)
+{
+ /* note: its a down counter */
+ return 0xFFFF - readw(TCNTO4);
+}
+
+static struct clocksource cs = {
+ .read = s3c24xx_clocksource_read,
+ .mask = CLOCKSOURCE_MASK(16),
+ .shift = 10,
+};
+
+static int clocksource_init(void)
+{
+ uint32_t p_clk = s3c_get_pclk();
+
+ writel(0x00000000, TCON); /* stop all timers */
+ writel(0x00ffffff, TCFG0); /* PCLK / (255 + 1) for timer 4 */
+ writel(0x00030000, TCFG1); /* /16 */
+
+ writew(0xffff, TCNTB4); /* reload value is TOP */
+
+ writel(0x00600000, TCON); /* force a first reload */
+ writel(0x00400000, TCON);
+ writel(0x00500000, TCON); /* enable timer 4 with auto reload */
+
+ cs.mult = clocksource_hz2mult(p_clk / ((255 + 1) * 16), cs.shift);
+ init_clock(&cs);
+
+ return 0;
+}
+core_initcall(clocksource_init);
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 09/14] MACH SAMSUNG/S3C: Rename register macros to reflect the MACH they are valid for
2012-01-02 11:43 [PATCH v2] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (7 preceding siblings ...)
2012-01-02 11:43 ` [PATCH 08/14] MACH SAMSUNG/S3C: Separate the clocksource for the S3C family Juergen Beisert
@ 2012-01-02 11:43 ` Juergen Beisert
2012-01-02 11:43 ` [PATCH 10/14] MACH SAMSUNG/S3C: Re-work the S3C family timer driver Juergen Beisert
` (4 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2012-01-02 11:43 UTC (permalink / raw)
To: barebox
Most members of the S3Cxxxx family share similar timer units. But they are
not really register compatible. To reflect this, use a separate name space for
the S3C family.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/mach-samsung/include/mach/s3c-iomap.h | 20 +-------------
arch/arm/mach-samsung/s3c-timer.c | 33 ++++++++++++++++++------
2 files changed, 26 insertions(+), 27 deletions(-)
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index 7cedf6a..807660a 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -29,7 +29,7 @@
#define S3C2410_LCD_BASE 0x4D000000
#define S3C24X0_NAND_BASE 0x4E000000
#define S3C24X0_UART_BASE 0x50000000
-#define S3C24X0_TIMER_BASE 0x51000000
+#define S3C_TIMER_BASE 0x51000000
#define S3C2410_USB_DEVICE_BASE 0x52000140
#define S3C24X0_WATCHDOG_BASE 0x53000000
#define S3C2410_I2C_BASE 0x54000000
@@ -40,24 +40,6 @@
#define S3C2410_SPI_BASE 0x59000000
#define S3C2410_SDI_BASE 0x5A000000
-/* Timer (direct access) */
-#define TCFG0 (S3C24X0_TIMER_BASE + 0x00)
-#define TCFG1 (S3C24X0_TIMER_BASE + 0x04)
-#define TCON (S3C24X0_TIMER_BASE + 0x08)
-#define TCNTB0 (S3C24X0_TIMER_BASE + 0x0c)
-#define TCMPB0 (S3C24X0_TIMER_BASE + 0x10)
-#define TCNTO0 (S3C24X0_TIMER_BASE + 0x14)
-#define TCNTB1 (S3C24X0_TIMER_BASE + 0x18)
-#define TCMPB1 (S3C24X0_TIMER_BASE + 0x1c)
-#define TCNTO1 (S3C24X0_TIMER_BASE + 0x20)
-#define TCNTB2 (S3C24X0_TIMER_BASE + 0x24)
-#define TCMPB2 (S3C24X0_TIMER_BASE + 0x28)
-#define TCNTO2 (S3C24X0_TIMER_BASE + 0x2c)
-#define TCNTB3 (S3C24X0_TIMER_BASE + 0x30)
-#define TCMPB3 (S3C24X0_TIMER_BASE + 0x34)
-#define TCNTO3 (S3C24X0_TIMER_BASE + 0x38)
-#define TCNTB4 (S3C24X0_TIMER_BASE + 0x3c)
-#define TCNTO4 (S3C24X0_TIMER_BASE + 0x40)
/* Watchdog (direct access) */
#define WTCON (S3C24X0_WATCHDOG_BASE)
diff --git a/arch/arm/mach-samsung/s3c-timer.c b/arch/arm/mach-samsung/s3c-timer.c
index 2b0b38a..d9dae55 100644
--- a/arch/arm/mach-samsung/s3c-timer.c
+++ b/arch/arm/mach-samsung/s3c-timer.c
@@ -21,10 +21,27 @@
#include <mach/s3c-iomap.h>
#include <mach/s3c-generic.h>
+#define S3C_TCFG0 (S3C_TIMER_BASE + 0x00)
+# define S3C_TCFG0_T4MASK 0xff00
+# define S3C_TCFG0_SET_PSCL234(x) ((x) << 8)
+# define S3C_TCFG0_GET_PSCL234(x) (((x) >> 8) & 0xff)
+#define S3C_TCFG1 (S3C_TIMER_BASE + 0x04)
+# define S3C_TCFG1_T4MASK 0xf0000
+# define S3C_TCFG1_SET_T4MUX(x) ((x) << 16)
+# define S3C_TCFG1_GET_T4MUX(x) (((x) >> 16) & 0xf)
+#define S3C_TCON (S3C_TIMER_BASE + 0x08)
+# define S3C_TCON_T4MASK (7 << 20)
+# define S3C_TCON_T4START (1 << 20)
+# define S3C_TCON_T4MANUALUPD (1 << 21)
+# define S3C_TCON_T4RELOAD (1 <<22)
+#define S3C_TCNTB4 (S3C_TIMER_BASE + 0x3c)
+#define S3C_TCNTO4 (S3C_TIMER_BASE + 0x40)
+
+
static uint64_t s3c24xx_clocksource_read(void)
{
/* note: its a down counter */
- return 0xFFFF - readw(TCNTO4);
+ return 0xFFFF - readw(S3C_TCNTO4);
}
static struct clocksource cs = {
@@ -37,15 +54,15 @@ static int clocksource_init(void)
{
uint32_t p_clk = s3c_get_pclk();
- writel(0x00000000, TCON); /* stop all timers */
- writel(0x00ffffff, TCFG0); /* PCLK / (255 + 1) for timer 4 */
- writel(0x00030000, TCFG1); /* /16 */
+ writel(0x00000000, S3C_TCON); /* stop all timers */
+ writel(0x00ffffff, S3C_TCFG0); /* PCLK / (255 + 1) for timer 4 */
+ writel(0x00030000, S3C_TCFG1); /* /16 */
- writew(0xffff, TCNTB4); /* reload value is TOP */
+ writew(0xffff, S3C_TCNTB4); /* reload value is TOP */
- writel(0x00600000, TCON); /* force a first reload */
- writel(0x00400000, TCON);
- writel(0x00500000, TCON); /* enable timer 4 with auto reload */
+ writel(0x00600000, S3C_TCON); /* force a first reload */
+ writel(0x00400000, S3C_TCON);
+ writel(0x00500000, S3C_TCON); /* enable timer 4 with auto reload */
cs.mult = clocksource_hz2mult(p_clk / ((255 + 1) * 16), cs.shift);
init_clock(&cs);
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 10/14] MACH SAMSUNG/S3C: Re-work the S3C family timer driver
2012-01-02 11:43 [PATCH v2] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (8 preceding siblings ...)
2012-01-02 11:43 ` [PATCH 09/14] MACH SAMSUNG/S3C: Rename register macros to reflect the MACH they are valid for Juergen Beisert
@ 2012-01-02 11:43 ` Juergen Beisert
2012-01-02 11:43 ` [PATCH 11/14] MACH SAMSUNG/S3C: Prepare watchdog unit to be shared in the S3C family Juergen Beisert
` (3 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2012-01-02 11:43 UTC (permalink / raw)
To: barebox
After separation and after all S3C macros are now present, change the driver
to be more generic for future additions.
The timer registers in the S3C24XX family are only 16 bit wide. But these
registers can be read and written in a 32 bit manner. This is important to share
code with more recent CPUs which comes with 32 bit registers.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/mach-samsung/s3c-timer.c | 78 ++++++++++++++++++++++++++++--------
1 files changed, 60 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-samsung/s3c-timer.c b/arch/arm/mach-samsung/s3c-timer.c
index d9dae55..6665c8c 100644
--- a/arch/arm/mach-samsung/s3c-timer.c
+++ b/arch/arm/mach-samsung/s3c-timer.c
@@ -37,36 +37,78 @@
#define S3C_TCNTB4 (S3C_TIMER_BASE + 0x3c)
#define S3C_TCNTO4 (S3C_TIMER_BASE + 0x40)
+#define TIMER_WIDTH 16
+#define TIMER_SHIFT 10
+#define PRE_MUX 3
+#define PRE_MUX_ADD 1
+static const uint32_t max = 0x0000ffff;
-static uint64_t s3c24xx_clocksource_read(void)
+static void s3c_init_t4_clk_source(void)
+{
+ unsigned reg;
+
+ reg = readl(S3C_TCON) & ~S3C_TCON_T4MASK; /* stop timer 4 */
+ writel(reg, S3C_TCON);
+ reg = readl(S3C_TCFG0) & ~S3C_TCFG0_T4MASK;
+ reg |= S3C_TCFG0_SET_PSCL234(0); /* 0 means pre scaler is '256' */
+ writel(reg, S3C_TCFG0);
+ reg = readl(S3C_TCFG1) & ~S3C_TCFG1_T4MASK;
+ reg |= S3C_TCFG1_SET_T4MUX(PRE_MUX); /* / 16 */
+ writel(reg, S3C_TCFG1);
+}
+
+static unsigned s3c_get_t4_clk(void)
+{
+ unsigned clk = s3c_get_pclk();
+ unsigned pre = S3C_TCFG0_GET_PSCL234(readl(S3C_TCFG0)) + 1;
+ unsigned div = S3C_TCFG1_GET_T4MUX(readl(S3C_TCFG1)) + PRE_MUX_ADD;
+
+ return clk / pre / (1 << div);
+}
+
+static void s3c_timer_init(void)
+{
+ unsigned tcon;
+
+ tcon = readl(S3C_TCON) & ~S3C_TCON_T4MASK;
+
+ writel(max, S3C_TCNTB4); /* reload value */
+ /* force a manual counter update */
+ writel(tcon | S3C_TCON_T4MANUALUPD, S3C_TCON);
+}
+
+static void s3c_timer_start(void)
+{
+ unsigned tcon;
+
+ tcon = readl(S3C_TCON) & ~S3C_TCON_T4MANUALUPD;
+ tcon |= S3C_TCON_T4START | S3C_TCON_T4RELOAD;
+ writel(tcon, S3C_TCON);
+}
+
+static uint64_t s3c_clocksource_read(void)
{
/* note: its a down counter */
- return 0xFFFF - readw(S3C_TCNTO4);
+ return max - readl(S3C_TCNTO4);
}
static struct clocksource cs = {
- .read = s3c24xx_clocksource_read,
- .mask = CLOCKSOURCE_MASK(16),
- .shift = 10,
+ .read = s3c_clocksource_read,
+ .mask = CLOCKSOURCE_MASK(TIMER_WIDTH),
+ .shift = TIMER_SHIFT,
};
-static int clocksource_init(void)
+static int s3c_clk_src_init(void)
{
- uint32_t p_clk = s3c_get_pclk();
-
- writel(0x00000000, S3C_TCON); /* stop all timers */
- writel(0x00ffffff, S3C_TCFG0); /* PCLK / (255 + 1) for timer 4 */
- writel(0x00030000, S3C_TCFG1); /* /16 */
-
- writew(0xffff, S3C_TCNTB4); /* reload value is TOP */
+ /* select its clock source first */
+ s3c_init_t4_clk_source();
- writel(0x00600000, S3C_TCON); /* force a first reload */
- writel(0x00400000, S3C_TCON);
- writel(0x00500000, S3C_TCON); /* enable timer 4 with auto reload */
+ s3c_timer_init();
+ s3c_timer_start();
- cs.mult = clocksource_hz2mult(p_clk / ((255 + 1) * 16), cs.shift);
+ cs.mult = clocksource_hz2mult(s3c_get_t4_clk(), cs.shift);
init_clock(&cs);
return 0;
}
-core_initcall(clocksource_init);
+core_initcall(s3c_clk_src_init);
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 11/14] MACH SAMSUNG/S3C: Prepare watchdog unit to be shared in the S3C family
2012-01-02 11:43 [PATCH v2] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (9 preceding siblings ...)
2012-01-02 11:43 ` [PATCH 10/14] MACH SAMSUNG/S3C: Re-work the S3C family timer driver Juergen Beisert
@ 2012-01-02 11:43 ` Juergen Beisert
2012-01-02 11:44 ` [PATCH 12/14] MACH SAMSUNG/S3C: Unify the UART driver for the S3C family of CPUs Juergen Beisert
` (2 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2012-01-02 11:43 UTC (permalink / raw)
To: barebox
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/mach-samsung/generic.c | 10 +++++++---
arch/arm/mach-samsung/include/mach/s3c-iomap.h | 7 +------
arch/arm/mach-samsung/lowlevel-init.S | 2 +-
3 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
index 83222e1..4a0c87b 100644
--- a/arch/arm/mach-samsung/generic.c
+++ b/arch/arm/mach-samsung/generic.c
@@ -76,16 +76,20 @@ uint32_t s3c24x0_get_memory_size(void)
return size;
}
+#define S3C_WTCON (S3C_WATCHDOG_BASE)
+#define S3C_WTDAT (S3C_WATCHDOG_BASE + 0x04)
+#define S3C_WTCNT (S3C_WATCHDOG_BASE + 0x08)
+
void __noreturn reset_cpu(unsigned long addr)
{
/* Disable watchdog */
- writew(0x0000, WTCON);
+ writew(0x0000, S3C_WTCON);
/* Initialize watchdog timer count register */
- writew(0x0001, WTCNT);
+ writew(0x0001, S3C_WTCNT);
/* Enable watchdog timer; assert reset at timer timeout */
- writew(0x0021, WTCON);
+ writew(0x0021, S3C_WTCON);
/* loop forever and wait for reset to happen */
while(1)
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index 807660a..9677803 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -31,7 +31,7 @@
#define S3C24X0_UART_BASE 0x50000000
#define S3C_TIMER_BASE 0x51000000
#define S3C2410_USB_DEVICE_BASE 0x52000140
-#define S3C24X0_WATCHDOG_BASE 0x53000000
+#define S3C_WATCHDOG_BASE 0x53000000
#define S3C2410_I2C_BASE 0x54000000
#define S3C2410_I2S_BASE 0x55000000
#define S3C24X0_GPIO_BASE 0x56000000
@@ -41,11 +41,6 @@
#define S3C2410_SDI_BASE 0x5A000000
-/* Watchdog (direct access) */
-#define WTCON (S3C24X0_WATCHDOG_BASE)
-#define WTDAT (S3C24X0_WATCHDOG_BASE + 0x04)
-#define WTCNT (S3C24X0_WATCHDOG_BASE + 0x08)
-
/*
* if we are booting from NAND, its internal SRAM occures at
* a different address than without this feature
diff --git a/arch/arm/mach-samsung/lowlevel-init.S b/arch/arm/mach-samsung/lowlevel-init.S
index e2e3fc0..93ea3ce 100644
--- a/arch/arm/mach-samsung/lowlevel-init.S
+++ b/arch/arm/mach-samsung/lowlevel-init.S
@@ -29,7 +29,7 @@
.globl s3c24x0_disable_wd
s3c24x0_disable_wd:
- ldr r0, =S3C24X0_WATCHDOG_BASE
+ ldr r0, =S3C_WATCHDOG_BASE
mov r1, #0x0
str r1, [r0]
mov pc, lr
--
1.7.7.3
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 12/14] MACH SAMSUNG/S3C: Unify the UART driver for the S3C family of CPUs
2012-01-02 11:43 [PATCH v2] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (10 preceding siblings ...)
2012-01-02 11:43 ` [PATCH 11/14] MACH SAMSUNG/S3C: Prepare watchdog unit to be shared in the S3C family Juergen Beisert
@ 2012-01-02 11:44 ` Juergen Beisert
2012-01-02 11:44 ` [PATCH 13/14] MACH SAMSUNG/S3C: Re-work the memory detection and handling Juergen Beisert
2012-01-02 11:44 ` [PATCH 14/14] MACH SAMSUNG/S3C: Re-work the GPIO handling for S3C24xx CPUs Juergen Beisert
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2012-01-02 11:44 UTC (permalink / raw)
To: barebox
The UART is one of the units which differs only slightly inside the S3C family.
Prepare this driver to share it with more recent CPUs.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/a9m2410/a9m2410.c | 2 +-
arch/arm/boards/a9m2440/a9m2440.c | 2 +-
arch/arm/boards/mini2440/mini2440.c | 2 +-
arch/arm/mach-samsung/include/mach/s3c-iomap.h | 15 ++---
drivers/serial/Kconfig | 10 ++--
drivers/serial/Makefile | 2 +-
drivers/serial/{serial_s3c24x0.c => serial_s3c.c} | 68 +++++++++++++--------
7 files changed, 58 insertions(+), 43 deletions(-)
rename drivers/serial/{serial_s3c24x0.c => serial_s3c.c} (68%)
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index 989dcf7..a66afb9 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -167,7 +167,7 @@ void __bare_init nand_boot(void)
static int a9m2410_console_init(void)
{
- add_generic_device("s3c24x0_serial", -1, NULL, UART1_BASE, UART1_SIZE,
+ add_generic_device("s3c_serial", -1, NULL, S3C_UART1_BASE, S3C_UART1_SIZE,
IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 1986efb..077d726 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -168,7 +168,7 @@ void __bare_init nand_boot(void)
static int a9m2440_console_init(void)
{
- add_generic_device("s3c24x0_serial", -1, NULL, UART1_BASE, UART1_SIZE,
+ add_generic_device("s3c_serial", -1, NULL, S3C_UART1_BASE, S3C_UART1_SIZE,
IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 0186465..ec4eb05 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -342,7 +342,7 @@ static int mini2440_console_init(void)
s3c_gpio_mode(GPH2_TXD0);
s3c_gpio_mode(GPH3_RXD0);
- add_generic_device("s3c24x0_serial", -1, NULL, UART1_BASE, UART1_SIZE,
+ add_generic_device("s3c_serial", -1, NULL, S3C_UART1_BASE, S3C_UART1_SIZE,
IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index 9677803..7c45c53 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -28,7 +28,7 @@
#define S3C_CLOCK_POWER_BASE 0x4C000000
#define S3C2410_LCD_BASE 0x4D000000
#define S3C24X0_NAND_BASE 0x4E000000
-#define S3C24X0_UART_BASE 0x50000000
+#define S3C_UART_BASE 0x50000000
#define S3C_TIMER_BASE 0x51000000
#define S3C2410_USB_DEVICE_BASE 0x52000140
#define S3C_WATCHDOG_BASE 0x53000000
@@ -52,13 +52,12 @@
#endif
#define NFC_RAM_SIZE 4096
-/* internal UARTs (driver based) */
-#define UART1_BASE (S3C24X0_UART_BASE)
-#define UART1_SIZE 0x4000
-#define UART2_BASE (S3C24X0_UART_BASE + 0x4000)
-#define UART2_SIZE 0x4000
-#define UART3_BASE (S3C24X0_UART_BASE + 0x8000)
-#define UART3_SIZE 0x4000
+#define S3C_UART1_BASE (S3C_UART_BASE)
+#define S3C_UART1_SIZE 0x4000
+#define S3C_UART2_BASE (S3C_UART_BASE + 0x4000)
+#define S3C_UART2_SIZE 0x4000
+#define S3C_UART3_BASE (S3C_UART_BASE + 0x8000)
+#define S3C_UART3_SIZE 0x4000
/* CS configuration (direct access) */
#define BWSCON (S3C24X0_MEMCTL_BASE)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 592d543..186b596 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -78,16 +78,16 @@ config DRIVER_SERIAL_PL010
help
Enable this to get support for AMBA PL010 based serial devices
-config DRIVER_SERIAL_S3C24X0
- bool "Samsung S3C24X0 serial driver"
+config DRIVER_SERIAL_S3C
+ bool "Samsung S3C serial driver"
depends on ARCH_S3C24xx
default y
help
- Say Y here if you want to use the CONS on a S3C24X0 CPU
+ Say Y here if you want to use the CONS on a Samsung S3C CPU
-config DRIVER_SERIAL_S3C24X0_AUTOSYNC
+config DRIVER_SERIAL_S3C_AUTOSYNC
bool "Enable auto flow"
- depends on DRIVER_SERIAL_S3C24X0
+ depends on DRIVER_SERIAL_S3C
help
Say Y here if you want to use the auto flow feature of this
UART. RTS and CTS will be handled by the hardware when enabled.
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index a702125..e2d56b9 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_DRIVER_SERIAL_MPC5XXX) += serial_mpc5xxx.o
obj-$(CONFIG_DRIVER_SERIAL_BLACKFIN) += serial_blackfin.o
obj-$(CONFIG_DRIVER_SERIAL_NS16550) += serial_ns16550.o
obj-$(CONFIG_DRIVER_SERIAL_PL010) += serial_pl010.o
-obj-$(CONFIG_DRIVER_SERIAL_S3C24X0) += serial_s3c24x0.o
+obj-$(CONFIG_DRIVER_SERIAL_S3C) += serial_s3c.o
obj-$(CONFIG_DRIVER_SERIAL_ALTERA) += serial_altera.o
obj-$(CONFIG_DRIVER_SERIAL_ALTERA_JTAG) += serial_altera_jtag.o
obj-$(CONFIG_DRIVER_SERIAL_PXA) += serial_pxa.o
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c.c
similarity index 68%
rename from drivers/serial/serial_s3c24x0.c
rename to drivers/serial/serial_s3c.c
index 4191a49..b7e0987 100644
--- a/drivers/serial/serial_s3c24x0.c
+++ b/drivers/serial/serial_s3c.c
@@ -1,5 +1,5 @@
/*
- * (c) 2009 Juergen Beisert <j.beisert@saschahauer.de>
+ * (c) 2009...2011 Juergen Beisert <j.beisert@pengutronix.de>
*
* Based on code from:
* (c) 2004 Sascha Hauer <sascha@saschahauer.de>
@@ -41,20 +41,36 @@
#define URXH 0x24 /* receive */
#define UBRDIV 0x28 /* baudrate generator */
-static int s3c24x0_serial_setbaudrate(struct console_device *cdev, int baudrate)
+static unsigned s3c_get_arch_uart_input_clock(void __iomem *base)
+{
+ unsigned reg = readw(base + UCON);
+
+ switch (reg & 0xc00) {
+ case 0x000:
+ case 0x800:
+ return s3c_get_pclk();
+ case 0x400:
+ break; /* TODO UEXTCLK */
+ case 0xc00:
+ break; /* TODO FCLK/n */
+ }
+
+ return 0; /* not nice, but we can't emit an error message! */
+}
+
+static int s3c_serial_setbaudrate(struct console_device *cdev, int baudrate)
{
struct device_d *dev = cdev->dev;
void __iomem *base = dev->priv;
unsigned val;
- /* value is calculated so : PCLK / (16 * baudrate) -1 */
- val = s3c_get_pclk() / (16 * baudrate) - 1;
+ val = s3c_get_arch_uart_input_clock(base) / (16 * baudrate) - 1;
writew(val, base + UBRDIV);
return 0;
}
-static int s3c24x0_serial_init_port(struct console_device *cdev)
+static int s3c_serial_init_port(struct console_device *cdev)
{
struct device_d *dev = cdev->dev;
void __iomem *base = dev->priv;
@@ -71,7 +87,7 @@ static int s3c24x0_serial_init_port(struct console_device *cdev)
*/
writew(0x0245, base + UCON);
-#ifdef CONFIG_DRIVER_SERIAL_S3C24X0_AUTOSYNC
+#ifdef CONFIG_DRIVER_SERIAL_S3C_AUTOSYNC
writeb(0x10, base + UMCON); /* enable auto flow control */
#else
writeb(0x01, base + UMCON); /* RTS up */
@@ -80,7 +96,7 @@ static int s3c24x0_serial_init_port(struct console_device *cdev)
return 0;
}
-static void s3c24x0_serial_putc(struct console_device *cdev, char c)
+static void s3c_serial_putc(struct console_device *cdev, char c)
{
struct device_d *dev = cdev->dev;
void __iomem *base = dev->priv;
@@ -92,7 +108,7 @@ static void s3c24x0_serial_putc(struct console_device *cdev, char c)
writeb(c, base + UTXH);
}
-static int s3c24x0_serial_tstc(struct console_device *cdev)
+static int s3c_serial_tstc(struct console_device *cdev)
{
struct device_d *dev = cdev->dev;
void __iomem *base = dev->priv;
@@ -104,7 +120,7 @@ static int s3c24x0_serial_tstc(struct console_device *cdev)
return 0;
}
-static int s3c24x0_serial_getc(struct console_device *cdev)
+static int s3c_serial_getc(struct console_device *cdev)
{
struct device_d *dev = cdev->dev;
void __iomem *base = dev->priv;
@@ -116,7 +132,7 @@ static int s3c24x0_serial_getc(struct console_device *cdev)
return readb(base + URXH);
}
-static void s3c24x0_serial_flush(struct console_device *cdev)
+static void s3c_serial_flush(struct console_device *cdev)
{
struct device_d *dev = cdev->dev;
void __iomem *base = dev->priv;
@@ -125,7 +141,7 @@ static void s3c24x0_serial_flush(struct console_device *cdev)
;
}
-static int s3c24x0_serial_probe(struct device_d *dev)
+static int s3c_serial_probe(struct device_d *dev)
{
struct console_device *cdev;
@@ -134,13 +150,13 @@ static int s3c24x0_serial_probe(struct device_d *dev)
dev->priv = dev_request_mem_region(dev, 0);
cdev->dev = dev;
cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
- cdev->tstc = s3c24x0_serial_tstc;
- cdev->putc = s3c24x0_serial_putc;
- cdev->getc = s3c24x0_serial_getc;
- cdev->flush = s3c24x0_serial_flush;
- cdev->setbrg = s3c24x0_serial_setbaudrate;
+ cdev->tstc = s3c_serial_tstc;
+ cdev->putc = s3c_serial_putc;
+ cdev->getc = s3c_serial_getc;
+ cdev->flush = s3c_serial_flush;
+ cdev->setbrg = s3c_serial_setbaudrate;
- s3c24x0_serial_init_port(cdev);
+ s3c_serial_init_port(cdev);
/* Enable UART */
console_register(cdev);
@@ -148,25 +164,25 @@ static int s3c24x0_serial_probe(struct device_d *dev)
return 0;
}
-static void s3c24x0_serial_remove(struct device_d *dev)
+static void s3c_serial_remove(struct device_d *dev)
{
struct console_device *cdev = dev->type_data;
- s3c24x0_serial_flush(cdev);
+ s3c_serial_flush(cdev);
free(cdev);
dev->type_data = NULL;
}
-static struct driver_d s3c24x0_serial_driver = {
- .name = "s3c24x0_serial",
- .probe = s3c24x0_serial_probe,
- .remove = s3c24x0_serial_remove,
+static struct driver_d s3c_serial_driver = {
+ .name = "s3c_serial",
+ .probe = s3c_serial_probe,
+ .remove = s3c_serial_remove,
};
-static int s3c24x0_serial_init(void)
+static int s3c_serial_init(void)
{
- register_driver(&s3c24x0_serial_driver);
+ register_driver(&s3c_serial_driver);
return 0;
}
-console_initcall(s3c24x0_serial_init);
+console_initcall(s3c_serial_init);
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 13/14] MACH SAMSUNG/S3C: Re-work the memory detection and handling
2012-01-02 11:43 [PATCH v2] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (11 preceding siblings ...)
2012-01-02 11:44 ` [PATCH 12/14] MACH SAMSUNG/S3C: Unify the UART driver for the S3C family of CPUs Juergen Beisert
@ 2012-01-02 11:44 ` Juergen Beisert
2012-01-02 11:44 ` [PATCH 14/14] MACH SAMSUNG/S3C: Re-work the GPIO handling for S3C24xx CPUs Juergen Beisert
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2012-01-02 11:44 UTC (permalink / raw)
To: barebox
Keep common code in the MACH instead of re-inventing it in each platform.
Also use S3C* macros for all memory related register.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/a9m2410/a9m2410.c | 47 ++++++----------------
arch/arm/boards/a9m2410/lowlevel_init.S | 4 +-
arch/arm/boards/a9m2440/a9m2410dev.c | 9 ++--
arch/arm/boards/a9m2440/a9m2440.c | 37 +++++++----------
arch/arm/boards/a9m2440/lowlevel_init.S | 6 +-
arch/arm/boards/mini2440/lowlevel_init.S | 4 +-
arch/arm/boards/mini2440/mini2440.c | 13 +++---
arch/arm/mach-samsung/generic.c | 28 ++++++++-----
arch/arm/mach-samsung/include/mach/s3c-busctl.h | 32 +++++++++++++++
arch/arm/mach-samsung/include/mach/s3c-generic.h | 3 +-
arch/arm/mach-samsung/include/mach/s3c-iomap.h | 39 ++++++------------
arch/arm/mach-samsung/lowlevel-init.S | 4 +-
arch/arm/mach-samsung/s3c24xx-clocks.c | 9 +++-
13 files changed, 119 insertions(+), 116 deletions(-)
create mode 100644 arch/arm/mach-samsung/include/mach/s3c-busctl.h
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index a66afb9..daaa5c1 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -34,6 +34,8 @@
#include <io.h>
#include <mach/s3c-iomap.h>
#include <mach/s3c24xx-nand.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-busctl.h>
// {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
static struct s3c24x0_nand_platform_data nand_info = {
@@ -42,38 +44,13 @@ static struct s3c24x0_nand_platform_data nand_info = {
static int a9m2410_mem_init(void)
{
- resource_size_t size = 0;
- uint32_t reg;
+ resource_size_t size;
/*
- * detect the current memory size
* Note: On this card the second SDRAM page is not used
*/
- reg = readl(BANKSIZE);
-
- switch (reg &= 0x7) {
- case 0:
- size = 32 * 1024 * 1024;
- break;
- case 1:
- size = 64 * 1024 * 1024;
- break;
- case 2:
- size = 128 * 1024 * 1024;
- break;
- case 4:
- size = 2 * 1024 * 1024;
- break;
- case 5:
- size = 4 * 1024 * 1024;
- break;
- case 6:
- size = 8 * 1024 * 1024;
- break;
- case 7:
- size = 16 * 1024 * 1024;
- break;
- }
+ s3c24xx_disable_second_sdram_bank();
+ size = s3c24xx_get_memory_size();
/* ---------- configure the GPIOs ------------- */
writel(0x007FFFFF, GPACON);
@@ -100,7 +77,7 @@ static int a9m2410_mem_init(void)
*/
writel(0x40140, MISCCR);
- arm_add_mem_device("ram0", CS6_BASE, size);
+ arm_add_mem_device("ram0", S3C_SDRAM_BASE, size);
return 0;
}
@@ -111,19 +88,19 @@ static int a9m2410_devices_init(void)
uint32_t reg;
/* ----------- configure the access to the outer space ---------- */
- reg = readl(BWSCON);
+ reg = readl(S3C_BWSCON);
/* CS#1 to access the network controller */
reg &= ~0xf0;
reg |= 0xe0;
- writel(0x1350, BANKCON1);
+ writel(0x1350, S3C_BANKCON1);
/* CS#2 to the dual 16550 UART */
reg &= ~0xf00;
reg |= 0x400;
- writel(0x0d50, BANKCON2);
+ writel(0x0d50, S3C_BANKCON2);
- writel(reg, BWSCON);
+ writel(reg, S3C_BWSCON);
/* release the reset signal to the network and UART device */
reg = readl(MISCCR);
@@ -138,7 +115,7 @@ static int a9m2410_devices_init(void)
* connected to CS line 1 and interrupt line
* GPIO3, data width is 32 bit
*/
- add_generic_device("smc91c111", -1, NULL, CS1_BASE + 0x300, 16,
+ add_generic_device("smc91c111", -1, NULL, S3C_CS1_BASE + 0x300, 16,
IORESOURCE_MEM, NULL);
#ifdef CONFIG_NAND
@@ -150,7 +127,7 @@ static int a9m2410_devices_init(void)
dev_add_bb_dev("env_raw", "env0");
#endif
- armlinux_set_bootparams((void*)CS6_BASE + 0x100);
+ armlinux_set_bootparams((void*)S3C_SDRAM_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_A9M2410);
return 0;
diff --git a/arch/arm/boards/a9m2410/lowlevel_init.S b/arch/arm/boards/a9m2410/lowlevel_init.S
index 752c668..a106d53 100644
--- a/arch/arm/boards/a9m2410/lowlevel_init.S
+++ b/arch/arm/boards/a9m2410/lowlevel_init.S
@@ -15,9 +15,9 @@ board_init_lowlevel:
bl s3c24x0_disable_wd
/* skip everything here if we are already running from SDRAM */
- cmp pc, #S3C24X0_SDRAM_BASE
+ cmp pc, #S3C_SDRAM_BASE
blo 1f
- cmp pc, #S3C24X0_SDRAM_END
+ cmp pc, #S3C_SDRAM_END
bhs 1f
mov pc, r10
diff --git a/arch/arm/boards/a9m2440/a9m2410dev.c b/arch/arm/boards/a9m2440/a9m2410dev.c
index aa5da88..1da69eb 100644
--- a/arch/arm/boards/a9m2440/a9m2410dev.c
+++ b/arch/arm/boards/a9m2440/a9m2410dev.c
@@ -29,6 +29,7 @@
#include <init.h>
#include <io.h>
#include <mach/s3c-iomap.h>
+#include <mach/s3c-busctl.h>
/**
* Initialize the CPU to be able to work with the a9m2410dev evaluation board
@@ -72,19 +73,19 @@ int a9m2410dev_devices_init(void)
writel((readl(MISCCR) & ~0xFFFF) | 0x0140, MISCCR);
/* ----------- configure the access to the outer space ---------- */
- reg = readl(BWSCON);
+ reg = readl(S3C_BWSCON);
/* CS#1 to access the network controller */
reg &= ~0xf0;
reg |= 0xe0;
- writel(0x1350, BANKCON1);
+ writel(0x1350, S3C_BANKCON1);
/* CS#2 to the dual 16550 UART */
reg &= ~0xf00;
reg |= 0x400;
- writel(0x0d50, BANKCON2);
+ writel(0x0d50, S3C_BANKCON2);
- writel(reg, BWSCON);
+ writel(reg, S3C_BWSCON);
/* release the reset signal to the network and UART device */
reg = readl(MISCCR);
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 077d726..56ae914 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -35,6 +35,7 @@
#include <mach/s3c-iomap.h>
#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
+#include <mach/s3c-busctl.h>
#include "baseboards.h"
@@ -66,12 +67,6 @@ static int a9m2440_check_for_ram(uint32_t addr)
return rc;
}
-static void a9m2440_disable_second_sdram_bank(void)
-{
- writel(readl(BANKCON7) & ~(0x3 << 15),BANKCON7);
- writel(readl(MISCCR) | (1 << 18), MISCCR); /* disable clock */
-}
-
static int a9m2440_mem_init(void)
{
/*
@@ -80,30 +75,30 @@ static int a9m2440_mem_init(void)
* So we must check here, if the second bank is populated to get the
* correct RAM size.
*/
- switch (readl(BANKSIZE) & 0x7) {
+ switch (readl(S3C_BANKSIZE) & 0x7) {
case 0:
- if (a9m2440_check_for_ram(S3C24X0_SDRAM_BASE + 32 * 1024 * 1024))
- a9m2440_disable_second_sdram_bank();
+ if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 32 * 1024 * 1024))
+ s3c24xx_disable_second_sdram_bank();
break;
case 1:
- if (a9m2440_check_for_ram(S3C24X0_SDRAM_BASE + 64 * 1024 * 1024))
- a9m2440_disable_second_sdram_bank();
+ if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 64 * 1024 * 1024))
+ s3c24xx_disable_second_sdram_bank();
break;
case 2:
- if (a9m2440_check_for_ram(S3C24X0_SDRAM_BASE + 128 * 1024 * 1024))
- a9m2440_disable_second_sdram_bank();
+ if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 128 * 1024 * 1024))
+ s3c24xx_disable_second_sdram_bank();
break;
case 4:
case 5:
case 6: /* not supported on this machine */
break;
default:
- if (a9m2440_check_for_ram(S3C24X0_SDRAM_BASE + 16 * 1024 * 1024))
- a9m2440_disable_second_sdram_bank();
+ if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 16 * 1024 * 1024))
+ s3c24xx_disable_second_sdram_bank();
break;
}
- arm_add_mem_device("ram0", CS6_BASE, s3c24x0_get_memory_size());
+ arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c24xx_get_memory_size());
return 0;
}
@@ -114,14 +109,14 @@ static int a9m2440_devices_init(void)
uint32_t reg;
/* ----------- configure the access to the outer space ---------- */
- reg = readl(BWSCON);
+ reg = readl(S3C_BWSCON);
/* CS#5 to access the network controller */
reg &= ~0x00f00000;
reg |= 0x00d00000; /* 16 bit */
- writel(0x1f4c, BANKCON5);
+ writel(0x1f4c, S3C_BANKCON5);
- writel(reg, BWSCON);
+ writel(reg, S3C_BWSCON);
#ifdef CONFIG_MACH_A9M2410DEV
a9m2410dev_devices_init();
@@ -140,7 +135,7 @@ static int a9m2440_devices_init(void)
* Connected to CS line 5 + A24 and interrupt line EINT9,
* data width is 16 bit
*/
- add_generic_device("cs8900", -1, NULL, CS5_BASE + (1 << 24) + 0x300, 16,
+ add_generic_device("cs8900", -1, NULL, S3C_CS5_BASE + (1 << 24) + 0x300, 16,
IORESOURCE_MEM, NULL);
#ifdef CONFIG_NAND
@@ -151,7 +146,7 @@ static int a9m2440_devices_init(void)
devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
#endif
- armlinux_set_bootparams((void*)CS6_BASE + 0x100);
+ armlinux_set_bootparams((void*)S3C_SDRAM_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_A9M2440);
return 0;
diff --git a/arch/arm/boards/a9m2440/lowlevel_init.S b/arch/arm/boards/a9m2440/lowlevel_init.S
index bfdd7f0..57ebe3f 100644
--- a/arch/arm/boards/a9m2440/lowlevel_init.S
+++ b/arch/arm/boards/a9m2440/lowlevel_init.S
@@ -37,7 +37,7 @@ sdram_init:
ldr r4, [r1]
and r4, r4, #0x3
- ldr r1, =S3C24X0_MEMCTL_BASE
+ ldr r1, =S3C_MEMCTL_BASE
/* configure both SDRAM areas with 32 bit data bus width */
ldr r0, =((0x2 << 24) + (0x2 << 28))
str r0, [r1], #0x1c /* post add register offset for bank6 */
@@ -218,9 +218,9 @@ board_init_lowlevel:
bl s3c24x0_disable_wd
/* skip everything here if we are already running from SDRAM */
- cmp pc, #S3C24X0_SDRAM_BASE
+ cmp pc, #S3C_SDRAM_BASE
blo 1f
- cmp pc, #S3C24X0_SDRAM_END
+ cmp pc, #S3C_SDRAM_END
bhs 1f
mov pc, r10
diff --git a/arch/arm/boards/mini2440/lowlevel_init.S b/arch/arm/boards/mini2440/lowlevel_init.S
index f114bb7..1c8860a 100644
--- a/arch/arm/boards/mini2440/lowlevel_init.S
+++ b/arch/arm/boards/mini2440/lowlevel_init.S
@@ -17,9 +17,9 @@ board_init_lowlevel:
bl s3c24x0_disable_wd
/* skip everything here if we are already running from SDRAM */
- cmp pc, #S3C24X0_SDRAM_BASE
+ cmp pc, #S3C_SDRAM_BASE
blo 1f
- cmp pc, #S3C24X0_SDRAM_END
+ cmp pc, #S3C_SDRAM_END
bhs 1f
mov pc, r10
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index ec4eb05..29fd5a8 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -43,6 +43,7 @@
#include <mach/s3c-generic.h>
#include <mach/s3c-mci.h>
#include <mach/s3c24xx-fb.h>
+#include <mach/s3c-busctl.h>
static struct s3c24x0_nand_platform_data nand_info = {
.nand_timing = CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0,
@@ -266,7 +267,7 @@ static const unsigned pin_usage[] = {
static int mini2440_mem_init(void)
{
- arm_add_mem_device("ram0", CS6_BASE, s3c24x0_get_memory_size());
+ arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c24xx_get_memory_size());
return 0;
}
@@ -281,14 +282,14 @@ static int mini2440_devices_init(void)
for (i = 0; i < ARRAY_SIZE(pin_usage); i++)
s3c_gpio_mode(pin_usage[i]);
- reg = readl(BWSCON);
+ reg = readl(S3C_BWSCON);
/* CS#4 to access the network controller */
reg &= ~0x000f0000;
reg |= 0x000d0000; /* 16 bit */
- writel(0x1f4c, BANKCON4);
+ writel(0x1f4c, S3C_BANKCON4);
- writel(reg, BWSCON);
+ writel(reg, S3C_BWSCON);
/* release the reset signal to external devices */
reg = readl(MISCCR);
@@ -298,7 +299,7 @@ static int mini2440_devices_init(void)
add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
IORESOURCE_MEM, &nand_info);
- add_dm9000_device(0, CS4_BASE + 0x300, CS4_BASE + 0x304,
+ add_dm9000_device(0, S3C_CS4_BASE + 0x300, S3C_CS4_BASE + 0x304,
IORESOURCE_MEM_16BIT, &dm9000_data);
#ifdef CONFIG_NAND
/* ----------- add some vital partitions -------- */
@@ -316,7 +317,7 @@ static int mini2440_devices_init(void)
IORESOURCE_MEM, &s3c24x0_fb_data);
add_generic_device("ohci", 0, NULL, S3C2410_USB_HOST_BASE, 0x100,
IORESOURCE_MEM, NULL);
- armlinux_set_bootparams((void*)CS6_BASE + 0x100);
+ armlinux_set_bootparams((void*)S3C_SDRAM_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_MINI2440);
return 0;
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
index 4a0c87b..cbe0321 100644
--- a/arch/arm/mach-samsung/generic.c
+++ b/arch/arm/mach-samsung/generic.c
@@ -27,55 +27,63 @@
#include <init.h>
#include <clock.h>
#include <io.h>
+#include <sizes.h>
#include <mach/s3c-iomap.h>
#include <mach/s3c-generic.h>
+#include <mach/s3c-busctl.h>
/**
* Calculate the amount of connected and available memory
* @return Memory size in bytes
*/
-uint32_t s3c24x0_get_memory_size(void)
+uint32_t s3c24xx_get_memory_size(void)
{
uint32_t reg, size;
/*
* detect the current memory size
*/
- reg = readl(BANKSIZE);
+ reg = readl(S3C_BANKSIZE);
switch (reg & 0x7) {
case 0:
- size = 32 * 1024 * 1024;
+ size = SZ_32M;
break;
case 1:
- size = 64 * 1024 * 1024;
+ size = SZ_64M;
break;
case 2:
- size = 128 * 1024 * 1024;
+ size = SZ_128M;
break;
case 4:
- size = 2 * 1024 * 1024;
+ size = SZ_2M;
break;
case 5:
- size = 4 * 1024 * 1024;
+ size = SZ_4M;
break;
case 6:
- size = 8 * 1024 * 1024;
+ size = SZ_8M;
break;
default:
- size = 16 * 1024 * 1024;
+ size = SZ_16M;
break;
}
/*
* Is bank7 also configured for SDRAM usage?
*/
- if ((readl(BANKCON7) & (0x3 << 15)) == (0x3 << 15))
+ if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15))
size <<= 1; /* also count this bank */
return size;
}
+void s3c24xx_disable_second_sdram_bank(void)
+{
+ writel(readl(S3C_BANKCON7) & ~(0x3 << 15), S3C_BANKCON7);
+ writel(readl(MISCCR) | (1 << 18), MISCCR); /* disable its clock */
+}
+
#define S3C_WTCON (S3C_WATCHDOG_BASE)
#define S3C_WTDAT (S3C_WATCHDOG_BASE + 0x04)
#define S3C_WTCNT (S3C_WATCHDOG_BASE + 0x08)
diff --git a/arch/arm/mach-samsung/include/mach/s3c-busctl.h b/arch/arm/mach-samsung/include/mach/s3c-busctl.h
new file mode 100644
index 0000000..4bcf0a7
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c-busctl.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2011 Juergen Beisert, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_S3C_BUSCTL_H
+# define __MACH_S3C_BUSCTL_H
+
+#define S3C_BWSCON (S3C_MEMCTL_BASE)
+#define S3C_BANKCON0 (S3C_MEMCTL_BASE + 0x04)
+#define S3C_BANKCON1 (S3C_MEMCTL_BASE + 0x08)
+#define S3C_BANKCON2 (S3C_MEMCTL_BASE + 0x0c)
+#define S3C_BANKCON3 (S3C_MEMCTL_BASE + 0x10)
+#define S3C_BANKCON4 (S3C_MEMCTL_BASE + 0x14)
+#define S3C_BANKCON5 (S3C_MEMCTL_BASE + 0x18)
+#define S3C_BANKCON6 (S3C_MEMCTL_BASE + 0x1c)
+#define S3C_BANKCON7 (S3C_MEMCTL_BASE + 0x20)
+#define S3C_REFRESH (S3C_MEMCTL_BASE + 0x24)
+#define S3C_BANKSIZE (S3C_MEMCTL_BASE + 0x28)
+#define S3C_MRSRB6 (S3C_MEMCTL_BASE + 0x2c)
+#define S3C_MRSRB7 (S3C_MEMCTL_BASE + 0x30)
+
+#endif /* __MACH_S3C_BUSCTL_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-generic.h b/arch/arm/mach-samsung/include/mach/s3c-generic.h
index 33f025d..4ea3dd7 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-generic.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-generic.h
@@ -30,4 +30,5 @@ uint32_t s3c_get_fclk(void);
uint32_t s3c_get_hclk(void);
uint32_t s3c_get_pclk(void);
uint32_t s3c_get_uclk(void);
-uint32_t s3c24x0_get_memory_size(void);
+uint32_t s3c24xx_get_memory_size(void);
+void s3c24xx_disable_second_sdram_bank(void);
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index 7c45c53..4f713be 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -19,9 +19,7 @@
*/
/* S3C2410 device base addresses */
-#define S3C24X0_SDRAM_BASE 0x30000000
-#define S3C24X0_SDRAM_END 0x40000000
-#define S3C24X0_MEMCTL_BASE 0x48000000
+#define S3C_MEMCTL_BASE 0x48000000
#define S3C2410_USB_HOST_BASE 0x49000000
#define S3C2410_INTERRUPT_BASE 0x4A000000
#define S3C2410_DMA_BASE 0x4B000000
@@ -40,6 +38,17 @@
#define S3C2410_SPI_BASE 0x59000000
#define S3C2410_SDI_BASE 0x5A000000
+/* external IO space */
+#define S3C_CS0_BASE 0x00000000
+#define S3C_CS1_BASE 0x08000000
+#define S3C_CS2_BASE 0x10000000
+#define S3C_CS3_BASE 0x18000000
+#define S3C_CS4_BASE 0x20000000
+#define S3C_CS5_BASE 0x28000000
+#define S3C_CS6_BASE 0x30000000
+
+#define S3C_SDRAM_BASE S3C_CS6_BASE
+#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x10000000)
/*
* if we are booting from NAND, its internal SRAM occures at
@@ -59,21 +68,6 @@
#define S3C_UART3_BASE (S3C_UART_BASE + 0x8000)
#define S3C_UART3_SIZE 0x4000
-/* CS configuration (direct access) */
-#define BWSCON (S3C24X0_MEMCTL_BASE)
-#define BANKCON0 (S3C24X0_MEMCTL_BASE + 0x04)
-#define BANKCON1 (S3C24X0_MEMCTL_BASE + 0x08)
-#define BANKCON2 (S3C24X0_MEMCTL_BASE + 0x0c)
-#define BANKCON3 (S3C24X0_MEMCTL_BASE + 0x10)
-#define BANKCON4 (S3C24X0_MEMCTL_BASE + 0x14)
-#define BANKCON5 (S3C24X0_MEMCTL_BASE + 0x18)
-#define BANKCON6 (S3C24X0_MEMCTL_BASE + 0x1c)
-#define BANKCON7 (S3C24X0_MEMCTL_BASE + 0x20)
-#define REFRESH (S3C24X0_MEMCTL_BASE + 0x24)
-#define BANKSIZE (S3C24X0_MEMCTL_BASE + 0x28)
-#define MRSRB6 (S3C24X0_MEMCTL_BASE + 0x2c)
-#define MRSRB7 (S3C24X0_MEMCTL_BASE + 0x30)
-
/* GPIO registers (direct access) */
#define GPACON (S3C24X0_GPIO_BASE)
#define GPADAT (S3C24X0_GPIO_BASE + 0x04)
@@ -133,12 +127,3 @@
# define DSC0 (S3C24X0_GPIO_BASE + 0xc4)
# define DSC1 (S3C24X0_GPIO_BASE + 0xc8)
#endif
-
-/* external IO space */
-#define CS0_BASE 0x00000000
-#define CS1_BASE 0x08000000
-#define CS2_BASE 0x10000000
-#define CS3_BASE 0x18000000
-#define CS4_BASE 0x20000000
-#define CS5_BASE 0x28000000
-#define CS6_BASE 0x30000000
diff --git a/arch/arm/mach-samsung/lowlevel-init.S b/arch/arm/mach-samsung/lowlevel-init.S
index 93ea3ce..31c6196 100644
--- a/arch/arm/mach-samsung/lowlevel-init.S
+++ b/arch/arm/mach-samsung/lowlevel-init.S
@@ -192,7 +192,7 @@ With m = MDIV + 8, p = PDIV + 2 and s = SDIV.
s3c24x0_sdram_init:
adr r0, SDRAMDATA /* get the current relative address of the table */
- mov r1, #S3C24X0_MEMCTL_BASE
+ mov r1, #S3C_MEMCTL_BASE
mov r2, #6 /* we *know* it contains 6 entries */
ldr r3, [r0], #4 /* write BSWCON first */
@@ -255,7 +255,7 @@ s3c24x0_nand_boot:
* In the case of NOR boot we are running from the same address space.
* Detect this case to handle it correctly.
*/
- mov r1, #S3C24X0_MEMCTL_BASE
+ mov r1, #S3C_MEMCTL_BASE
ldr r3, [r1]
and r3, r3, #0x6
cmp r3, #0x0 /* check for NAND case */
diff --git a/arch/arm/mach-samsung/s3c24xx-clocks.c b/arch/arm/mach-samsung/s3c24xx-clocks.c
index beacc76..a99d1b9 100644
--- a/arch/arm/mach-samsung/s3c24xx-clocks.c
+++ b/arch/arm/mach-samsung/s3c24xx-clocks.c
@@ -21,6 +21,7 @@
#include <mach/s3c-iomap.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-clocks.h>
+#include <mach/s3c-busctl.h>
/**
* Calculate the current M-PLL clock.
@@ -127,9 +128,11 @@ int s3c24xx_dump_clocks(void)
printf("fclk: %7d kHz\n", s3c_get_fclk() / 1000);
printf("hclk: %7d kHz\n", s3c_get_hclk() / 1000);
printf("pclk: %7d kHz\n", s3c_get_pclk() / 1000);
- printf("SDRAM1: CL%d@%dMHz\n", ((readl(BANKCON6) & 0xc) >> 2) + 2, s3c_get_hclk() / 1000000);
- if ((readl(BANKCON7) & (0x3 << 15)) == (0x3 << 15))
- printf("SDRAM2: CL%d@%dMHz\n", ((readl(BANKCON7) & 0xc) >> 2) + 2,
+ printf("SDRAM1: CL%d@%dMHz\n", ((readl(S3C_BANKCON6) & 0xc) >> 2) + 2,
+ s3c_get_hclk() / 1000000);
+ if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15))
+ printf("SDRAM2: CL%d@%dMHz\n",
+ ((readl(S3C_BANKCON7) & 0xc) >> 2) + 2,
s3c_get_hclk() / 1000000);
return 0;
}
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 14/14] MACH SAMSUNG/S3C: Re-work the GPIO handling for S3C24xx CPUs
2012-01-02 11:43 [PATCH v2] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (12 preceding siblings ...)
2012-01-02 11:44 ` [PATCH 13/14] MACH SAMSUNG/S3C: Re-work the memory detection and handling Juergen Beisert
@ 2012-01-02 11:44 ` Juergen Beisert
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2012-01-02 11:44 UTC (permalink / raw)
To: barebox
a) use the more CPU specific S3C* macro names
b) move the register description out of the way, as more recent CPUs using a
different layout and more features
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/a9m2410/a9m2410.c | 41 ++++++------
arch/arm/boards/a9m2440/a9m2410dev.c | 53 +++++++-------
arch/arm/boards/a9m2440/a9m2440.c | 5 +-
arch/arm/boards/a9m2440/lowlevel_init.S | 3 +-
arch/arm/boards/mini2440/mini2440.c | 5 +-
arch/arm/mach-samsung/generic.c | 3 +-
arch/arm/mach-samsung/gpio-s3c24x0.c | 31 ++++----
arch/arm/mach-samsung/include/mach/s3c-iomap.h | 62 +----------------
arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h | 77 +++++++++++++++++++++
9 files changed, 152 insertions(+), 128 deletions(-)
create mode 100644 arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index daaa5c1..adeaacc 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -36,6 +36,7 @@
#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-busctl.h>
+#include <mach/s3c24xx-gpio.h>
// {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
static struct s3c24x0_nand_platform_data nand_info = {
@@ -53,29 +54,29 @@ static int a9m2410_mem_init(void)
size = s3c24xx_get_memory_size();
/* ---------- configure the GPIOs ------------- */
- writel(0x007FFFFF, GPACON);
- writel(0x00000000, GPCCON);
- writel(0x00000000, GPCUP);
- writel(0x00000000, GPDCON);
- writel(0x00000000, GPDUP);
- writel(0xAAAAAAAA, GPECON);
- writel(0x0000E03F, GPEUP);
- writel(0x00000000, GPBCON); /* all inputs */
- writel(0x00000007, GPBUP); /* pullup disabled for GPB0..3 */
- writel(0x00009000, GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */
- writel(0x000000FF, GPFUP);
- writel(readl(GPGDAT) | 0x0010, GPGDAT); /* switch off LCD backlight */
- writel(0xFF00A938, GPGCON); /* switch off USB device */
- writel(0x0000F000, GPGUP);
- writel(readl(GPHDAT) | 0x100, GPHDAT); /* switch BOOTINT/GPIO_ON# to high */
- writel(0x000007FF, GPHUP);
- writel(0x0029FAAA, GPHCON);
+ writel(0x007FFFFF, S3C_GPACON);
+ writel(0x00000000, S3C_GPCCON);
+ writel(0x00000000, S3C_GPCUP);
+ writel(0x00000000, S3C_GPDCON);
+ writel(0x00000000, S3C_GPDUP);
+ writel(0xAAAAAAAA, S3C_GPECON);
+ writel(0x0000E03F, S3C_GPEUP);
+ writel(0x00000000, S3C_GPBCON); /* all inputs */
+ writel(0x00000007, S3C_GPBUP); /* pullup disabled for GPB0..3 */
+ writel(0x00009000, S3C_GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */
+ writel(0x000000FF, S3C_GPFUP);
+ writel(readl(S3C_GPGDAT) | 0x0010, S3C_GPGDAT); /* switch off LCD backlight */
+ writel(0xFF00A938, S3C_GPGCON); /* switch off USB device */
+ writel(0x0000F000, S3C_GPGUP);
+ writel(readl(S3C_GPHDAT) | 0x100, S3C_GPHDAT); /* switch BOOTINT/GPIO_ON# to high */
+ writel(0x000007FF, S3C_GPHUP);
+ writel(0x0029FAAA, S3C_GPHCON);
/*
* USB port1 normal, USB port0 normal, USB1 pads for device
* PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1,
* 2nd SDRAM bank off (only bank 1 is used)
*/
- writel(0x40140, MISCCR);
+ writel(0x40140, S3C_MISCCR);
arm_add_mem_device("ram0", S3C_SDRAM_BASE, size);
@@ -103,9 +104,9 @@ static int a9m2410_devices_init(void)
writel(reg, S3C_BWSCON);
/* release the reset signal to the network and UART device */
- reg = readl(MISCCR);
+ reg = readl(S3C_MISCCR);
reg |= 0x10000;
- writel(reg, MISCCR);
+ writel(reg, S3C_MISCCR);
/* ----------- the devices the boot loader should work with -------- */
add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
diff --git a/arch/arm/boards/a9m2440/a9m2410dev.c b/arch/arm/boards/a9m2440/a9m2410dev.c
index 1da69eb..bedb0f7 100644
--- a/arch/arm/boards/a9m2440/a9m2410dev.c
+++ b/arch/arm/boards/a9m2440/a9m2410dev.c
@@ -30,6 +30,7 @@
#include <io.h>
#include <mach/s3c-iomap.h>
#include <mach/s3c-busctl.h>
+#include <mach/s3c24xx-gpio.h>
/**
* Initialize the CPU to be able to work with the a9m2410dev evaluation board
@@ -39,38 +40,38 @@ int a9m2410dev_devices_init(void)
unsigned int reg;
/* ---------- configure the GPIOs ------------- */
- writel(0x007FFFFF, GPACON);
- writel(0x00000000, GPCCON);
- writel(0x00000000, GPCUP);
- writel(0x00000000, GPDCON);
- writel(0x00000000, GPDUP);
- writel(0xAAAAAAAA, GPECON);
- writel(0x0000E03F, GPEUP);
- writel(0x00000000, GPBCON); /* all inputs */
- writel(0x00000007, GPBUP); /* pullup disabled for GPB0..3 */
- writel(0x00009000, GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */
- writel(0x000000FF, GPFUP);
- writel(readl(GPGDAT) | 0x1010, GPGDAT); /* switch off IDLE_SW#, switch off LCD backlight */
- writel(0x0100A93A, GPGCON); /* switch on USB device */
- writel(0x0000F000, GPGUP);
- writel(0x0029FAAA, GPHCON);
+ writel(0x007FFFFF, S3C_GPACON);
+ writel(0x00000000, S3C_GPCCON);
+ writel(0x00000000, S3C_GPCUP);
+ writel(0x00000000, S3C_GPDCON);
+ writel(0x00000000, S3C_GPDUP);
+ writel(0xAAAAAAAA, S3C_GPECON);
+ writel(0x0000E03F, S3C_GPEUP);
+ writel(0x00000000, S3C_GPBCON); /* all inputs */
+ writel(0x00000007, S3C_GPBUP); /* pullup disabled for GPB0..3 */
+ writel(0x00009000, S3C_GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */
+ writel(0x000000FF, S3C_GPFUP);
+ writel(readl(S3C_GPGDAT) | 0x1010, S3C_GPGDAT); /* switch off IDLE_SW#, switch off LCD backlight */
+ writel(0x0100A93A, S3C_GPGCON); /* switch on USB device */
+ writel(0x0000F000, S3C_GPGUP);
+ writel(0x0029FAAA, S3C_GPHCON);
- writel((1 << 12) | (0 << 11), GPJDAT);
- writel(0x0016aaaa, GPJCON);
- writel(~((0<<12)| (1<<11)), GPJUP);
+ writel((1 << 12) | (0 << 11), S3C_GPJDAT);
+ writel(0x0016aaaa, S3C_GPJCON);
+ writel(~((0<<12)| (1<<11)), S3C_GPJUP);
- writel((0 << 12) | (0 << 11), GPJDAT);
- writel(0x0016aaaa, GPJCON);
- writel(0x00001fff, GPJUP);
+ writel((0 << 12) | (0 << 11), S3C_GPJDAT);
+ writel(0x0016aaaa, S3C_GPJCON);
+ writel(0x00001fff, S3C_GPJUP);
- writel(0x00000000, DSC0);
- writel(0x00000000, DSC1);
+ writel(0x00000000, S3C_DSC0);
+ writel(0x00000000, S3C_DSC1);
/*
* USB port1 normal, USB port0 normal, USB1 pads for device
* PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1,
*/
- writel((readl(MISCCR) & ~0xFFFF) | 0x0140, MISCCR);
+ writel((readl(S3C_MISCCR) & ~0xFFFF) | 0x0140, S3C_MISCCR);
/* ----------- configure the access to the outer space ---------- */
reg = readl(S3C_BWSCON);
@@ -88,9 +89,9 @@ int a9m2410dev_devices_init(void)
writel(reg, S3C_BWSCON);
/* release the reset signal to the network and UART device */
- reg = readl(MISCCR);
+ reg = readl(S3C_MISCCR);
reg |= 0x10000;
- writel(reg, MISCCR);
+ writel(reg, S3C_MISCCR);
return 0;
}
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 56ae914..6c6ccdb 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -36,6 +36,7 @@
#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-busctl.h>
+#include <mach/s3c24xx-gpio.h>
#include "baseboards.h"
@@ -123,9 +124,9 @@ static int a9m2440_devices_init(void)
#endif
/* release the reset signal to external devices */
- reg = readl(MISCCR);
+ reg = readl(S3C_MISCCR);
reg |= 0x10000;
- writel(reg, MISCCR);
+ writel(reg, S3C_MISCCR);
/* ----------- the devices the boot loader should work with -------- */
add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
diff --git a/arch/arm/boards/a9m2440/lowlevel_init.S b/arch/arm/boards/a9m2440/lowlevel_init.S
index 57ebe3f..e915a16 100644
--- a/arch/arm/boards/a9m2440/lowlevel_init.S
+++ b/arch/arm/boards/a9m2440/lowlevel_init.S
@@ -4,6 +4,7 @@
#include <config.h>
#include <mach/s3c-iomap.h>
+#include <mach/s3c24xx-gpio.h>
.section ".text_bare_init.board_init_lowlevel","ax"
@@ -33,7 +34,7 @@ sdram_init:
* configured yet, these pins show external settings, to detect
* the SDRAM size.
*/
- ldr r1, =GPBDAT
+ ldr r1, =S3C_GPBDAT
ldr r4, [r1]
and r4, r4, #0x3
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 29fd5a8..97e56db 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -44,6 +44,7 @@
#include <mach/s3c-mci.h>
#include <mach/s3c24xx-fb.h>
#include <mach/s3c-busctl.h>
+#include <mach/s3c24xx-gpio.h>
static struct s3c24x0_nand_platform_data nand_info = {
.nand_timing = CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0,
@@ -292,9 +293,9 @@ static int mini2440_devices_init(void)
writel(reg, S3C_BWSCON);
/* release the reset signal to external devices */
- reg = readl(MISCCR);
+ reg = readl(S3C_MISCCR);
reg |= 0x10000;
- writel(reg, MISCCR);
+ writel(reg, S3C_MISCCR);
add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
IORESOURCE_MEM, &nand_info);
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
index cbe0321..7706be2 100644
--- a/arch/arm/mach-samsung/generic.c
+++ b/arch/arm/mach-samsung/generic.c
@@ -31,6 +31,7 @@
#include <mach/s3c-iomap.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-busctl.h>
+#include <mach/s3c24xx-gpio.h>
/**
* Calculate the amount of connected and available memory
@@ -81,7 +82,7 @@ uint32_t s3c24xx_get_memory_size(void)
void s3c24xx_disable_second_sdram_bank(void)
{
writel(readl(S3C_BANKCON7) & ~(0x3 << 15), S3C_BANKCON7);
- writel(readl(MISCCR) | (1 << 18), MISCCR); /* disable its clock */
+ writel(readl(S3C_MISCCR) | (1 << 18), S3C_MISCCR); /* disable its clock */
}
#define S3C_WTCON (S3C_WATCHDOG_BASE)
diff --git a/arch/arm/mach-samsung/gpio-s3c24x0.c b/arch/arm/mach-samsung/gpio-s3c24x0.c
index 23b2609..4f1c5cc 100644
--- a/arch/arm/mach-samsung/gpio-s3c24x0.c
+++ b/arch/arm/mach-samsung/gpio-s3c24x0.c
@@ -20,6 +20,7 @@
#include <io.h>
#include <mach/s3c-iomap.h>
#include <mach/gpio.h>
+#include <mach/s3c24xx-gpio.h>
static const unsigned char group_offset[] =
{
@@ -45,10 +46,10 @@ void gpio_set_value(unsigned gpio, int value)
offset = group_offset[group];
- reg = readl(GPADAT + offset);
+ reg = readl(S3C_GPADAT + offset);
reg &= ~(1 << bit);
reg |= (!!value) << bit;
- writel(reg, GPADAT + offset);
+ writel(reg, S3C_GPADAT + offset);
}
int gpio_direction_input(unsigned gpio)
@@ -60,9 +61,9 @@ int gpio_direction_input(unsigned gpio)
offset = group_offset[group];
- reg = readl(GPACON + offset);
+ reg = readl(S3C_GPACON + offset);
reg &= ~(0x3 << (bit << 1));
- writel(reg, GPACON + offset);
+ writel(reg, S3C_GPACON + offset);
return 0;
}
@@ -81,14 +82,14 @@ int gpio_direction_output(unsigned gpio, int value)
gpio_set_value(gpio,value);
/* direction */
if (group == 0) { /* GPA is special */
- reg = readl(GPACON);
+ reg = readl(S3C_GPACON);
reg &= ~(1 << bit);
- writel(reg, GPACON);
+ writel(reg, S3C_GPACON);
} else {
- reg = readl(GPACON + offset);
+ reg = readl(S3C_GPACON + offset);
reg &= ~(0x3 << (bit << 1));
reg |= 0x1 << (bit << 1);
- writel(reg, GPACON + offset);
+ writel(reg, S3C_GPACON + offset);
}
return 0;
@@ -107,7 +108,7 @@ int gpio_get_value(unsigned gpio)
offset = group_offset[group];
/* value */
- reg = readl(GPADAT + offset);
+ reg = readl(S3C_GPADAT + offset);
return !!(reg & (1 << bit));
}
@@ -132,9 +133,9 @@ void s3c_gpio_mode(unsigned gpio_mode)
gpio_direction_output(bit, GET_GPIOVAL(gpio_mode));
break;
default:
- reg = readl(GPACON);
+ reg = readl(S3C_GPACON);
reg |= 1 << bit;
- writel(reg, GPACON);
+ writel(reg, S3C_GPACON);
break;
}
return;
@@ -143,12 +144,12 @@ void s3c_gpio_mode(unsigned gpio_mode)
offset = group_offset[group];
if (PU_PRESENT(gpio_mode)) {
- reg = readl(GPACON + offset + 8);
+ reg = readl(S3C_GPACON + offset + 8);
if (GET_PU(gpio_mode))
reg |= (1 << bit); /* set means _disabled_ */
else
reg &= ~(1 << bit);
- writel(reg, GPACON + offset + 8);
+ writel(reg, S3C_GPACON + offset + 8);
}
switch (func) {
@@ -160,10 +161,10 @@ void s3c_gpio_mode(unsigned gpio_mode)
break;
case 2: /* function one */
case 3: /* function two */
- reg = readl(GPACON + offset);
+ reg = readl(S3C_GPACON + offset);
reg &= ~(0x3 << (bit << 1));
reg |= func << (bit << 1);
- writel(reg, GPACON + offset);
+ writel(reg, S3C_GPACON + offset);
break;
}
}
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index 4f713be..9e867f8 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -32,7 +32,7 @@
#define S3C_WATCHDOG_BASE 0x53000000
#define S3C2410_I2C_BASE 0x54000000
#define S3C2410_I2S_BASE 0x55000000
-#define S3C24X0_GPIO_BASE 0x56000000
+#define S3C_GPIO_BASE 0x56000000
#define S3C2410_RTC_BASE 0x57000000
#define S3C2410_ADC_BASE 0x58000000
#define S3C2410_SPI_BASE 0x59000000
@@ -67,63 +67,3 @@
#define S3C_UART2_SIZE 0x4000
#define S3C_UART3_BASE (S3C_UART_BASE + 0x8000)
#define S3C_UART3_SIZE 0x4000
-
-/* GPIO registers (direct access) */
-#define GPACON (S3C24X0_GPIO_BASE)
-#define GPADAT (S3C24X0_GPIO_BASE + 0x04)
-
-#define GPBCON (S3C24X0_GPIO_BASE + 0x10)
-#define GPBDAT (S3C24X0_GPIO_BASE + 0x14)
-#define GPBUP (S3C24X0_GPIO_BASE + 0x18)
-
-#define GPCCON (S3C24X0_GPIO_BASE + 0x20)
-#define GPCDAT (S3C24X0_GPIO_BASE + 0x24)
-#define GPCUP (S3C24X0_GPIO_BASE + 0x28)
-
-#define GPDCON (S3C24X0_GPIO_BASE + 0x30)
-#define GPDDAT (S3C24X0_GPIO_BASE + 0x34)
-#define GPDUP (S3C24X0_GPIO_BASE + 0x38)
-
-#define GPECON (S3C24X0_GPIO_BASE + 0x40)
-#define GPEDAT (S3C24X0_GPIO_BASE + 0x44)
-#define GPEUP (S3C24X0_GPIO_BASE + 0x48)
-
-#define GPFCON (S3C24X0_GPIO_BASE + 0x50)
-#define GPFDAT (S3C24X0_GPIO_BASE + 0x54)
-#define GPFUP (S3C24X0_GPIO_BASE + 0x58)
-
-#define GPGCON (S3C24X0_GPIO_BASE + 0x60)
-#define GPGDAT (S3C24X0_GPIO_BASE + 0x64)
-#define GPGUP (S3C24X0_GPIO_BASE + 0x68)
-
-#define GPHCON (S3C24X0_GPIO_BASE + 0x70)
-#define GPHDAT (S3C24X0_GPIO_BASE + 0x74)
-#define GPHUP (S3C24X0_GPIO_BASE + 0x78)
-
-#ifdef CONFIG_CPU_S3C2440
-# define GPJCON (S3C24X0_GPIO_BASE + 0xd0)
-# define GPJDAT (S3C24X0_GPIO_BASE + 0xd4)
-# define GPJUP (S3C24X0_GPIO_BASE + 0xd8)
-#endif
-
-#define MISCCR (S3C24X0_GPIO_BASE + 0x80)
-#define DCLKCON (S3C24X0_GPIO_BASE + 0x84)
-#define EXTINT0 (S3C24X0_GPIO_BASE + 0x88)
-#define EXTINT1 (S3C24X0_GPIO_BASE + 0x8c)
-#define EXTINT2 (S3C24X0_GPIO_BASE + 0x90)
-#define EINTFLT0 (S3C24X0_GPIO_BASE + 0x94)
-#define EINTFLT1 (S3C24X0_GPIO_BASE + 0x98)
-#define EINTFLT2 (S3C24X0_GPIO_BASE + 0x9c)
-#define EINTFLT3 (S3C24X0_GPIO_BASE + 0xa0)
-#define EINTMASK (S3C24X0_GPIO_BASE + 0xa4)
-#define EINTPEND (S3C24X0_GPIO_BASE + 0xa8)
-#define GSTATUS0 (S3C24X0_GPIO_BASE + 0xac)
-#define GSTATUS1 (S3C24X0_GPIO_BASE + 0xb0)
-#define GSTATUS2 (S3C24X0_GPIO_BASE + 0xb4)
-#define GSTATUS3 (S3C24X0_GPIO_BASE + 0xb8)
-#define GSTATUS4 (S3C24X0_GPIO_BASE + 0xbc)
-
-#ifdef CONFIG_CPU_S3C2440
-# define DSC0 (S3C24X0_GPIO_BASE + 0xc4)
-# define DSC1 (S3C24X0_GPIO_BASE + 0xc8)
-#endif
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h b/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h
new file mode 100644
index 0000000..c835974
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2011 Juergen Beisert, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_S3C24XX_GPIO_H
+# define __MACH_S3C24XX_GPIO_H
+
+#define S3C_GPACON (S3C_GPIO_BASE)
+#define S3C_GPADAT (S3C_GPIO_BASE + 0x04)
+
+#define S3C_GPBCON (S3C_GPIO_BASE + 0x10)
+#define S3C_GPBDAT (S3C_GPIO_BASE + 0x14)
+#define S3C_GPBUP (S3C_GPIO_BASE + 0x18)
+
+#define S3C_GPCCON (S3C_GPIO_BASE + 0x20)
+#define S3C_GPCDAT (S3C_GPIO_BASE + 0x24)
+#define S3C_GPCUP (S3C_GPIO_BASE + 0x28)
+
+#define S3C_GPDCON (S3C_GPIO_BASE + 0x30)
+#define S3C_GPDDAT (S3C_GPIO_BASE + 0x34)
+#define S3C_GPDUP (S3C_GPIO_BASE + 0x38)
+
+#define S3C_GPECON (S3C_GPIO_BASE + 0x40)
+#define S3C_GPEDAT (S3C_GPIO_BASE + 0x44)
+#define S3C_GPEUP (S3C_GPIO_BASE + 0x48)
+
+#define S3C_GPFCON (S3C_GPIO_BASE + 0x50)
+#define S3C_GPFDAT (S3C_GPIO_BASE + 0x54)
+#define S3C_GPFUP (S3C_GPIO_BASE + 0x58)
+
+#define S3C_GPGCON (S3C_GPIO_BASE + 0x60)
+#define S3C_GPGDAT (S3C_GPIO_BASE + 0x64)
+#define S3C_GPGUP (S3C_GPIO_BASE + 0x68)
+
+#define S3C_GPHCON (S3C_GPIO_BASE + 0x70)
+#define S3C_GPHDAT (S3C_GPIO_BASE + 0x74)
+#define S3C_GPHUP (S3C_GPIO_BASE + 0x78)
+
+#ifdef CONFIG_CPU_S3C2440
+# define S3C_GPJCON (S3C_GPIO_BASE + 0xd0)
+# define S3C_GPJDAT (S3C_GPIO_BASE + 0xd4)
+# define S3C_GPJUP (S3C_GPIO_BASE + 0xd8)
+#endif
+
+#define S3C_MISCCR (S3C_GPIO_BASE + 0x80)
+#define S3C_DCLKCON (S3C_GPIO_BASE + 0x84)
+#define S3C_EXTINT0 (S3C_GPIO_BASE + 0x88)
+#define S3C_EXTINT1 (S3C_GPIO_BASE + 0x8c)
+#define S3C_EXTINT2 (S3C_GPIO_BASE + 0x90)
+#define S3C_EINTFLT0 (S3C_GPIO_BASE + 0x94)
+#define S3C_EINTFLT1 (S3C_GPIO_BASE + 0x98)
+#define S3C_EINTFLT2 (S3C_GPIO_BASE + 0x9c)
+#define S3C_EINTFLT3 (S3C_GPIO_BASE + 0xa0)
+#define S3C_EINTMASK (S3C_GPIO_BASE + 0xa4)
+#define S3C_EINTPEND (S3C_GPIO_BASE + 0xa8)
+#define S3C_GSTATUS0 (S3C_GPIO_BASE + 0xac)
+#define S3C_GSTATUS1 (S3C_GPIO_BASE + 0xb0)
+#define S3C_GSTATUS2 (S3C_GPIO_BASE + 0xb4)
+#define S3C_GSTATUS3 (S3C_GPIO_BASE + 0xb8)
+#define S3C_GSTATUS4 (S3C_GPIO_BASE + 0xbc)
+
+#ifdef CONFIG_CPU_S3C2440
+# define S3C_DSC0 (S3C_GPIO_BASE + 0xc4)
+# define S3C_DSC1 (S3C_GPIO_BASE + 0xc8)
+#endif
+
+#endif /* __MACH_S3C24XX_GPIO_H */
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 06/14] MACH SAMSUNG/S3C: Reflect the CPU name the LCD driver is for
2011-12-25 20:38 [PATCH] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
@ 2011-12-25 20:38 ` Juergen Beisert
0 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2011-12-25 20:38 UTC (permalink / raw)
To: barebox
This LCD driver is for the LCD controller in the S3C2410/S3C2440 CPUs only.
Change its name to reflect its usage and free the way to add LCD controller
drivers for more recent Samsung CPUs.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/mini2440/mini2440.c | 2 +-
arch/arm/mach-samsung/include/mach/fb.h | 59 ---
arch/arm/mach-samsung/include/mach/s3c24xx-fb.h | 59 +++
drivers/video/Kconfig | 2 +-
drivers/video/Makefile | 2 +-
drivers/video/s3c.c | 431 -----------------------
drivers/video/s3c24xx.c | 431 +++++++++++++++++++++++
7 files changed, 493 insertions(+), 493 deletions(-)
delete mode 100644 arch/arm/mach-samsung/include/mach/fb.h
create mode 100644 arch/arm/mach-samsung/include/mach/s3c24xx-fb.h
delete mode 100644 drivers/video/s3c.c
create mode 100644 drivers/video/s3c24xx.c
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 233f337..0186465 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -42,7 +42,7 @@
#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-mci.h>
-#include <mach/fb.h>
+#include <mach/s3c24xx-fb.h>
static struct s3c24x0_nand_platform_data nand_info = {
.nand_timing = CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0,
diff --git a/arch/arm/mach-samsung/include/mach/fb.h b/arch/arm/mach-samsung/include/mach/fb.h
deleted file mode 100644
index 05e013a..0000000
--- a/arch/arm/mach-samsung/include/mach/fb.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (C) 2010 Juergen Beisert
- * Copyright (C) 2011 Alexey Galakhov
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __MACH_FB_H_
-# define __MACH_FB_H_
-
-#include <fb.h>
-
-/** Proprietary flags corresponding to S3C24x0 LCDCON5 register */
-
-/** ! INVVDEN - DE active high */
-#define FB_SYNC_DE_HIGH_ACT (1 << 23)
-/** INVVCLK - invert CLK signal */
-#define FB_SYNC_CLK_INVERT (1 << 24)
-/** INVVD - invert data */
-#define FB_SYNC_DATA_INVERT (1 << 25)
-/** INVPWREN - use PWREN signal */
-#define FB_SYNC_INVERT_PWREN (1 << 26)
-/** INVLEND - use LEND signal */
-#define FB_SYNC_INVERT_LEND (1 << 27)
-/** PWREN - use PWREN signal */
-#define FB_SYNC_USE_PWREN (1 << 28)
-/** ENLEND - use LEND signal */
-#define FB_SYNC_USE_LEND (1 << 29)
-/** BSWP - swap bytes */
-#define FB_SYNC_SWAP_BYTES (1 << 30)
-/** HWSWP - swap half words */
-#define FB_SYNC_SWAP_HW (1 << 31)
-
-struct s3c_fb_platform_data {
- struct fb_videomode *mode_list;
- unsigned mode_cnt;
-
- unsigned bits_per_pixel;
- int passive_display; /**< enable support for STN or CSTN displays */
-
- /** hook to enable backlight and stuff */
- void (*enable)(int enable);
-};
-
-#endif /* __MACH_FB_H_ */
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-fb.h b/arch/arm/mach-samsung/include/mach/s3c24xx-fb.h
new file mode 100644
index 0000000..05e013a
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c24xx-fb.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2010 Juergen Beisert
+ * Copyright (C) 2011 Alexey Galakhov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MACH_FB_H_
+# define __MACH_FB_H_
+
+#include <fb.h>
+
+/** Proprietary flags corresponding to S3C24x0 LCDCON5 register */
+
+/** ! INVVDEN - DE active high */
+#define FB_SYNC_DE_HIGH_ACT (1 << 23)
+/** INVVCLK - invert CLK signal */
+#define FB_SYNC_CLK_INVERT (1 << 24)
+/** INVVD - invert data */
+#define FB_SYNC_DATA_INVERT (1 << 25)
+/** INVPWREN - use PWREN signal */
+#define FB_SYNC_INVERT_PWREN (1 << 26)
+/** INVLEND - use LEND signal */
+#define FB_SYNC_INVERT_LEND (1 << 27)
+/** PWREN - use PWREN signal */
+#define FB_SYNC_USE_PWREN (1 << 28)
+/** ENLEND - use LEND signal */
+#define FB_SYNC_USE_LEND (1 << 29)
+/** BSWP - swap bytes */
+#define FB_SYNC_SWAP_BYTES (1 << 30)
+/** HWSWP - swap half words */
+#define FB_SYNC_SWAP_HW (1 << 31)
+
+struct s3c_fb_platform_data {
+ struct fb_videomode *mode_list;
+ unsigned mode_cnt;
+
+ unsigned bits_per_pixel;
+ int passive_display; /**< enable support for STN or CSTN displays */
+
+ /** hook to enable backlight and stuff */
+ void (*enable)(int enable);
+};
+
+#endif /* __MACH_FB_H_ */
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index df2157e..4a05af9 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -27,7 +27,7 @@ config DRIVER_VIDEO_STM
Say 'Y' here to enable framebuffer and splash screen support for
i.MX23 and i.MX28 based systems.
-config DRIVER_VIDEO_S3C
+config DRIVER_VIDEO_S3C24XX
bool "S3C244x framebuffer driver"
depends on ARCH_S3C24xx
help
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 123c46f..913c78d 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -3,5 +3,5 @@ obj-$(CONFIG_VIDEO) += fb.o
obj-$(CONFIG_DRIVER_VIDEO_STM) += stm.o
obj-$(CONFIG_DRIVER_VIDEO_IMX) += imx.o
obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
-obj-$(CONFIG_DRIVER_VIDEO_S3C) += s3c.o
+obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
diff --git a/drivers/video/s3c.c b/drivers/video/s3c.c
deleted file mode 100644
index a03ec3d..0000000
--- a/drivers/video/s3c.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/*
- * Copyright (C) 2010 Juergen Beisert
- * Copyright (C) 2011 Alexey Galakhov
- *
- * This driver is based on a patch found in the web:
- * (C) Copyright 2006 by OpenMoko, Inc.
- * Author: Harald Welte <laforge at openmoko.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <init.h>
-#include <fb.h>
-#include <driver.h>
-#include <malloc.h>
-#include <errno.h>
-#include <io.h>
-#include <mach/gpio.h>
-#include <mach/s3c-generic.h>
-#include <mach/fb.h>
-
-#define LCDCON1 0x00
-# define PNRMODE(x) (((x) & 3) << 5)
-# define BPPMODE(x) (((x) & 0xf) << 1)
-# define SET_CLKVAL(x) (((x) & 0x3ff) << 8)
-# define GET_CLKVAL(x) (((x) >> 8) & 0x3ff)
-# define ENVID (1 << 0)
-
-#define LCDCON2 0x04
-# define SET_VBPD(x) (((x) & 0xff) << 24)
-# define SET_LINEVAL(x) (((x) & 0x3ff) << 14)
-# define SET_VFPD(x) (((x) & 0xff) << 6)
-# define SET_VSPW(x) ((x) & 0x3f)
-
-#define LCDCON3 0x08
-# define SET_HBPD(x) (((x) & 0x7f) << 19)
-# define SET_HOZVAL(x) (((x) & 0x7ff) << 8)
-# define SET_HFPD(x) ((x) & 0xff)
-
-#define LCDCON4 0x0c
-# define SET_HSPW(x) ((x) & 0xff)
-
-#define LCDCON5 0x10
-# define BPP24BL (1 << 12)
-# define FRM565 (1 << 11)
-# define INV_CLK (1 << 10)
-# define INV_HS (1 << 9)
-# define INV_VS (1 << 8)
-# define INV_DTA (1 << 7)
-# define INV_DE (1 << 6)
-# define INV_PWREN (1 << 5)
-# define INV_LEND (1 << 4)
-# define ENA_PWREN (1 << 3)
-# define ENA_LEND (1 << 2)
-# define BSWP (1 << 1)
-# define HWSWP (1 << 0)
-
-#define LCDSADDR1 0x14
-# define SET_LCDBANK(x) (((x) & 0x1ff) << 21)
-# define GET_LCDBANK(x) (((x) >> 21) & 0x1ff)
-# define SET_LCDBASEU(x) ((x) & 0x1fffff)
-# define GET_LCDBASEU(x) ((x) & 0x1fffff)
-
-#define LCDSADDR2 0x18
-# define SET_LCDBASEL(x) ((x) & 0x1fffff)
-# define GET_LCDBASEL(x) ((x) & 0x1fffff)
-
-#define LCDSADDR3 0x1c
-# define SET_OFFSIZE(x) (((x) & 0x7ff) << 11)
-# define GET_OFFSIZE(x) (((x) >> 11) & 0x7ff)
-# define SET_PAGE_WIDTH(x) ((x) & 0x3ff)
-# define GET_PAGE_WIDTH(x) ((x) & 0x3ff)
-
-#define RED_LUT 0x20
-#define GREEN_LUT 0x24
-#define BLUE_LUT 0x28
-
-#define DITHMODE 0x4c
-
-#define TPAL 0x50
-
-#define LCDINTPND 0x54
-#define LCDSRCPND 0x58
-#define LCDINTMSK 0x5c
-# define FIWSEL (1 << 2)
-# define INT_FrSyn (1 << 1)
-# define INT_FiCnt (1 << 0)
-
-#define TCONSEL 0x60
-
-#define RED 0
-#define GREEN 1
-#define BLUE 2
-#define TRANSP 3
-
-struct s3cfb_info {
- void __iomem *base;
- unsigned memory_size;
- struct fb_info info;
- struct device_d *hw_dev;
- int passive_display;
- void (*enable)(int enable);
-};
-
-/* the RGB565 true colour mode */
-static const struct fb_bitfield def_rgb565[] = {
- [RED] = {
- .offset = 11,
- .length = 5,
- },
- [GREEN] = {
- .offset = 5,
- .length = 6,
- },
- [BLUE] = {
- .offset = 0,
- .length = 5,
- },
- [TRANSP] = { /* no support for transparency */
- .length = 0,
- }
-};
-
-/* the RGB888 true colour mode */
-static const struct fb_bitfield def_rgb888[] = {
- [RED] = {
- .offset = 16,
- .length = 8,
- },
- [GREEN] = {
- .offset = 8,
- .length = 8,
- },
- [BLUE] = {
- .offset = 0,
- .length = 8,
- },
- [TRANSP] = { /* no support for transparency */
- .length = 0,
- }
-};
-
-/**
- * @param fb_info Framebuffer information
- */
-static void s3cfb_enable_controller(struct fb_info *fb_info)
-{
- struct s3cfb_info *fbi = fb_info->priv;
- uint32_t con1;
-
- con1 = readl(fbi->base + LCDCON1);
-
- con1 |= ENVID;
-
- writel(con1, fbi->base + LCDCON1);
-
- if (fbi->enable)
- fbi->enable(1);
-}
-
-/**
- * @param fb_info Framebuffer information
- */
-static void s3cfb_disable_controller(struct fb_info *fb_info)
-{
- struct s3cfb_info *fbi = fb_info->priv;
- uint32_t con1;
-
- if (fbi->enable)
- fbi->enable(0);
-
- con1 = readl(fbi->base + LCDCON1);
-
- con1 &= ~ENVID;
-
- writel(con1, fbi->base + LCDCON1);
-}
-
-/**
- * Prepare the video hardware for a specified video mode
- * @param fb_info Framebuffer information
- * @param mode The video mode description to initialize
- * @return 0 on success
- */
-static int s3cfb_activate_var(struct fb_info *fb_info)
-{
- struct s3cfb_info *fbi = fb_info->priv;
- struct fb_videomode *mode = fb_info->mode;
- unsigned size, hclk, div;
- uint32_t con1, con2, con3, con4, con5 = 0;
-
- if (fbi->passive_display != 0) {
- dev_err(fbi->hw_dev, "Passive displays are currently not supported\n");
- return -EINVAL;
- }
-
- /*
- * we need at least this amount of memory for the framebuffer
- */
- size = mode->xres * mode->yres * (fb_info->bits_per_pixel >> 3);
- if (fbi->memory_size != size || fb_info->screen_base == NULL) {
- if (fb_info->screen_base)
- free(fb_info->screen_base);
- fbi->memory_size = 0;
- fb_info->screen_base = malloc(size);
- if (! fb_info->screen_base)
- return -ENOMEM;
- memset(fb_info->screen_base, 0, size);
- fbi->memory_size = size;
- }
-
- /* ensure video output is _off_ */
- writel(0x00000000, fbi->base + LCDCON1);
-
- hclk = s3c24xx_get_hclk() / 1000U; /* hclk in kHz */
- div = hclk / PICOS2KHZ(mode->pixclock);
- if (div < 3)
- div = 3;
- /* pixel clock is: (hclk) / ((div + 1) * 2) */
- div += 1;
- div >>= 1;
- div -= 1;
-
- con1 = PNRMODE(3) | SET_CLKVAL(div); /* PNRMODE=3 is TFT */
-
- switch (fb_info->bits_per_pixel) {
- case 16:
- con1 |= BPPMODE(12);
- con5 |= FRM565;
- con5 |= HWSWP;
- fb_info->red = def_rgb565[RED];
- fb_info->green = def_rgb565[GREEN];
- fb_info->blue = def_rgb565[BLUE];
- fb_info->transp = def_rgb565[TRANSP];
- break;
- case 24:
- con1 |= BPPMODE(13);
- /* con5 |= BPP24BL; */ /* FIXME maybe needed, check alignment */
- fb_info->red = def_rgb888[RED];
- fb_info->green = def_rgb888[GREEN];
- fb_info->blue = def_rgb888[BLUE];
- fb_info->transp = def_rgb888[TRANSP];
- break;
- default:
- dev_err(fbi->hw_dev, "Invalid bits per pixel value: %u\n", fb_info->bits_per_pixel);
- return -EINVAL;
- }
-
- /* 'normal' in register description means positive logic */
- if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
- con5 |= INV_HS;
- if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
- con5 |= INV_VS;
- if (!(mode->sync & FB_SYNC_DE_HIGH_ACT))
- con5 |= INV_DE;
- if (mode->sync & FB_SYNC_CLK_INVERT)
- con5 |= INV_CLK; /* display should latch at the rising edge */
- if (mode->sync & FB_SYNC_DATA_INVERT)
- con5 |= INV_DTA;
- if (mode->sync & FB_SYNC_INVERT_PWREN)
- con5 |= INV_PWREN;
- if (mode->sync & FB_SYNC_INVERT_LEND)
- con5 |= INV_LEND;
- if (mode->sync & FB_SYNC_USE_PWREN)
- con5 |= ENA_PWREN; /* FIXME should this be done conditionally/later? */
- if (mode->sync & FB_SYNC_USE_LEND)
- con5 |= ENA_LEND;
- if (mode->sync & FB_SYNC_SWAP_BYTES)
- con5 ^= BSWP;
- if (mode->sync & FB_SYNC_SWAP_HW)
- con5 ^= HWSWP;
-
- /* vertical timing */
- con2 = SET_VBPD(mode->upper_margin - 1) |
- SET_LINEVAL(mode->yres - 1) |
- SET_VFPD(mode->lower_margin - 1) |
- SET_VSPW(mode->vsync_len - 1);
-
- /* horizontal timing */
- con3 = SET_HBPD(mode->left_margin - 1) |
- SET_HOZVAL(mode->xres - 1) |
- SET_HFPD(mode->right_margin - 1);
- con4 = SET_HSPW(mode->hsync_len - 1);
-
- /* basic timing setup */
- writel(con1, fbi->base + LCDCON1);
- dev_dbg(fbi->hw_dev, "writing %08X into %p (con1)\n", con1, fbi->base + LCDCON1);
- writel(con2, fbi->base + LCDCON2);
- dev_dbg(fbi->hw_dev, "writing %08X into %p (con2)\n", con2, fbi->base + LCDCON2);
- writel(con3, fbi->base + LCDCON3);
- dev_dbg(fbi->hw_dev, "writing %08X into %p (con3)\n", con3, fbi->base + LCDCON3);
- writel(con4, fbi->base + LCDCON4);
- dev_dbg(fbi->hw_dev, "writing %08X into %p (con4)\n", con4, fbi->base + LCDCON4);
- writel(con5, fbi->base + LCDCON5);
- dev_dbg(fbi->hw_dev, "writing %08X into %p (con5)\n", con5, fbi->base + LCDCON5);
-
- dev_dbg(fbi->hw_dev, "setting up the fb baseadress to %p\n", fb_info->screen_base);
-
- /* framebuffer memory setup */
- writel((unsigned)fb_info->screen_base >> 1, fbi->base + LCDSADDR1);
- size = mode->xres * (fb_info->bits_per_pixel >> 3) * (mode->yres);
- writel(SET_LCDBASEL(((unsigned)fb_info->screen_base + size) >> 1), fbi->base + LCDSADDR2);
- writel(SET_OFFSIZE(0) |
- SET_PAGE_WIDTH((mode->xres * fb_info->bits_per_pixel) >> 4),
- fbi->base + LCDSADDR3);
- writel(FIWSEL | INT_FrSyn | INT_FiCnt, fbi->base + LCDINTMSK);
-
- return 0;
-}
-
-/**
- * Print some information about the current hardware state
- * @param hw_dev S3C video device
- */
-#ifdef CONFIG_DRIVER_VIDEO_S3C_VERBOSE
-static void s3cfb_info(struct device_d *hw_dev)
-{
- uint32_t con1, addr1, addr2, addr3;
- struct s3cfb_info *fbi = hw_dev->priv;
-
- con1 = readl(fbi->base + LCDCON1);
- addr1 = readl(fbi->base + LCDSADDR1);
- addr2 = readl(fbi->base + LCDSADDR2);
- addr3 = readl(fbi->base + LCDSADDR3);
-
- printf(" Video hardware info:\n");
- printf(" Video clock is running at %u Hz\n", s3c24xx_get_hclk() / ((GET_CLKVAL(con1) + 1) * 2));
- printf(" Video memory bank starts at 0x%08X\n", GET_LCDBANK(addr1) << 22);
- printf(" Video memory bank offset: 0x%08X\n", GET_LCDBASEU(addr1));
- printf(" Video memory end: 0x%08X\n", GET_LCDBASEU(addr2));
- printf(" Virtual screen offset size: %u half words\n", GET_OFFSIZE(addr3));
- printf(" Virtual screen page width: %u half words\n", GET_PAGE_WIDTH(addr3));
-}
-#endif
-
-/*
- * There is only one video hardware instance available.
- * It makes no sense to dynamically allocate this data
- */
-static struct fb_ops s3cfb_ops = {
- .fb_activate_var = s3cfb_activate_var,
- .fb_enable = s3cfb_enable_controller,
- .fb_disable = s3cfb_disable_controller,
-};
-
-static struct s3cfb_info fbi = {
- .info = {
- .fbops = &s3cfb_ops,
- },
-};
-
-static int s3cfb_probe(struct device_d *hw_dev)
-{
- struct s3c_fb_platform_data *pdata = hw_dev->platform_data;
- int ret;
-
- if (! pdata)
- return -ENODEV;
-
- fbi.base = dev_request_mem_region(hw_dev, 0);
- writel(0, fbi.base + LCDCON1);
- writel(0, fbi.base + LCDCON5); /* FIXME not 0 for some displays */
-
- /* just init */
- fbi.info.priv = &fbi;
-
- /* add runtime hardware info */
- fbi.hw_dev = hw_dev;
- hw_dev->priv = &fbi;
-
- /* add runtime video info */
- fbi.info.mode_list = pdata->mode_list;
- fbi.info.num_modes = pdata->mode_cnt;
- fbi.info.mode = &fbi.info.mode_list[1];
- fbi.info.xres = fbi.info.mode->xres;
- fbi.info.yres = fbi.info.mode->yres;
- if (pdata->bits_per_pixel)
- fbi.info.bits_per_pixel = pdata->bits_per_pixel;
- else
- fbi.info.bits_per_pixel = 16;
- fbi.passive_display = pdata->passive_display;
- fbi.enable = pdata->enable;
-
- ret = register_framebuffer(&fbi.info);
- if (ret != 0) {
- dev_err(hw_dev, "Failed to register framebuffer\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-static struct driver_d s3cfb_driver = {
- .name = "s3c_fb",
- .probe = s3cfb_probe,
-#ifdef CONFIG_DRIVER_VIDEO_S3C_VERBOSE
- .info = s3cfb_info,
-#endif
-};
-
-static int s3cfb_init(void)
-{
- return register_driver(&s3cfb_driver);
-}
-
-device_initcall(s3cfb_init);
-
-/**
- * The S3C244x LCD controller supports passive (CSTN/STN) and active (TFT) LC displays
- *
- * The driver itself currently supports only active TFT LC displays in the follwing manner:
- *
- * * True colours
- * - 16 bpp
- * - 24 bpp (untested)
- */
diff --git a/drivers/video/s3c24xx.c b/drivers/video/s3c24xx.c
new file mode 100644
index 0000000..75677c3
--- /dev/null
+++ b/drivers/video/s3c24xx.c
@@ -0,0 +1,431 @@
+/*
+ * Copyright (C) 2010 Juergen Beisert
+ * Copyright (C) 2011 Alexey Galakhov
+ *
+ * This driver is based on a patch found in the web:
+ * (C) Copyright 2006 by OpenMoko, Inc.
+ * Author: Harald Welte <laforge at openmoko.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <fb.h>
+#include <driver.h>
+#include <malloc.h>
+#include <errno.h>
+#include <io.h>
+#include <mach/s3c-gpio.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c24xx-fb.h>
+
+#define LCDCON1 0x00
+# define PNRMODE(x) (((x) & 3) << 5)
+# define BPPMODE(x) (((x) & 0xf) << 1)
+# define SET_CLKVAL(x) (((x) & 0x3ff) << 8)
+# define GET_CLKVAL(x) (((x) >> 8) & 0x3ff)
+# define ENVID (1 << 0)
+
+#define LCDCON2 0x04
+# define SET_VBPD(x) (((x) & 0xff) << 24)
+# define SET_LINEVAL(x) (((x) & 0x3ff) << 14)
+# define SET_VFPD(x) (((x) & 0xff) << 6)
+# define SET_VSPW(x) ((x) & 0x3f)
+
+#define LCDCON3 0x08
+# define SET_HBPD(x) (((x) & 0x7f) << 19)
+# define SET_HOZVAL(x) (((x) & 0x7ff) << 8)
+# define SET_HFPD(x) ((x) & 0xff)
+
+#define LCDCON4 0x0c
+# define SET_HSPW(x) ((x) & 0xff)
+
+#define LCDCON5 0x10
+# define BPP24BL (1 << 12)
+# define FRM565 (1 << 11)
+# define INV_CLK (1 << 10)
+# define INV_HS (1 << 9)
+# define INV_VS (1 << 8)
+# define INV_DTA (1 << 7)
+# define INV_DE (1 << 6)
+# define INV_PWREN (1 << 5)
+# define INV_LEND (1 << 4)
+# define ENA_PWREN (1 << 3)
+# define ENA_LEND (1 << 2)
+# define BSWP (1 << 1)
+# define HWSWP (1 << 0)
+
+#define LCDSADDR1 0x14
+# define SET_LCDBANK(x) (((x) & 0x1ff) << 21)
+# define GET_LCDBANK(x) (((x) >> 21) & 0x1ff)
+# define SET_LCDBASEU(x) ((x) & 0x1fffff)
+# define GET_LCDBASEU(x) ((x) & 0x1fffff)
+
+#define LCDSADDR2 0x18
+# define SET_LCDBASEL(x) ((x) & 0x1fffff)
+# define GET_LCDBASEL(x) ((x) & 0x1fffff)
+
+#define LCDSADDR3 0x1c
+# define SET_OFFSIZE(x) (((x) & 0x7ff) << 11)
+# define GET_OFFSIZE(x) (((x) >> 11) & 0x7ff)
+# define SET_PAGE_WIDTH(x) ((x) & 0x3ff)
+# define GET_PAGE_WIDTH(x) ((x) & 0x3ff)
+
+#define RED_LUT 0x20
+#define GREEN_LUT 0x24
+#define BLUE_LUT 0x28
+
+#define DITHMODE 0x4c
+
+#define TPAL 0x50
+
+#define LCDINTPND 0x54
+#define LCDSRCPND 0x58
+#define LCDINTMSK 0x5c
+# define FIWSEL (1 << 2)
+# define INT_FrSyn (1 << 1)
+# define INT_FiCnt (1 << 0)
+
+#define TCONSEL 0x60
+
+#define RED 0
+#define GREEN 1
+#define BLUE 2
+#define TRANSP 3
+
+struct s3cfb_info {
+ void __iomem *base;
+ unsigned memory_size;
+ struct fb_info info;
+ struct device_d *hw_dev;
+ int passive_display;
+ void (*enable)(int enable);
+};
+
+/* the RGB565 true colour mode */
+static const struct fb_bitfield def_rgb565[] = {
+ [RED] = {
+ .offset = 11,
+ .length = 5,
+ },
+ [GREEN] = {
+ .offset = 5,
+ .length = 6,
+ },
+ [BLUE] = {
+ .offset = 0,
+ .length = 5,
+ },
+ [TRANSP] = { /* no support for transparency */
+ .length = 0,
+ }
+};
+
+/* the RGB888 true colour mode */
+static const struct fb_bitfield def_rgb888[] = {
+ [RED] = {
+ .offset = 16,
+ .length = 8,
+ },
+ [GREEN] = {
+ .offset = 8,
+ .length = 8,
+ },
+ [BLUE] = {
+ .offset = 0,
+ .length = 8,
+ },
+ [TRANSP] = { /* no support for transparency */
+ .length = 0,
+ }
+};
+
+/**
+ * @param fb_info Framebuffer information
+ */
+static void s3cfb_enable_controller(struct fb_info *fb_info)
+{
+ struct s3cfb_info *fbi = fb_info->priv;
+ uint32_t con1;
+
+ con1 = readl(fbi->base + LCDCON1);
+
+ con1 |= ENVID;
+
+ writel(con1, fbi->base + LCDCON1);
+
+ if (fbi->enable)
+ fbi->enable(1);
+}
+
+/**
+ * @param fb_info Framebuffer information
+ */
+static void s3cfb_disable_controller(struct fb_info *fb_info)
+{
+ struct s3cfb_info *fbi = fb_info->priv;
+ uint32_t con1;
+
+ if (fbi->enable)
+ fbi->enable(0);
+
+ con1 = readl(fbi->base + LCDCON1);
+
+ con1 &= ~ENVID;
+
+ writel(con1, fbi->base + LCDCON1);
+}
+
+/**
+ * Prepare the video hardware for a specified video mode
+ * @param fb_info Framebuffer information
+ * @param mode The video mode description to initialize
+ * @return 0 on success
+ */
+static int s3cfb_activate_var(struct fb_info *fb_info)
+{
+ struct s3cfb_info *fbi = fb_info->priv;
+ struct fb_videomode *mode = fb_info->mode;
+ unsigned size, hclk, div;
+ uint32_t con1, con2, con3, con4, con5 = 0;
+
+ if (fbi->passive_display != 0) {
+ dev_err(fbi->hw_dev, "Passive displays are currently not supported\n");
+ return -EINVAL;
+ }
+
+ /*
+ * we need at least this amount of memory for the framebuffer
+ */
+ size = mode->xres * mode->yres * (fb_info->bits_per_pixel >> 3);
+ if (fbi->memory_size != size || fb_info->screen_base == NULL) {
+ if (fb_info->screen_base)
+ free(fb_info->screen_base);
+ fbi->memory_size = 0;
+ fb_info->screen_base = malloc(size);
+ if (! fb_info->screen_base)
+ return -ENOMEM;
+ memset(fb_info->screen_base, 0, size);
+ fbi->memory_size = size;
+ }
+
+ /* ensure video output is _off_ */
+ writel(0x00000000, fbi->base + LCDCON1);
+
+ hclk = s3c24xx_get_hclk() / 1000U; /* hclk in kHz */
+ div = hclk / PICOS2KHZ(mode->pixclock);
+ if (div < 3)
+ div = 3;
+ /* pixel clock is: (hclk) / ((div + 1) * 2) */
+ div += 1;
+ div >>= 1;
+ div -= 1;
+
+ con1 = PNRMODE(3) | SET_CLKVAL(div); /* PNRMODE=3 is TFT */
+
+ switch (fb_info->bits_per_pixel) {
+ case 16:
+ con1 |= BPPMODE(12);
+ con5 |= FRM565;
+ con5 |= HWSWP;
+ fb_info->red = def_rgb565[RED];
+ fb_info->green = def_rgb565[GREEN];
+ fb_info->blue = def_rgb565[BLUE];
+ fb_info->transp = def_rgb565[TRANSP];
+ break;
+ case 24:
+ con1 |= BPPMODE(13);
+ /* con5 |= BPP24BL; */ /* FIXME maybe needed, check alignment */
+ fb_info->red = def_rgb888[RED];
+ fb_info->green = def_rgb888[GREEN];
+ fb_info->blue = def_rgb888[BLUE];
+ fb_info->transp = def_rgb888[TRANSP];
+ break;
+ default:
+ dev_err(fbi->hw_dev, "Invalid bits per pixel value: %u\n", fb_info->bits_per_pixel);
+ return -EINVAL;
+ }
+
+ /* 'normal' in register description means positive logic */
+ if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
+ con5 |= INV_HS;
+ if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
+ con5 |= INV_VS;
+ if (!(mode->sync & FB_SYNC_DE_HIGH_ACT))
+ con5 |= INV_DE;
+ if (mode->sync & FB_SYNC_CLK_INVERT)
+ con5 |= INV_CLK; /* display should latch at the rising edge */
+ if (mode->sync & FB_SYNC_DATA_INVERT)
+ con5 |= INV_DTA;
+ if (mode->sync & FB_SYNC_INVERT_PWREN)
+ con5 |= INV_PWREN;
+ if (mode->sync & FB_SYNC_INVERT_LEND)
+ con5 |= INV_LEND;
+ if (mode->sync & FB_SYNC_USE_PWREN)
+ con5 |= ENA_PWREN; /* FIXME should this be done conditionally/later? */
+ if (mode->sync & FB_SYNC_USE_LEND)
+ con5 |= ENA_LEND;
+ if (mode->sync & FB_SYNC_SWAP_BYTES)
+ con5 ^= BSWP;
+ if (mode->sync & FB_SYNC_SWAP_HW)
+ con5 ^= HWSWP;
+
+ /* vertical timing */
+ con2 = SET_VBPD(mode->upper_margin - 1) |
+ SET_LINEVAL(mode->yres - 1) |
+ SET_VFPD(mode->lower_margin - 1) |
+ SET_VSPW(mode->vsync_len - 1);
+
+ /* horizontal timing */
+ con3 = SET_HBPD(mode->left_margin - 1) |
+ SET_HOZVAL(mode->xres - 1) |
+ SET_HFPD(mode->right_margin - 1);
+ con4 = SET_HSPW(mode->hsync_len - 1);
+
+ /* basic timing setup */
+ writel(con1, fbi->base + LCDCON1);
+ dev_dbg(fbi->hw_dev, "writing %08X into %p (con1)\n", con1, fbi->base + LCDCON1);
+ writel(con2, fbi->base + LCDCON2);
+ dev_dbg(fbi->hw_dev, "writing %08X into %p (con2)\n", con2, fbi->base + LCDCON2);
+ writel(con3, fbi->base + LCDCON3);
+ dev_dbg(fbi->hw_dev, "writing %08X into %p (con3)\n", con3, fbi->base + LCDCON3);
+ writel(con4, fbi->base + LCDCON4);
+ dev_dbg(fbi->hw_dev, "writing %08X into %p (con4)\n", con4, fbi->base + LCDCON4);
+ writel(con5, fbi->base + LCDCON5);
+ dev_dbg(fbi->hw_dev, "writing %08X into %p (con5)\n", con5, fbi->base + LCDCON5);
+
+ dev_dbg(fbi->hw_dev, "setting up the fb baseadress to %p\n", fb_info->screen_base);
+
+ /* framebuffer memory setup */
+ writel((unsigned)fb_info->screen_base >> 1, fbi->base + LCDSADDR1);
+ size = mode->xres * (fb_info->bits_per_pixel >> 3) * (mode->yres);
+ writel(SET_LCDBASEL(((unsigned)fb_info->screen_base + size) >> 1), fbi->base + LCDSADDR2);
+ writel(SET_OFFSIZE(0) |
+ SET_PAGE_WIDTH((mode->xres * fb_info->bits_per_pixel) >> 4),
+ fbi->base + LCDSADDR3);
+ writel(FIWSEL | INT_FrSyn | INT_FiCnt, fbi->base + LCDINTMSK);
+
+ return 0;
+}
+
+/**
+ * Print some information about the current hardware state
+ * @param hw_dev S3C video device
+ */
+#ifdef CONFIG_DRIVER_VIDEO_S3C_VERBOSE
+static void s3cfb_info(struct device_d *hw_dev)
+{
+ uint32_t con1, addr1, addr2, addr3;
+ struct s3cfb_info *fbi = hw_dev->priv;
+
+ con1 = readl(fbi->base + LCDCON1);
+ addr1 = readl(fbi->base + LCDSADDR1);
+ addr2 = readl(fbi->base + LCDSADDR2);
+ addr3 = readl(fbi->base + LCDSADDR3);
+
+ printf(" Video hardware info:\n");
+ printf(" Video clock is running at %u Hz\n", s3c24xx_get_hclk() / ((GET_CLKVAL(con1) + 1) * 2));
+ printf(" Video memory bank starts at 0x%08X\n", GET_LCDBANK(addr1) << 22);
+ printf(" Video memory bank offset: 0x%08X\n", GET_LCDBASEU(addr1));
+ printf(" Video memory end: 0x%08X\n", GET_LCDBASEU(addr2));
+ printf(" Virtual screen offset size: %u half words\n", GET_OFFSIZE(addr3));
+ printf(" Virtual screen page width: %u half words\n", GET_PAGE_WIDTH(addr3));
+}
+#endif
+
+/*
+ * There is only one video hardware instance available.
+ * It makes no sense to dynamically allocate this data
+ */
+static struct fb_ops s3cfb_ops = {
+ .fb_activate_var = s3cfb_activate_var,
+ .fb_enable = s3cfb_enable_controller,
+ .fb_disable = s3cfb_disable_controller,
+};
+
+static struct s3cfb_info fbi = {
+ .info = {
+ .fbops = &s3cfb_ops,
+ },
+};
+
+static int s3cfb_probe(struct device_d *hw_dev)
+{
+ struct s3c_fb_platform_data *pdata = hw_dev->platform_data;
+ int ret;
+
+ if (! pdata)
+ return -ENODEV;
+
+ fbi.base = dev_request_mem_region(hw_dev, 0);
+ writel(0, fbi.base + LCDCON1);
+ writel(0, fbi.base + LCDCON5); /* FIXME not 0 for some displays */
+
+ /* just init */
+ fbi.info.priv = &fbi;
+
+ /* add runtime hardware info */
+ fbi.hw_dev = hw_dev;
+ hw_dev->priv = &fbi;
+
+ /* add runtime video info */
+ fbi.info.mode_list = pdata->mode_list;
+ fbi.info.num_modes = pdata->mode_cnt;
+ fbi.info.mode = &fbi.info.mode_list[1];
+ fbi.info.xres = fbi.info.mode->xres;
+ fbi.info.yres = fbi.info.mode->yres;
+ if (pdata->bits_per_pixel)
+ fbi.info.bits_per_pixel = pdata->bits_per_pixel;
+ else
+ fbi.info.bits_per_pixel = 16;
+ fbi.passive_display = pdata->passive_display;
+ fbi.enable = pdata->enable;
+
+ ret = register_framebuffer(&fbi.info);
+ if (ret != 0) {
+ dev_err(hw_dev, "Failed to register framebuffer\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static struct driver_d s3cfb_driver = {
+ .name = "s3c_fb",
+ .probe = s3cfb_probe,
+#ifdef CONFIG_DRIVER_VIDEO_S3C_VERBOSE
+ .info = s3cfb_info,
+#endif
+};
+
+static int s3cfb_init(void)
+{
+ return register_driver(&s3cfb_driver);
+}
+
+device_initcall(s3cfb_init);
+
+/**
+ * The S3C244x LCD controller supports passive (CSTN/STN) and active (TFT) LC displays
+ *
+ * The driver itself currently supports only active TFT LC displays in the follwing manner:
+ *
+ * * True colours
+ * - 16 bpp
+ * - 24 bpp (untested)
+ */
--
1.7.7.3
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