* [PATCH 1/5] pcm049: Update RAM timings
@ 2012-03-15 12:49 Teresa Gámez
2012-03-15 12:49 ` [PATCH 2/5] pcm049: Update muxing Teresa Gámez
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Teresa Gámez @ 2012-03-15 12:49 UTC (permalink / raw)
To: barebox
Updated RAM Timings for phyCORE-OMAP4.
Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
---
arch/arm/boards/pcm049/lowlevel.c | 27 +++++++++++++--------------
1 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c
index 444a394..5b91098 100644
--- a/arch/arm/boards/pcm049/lowlevel.c
+++ b/arch/arm/boards/pcm049/lowlevel.c
@@ -30,23 +30,22 @@
void set_muxconf_regs(void);
-/* Erstmal 200Mhz... */
-static const struct ddr_regs ddr_regs_mt42L64M64_3_200_mhz = {
- .tim1 = 0x0aa8d4e3,
- .tim2 = 0x202e0b92,
- .tim3 = 0x009da2b3,
- .phy_ctrl_1 = 0x849FF404, /* mostly from elpida */
- .ref_ctrl = 0x0000030c, /* from elpida 200MHz! */
- .config_init = 0x80000eb1,
- .config_final = 0x80000eb1,
- .zq_config = 0x500b3215, /* mostly from elpida */
- .mr1 = 0x23, /* from elpida 200MHz! */
- .mr2 = 0x1 /* from elpida 200MHz! */
+static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
+ .tim1 = 0x0EEB0662,
+ .tim2 = 0x20370DD2,
+ .tim3 = 0x00BFC33F,
+ .phy_ctrl_1 = 0x849FF408,
+ .ref_ctrl = 0x00000618,
+ .config_init = 0x80001AB1,
+ .config_final = 0x80001AB1,
+ .zq_config = 0xd0093215,
+ .mr1 = 0x83,
+ .mr2 = 0x4
};
static void noinline pcm049_init_lowlevel(void)
{
- struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR200;
+ struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2;
struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
@@ -55,7 +54,7 @@ static void noinline pcm049_init_lowlevel(void)
set_muxconf_regs();
- omap4_ddr_init(&ddr_regs_mt42L64M64_3_200_mhz, &core);
+ omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
omap4_scale_vcores();
--
1.7.0.4
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^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 2/5] pcm049: Update muxing 2012-03-15 12:49 [PATCH 1/5] pcm049: Update RAM timings Teresa Gámez @ 2012-03-15 12:49 ` Teresa Gámez 2012-03-15 12:49 ` [PATCH 3/5] pcm049: Update GPMC net conf Teresa Gámez ` (3 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: Teresa Gámez @ 2012-03-15 12:49 UTC (permalink / raw) To: barebox Update muxing setup for phyCORE-OMAP4. Signed-off-by: Teresa Gámez <t.gamez@phytec.de> --- arch/arm/boards/pcm049/mux.c | 238 +++++++++++++++++++++--------------------- 1 files changed, 119 insertions(+), 119 deletions(-) diff --git a/arch/arm/boards/pcm049/mux.c b/arch/arm/boards/pcm049/mux.c index 0e7adea..a7a77b5 100644 --- a/arch/arm/boards/pcm049/mux.c +++ b/arch/arm/boards/pcm049/mux.c @@ -49,27 +49,27 @@ static const struct pad_conf_entry core_padconf_array[] = { {C2C_DATA13, (IDIS | PTU | EN | M0)}, /* gpmc_nsc5 */ {C2C_DATA14, (SAFE_MODE)}, /* nc */ {C2C_DATA15, (SAFE_MODE)}, /* nc */ - {HDMI_HPD, (M0)}, /* hdmi_hpd */ - {HDMI_CEC, (DIS | IEN | M3)}, /* gpio_64 */ - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ + {HDMI_HPD, (SAFE_MODE)}, /* unused */ + {HDMI_CEC, (SAFE_MODE)}, /* unused */ + {HDMI_DDC_SCL, (SAFE_MODE)}, /* unused */ + {HDMI_DDC_SDA, (SAFE_MODE)}, /* unused */ + {CSI21_DX0, (SAFE_MODE)}, /* unused */ + {CSI21_DY0, (SAFE_MODE)}, /* unused */ + {CSI21_DX1, (SAFE_MODE)}, /* unused */ + {CSI21_DY1, (SAFE_MODE)}, /* unused */ + {CSI21_DX2, (SAFE_MODE)}, /* unused */ + {CSI21_DY2, (SAFE_MODE)}, /* unused */ + {CSI21_DX3, (SAFE_MODE)}, /* unused */ + {CSI21_DY3, (SAFE_MODE)}, /* unused */ + {CSI21_DX4, (SAFE_MODE)}, /* unused */ + {CSI21_DY4, (SAFE_MODE)}, /* unused */ + {CSI22_DX0, (SAFE_MODE)}, /* unused */ + {CSI22_DY0, (SAFE_MODE)}, /* unused */ + {CSI22_DX1, (SAFE_MODE)}, /* unused */ + {CSI22_DY1, (SAFE_MODE)}, /* unused */ + {CAM_SHUTTER, (SAFE_MODE)}, /* unused */ + {CAM_STROBE, (SAFE_MODE)}, /* unused */ + {CAM_GLOBALRESET, (SAFE_MODE)}, /* unused */ {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ @@ -82,57 +82,57 @@ static const struct pad_conf_entry core_padconf_array[] = { {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ - {USBB1_HSIC_DATA, (DIS | IEN | M3)}, /* gpio_96 */ - {USBB1_HSIC_STROBE, (DIS | IEN | M3)}, /* gpio_97 */ - {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ - {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ + {USBB1_HSIC_DATA, (SAFE_MODE)}, /* nc */ + {USBB1_HSIC_STROBE, (SAFE_MODE)}, /* nc */ + {USBC1_ICUSB_DP, (SAFE_MODE)}, /* unused */ + {USBC1_ICUSB_DM, (SAFE_MODE)}, /* unused */ {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ - {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ - {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ - {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ - {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (DIS | IEN | M3)}, /* gpio_114 */ - {ABE_MCBSP1_DR, (DIS | IEN | M3)}, /* gpio_115 */ - {ABE_MCBSP1_DX, (DIS | IEN | M3)}, /* gpio_116 */ - {ABE_MCBSP1_FSX, (DIS | IEN | M2)}, /* abe_mcasp_amutein */ - {ABE_PDM_UL_DATA, (IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* abe_mcbsp3_dr */ - {ABE_PDM_DL_DATA, (OFF_EN | OFF_OUT_PTD | M1)}, /* abe_mcbsp3_dx */ - {ABE_PDM_FRAME, (IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* abe_mcbsp3_clkx */ - {ABE_PDM_LB_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* abe_mcbsp3_fsx */ - {ABE_CLKS, (DIS | IEN | M3)}, /* gpio_118 */ + {SDMMC1_DAT4, (SAFE_MODE)}, /* unused */ + {SDMMC1_DAT5, (SAFE_MODE)}, /* unused */ + {SDMMC1_DAT6, (SAFE_MODE)}, /* unused */ + {SDMMC1_DAT7, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP2_CLKX, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP2_DR, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP2_DX, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP2_FSX, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP1_CLKX, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP1_DR, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP1_DX, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP1_FSX, (SAFE_MODE)}, /* unused */ + {ABE_PDM_UL_DATA, (SAFE_MODE)}, /* unused */ + {ABE_PDM_DL_DATA, (SAFE_MODE)}, /* unused */ + {ABE_PDM_FRAME, (SAFE_MODE)}, /* unused */ + {ABE_PDM_LB_CLK, (SAFE_MODE)}, /* unused */ + {ABE_CLKS, (SAFE_MODE)}, /* unused */ {ABE_DMIC_CLK1, (SAFE_MODE)}, /* nc */ - {ABE_DMIC_DIN1, (SAFE_MODE)}, /* nc */ - {ABE_DMIC_DIN2, (SAFE_MODE)}, /* nc */ - {ABE_DMIC_DIN3, (SAFE_MODE)}, /* nc */ - {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ - {UART2_RTS, (M0)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ - {UART2_TX, (M0)}, /* uart2_tx */ - {HDQ_SIO, (M0)}, /* hdq_sio */ + {ABE_DMIC_DIN1, (SAFE_MODE)}, /* unused */ + {ABE_DMIC_DIN2, (DIS | IEN | M3)}, /* gpio_121 */ + {ABE_DMIC_DIN3, (SAFE_MODE)}, /* unused */ + {UART2_CTS, (SAFE_MODE)}, /* unused */ + {UART2_RTS, (SAFE_MODE)}, /* unused */ + {UART2_RX, (SAFE_MODE)}, /* unused */ + {UART2_TX, (SAFE_MODE)}, /* unused */ + {HDQ_SIO, (SAFE_MODE)}, /* unused */ {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (PTU | IEN | M1)}, /* uart1_rx */ - {I2C2_SDA, (M1)}, /* uart1_tx */ + {I2C2_SCL, (SAFE_MODE)}, /* unused */ + {I2C2_SDA, (SAFE_MODE)}, /* unused */ {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs1 */ - {MCSPI1_CS2, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs2 */ - {MCSPI1_CS3, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs3 */ + {MCSPI1_CLK, (SAFE_MODE)}, /* unused */ + {MCSPI1_SOMI, (SAFE_MODE)}, /* unused */ + {MCSPI1_SIMO, (SAFE_MODE)}, /* unused */ + {MCSPI1_CS0, (SAFE_MODE)}, /* unused */ + {MCSPI1_CS1, (SAFE_MODE)}, /* unused */ + {MCSPI1_CS2, (SAFE_MODE)}, /* unused */ + {MCSPI1_CS3, (SAFE_MODE)}, /* unused */ {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ @@ -147,82 +147,82 @@ static const struct pad_conf_entry core_padconf_array[] = { {MCSPI4_SIMO, (PTU | IEN | M3)}, /* gpio_152 */ {MCSPI4_SOMI, (PTU | IEN | M3)}, /* gpio_153 */ {MCSPI4_CS0, (SAFE_MODE)}, /* nc */ - {UART4_RX, (IEN | M0)}, /* uart4_rx */ - {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ + {UART4_RX, (SAFE_MODE)}, /* unused */ + {UART4_TX, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_CLK, (SAFE_MODE)}, /* nc */ + {USBB2_ULPITLL_STP, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DIR, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_NXT, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT0, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT1, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT2, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT3, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT4, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT5, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT6, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT7, (SAFE_MODE)}, /* unused */ {USBB2_HSIC_DATA, (SAFE_MODE)}, /* nc */ {USBB2_HSIC_STROBE, (SAFE_MODE)}, /* nc */ - {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ - {UNIPRO_TY2, (SAFE_MODE)}, /* nc */ - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ - {UNIPRO_RY2, (DIS | IEN | M3)}, /* gpio_3 */ + {UNIPRO_TX0, (SAFE_MODE)}, /* unused */ + {UNIPRO_TY0, (SAFE_MODE)}, /* unused */ + {UNIPRO_TX1, (SAFE_MODE)}, /* unused */ + {UNIPRO_TY1, (SAFE_MODE)}, /* unused */ + {UNIPRO_TX2, (SAFE_MODE)}, /* unused */ + {UNIPRO_TY2, (SAFE_MODE)}, /* unused */ + {UNIPRO_RX0, (SAFE_MODE)}, /* unused */ + {UNIPRO_RY0, (SAFE_MODE)}, /* unused */ + {UNIPRO_RX1, (SAFE_MODE)}, /* unused */ + {UNIPRO_RY1, (SAFE_MODE)}, /* unused */ + {UNIPRO_RX2, (SAFE_MODE)}, /* unused */ + {UNIPRO_RY2, (SAFE_MODE)}, /* unused */ {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ {FREF_CLK1_OUT, (SAFE_MODE)}, /* nc */ {FREF_CLK2_OUT, (SAFE_MODE)}, /* nc */ {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (DIS | IEN | M3)}, /* gpio_183 */ - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ - {SYS_BOOT1, (M3)}, /* gpio_185 */ - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (M3)}, /* gpio_187 */ - {SYS_BOOT4, (M3)}, /* gpio_188 */ - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ + {SYS_NIRQ2, (M0)}, /* sys_boot0 */ + {SYS_BOOT0, (M0)}, /* sys_boot */ + {SYS_BOOT1, (M0)}, /* sys_boot */ + {SYS_BOOT2, (M0)}, /* sys_boot */ + {SYS_BOOT3, (M0)}, /* sys_boot */ + {SYS_BOOT4, (M0)}, /* sys_boot */ + {SYS_BOOT5, (M0)}, /* sys_boot */ {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (SAFE_MODE)}, /* nc */ - {DPM_EMU3, (SAFE_MODE)}, /* nc */ - {DPM_EMU4, (SAFE_MODE)}, /* nc */ - {DPM_EMU5, (SAFE_MODE)}, /* nc */ - {DPM_EMU6, (SAFE_MODE)}, /* nc */ - {DPM_EMU7, (SAFE_MODE)}, /* nc */ - {DPM_EMU8, (SAFE_MODE)}, /* nc */ - {DPM_EMU9, (SAFE_MODE)}, /* nc */ - {DPM_EMU10, (SAFE_MODE)}, /* nc */ - {DPM_EMU11, (SAFE_MODE)}, /* nc */ - {DPM_EMU12, (SAFE_MODE)}, /* nc */ - {DPM_EMU13, (SAFE_MODE)}, /* nc */ - {DPM_EMU14, (SAFE_MODE)}, /* nc */ - {DPM_EMU15, (DIS | M3)}, /* gpio_26 */ - {DPM_EMU16, (M1)}, /* dmtimer8_pwm_evt */ - {DPM_EMU17, (M1)}, /* dmtimer9_pwm_evt */ - {DPM_EMU18, (IEN | M3)}, /* gpio_190 */ - {DPM_EMU19, (IEN | M3)}, /* gpio_191 */ + {DPM_EMU2, (SAFE_MODE)}, /* unused */ + {DPM_EMU3, (SAFE_MODE)}, /* unused */ + {DPM_EMU4, (SAFE_MODE)}, /* unused */ + {DPM_EMU5, (SAFE_MODE)}, /* unused */ + {DPM_EMU6, (SAFE_MODE)}, /* unused */ + {DPM_EMU7, (SAFE_MODE)}, /* unused */ + {DPM_EMU8, (SAFE_MODE)}, /* unused */ + {DPM_EMU9, (SAFE_MODE)}, /* unused */ + {DPM_EMU10, (SAFE_MODE)}, /* unused */ + {DPM_EMU11, (SAFE_MODE)}, /* unused */ + {DPM_EMU12, (SAFE_MODE)}, /* unused */ + {DPM_EMU13, (SAFE_MODE)}, /* unused */ + {DPM_EMU14, (SAFE_MODE)}, /* unused */ + {DPM_EMU15, (SAFE_MODE)}, /* unused */ + {DPM_EMU16, (SAFE_MODE)}, /* unused */ + {DPM_EMU17, (SAFE_MODE)}, /* unused */ + {DPM_EMU18, (SAFE_MODE)}, /* unused */ + {DPM_EMU19, (SAFE_MODE)}, /* unused */ }; static const struct pad_conf_entry wkup_padconf_array[] = { - {PAD0_SIM_IO, (IEN | M3)}, /* gpio_wk0 */ - {PAD1_SIM_CLK, (IEN | M3)}, /* gpio_wk1 */ - {PAD0_SIM_RESET, (IEN | M3)}, /* gpio_wk2 */ - {PAD1_SIM_CD, (SAFE_MODE)}, /* should be gpio_wk3 but muxed with gpio_3*/ - {PAD0_SIM_PWRCTRL, (IEN | M3)}, /* gpio_wk4 */ + {PAD0_SIM_IO, (SAFE_MODE)}, /* nc */ + {PAD1_SIM_CLK, (SAFE_MODE)}, /* nc */ + {PAD0_SIM_RESET, (SAFE_MODE)}, /* nc */ + {PAD1_SIM_CD, (SAFE_MODE)}, /* nc */ + {PAD0_SIM_PWRCTRL, (SAFE_MODE)}, /* nc */ {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ {PAD1_FREF_XTAL_IN, (M0)}, /* # */ {PAD0_FREF_SLICER_IN, (SAFE_MODE)}, /* nc */ - {PAD1_FREF_CLK_IOREQ, (SAFE_MODE)}, /* nc */ + {PAD1_FREF_CLK_IOREQ, (SAFE_MODE)}, /* nc */ {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, (SAFE_MODE)}, /* nc */ + {PAD1_FREF_CLK3_REQ, (IEN | M3)}, /* gpio_wk30 */ {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ {PAD1_FREF_CLK4_REQ, (M0)}, /* fref_clk4_req */ {PAD0_FREF_CLK4_OUT, (M0)}, /* fref_clk4_out */ @@ -231,8 +231,8 @@ static const struct pad_conf_entry wkup_padconf_array[] = { {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ {PAD1_SYS_PWRON_RESET, (M0)}, /* sys_pwron_reset_out */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ + {PAD0_SYS_BOOT6, (M0)}, /* sys_boot6 */ + {PAD1_SYS_BOOT7, (M0)}, /* sys_boot7 */ }; void set_muxconf_regs(void) -- 1.7.0.4 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/5] pcm049: Update GPMC net conf 2012-03-15 12:49 [PATCH 1/5] pcm049: Update RAM timings Teresa Gámez 2012-03-15 12:49 ` [PATCH 2/5] pcm049: Update muxing Teresa Gámez @ 2012-03-15 12:49 ` Teresa Gámez 2012-03-15 12:49 ` [PATCH 4/5] devices-gpmc-nand: Add OMAP4 gpmc nand timings Teresa Gámez ` (2 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: Teresa Gámez @ 2012-03-15 12:49 UTC (permalink / raw) To: barebox Updated GPMC settings for ethernet to increase performance. Signed-off-by: Teresa Gámez <t.gamez@phytec.de> --- arch/arm/boards/pcm049/board.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boards/pcm049/board.c b/arch/arm/boards/pcm049/board.c index 826856c..4d52155 100644 --- a/arch/arm/boards/pcm049/board.c +++ b/arch/arm/boards/pcm049/board.c @@ -68,12 +68,12 @@ mem_initcall(pcm049_mem_init); static struct gpmc_config net_cfg = { .cfg = { - 0x00001000, /* CONF1 */ - 0x001e1e01, /* CONF2 */ - 0x00080300, /* CONF3 */ - 0x1c091c09, /* CONF4 */ - 0x04181f1f, /* CONF5 */ - 0x00000FCF, /* CONF6 */ + 0xc1001000, /* CONF1 */ + 0x00070700, /* CONF2 */ + 0x00000000, /* CONF3 */ + 0x07000700, /* CONF4 */ + 0x09060909, /* CONF5 */ + 0x000003c2, /* CONF6 */ }, .base = 0x2C000000, .size = GPMC_SIZE_16M, -- 1.7.0.4 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 4/5] devices-gpmc-nand: Add OMAP4 gpmc nand timings 2012-03-15 12:49 [PATCH 1/5] pcm049: Update RAM timings Teresa Gámez 2012-03-15 12:49 ` [PATCH 2/5] pcm049: Update muxing Teresa Gámez 2012-03-15 12:49 ` [PATCH 3/5] pcm049: Update GPMC net conf Teresa Gámez @ 2012-03-15 12:49 ` Teresa Gámez 2012-03-15 12:49 ` [PATCH 5/5] pcm049_xload_defconfig: activate Thumb-2 support Teresa Gámez 2012-03-15 19:55 ` [PATCH 1/5] pcm049: Update RAM timings Sascha Hauer 4 siblings, 0 replies; 6+ messages in thread From: Teresa Gámez @ 2012-03-15 12:49 UTC (permalink / raw) To: barebox Add a OMAP4 specific GMPC nand config for pcm049 and phyCARD-A-XL2 to increase performance. Also add the possiblility to pass a board GPMC nand config. Signed-off-by: Teresa Gámez <t.gamez@phytec.de> --- arch/arm/boards/beagle/board.c | 3 +- arch/arm/boards/pcm049/board.c | 3 +- arch/arm/boards/phycard-a-l1/pca-a-l1.c | 2 +- arch/arm/boards/phycard-a-xl2/pca-a-xl2.c | 4 +- arch/arm/mach-omap/devices-gpmc-nand.c | 33 ++++---------------------- arch/arm/mach-omap/include/mach/gpmc_nand.h | 6 ++++- arch/arm/mach-omap/omap3_generic.c | 16 +++++++++++++ arch/arm/mach-omap/omap4_generic.c | 16 +++++++++++++ 8 files changed, 49 insertions(+), 34 deletions(-) diff --git a/arch/arm/boards/beagle/board.c b/arch/arm/boards/beagle/board.c index faeaf8e..90525d8 100644 --- a/arch/arm/boards/beagle/board.c +++ b/arch/arm/boards/beagle/board.c @@ -306,7 +306,8 @@ static int beagle_devices_init(void) /* WP is made high and WAIT1 active Low */ gpmc_generic_init(0x10); #endif - gpmc_generic_nand_devices_init(0, 16, OMAP_ECC_HAMMING_CODE_HW_ROMCODE); + gpmc_generic_nand_devices_init(0, 16, + OMAP_ECC_HAMMING_CODE_HW_ROMCODE, &omap3_nand_cfg); add_generic_device("omap-hsmmc", -1, NULL, OMAP_MMC1_BASE, SZ_4K, IORESOURCE_MEM, NULL); diff --git a/arch/arm/boards/pcm049/board.c b/arch/arm/boards/pcm049/board.c index 4d52155..0c82261 100644 --- a/arch/arm/boards/pcm049/board.c +++ b/arch/arm/boards/pcm049/board.c @@ -106,7 +106,8 @@ static int pcm049_devices_init(void) pcm049_network_init(); - gpmc_generic_nand_devices_init(0, 8, OMAP_ECC_BCH8_CODE_HW); + gpmc_generic_nand_devices_init(0, 8, + OMAP_ECC_BCH8_CODE_HW, &omap4_nand_cfg); #ifdef CONFIG_PARTITION devfs_add_partition("nand0", 0x00000, SZ_128K, PARTITION_FIXED, "xload_raw"); diff --git a/arch/arm/boards/phycard-a-l1/pca-a-l1.c b/arch/arm/boards/phycard-a-l1/pca-a-l1.c index e4f2483..3fc3542 100644 --- a/arch/arm/boards/phycard-a-l1/pca-a-l1.c +++ b/arch/arm/boards/phycard-a-l1/pca-a-l1.c @@ -332,7 +332,7 @@ static int pcaal1_late_init(void) { struct device_d *nand; - gpmc_generic_nand_devices_init(0, 16, OMAP_ECC_SOFT); + gpmc_generic_nand_devices_init(0, 16, OMAP_ECC_SOFT, &omap3_nand_cfg); nand = get_device_by_name("nand0"); diff --git a/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c b/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c index 5513661..72fc18f 100644 --- a/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c +++ b/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c @@ -95,7 +95,6 @@ static struct i2c_board_info i2c_devices[] = { }, }; - static struct omap_hsmmc_platform_data mmc_device = { .f_max = 26000000, }; @@ -125,7 +124,8 @@ static int pcaaxl2_devices_init(void) pcaaxl2_network_init(); - gpmc_generic_nand_devices_init(0, 16, OMAP_ECC_BCH8_CODE_HW); + gpmc_generic_nand_devices_init(0, 16, + OMAP_ECC_BCH8_CODE_HW, &omap4_nand_cfg); #ifdef CONFIG_PARTITION devfs_add_partition("nand0", 0x00000, SZ_128K, diff --git a/arch/arm/mach-omap/devices-gpmc-nand.c b/arch/arm/mach-omap/devices-gpmc-nand.c index 197d4be..54625ca 100644 --- a/arch/arm/mach-omap/devices-gpmc-nand.c +++ b/arch/arm/mach-omap/devices-gpmc-nand.c @@ -4,7 +4,6 @@ * * FileName: arch/arm/boards/omap/devices-gpmc-nand.c * - * GPMC NAND Devices such as those from Micron, Samsung are listed here */ /* * (C) Copyright 2006-2008 @@ -39,35 +38,12 @@ #define GPMC_CONF1_VALx8 0x00000800 #define GPMC_CONF1_VALx16 0x00001800 -/* Set up the generic params */ - -/** GPMC timing for our nand device */ -static struct gpmc_config nand_cfg = { - .cfg = { - 0, /*CONF1 */ - 0x00141400, /*CONF2 */ - 0x00141400, /*CONF3 */ - 0x0F010F01, /*CONF4 */ - 0x010C1414, /*CONF5 */ -#ifdef CONFIG_ARCH_OMAP3 - /* Additional bits in OMAP3 */ - 0x1F040000 | -#endif - 0x00000A80, /*CONF6 */ - }, - - /* Nand: dont care about base address */ - .base = 0x28000000, - /* GPMC address map as small as possible */ - .size = GPMC_SIZE_16M, -}; /** NAND platform specific settings settings */ static struct gpmc_nand_platform_data nand_plat = { .cs = 0, .max_timeout = MSECOND, .wait_mon_pin = 0, - .priv = (void *)&nand_cfg, }; /** @@ -76,20 +52,21 @@ static struct gpmc_nand_platform_data nand_plat = { * @return success/fail based on device funtion */ int gpmc_generic_nand_devices_init(int cs, int width, - enum gpmc_ecc_mode eccmode) + enum gpmc_ecc_mode eccmode, struct gpmc_config *nand_cfg) { nand_plat.cs = cs; if (width == 16) - nand_cfg.cfg[0] = GPMC_CONF1_VALx16; + nand_cfg->cfg[0] = GPMC_CONF1_VALx16; else - nand_cfg.cfg[0] = GPMC_CONF1_VALx8; + nand_cfg->cfg[0] = GPMC_CONF1_VALx8; nand_plat.device_width = width; nand_plat.ecc_mode = eccmode; + nand_plat.priv = nand_cfg; /* Configure GPMC CS before register */ - gpmc_cs_config(nand_plat.cs, &nand_cfg); + gpmc_cs_config(nand_plat.cs, nand_cfg); add_generic_device("gpmc_nand", -1, NULL, OMAP_GPMC_BASE, 1024 * 4, IORESOURCE_MEM, &nand_plat); diff --git a/arch/arm/mach-omap/include/mach/gpmc_nand.h b/arch/arm/mach-omap/include/mach/gpmc_nand.h index 1bc52ff..b9c659d 100644 --- a/arch/arm/mach-omap/include/mach/gpmc_nand.h +++ b/arch/arm/mach-omap/include/mach/gpmc_nand.h @@ -78,6 +78,10 @@ struct gpmc_nand_platform_data { #define NAND_WAITPOL_HIGH (1 << 0) #define NAND_WAITPOL_MASK (1 << 0) -int gpmc_generic_nand_devices_init(int cs, int width, enum gpmc_ecc_mode); +int gpmc_generic_nand_devices_init(int cs, int width, + enum gpmc_ecc_mode, struct gpmc_config *nand_cfg); + +extern struct gpmc_config omap3_nand_cfg; +extern struct gpmc_config omap4_nand_cfg; #endif /* __ASM_OMAP_NAND_GPMC_H */ diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c index fe7363a..4ab265a 100644 --- a/arch/arm/mach-omap/omap3_generic.c +++ b/arch/arm/mach-omap/omap3_generic.c @@ -499,3 +499,19 @@ enum omap_boot_src omap3_bootsrc(void) return OMAP_BOOTSRC_MMC1; return OMAP_BOOTSRC_UNKNOWN; } + +/* GPMC timing for OMAP3 nand device */ +const struct gpmc_config omap3_nand_cfg = { + .cfg = { + 0x00000000, /* CONF1 */ + 0x00141400, /* CONF2 */ + 0x00141400, /* CONF3 */ + 0x0F010F01, /* CONF4 */ + 0x010C1414, /* CONF5 */ + 0x1F040000 | + 0x00000A80, /* CONF6 */ + }, + /* GPMC address map as small as possible */ + .base = 0x28000000, + .size = GPMC_SIZE_16M, +}; diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c index baa138d..db26a59 100644 --- a/arch/arm/mach-omap/omap4_generic.c +++ b/arch/arm/mach-omap/omap4_generic.c @@ -7,6 +7,7 @@ #include <mach/omap4-clock.h> #include <mach/syslib.h> #include <mach/xload.h> +#include <mach/gpmc.h> void __noreturn reset_cpu(unsigned long addr) { @@ -460,3 +461,18 @@ void omap4_do_set_mux(u32 base, struct pad_conf_entry const *array, int size) for (i = 0; i < size; i++, pad++) writew(pad->val, base + pad->offset); } + +/* GPMC timing for OMAP4 nand device */ +const struct gpmc_config omap4_nand_cfg = { + .cfg = { + 0x00000800, /* CONF1 */ + 0x00050500, /* CONF2 */ + 0x00040400, /* CONF3 */ + 0x03000300, /* CONF4 */ + 0x00050808, /* CONF5 */ + 0x00000000, /* CONF6 */ + }, + /* GPMC address map as small as possible */ + .base = 0x28000000, + .size = GPMC_SIZE_16M, +}; -- 1.7.0.4 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 5/5] pcm049_xload_defconfig: activate Thumb-2 support 2012-03-15 12:49 [PATCH 1/5] pcm049: Update RAM timings Teresa Gámez ` (2 preceding siblings ...) 2012-03-15 12:49 ` [PATCH 4/5] devices-gpmc-nand: Add OMAP4 gpmc nand timings Teresa Gámez @ 2012-03-15 12:49 ` Teresa Gámez 2012-03-15 19:55 ` [PATCH 1/5] pcm049: Update RAM timings Sascha Hauer 4 siblings, 0 replies; 6+ messages in thread From: Teresa Gámez @ 2012-03-15 12:49 UTC (permalink / raw) To: barebox To reduce the size of the MLO we have to activate thumb-2 support. Otherwise the board will not boot. Signed-off-by: Teresa Gámez <t.gamez@phytec.de> --- arch/arm/configs/pcm049_xload_defconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/configs/pcm049_xload_defconfig b/arch/arm/configs/pcm049_xload_defconfig index bf30941..b6d3a7a 100644 --- a/arch/arm/configs/pcm049_xload_defconfig +++ b/arch/arm/configs/pcm049_xload_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_OMAP4=y CONFIG_OMAP_BUILD_IFT=y CONFIG_MACH_PCM049=y CONFIG_AEABI=y +CONFIG_THUMB2_BAREBOX=y # CONFIG_CMD_ARM_CPUINFO is not set # CONFIG_ARM_EXCEPTIONS is not set CONFIG_MMU=y -- 1.7.0.4 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/5] pcm049: Update RAM timings 2012-03-15 12:49 [PATCH 1/5] pcm049: Update RAM timings Teresa Gámez ` (3 preceding siblings ...) 2012-03-15 12:49 ` [PATCH 5/5] pcm049_xload_defconfig: activate Thumb-2 support Teresa Gámez @ 2012-03-15 19:55 ` Sascha Hauer 4 siblings, 0 replies; 6+ messages in thread From: Sascha Hauer @ 2012-03-15 19:55 UTC (permalink / raw) To: Teresa Gámez; +Cc: barebox On Thu, Mar 15, 2012 at 01:49:23PM +0100, Teresa Gámez wrote: > Updated RAM Timings for phyCORE-OMAP4. > > Signed-off-by: Teresa Gámez <t.gamez@phytec.de> Applied this series, thanks Sascha > --- > arch/arm/boards/pcm049/lowlevel.c | 27 +++++++++++++-------------- > 1 files changed, 13 insertions(+), 14 deletions(-) > > diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c > index 444a394..5b91098 100644 > --- a/arch/arm/boards/pcm049/lowlevel.c > +++ b/arch/arm/boards/pcm049/lowlevel.c > @@ -30,23 +30,22 @@ > > void set_muxconf_regs(void); > > -/* Erstmal 200Mhz... */ > -static const struct ddr_regs ddr_regs_mt42L64M64_3_200_mhz = { > - .tim1 = 0x0aa8d4e3, > - .tim2 = 0x202e0b92, > - .tim3 = 0x009da2b3, > - .phy_ctrl_1 = 0x849FF404, /* mostly from elpida */ > - .ref_ctrl = 0x0000030c, /* from elpida 200MHz! */ > - .config_init = 0x80000eb1, > - .config_final = 0x80000eb1, > - .zq_config = 0x500b3215, /* mostly from elpida */ > - .mr1 = 0x23, /* from elpida 200MHz! */ > - .mr2 = 0x1 /* from elpida 200MHz! */ > +static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { > + .tim1 = 0x0EEB0662, > + .tim2 = 0x20370DD2, > + .tim3 = 0x00BFC33F, > + .phy_ctrl_1 = 0x849FF408, > + .ref_ctrl = 0x00000618, > + .config_init = 0x80001AB1, > + .config_final = 0x80001AB1, > + .zq_config = 0xd0093215, > + .mr1 = 0x83, > + .mr2 = 0x4 > }; > > static void noinline pcm049_init_lowlevel(void) > { > - struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR200; > + struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; > struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; > struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2; > struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2; > @@ -55,7 +54,7 @@ static void noinline pcm049_init_lowlevel(void) > > set_muxconf_regs(); > > - omap4_ddr_init(&ddr_regs_mt42L64M64_3_200_mhz, &core); > + omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); > > /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ > omap4_scale_vcores(); > -- > 1.7.0.4 > > > _______________________________________________ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2012-03-15 19:55 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2012-03-15 12:49 [PATCH 1/5] pcm049: Update RAM timings Teresa Gámez 2012-03-15 12:49 ` [PATCH 2/5] pcm049: Update muxing Teresa Gámez 2012-03-15 12:49 ` [PATCH 3/5] pcm049: Update GPMC net conf Teresa Gámez 2012-03-15 12:49 ` [PATCH 4/5] devices-gpmc-nand: Add OMAP4 gpmc nand timings Teresa Gámez 2012-03-15 12:49 ` [PATCH 5/5] pcm049_xload_defconfig: activate Thumb-2 support Teresa Gámez 2012-03-15 19:55 ` [PATCH 1/5] pcm049: Update RAM timings Sascha Hauer
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