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From: Alexander Shiyan <shc_work@mail.ru>
To: barebox@lists.infradead.org
Subject: [PATCH] i.MX51: Raise frequency for SDHC by switch to PLL2 source
Date: Thu, 24 May 2012 12:44:29 +0400	[thread overview]
Message-ID: <1337849069-1893-1-git-send-email-shc_work@mail.ru> (raw)

Currently, both SDHC clock source is PLL3. We can raise clock
for SDHC driver by change source from PLL3 to PLL2.
Below, is debug ouputs with old and new settings.

Detection (PLL3):
set clock: wanted: 400000 got: 375000
Operation (PLL3):
set clock: wanted: 25000000 got: 18000000
Operation SD4.0 (PLL3):
set clock: wanted: 52000000 got: 27000000

Detection (PLL2):
set clock: wanted: 400000 got: 399639
Operation (PLL2):
set clock: wanted: 25000000 got: 23750000
Operation SD4.0 (PLL2):
set clock: wanted: 52000000 got: 41562500

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/mach-imx/imx51.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index 25cc6da..53205a9 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -269,7 +269,7 @@ void imx51_init_lowlevel(unsigned int cpufreq_mhz)
 	writel(0xffffffff, ccm + MX5_CCM_CCGR6);
 
 	/* Use PLL 2 for UART's, get 66.5MHz from it */
-	writel(0xA5A2A020, ccm + MX5_CCM_CSCMR1);
+	writel(0xA591A020, ccm + MX5_CCM_CSCMR1);
 	writel(0x00C30321, ccm + MX5_CCM_CSCDR1);
 
 	/* make sure divider effective */
-- 
1.7.3.4


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             reply	other threads:[~2012-05-24  8:44 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-05-24  8:44 Alexander Shiyan [this message]
2012-05-25  6:41 ` Sascha Hauer

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