From: Jan Weitzel <j.weitzel@phytec.de>
To: barebox@lists.infradead.org
Subject: [PATCH 2/3] OMAP4460: ram init changes
Date: Fri, 27 Jul 2012 15:40:03 +0200 [thread overview]
Message-ID: <1343396404-10288-3-git-send-email-j.weitzel@phytec.de> (raw)
In-Reply-To: <1343396404-10288-1-git-send-email-j.weitzel@phytec.de>
configure Memory Adapter for 4460
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
---
arch/arm/mach-omap/include/mach/omap4-silicon.h | 4 ++++
arch/arm/mach-omap/omap4_generic.c | 21 +++++++++++++++++++--
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
index d5517c5..4082bac 100644
--- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
@@ -101,6 +101,10 @@
#define DMM_LISA_MAP_SYS_SIZE_MASK (7 << 20)
#define DMM_LISA_MAP_SYS_SIZE_SHIFT 20
#define DMM_LISA_MAP_SYS_ADDR_MASK (0xFF << 24)
+
+/* Memory Adapter (4460 onwards) */
+#define OMAP44XX_MA_BASE 0x482AF000
+
/*
* Hardware Register Details
*/
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index 07aa2b4..a368759 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -29,6 +29,10 @@
#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
+/* EMIF_L3_CONFIG register value */
+#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF
+#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000
+
void __noreturn reset_cpu(unsigned long addr)
{
writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
@@ -270,8 +274,7 @@ static void reset_phy(unsigned int base)
void omap4_ddr_init(const struct ddr_regs *ddr_regs,
const struct dpll_param *core)
{
- unsigned int rev;
- rev = omap4_revision();
+ unsigned int rev = omap4_revision();
if (rev == OMAP4430_ES2_0) {
writel(0x9e9e9e9e, 0x4A100638);
@@ -294,6 +297,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_2) = 0x00000000;
*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100;
+ if (rev >= OMAP4460_ES1_0) {
+ writel(0x80640300, OMAP44XX_MA_BASE + DMM_LISA_MAP_0);
+
+ *(volatile int*)(OMAP44XX_MA_BASE + DMM_LISA_MAP_2) = 0x00000000;
+ *(volatile int*)(OMAP44XX_MA_BASE + DMM_LISA_MAP_3) = 0xFF020100;
+ }
+
/* DDR needs to be initialised @ 19.2 MHz
* So put core DPLL in bypass mode
* Configure the Core DPLL but don't lock it
@@ -336,6 +346,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
+ if (rev >= OMAP4460_ES1_0) {
+ writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
+ OMAP44XX_EMIF1_BASE + EMIF_L3_CONFIG);
+ writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
+ OMAP44XX_EMIF2_BASE + EMIF_L3_CONFIG);
+ }
+
/*
* DMM : DMM_LISA_MAP_0(Section_0)
* [31:24] SYS_ADDR 0x80
--
1.7.0.4
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next prev parent reply other threads:[~2012-07-27 13:40 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-27 13:40 [PATCH 0/3] omap: 4460 support Jan Weitzel
2012-07-27 13:40 ` [PATCH 1/3] Add support for OMAP4460 TPS62361 Jan Weitzel
2012-08-03 16:57 ` Sascha Hauer
2012-08-13 6:07 ` [PATCH 3/3] OMAP4460: clock init Jan Weitzel
2012-08-13 19:08 ` Sascha Hauer
2012-07-27 13:40 ` Jan Weitzel [this message]
2012-07-27 14:13 ` [PATCH 2/3] OMAP4460: ram init changes Jean-Christophe PLAGNIOL-VILLARD
2012-07-27 15:12 ` Sascha Hauer
2012-08-02 10:55 ` [PATCH] OMAP4: use writel and readl Jan Weitzel
2012-08-13 12:32 ` [PATCH v2] " Jan Weitzel
2012-08-13 18:42 ` Sascha Hauer
2012-07-27 13:40 ` [PATCH 3/3] OMAP4460: clock init Jan Weitzel
2012-07-27 14:18 ` Jean-Christophe PLAGNIOL-VILLARD
2012-08-02 10:36 ` Jan Weitzel
2012-08-14 7:04 [PATCH 0/3 v2] omap: 4460 support Jan Weitzel
2012-08-14 7:04 ` [PATCH 2/3] OMAP4460: ram init changes Jan Weitzel
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