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From: Sascha Hauer <s.hauer@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH 1/4] ARM __mmu_cache_*: Do not clobber registers
Date: Sun, 12 Aug 2012 16:30:29 +0200	[thread overview]
Message-ID: <1344781832-17978-2-git-send-email-s.hauer@pengutronix.de> (raw)
In-Reply-To: <1344781832-17978-1-git-send-email-s.hauer@pengutronix.de>

Save/restore the registers used in __mmu_cache_* so that they can
be called as regular C functions.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/cpu/cache-armv4.S |    3 ++-
 arch/arm/cpu/cache-armv7.S |    6 ++++--
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S
index 2231eee..22fab14 100644
--- a/arch/arm/cpu/cache-armv4.S
+++ b/arch/arm/cpu/cache-armv4.S
@@ -46,6 +46,7 @@ ENDPROC(__mmu_cache_off)
 
 .section .text.__mmu_cache_flush
 ENTRY(__mmu_cache_flush)
+		stmfd	sp!, {r6, r11, lr}
 		mrc	p15, 0, r6, c0, c0	@ get processor ID
 		mov	r2, #64*1024		@ default: 32K dcache size (*2)
 		mov	r11, #32		@ default: 32 byte line size
@@ -74,7 +75,7 @@ no_cache_id:
 		mcr	p15, 0, r1, c7, c5, 0	@ flush I cache
 		mcr	p15, 0, r1, c7, c6, 0	@ flush D cache
 		mcr	p15, 0, r1, c7, c10, 4	@ drain WB
-		mov	pc, lr
+		ldmfd	sp!, {r6, r11, pc}
 ENDPROC(__mmu_cache_flush)
 
 /*
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index 9bd7425..2eba959 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -3,6 +3,7 @@
 
 .section .text.__mmu_cache_on
 ENTRY(__mmu_cache_on)
+		stmfd	sp!, {r11, lr}
 		mov	r12, lr
 #ifdef CONFIG_MMU
 		mrc	p15, 0, r11, c0, c1, 4	@ read ID_MMFR0
@@ -28,7 +29,7 @@ ENTRY(__mmu_cache_on)
 		mrc	p15, 0, r0, c1, c0, 0	@ and read it back
 		mov	r0, #0
 		mcr	p15, 0, r0, c7, c5, 4	@ ISB
-		mov	pc, r12
+		ldmfd	sp!, {r11, pc}
 ENDPROC(__mmu_cache_on)
 
 .section .text.__mmu_cache_off
@@ -54,6 +55,7 @@ ENDPROC(__mmu_cache_off)
 
 .section .text.__mmu_cache_flush
 ENTRY(__mmu_cache_flush)
+		stmfd	sp!, {r10, lr}
 		mrc	p15, 0, r10, c0, c1, 5	@ read ID_MMFR1
 		tst	r10, #0xf << 16		@ hierarchical cache (ARMv7)
 		mov	r10, #0
@@ -111,7 +113,7 @@ iflush:
 		mcr	p15, 0, r10, c7, c5, 0	@ invalidate I+BTB
 		mcr	p15, 0, r10, c7, c10, 4	@ DSB
 		mcr	p15, 0, r10, c7, c5, 4	@ ISB
-		mov	pc, lr
+		ldmfd	sp!, {r10, pc}
 ENDPROC(__mmu_cache_flush)
 
 /*
-- 
1.7.10.4


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  reply	other threads:[~2012-08-12 14:30 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-08-12 14:30 [PATCH] ARM: enable MMU in pbl Sascha Hauer
2012-08-12 14:30 ` Sascha Hauer [this message]
2012-08-12 14:30 ` [PATCH 2/4] ARM MMU: call __mmu_cache_* as regular C functions Sascha Hauer
2012-08-12 14:30 ` [PATCH 3/4] ARM pbl: enable MMU during decompression Sascha Hauer
2012-08-12 18:09   ` Jean-Christophe PLAGNIOL-VILLARD
2012-08-13 18:29     ` Sascha Hauer
2012-09-21 13:18       ` Jean-Christophe PLAGNIOL-VILLARD
2012-08-12 14:30 ` [PATCH 4/4] create a common ARM flush_icache function Sascha Hauer
2012-09-20 18:52 ` [PATCH] ARM: enable MMU in pbl Jean-Christophe PLAGNIOL-VILLARD
2012-09-20 19:56   ` Sascha Hauer
2012-09-21 13:23     ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-21 14:46       ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-22 10:21         ` Sascha Hauer
2012-09-22 11:41           ` Jean-Christophe PLAGNIOL-VILLARD

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