[PATCH 0/5] at91 framebuffer support

[PATCH 0/5] at91 framebuffer support

[Jean-Christophe PLAGNIOL-VILLARD]

Hi,

	The following patch serie add the support of the Framebuffer on at91
	sam9261/sam9263 and sam9g45. The sam9x5 series is not yet supported as
	they use an other IP.

	And enable it on sam0m10g45ek (9263ek and 9261ek will be availlable
	later).

	This is based on the next branch

The following changes since commit 6392955f283389fa4fecb0e2d5d1837bcb83f480:

  Merge branch 'for-next/testing-menu' into next (2012-09-20 23:11:42 +0200)

are available in the git repository at:


  git://git.jcrosoft.org/barebox.git delivery/atmel_fb

for you to fetch changes up to a60a81609fdc332ca8b84d2b8633dc59f8aacbc8:

  at91sam9m10g45ek: add lcdc support (2012-09-21 20:49:25 +0800)

----------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD (5):
      video: add atmel lcdc frambuffer support
      at91sam9263: add atmel lcdc frambuffer support
      at91sam9261: add atmel lcdc frambuffer support
      at91sam9g45: add atmel lcdc frambuffer support
      at91sam9m10g45ek: add lcdc support

 arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board |    7 +++
 arch/arm/boards/at91sam9m10g45ek/env/splash.png     |  Bin 0 -> 22747 bytes
 arch/arm/boards/at91sam9m10g45ek/init.c             |   35 +++++++++++++
 arch/arm/configs/at91sam9m10g45ek_defconfig         |   11 ++--
 arch/arm/mach-at91/at91sam9261.c                    |    1 +
 arch/arm/mach-at91/at91sam9261_devices.c            |   51 ++++++++++++++++++
 arch/arm/mach-at91/at91sam9263.c                    |    1 +
 arch/arm/mach-at91/at91sam9263_devices.c            |   40 +++++++++++++++
 arch/arm/mach-at91/at91sam9g45.c                    |    1 +
 arch/arm/mach-at91/at91sam9g45_devices.c            |   49 ++++++++++++++++++
 arch/arm/mach-at91/include/mach/atmel_lcdc.h        |  209 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-at91/include/mach/board.h             |    4 ++
 drivers/video/Kconfig                               |    4 ++
 drivers/video/Makefile                              |    1 +
 drivers/video/atmel_lcdfb.c                         |  477 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 15 files changed, 888 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/boards/at91sam9m10g45ek/env/splash.png
 create mode 100644 arch/arm/mach-at91/include/mach/atmel_lcdc.h
 create mode 100644 drivers/video/atmel_lcdfb.c

Best Regards,
J.

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[PATCH 1/5] video: add atmel lcdc frambuffer support

[Jean-Christophe PLAGNIOL-VILLARD]

This IP is present on the at91sam9 until the sam9g45, on the sam9x5 we use a
new IP.

This driver is based on the linux one.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/mach-at91/include/mach/atmel_lcdc.h |  209 +++++++++++
 arch/arm/mach-at91/include/mach/board.h      |    4 +
 drivers/video/Kconfig                        |    4 +
 drivers/video/Makefile                       |    1 +
 drivers/video/atmel_lcdfb.c                  |  477 ++++++++++++++++++++++++++
 5 files changed, 695 insertions(+)
 create mode 100644 arch/arm/mach-at91/include/mach/atmel_lcdc.h
 create mode 100644 drivers/video/atmel_lcdfb.c

diff --git a/arch/arm/mach-at91/include/mach/atmel_lcdc.h b/arch/arm/mach-at91/include/mach/atmel_lcdc.h
new file mode 100644
index 0000000..a85e4b8
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/atmel_lcdc.h
@@ -0,0 +1,209 @@
+/*
+ *  Header file for AT91/AT32 LCD Controller
+ *
+ *  Data structure and register user interface
+ *
+ *  Copyright (C) 2007 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ATMEL_LCDC_H__
+#define __ATMEL_LCDC_H__
+
+/* Way LCD wires are connected to the chip:
+ * Some Atmel chips use BGR color mode (instead of standard RGB)
+ * A swapped wiring onboard can bring to RGB mode.
+ */
+#define ATMEL_LCDC_WIRING_BGR	0
+#define ATMEL_LCDC_WIRING_RGB	1
+#define ATMEL_LCDC_WIRING_RGB555	2
+
+
+ /* LCD Controller info data structure, stored in device platform_data */
+struct atmel_lcdfb_info {
+	struct fb_info		info;
+	void __iomem		*mmio;
+	struct device_d		*device;
+
+	unsigned int		guard_time;
+	unsigned int 		smem_len;
+	struct clk		*bus_clk;
+	struct clk		*lcdc_clk;
+
+	bool			lcdcon_is_backlight;
+	bool			lcdcon_pol_negative;
+	u8			saved_lcdcon;
+
+	u8			default_bpp;
+	u8			lcd_wiring_mode;
+	unsigned int		default_lcdcon2;
+	unsigned int		default_dmacon;
+	void (*atmel_lcdfb_power_control)(int on);
+	u32			pseudo_palette[16];
+};
+
+#define ATMEL_LCDC_DMABADDR1	0x00
+#define ATMEL_LCDC_DMABADDR2	0x04
+#define ATMEL_LCDC_DMAFRMPT1	0x08
+#define ATMEL_LCDC_DMAFRMPT2	0x0c
+#define ATMEL_LCDC_DMAFRMADD1	0x10
+#define ATMEL_LCDC_DMAFRMADD2	0x14
+
+#define ATMEL_LCDC_DMAFRMCFG	0x18
+#define	ATMEL_LCDC_FRSIZE	(0x7fffff <<  0)
+#define	ATMEL_LCDC_BLENGTH_OFFSET	24
+#define	ATMEL_LCDC_BLENGTH	(0x7f     << ATMEL_LCDC_BLENGTH_OFFSET)
+
+#define ATMEL_LCDC_DMACON	0x1c
+#define	ATMEL_LCDC_DMAEN	(0x1 << 0)
+#define	ATMEL_LCDC_DMARST	(0x1 << 1)
+#define	ATMEL_LCDC_DMABUSY	(0x1 << 2)
+#define		ATMEL_LCDC_DMAUPDT	(0x1 << 3)
+#define		ATMEL_LCDC_DMA2DEN	(0x1 << 4)
+
+#define ATMEL_LCDC_DMA2DCFG	0x20
+#define		ATMEL_LCDC_ADDRINC_OFFSET	0
+#define		ATMEL_LCDC_ADDRINC		(0xffff)
+#define		ATMEL_LCDC_PIXELOFF_OFFSET	24
+#define		ATMEL_LCDC_PIXELOFF		(0x1f << 24)
+
+#define ATMEL_LCDC_LCDCON1	0x0800
+#define	ATMEL_LCDC_BYPASS	(1     <<  0)
+#define	ATMEL_LCDC_CLKVAL_OFFSET	12
+#define	ATMEL_LCDC_CLKVAL	(0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
+#define	ATMEL_LCDC_LINCNT	(0x7ff << 21)
+
+#define ATMEL_LCDC_LCDCON2	0x0804
+#define	ATMEL_LCDC_DISTYPE	(3 << 0)
+#define		ATMEL_LCDC_DISTYPE_STNMONO	(0 << 0)
+#define		ATMEL_LCDC_DISTYPE_STNCOLOR	(1 << 0)
+#define		ATMEL_LCDC_DISTYPE_TFT		(2 << 0)
+#define	ATMEL_LCDC_SCANMOD	(1 << 2)
+#define		ATMEL_LCDC_SCANMOD_SINGLE	(0 << 2)
+#define		ATMEL_LCDC_SCANMOD_DUAL		(1 << 2)
+#define	ATMEL_LCDC_IFWIDTH	(3 << 3)
+#define		ATMEL_LCDC_IFWIDTH_4		(0 << 3)
+#define		ATMEL_LCDC_IFWIDTH_8		(1 << 3)
+#define		ATMEL_LCDC_IFWIDTH_16		(2 << 3)
+#define	ATMEL_LCDC_PIXELSIZE	(7 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_1		(0 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_2		(1 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_4		(2 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_8		(3 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_16		(4 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_24		(5 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_32		(6 << 5)
+#define	ATMEL_LCDC_INVVD	(1 << 8)
+#define		ATMEL_LCDC_INVVD_NORMAL		(0 << 8)
+#define		ATMEL_LCDC_INVVD_INVERTED	(1 << 8)
+#define	ATMEL_LCDC_INVFRAME	(1 << 9 )
+#define		ATMEL_LCDC_INVFRAME_NORMAL	(0 << 9)
+#define		ATMEL_LCDC_INVFRAME_INVERTED	(1 << 9)
+#define	ATMEL_LCDC_INVLINE	(1 << 10)
+#define		ATMEL_LCDC_INVLINE_NORMAL	(0 << 10)
+#define		ATMEL_LCDC_INVLINE_INVERTED	(1 << 10)
+#define	ATMEL_LCDC_INVCLK	(1 << 11)
+#define		ATMEL_LCDC_INVCLK_NORMAL	(0 << 11)
+#define		ATMEL_LCDC_INVCLK_INVERTED	(1 << 11)
+#define	ATMEL_LCDC_INVDVAL	(1 << 12)
+#define		ATMEL_LCDC_INVDVAL_NORMAL	(0 << 12)
+#define		ATMEL_LCDC_INVDVAL_INVERTED	(1 << 12)
+#define	ATMEL_LCDC_CLKMOD	(1 << 15)
+#define		ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY	(0 << 15)
+#define		ATMEL_LCDC_CLKMOD_ALWAYSACTIVE	(1 << 15)
+#define	ATMEL_LCDC_MEMOR	(1 << 31)
+#define		ATMEL_LCDC_MEMOR_BIG		(0 << 31)
+#define		ATMEL_LCDC_MEMOR_LITTLE		(1 << 31)
+
+#define ATMEL_LCDC_TIM1		0x0808
+#define	ATMEL_LCDC_VFP		(0xffU <<  0)
+#define	ATMEL_LCDC_VBP_OFFSET		8
+#define	ATMEL_LCDC_VBP		(0xffU <<  ATMEL_LCDC_VBP_OFFSET)
+#define	ATMEL_LCDC_VPW_OFFSET		16
+#define	ATMEL_LCDC_VPW		(0x3fU << ATMEL_LCDC_VPW_OFFSET)
+#define	ATMEL_LCDC_VHDLY_OFFSET		24
+#define	ATMEL_LCDC_VHDLY	(0xfU  << ATMEL_LCDC_VHDLY_OFFSET)
+
+#define ATMEL_LCDC_TIM2		0x080c
+#define	ATMEL_LCDC_HBP		(0xffU  <<  0)
+#define	ATMEL_LCDC_HPW_OFFSET		8
+#define	ATMEL_LCDC_HPW		(0x3fU  <<  ATMEL_LCDC_HPW_OFFSET)
+#define	ATMEL_LCDC_HFP_OFFSET		21
+#define	ATMEL_LCDC_HFP		(0x7ffU << ATMEL_LCDC_HFP_OFFSET)
+
+#define ATMEL_LCDC_LCDFRMCFG	0x0810
+#define	ATMEL_LCDC_LINEVAL	(0x7ff <<  0)
+#define	ATMEL_LCDC_HOZVAL_OFFSET	21
+#define	ATMEL_LCDC_HOZVAL	(0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
+
+#define ATMEL_LCDC_FIFO		0x0814
+#define	ATMEL_LCDC_FIFOTH	(0xffff)
+
+#define ATMEL_LCDC_MVAL		0x0818
+
+#define ATMEL_LCDC_DP1_2	0x081c
+#define ATMEL_LCDC_DP4_7	0x0820
+#define ATMEL_LCDC_DP3_5	0x0824
+#define ATMEL_LCDC_DP2_3	0x0828
+#define ATMEL_LCDC_DP5_7	0x082c
+#define ATMEL_LCDC_DP3_4	0x0830
+#define ATMEL_LCDC_DP4_5	0x0834
+#define ATMEL_LCDC_DP6_7	0x0838
+#define	ATMEL_LCDC_DP1_2_VAL	(0xff)
+#define	ATMEL_LCDC_DP4_7_VAL	(0xfffffff)
+#define	ATMEL_LCDC_DP3_5_VAL	(0xfffff)
+#define	ATMEL_LCDC_DP2_3_VAL	(0xfff)
+#define	ATMEL_LCDC_DP5_7_VAL	(0xfffffff)
+#define	ATMEL_LCDC_DP3_4_VAL	(0xffff)
+#define	ATMEL_LCDC_DP4_5_VAL	(0xfffff)
+#define	ATMEL_LCDC_DP6_7_VAL	(0xfffffff)
+
+#define ATMEL_LCDC_PWRCON	0x083c
+#define	ATMEL_LCDC_PWR		(1    <<  0)
+#define	ATMEL_LCDC_GUARDT_OFFSET	1
+#define	ATMEL_LCDC_GUARDT	(0x7f <<  ATMEL_LCDC_GUARDT_OFFSET)
+#define	ATMEL_LCDC_BUSY		(1    << 31)
+
+#define ATMEL_LCDC_CONTRAST_CTR	0x0840
+#define	ATMEL_LCDC_PS		(3 << 0)
+#define		ATMEL_LCDC_PS_DIV1		(0 << 0)
+#define		ATMEL_LCDC_PS_DIV2		(1 << 0)
+#define		ATMEL_LCDC_PS_DIV4		(2 << 0)
+#define		ATMEL_LCDC_PS_DIV8		(3 << 0)
+#define	ATMEL_LCDC_POL		(1 << 2)
+#define		ATMEL_LCDC_POL_NEGATIVE		(0 << 2)
+#define		ATMEL_LCDC_POL_POSITIVE		(1 << 2)
+#define	ATMEL_LCDC_ENA		(1 << 3)
+#define		ATMEL_LCDC_ENA_PWMDISABLE	(0 << 3)
+#define		ATMEL_LCDC_ENA_PWMENABLE	(1 << 3)
+
+#define ATMEL_LCDC_CONTRAST_VAL	0x0844
+#define	ATMEL_LCDC_CVAL	(0xff)
+
+#define ATMEL_LCDC_IER		0x0848
+#define ATMEL_LCDC_IDR		0x084c
+#define ATMEL_LCDC_IMR		0x0850
+#define ATMEL_LCDC_ISR		0x0854
+#define ATMEL_LCDC_ICR		0x0858
+#define	ATMEL_LCDC_LNI		(1 << 0)
+#define	ATMEL_LCDC_LSTLNI	(1 << 1)
+#define	ATMEL_LCDC_EOFI		(1 << 2)
+#define	ATMEL_LCDC_UFLWI	(1 << 4)
+#define	ATMEL_LCDC_OWRI		(1 << 5)
+#define	ATMEL_LCDC_MERI		(1 << 6)
+
+#define ATMEL_LCDC_LUT(n)	(0x0c00 + ((n)*4))
+
+#endif /* __ATMEL_LCDC_H__ */
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 670c73d..a720a36 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -23,6 +23,8 @@
 #include <net.h>
 #include <spi/spi.h>
 #include <linux/mtd/mtd.h>
+#include <fb.h>
+#include <mach/atmel_lcdc.h>
 
  /* USB Host */
 struct at91_usbh_data {
@@ -154,4 +156,6 @@ struct at91_spi_platform_data {
 };
 
 void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata);
+
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
 #endif
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 519cdbf..38dbb7a 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -5,6 +5,10 @@ menuconfig VIDEO
 
 if VIDEO
 
+config DRIVER_VIDEO_ATMEL
+	bool "Atmel LCDC framebuffer driver"
+	depends on ARCH_AT91
+
 config DRIVER_VIDEO_IMX
 	bool "i.MX framebuffer driver"
 	depends on ARCH_IMX1 || ARCH_IMX21 || ARCH_IMX25 || ARCH_IMX27
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 913c78d..dcadcf6 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_DRIVER_VIDEO_IMX) += imx.o
 obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
 obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
 obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
+obj-$(CONFIG_DRIVER_VIDEO_ATMEL) += atmel_lcdfb.o
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
new file mode 100644
index 0000000..8659836
--- /dev/null
+++ b/drivers/video/atmel_lcdfb.c
@@ -0,0 +1,477 @@
+/*
+ * Driver for AT91/AT32 LCD Controller
+ *
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <io.h>
+#include <init.h>
+#include <linux/clk.h>
+#include <fb.h>
+#include <mach/atmel_lcdc.h>
+#include <mach/hardware.h>
+#include <mach/io.h>
+#include <mach/cpu.h>
+#include <errno.h>
+#include <linux/err.h>
+#include <malloc.h>
+#include <asm/mmu.h>
+
+#define lcdc_readl(sinfo, reg)		__raw_readl((sinfo)->mmio+(reg))
+#define lcdc_writel(sinfo, reg, val)	__raw_writel((val), (sinfo)->mmio+(reg))
+
+/* configurable parameters */
+#define ATMEL_LCDC_CVAL_DEFAULT		0xc8
+#define ATMEL_LCDC_DMA_BURST_LEN	8	/* words */
+#define ATMEL_LCDC_FIFO_SIZE		512	/* words */
+
+static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
+{
+	clk_enable(sinfo->bus_clk);
+	clk_enable(sinfo->lcdc_clk);
+}
+
+static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
+{
+	clk_disable(sinfo->bus_clk);
+	clk_disable(sinfo->lcdc_clk);
+}
+
+static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
+{
+	unsigned long value;
+
+	if (!(cpu_is_at91sam9261() || cpu_is_at91sam9g10()
+		|| cpu_is_at32ap7000()))
+		return xres;
+
+	value = xres;
+	if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
+		/* STN display */
+		if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR)
+			value *= 3;
+
+		if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
+		   || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
+		      && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
+			value = DIV_ROUND_UP(value, 4);
+		else
+			value = DIV_ROUND_UP(value, 8);
+	}
+
+	return value;
+}
+
+static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo)
+{
+	/* Turn off the LCD controller and the DMA controller */
+	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
+			sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
+
+	/* Wait for the LCDC core to become idle */
+	while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
+		mdelay(10);
+
+	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
+}
+
+static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo)
+{
+	atmel_lcdfb_stop_nowait(sinfo);
+
+	/* Wait for DMA engine to become idle... */
+	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
+		mdelay(10);
+}
+
+static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
+{
+	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
+	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
+		(sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
+		| ATMEL_LCDC_PWR);
+}
+
+/**
+ * @param fb_info Framebuffer information
+ */
+static void atmel_lcdc_enable_controller(struct fb_info *fb_info)
+{
+	struct atmel_lcdfb_info *sinfo = fb_info->priv;
+
+	if (sinfo->atmel_lcdfb_power_control)
+		sinfo->atmel_lcdfb_power_control(1);
+}
+
+/**
+ * @param fb_info Framebuffer information
+ */
+static void atmel_lcdc_disable_controller(struct fb_info *fb_info)
+{
+	struct atmel_lcdfb_info *sinfo = fb_info->priv;
+
+	if (sinfo->atmel_lcdfb_power_control)
+		sinfo->atmel_lcdfb_power_control(0);
+}
+
+static void atmel_lcdfb_update_dma(struct fb_info *info)
+{
+	struct atmel_lcdfb_info *sinfo = info->priv;
+	unsigned long dma_addr;
+
+	dma_addr = (unsigned long)info->screen_base;
+
+	dma_addr &= ~3UL;
+
+	/* Set framebuffer DMA base address and pixel offset */
+	lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
+}
+
+static void atmel_lcdfb_set_par(struct fb_info *info)
+{
+	struct atmel_lcdfb_info *sinfo = info->priv;
+	struct fb_videomode *mode = info->mode;
+	unsigned long clk_value_khz;
+	unsigned long value;
+	unsigned long pix_factor = 2;
+	unsigned long hozval_linesz;
+
+	atmel_lcdfb_stop(sinfo);
+
+	/* Re-initialize the DMA engine... */
+	dev_dbg(&info->dev, "  * update DMA engine\n");
+	atmel_lcdfb_update_dma(info);
+
+	/* ...set frame size and burst length = 8 words (?) */
+	value = (mode->yres * mode->xres * info->bits_per_pixel) / 32;
+	value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
+	lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
+
+	/* Now, the LCDC core... */
+
+	/* Set pixel clock */
+	if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es())
+		pix_factor = 1;
+
+	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
+
+	value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(mode->pixclock));
+
+	if (value < pix_factor) {
+		dev_notice(&info->dev, "Bypassing pixel clock divider\n");
+		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
+	} else {
+		value = (value / pix_factor) - 1;
+		dev_dbg(&info->dev, "  * programming CLKVAL = 0x%08lx\n",
+				value);
+		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
+				value << ATMEL_LCDC_CLKVAL_OFFSET);
+		mode->pixclock =
+			KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
+		dev_dbg(&info->dev, "  updated pixclk:     %lu KHz\n",
+					PICOS2KHZ(mode->pixclock));
+	}
+
+	/* Initialize control register 2 */
+	value = sinfo->default_lcdcon2;
+
+	if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
+		value |= ATMEL_LCDC_INVLINE_INVERTED;
+	if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
+		value |= ATMEL_LCDC_INVFRAME_INVERTED;
+
+	switch (info->bits_per_pixel) {
+		case 1:	value |= ATMEL_LCDC_PIXELSIZE_1; break;
+		case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
+		case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
+		case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
+		case 15: /* fall through */
+		case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
+		case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
+		case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
+		default: BUG(); break;
+	}
+	dev_dbg(&info->dev, "  * LCDCON2 = %08lx\n", value);
+	lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
+
+	/* Vertical timing */
+	value = (mode->vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
+	value |= mode->upper_margin << ATMEL_LCDC_VBP_OFFSET;
+	value |= mode->lower_margin;
+	dev_dbg(&info->dev, "  * LCDTIM1 = %08lx\n", value);
+	lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
+
+	/* Horizontal timing */
+	value = (mode->right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
+	value |= (mode->hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
+	value |= (mode->left_margin - 1);
+	dev_dbg(&info->dev, "  * LCDTIM2 = %08lx\n", value);
+	lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
+
+	/* Horizontal value (aka line size) */
+	hozval_linesz = compute_hozval(mode->xres,
+					lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
+
+	/* Display size */
+	value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
+	value |= mode->yres - 1;
+	dev_dbg(&info->dev, "  * LCDFRMCFG = %08lx\n", value);
+	lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
+
+	/* FIFO Threshold: Use formula from data sheet */
+	value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
+	lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
+
+	/* Toggle LCD_MODE every frame */
+	lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
+
+	/* Disable all interrupts */
+	lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
+
+	/* Enable FIFO & DMA errors */
+	lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
+
+	/* ...wait for DMA engine to become idle... */
+	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
+		mdelay(10);
+
+	atmel_lcdfb_start(sinfo);
+
+	dev_dbg(&info->dev, "  * DONE\n");
+}
+
+static int atmel_lcdfb_check_var(struct fb_info *info)
+{
+	struct device_d *dev = &info->dev;
+	struct atmel_lcdfb_info *sinfo = info->priv;
+	struct fb_videomode *mode = info->mode;
+	unsigned long clk_value_khz;
+
+	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
+
+	dev_dbg(dev, "%s:\n", __func__);
+
+	if (!(mode->pixclock && info->bits_per_pixel)) {
+		dev_err(dev, "needed value not specified\n");
+		return -EINVAL;
+	}
+
+	dev_dbg(dev, "  resolution: %ux%u\n", mode->xres, mode->yres);
+	dev_dbg(dev, "  pixclk:     %lu KHz\n", PICOS2KHZ(mode->pixclock));
+	dev_dbg(dev, "  bpp:        %u\n", info->bits_per_pixel);
+	dev_dbg(dev, "  clk:        %lu KHz\n", clk_value_khz);
+
+	if (PICOS2KHZ(mode->pixclock) > clk_value_khz) {
+		dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(mode->pixclock));
+		return -EINVAL;
+	}
+
+	/* Saturate vertical and horizontal timings at maximum values */
+	mode->vsync_len = min_t(u32, mode->vsync_len,
+			(ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
+	mode->upper_margin = min_t(u32, mode->upper_margin,
+			ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
+	mode->lower_margin = min_t(u32, mode->lower_margin,
+			ATMEL_LCDC_VFP);
+	mode->right_margin = min_t(u32, mode->right_margin,
+			(ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
+	mode->hsync_len = min_t(u32, mode->hsync_len,
+			(ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
+	mode->left_margin = min_t(u32, mode->left_margin,
+			ATMEL_LCDC_HBP + 1);
+
+	/* Some parameters can't be zero */
+	mode->vsync_len = max_t(u32, mode->vsync_len, 1);
+	mode->right_margin = max_t(u32, mode->right_margin, 1);
+	mode->hsync_len = max_t(u32, mode->hsync_len, 1);
+	mode->left_margin = max_t(u32, mode->left_margin, 1);
+
+	switch (info->bits_per_pixel) {
+	case 1:
+	case 2:
+	case 4:
+	case 8:
+		info->red.offset = info->green.offset = info->blue.offset = 0;
+		info->red.length = info->green.length = info->blue.length
+			= info->bits_per_pixel;
+		break;
+	case 16:
+		if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
+			/* RGB:565 mode */
+			info->red.offset = 11;
+			info->blue.offset = 0;
+		} else {
+			/* BGR:565 mode */
+			info->red.offset = 0;
+			info->blue.offset = 11;
+		}
+		info->green.offset = 5;
+		info->green.length = 6;
+		info->red.length = info->blue.length = 5;
+		break;
+	case 32:
+		info->transp.offset = 24;
+		info->transp.length = 8;
+		/* fall through */
+	case 24:
+		if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
+			/* RGB:888 mode */
+			info->red.offset = 16;
+			info->blue.offset = 0;
+		} else {
+			/* BGR:888 mode */
+			info->red.offset = 0;
+			info->blue.offset = 16;
+		}
+		info->green.offset = 8;
+		info->red.length = info->green.length = info->blue.length = 8;
+		break;
+	default:
+		dev_err(dev, "color depth %d not supported\n",
+					info->bits_per_pixel);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
+{
+	struct fb_info *info = &sinfo->info;
+	struct fb_videomode *mode = info->mode;
+	unsigned int smem_len;
+
+	free(info->screen_base);
+
+	smem_len = (mode->xres * mode->yres
+		    * ((info->bits_per_pixel + 7) / 8));
+	smem_len = max(smem_len, sinfo->smem_len);
+
+	info->screen_base = dma_alloc_coherent(smem_len);
+
+	if (!info->screen_base)
+		return -ENOMEM;
+
+	memset(info->screen_base, 0, smem_len);
+
+	return 0;
+}
+
+/**
+ * Prepare the video hardware for a specified video mode
+ * @param fb_info Framebuffer information
+ * @param mode The video mode description to initialize
+ * @return 0 on success
+ */
+static int atmel_lcdc_activate_var(struct fb_info *info)
+{
+	struct atmel_lcdfb_info *sinfo = info->priv;
+	unsigned long value;
+	int ret;
+
+	ret = atmel_lcdfb_alloc_video_memory(sinfo);
+	if (ret)
+		return ret;
+
+	atmel_lcdfb_set_par(info);
+
+	/* Set contrast */
+	value = ATMEL_LCDC_PS_DIV8 |
+		ATMEL_LCDC_POL_POSITIVE |
+		ATMEL_LCDC_ENA_PWMENABLE;
+	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, value);
+	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
+
+	return atmel_lcdfb_check_var(info);
+}
+
+/*
+ * There is only one video hardware instance available.
+ * It makes no sense to dynamically allocate this data
+ */
+static struct fb_ops atmel_lcdc_ops = {
+	.fb_activate_var = atmel_lcdc_activate_var,
+	.fb_enable = atmel_lcdc_enable_controller,
+	.fb_disable = atmel_lcdc_disable_controller,
+};
+
+static int atmel_lcdc_probe(struct device_d *hw_dev)
+{
+	struct atmel_lcdfb_info *sinfo = hw_dev->platform_data;
+	int ret = 0;
+	struct fb_info *info;
+
+	if (!sinfo)
+		return -ENODEV;
+
+	sinfo->mmio = dev_request_mem_region(hw_dev, 0);
+
+	/* just init */
+	info = &sinfo->info;
+	info->priv = sinfo;
+	info->fbops = &atmel_lcdc_ops,	
+	info->mode = &info->mode_list[0];
+	info->xres = info->mode->xres;
+	info->yres = info->mode->yres;
+	info->bits_per_pixel = sinfo->default_bpp;
+
+	/* Enable LCDC Clocks */
+	sinfo->bus_clk = clk_get(hw_dev, "hck1");
+	if (IS_ERR(sinfo->bus_clk)) {
+		ret = PTR_ERR(sinfo->bus_clk);
+		goto err;
+	}
+	sinfo->lcdc_clk = clk_get(hw_dev, "lcdc_clk");
+	if (IS_ERR(sinfo->lcdc_clk)) {
+		ret = PTR_ERR(sinfo->lcdc_clk);
+		goto put_bus_clk;
+	}
+
+	atmel_lcdfb_start_clock(sinfo);
+
+	ret = register_framebuffer(info);
+	if (ret != 0) {
+		dev_err(hw_dev, "Failed to register framebuffer\n");
+		goto stop_clk;
+	}
+
+	return ret;
+
+stop_clk:
+	atmel_lcdfb_stop_clock(sinfo);
+	clk_put(sinfo->lcdc_clk);
+put_bus_clk:
+	clk_put(sinfo->bus_clk);
+err:
+	return ret;
+}
+
+static struct driver_d atmel_lcdc_driver = {
+	.name	= "atmel_lcdfb",
+	.probe	= atmel_lcdc_probe,
+};
+
+static int atmel_lcdc_init(void)
+{
+	return register_driver(&atmel_lcdc_driver);
+}
+device_initcall(atmel_lcdc_init);
-- 
1.7.10.4


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[PATCH 2/5] at91sam9263: add atmel lcdc frambuffer support

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/mach-at91/at91sam9263.c         |    1 +
 arch/arm/mach-at91/at91sam9263_devices.c |   40 ++++++++++++++++++++++++++++++
 2 files changed, 41 insertions(+)

diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index b3116d3..4f987d8 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -168,6 +168,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
+	CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb0", &lcdc_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index e686480..ba0b0b2 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -218,6 +218,46 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata)
 void __init at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {}
 #endif
 
+
+/* --------------------------------------------------------------------
+ *  LCD Controller
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_DRIVER_VIDEO_ATMEL)
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
+{
+	BUG_ON(!data);
+
+	at91_set_A_periph(AT91_PIN_PC1, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PC2, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDDEN */
+	at91_set_B_periph(AT91_PIN_PB9, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PC8, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PC9, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PC10, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PC11, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PC14, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
+	at91_set_A_periph(AT91_PIN_PC22, 0);	/* LCDD18 */
+	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD19 */
+	at91_set_A_periph(AT91_PIN_PC24, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD21 */
+	at91_set_A_periph(AT91_PIN_PC26, 0);	/* LCDD22 */
+	at91_set_A_periph(AT91_PIN_PC27, 0);	/* LCDD23 */
+
+	add_generic_device("atmel_lcdfb", 0, NULL, AT91SAM9263_LCDC_BASE, SZ_4K,
+			   IORESOURCE_MEM, data);
+}
+#else
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
+#endif
+
 resource_size_t __init at91_configure_dbgu(void)
 {
 	at91_set_A_periph(AT91_PIN_PC30, 0);		/* DRXD */
-- 
1.7.10.4


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[PATCH 3/5] at91sam9261: add atmel lcdc frambuffer support

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/mach-at91/at91sam9261.c         |    1 +
 arch/arm/mach-at91/at91sam9261_devices.c |   51 ++++++++++++++++++++++++++++++
 2 files changed, 52 insertions(+)

diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index d20b250..41e4d84 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -136,6 +136,7 @@ static struct clk *periph_clocks[] = {
 static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
+	CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb0", &lcdc_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 0091e2d..a32b4df 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -168,6 +168,57 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata)
 void __init at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {}
 #endif
 
+/* --------------------------------------------------------------------
+ *  LCD Controller
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_DRIVER_VIDEO_ATMEL)
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
+{
+	BUG_ON(!data);
+
+#if defined(CONFIG_FB_ATMEL_STN)
+	at91_set_A_periph(AT91_PIN_PB0, 0);	/* LCDVSYNC */
+	at91_set_A_periph(AT91_PIN_PB1, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PB2, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PB3, 0);	/* LCDDEN */
+	at91_set_A_periph(AT91_PIN_PB4, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PB5, 0);	/* LCDD0 */
+	at91_set_A_periph(AT91_PIN_PB6, 0);	/* LCDD1 */
+	at91_set_A_periph(AT91_PIN_PB7, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PB8, 0);	/* LCDD3 */
+#else
+	at91_set_A_periph(AT91_PIN_PB1, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PB2, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PB3, 0);	/* LCDDEN */
+	at91_set_A_periph(AT91_PIN_PB4, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PB7, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PB8, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PB9, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PB10, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PB11, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PB12, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PB15, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PB16, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PB17, 0);	/* LCDD12 */
+	at91_set_A_periph(AT91_PIN_PB18, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PB19, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PB20, 0);	/* LCDD15 */
+	at91_set_B_periph(AT91_PIN_PB23, 0);	/* LCDD18 */
+	at91_set_B_periph(AT91_PIN_PB24, 0);	/* LCDD19 */
+	at91_set_B_periph(AT91_PIN_PB25, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PB26, 0);	/* LCDD21 */
+	at91_set_B_periph(AT91_PIN_PB27, 0);	/* LCDD22 */
+	at91_set_B_periph(AT91_PIN_PB28, 0);	/* LCDD23 */
+#endif
+
+	add_generic_device("atmel_lcdfb", 0, NULL, AT91SAM9261_LCDC_BASE, SZ_4K,
+			   IORESOURCE_MEM, data);
+}
+#else
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
+#endif
+
 resource_size_t __init at91_configure_dbgu(void)
 {
 	at91_set_A_periph(AT91_PIN_PA9, 0);		/* DRXD */
-- 
1.7.10.4


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[PATCH 4/5] at91sam9g45: add atmel lcdc frambuffer support

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/mach-at91/at91sam9g45.c         |    1 +
 arch/arm/mach-at91/at91sam9g45_devices.c |   49 ++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+)

diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index a6717f1..93e815f 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -190,6 +190,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
+	CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb0", &lcdc_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 22b455e..e08904b 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -324,3 +324,52 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata)
 #else
 void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {}
 #endif
+
+/* --------------------------------------------------------------------
+ *  LCD Controller
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_DRIVER_VIDEO_ATMEL)
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
+{
+	BUG_ON(!data);
+
+	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
+
+	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
+	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PE6, 0);	/* LCDDEN */
+	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
+	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
+	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
+	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
+	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
+	at91_set_A_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
+	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
+	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
+	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
+	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
+	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
+	at91_set_A_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
+	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
+	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
+
+	add_generic_device("atmel_lcdfb", 0, NULL, AT91SAM9G45_LCDC_BASE, SZ_4K,
+			   IORESOURCE_MEM, data);
+}
+#else
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
+#endif
+
-- 
1.7.10.4


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[PATCH 5/5] at91sam9m10g45ek: add lcdc support

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 .../arm/boards/at91sam9m10g45ek/env/bin/boot_board |    7 ++++
 arch/arm/boards/at91sam9m10g45ek/env/splash.png    |  Bin 0 -> 22747 bytes
 arch/arm/boards/at91sam9m10g45ek/init.c            |   35 ++++++++++++++++++++
 arch/arm/configs/at91sam9m10g45ek_defconfig        |   11 ++++--
 4 files changed, 50 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/boards/at91sam9m10g45ek/env/splash.png

diff --git a/arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board b/arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board
index 3d7426f..eeb7a76 100644
--- a/arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board
+++ b/arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board
@@ -5,6 +5,13 @@ export PATH
 
 . /env/config
 
+splash=/env/splash.png
+
+if [ -f ${splash} ]; then
+	splash ${splash}
+	fb0.enable=1
+fi
+
 menu -r -m boot
 menu -a -m boot -d "\e[1;36mWelcome on Barebox Boot Sequence\e[0m"
 menu -e -a -m boot -c 'menu_boot'			-d "boot (default)             "
diff --git a/arch/arm/boards/at91sam9m10g45ek/env/splash.png b/arch/arm/boards/at91sam9m10g45ek/env/splash.png
new file mode 100644
index 0000000000000000000000000000000000000000..08f2ac4fc106e6e38e503338b0fb047d20ac1f99
GIT binary patch
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HcmV?d00001

diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c
index f1c43cc..d77c998 100644
--- a/arch/arm/boards/at91sam9m10g45ek/init.c
+++ b/arch/arm/boards/at91sam9m10g45ek/init.c
@@ -218,6 +218,40 @@ static int at91sam9m10g45ek_mem_init(void)
 }
 mem_initcall(at91sam9m10g45ek_mem_init);
 
+static struct fb_videomode at91_tft_vga_modes[] = {
+	{
+		.name           = "LG",
+		.refresh	= 60,
+		.xres		= 480,		.yres		= 272,
+		.pixclock	= KHZ2PICOS(9000),
+
+		.left_margin	= 1,		.right_margin	= 1,
+		.upper_margin	= 40,		.lower_margin	= 1,
+		.hsync_len	= 45,		.vsync_len	= 1,
+
+		.sync		= 0,
+		.vmode		= FB_VMODE_NONINTERLACED,
+	},
+};
+
+#define AT91SAM9G45_DEFAULT_LCDCON2 	(ATMEL_LCDC_MEMOR_LITTLE \
+					| ATMEL_LCDC_DISTYPE_TFT \
+					| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
+
+/* Driver datas */
+static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
+	.lcdcon_is_backlight		= true,
+	.default_bpp			= 32,
+	.default_dmacon			= ATMEL_LCDC_DMAEN,
+	.default_lcdcon2		= AT91SAM9G45_DEFAULT_LCDCON2,
+	.guard_time			= 9,
+	.lcd_wiring_mode		= ATMEL_LCDC_WIRING_RGB,
+	.info = {
+		.mode_list		= at91_tft_vga_modes,
+		.num_modes		= ARRAY_SIZE(at91_tft_vga_modes),
+	},
+};
+
 static int at91sam9m10g45ek_devices_init(void)
 {
 	ek_add_device_nand();
@@ -225,6 +259,7 @@ static int at91sam9m10g45ek_devices_init(void)
 	ek_add_device_mci();
 	ek_device_add_leds();
 	ek_device_add_keyboard();
+	at91_add_device_lcdc(&ek_lcdc_data);
 
 	devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
 	dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
diff --git a/arch/arm/configs/at91sam9m10g45ek_defconfig b/arch/arm/configs/at91sam9m10g45ek_defconfig
index 1fa37d6..7e555b1 100644
--- a/arch/arm/configs/at91sam9m10g45ek_defconfig
+++ b/arch/arm/configs/at91sam9m10g45ek_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
 CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
+CONFIG_MALLOC_SIZE=0x800000
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="9M10G45-EK:"
 CONFIG_LONGHELP=y
@@ -29,8 +30,6 @@ CONFIG_CMD_PASSWD=y
 CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_LOADB=y
 CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MTEST=y
-CONFIG_CMD_MTEST_ALTERNATIVE=y
 CONFIG_CMD_FLASH=y
 CONFIG_CMD_BOOTM_SHOW_TYPE=y
 CONFIG_CMD_BOOTM_VERBOSE=y
@@ -38,13 +37,17 @@ CONFIG_CMD_BOOTM_INITRD=y
 CONFIG_CMD_BOOTM_OFTREE=y
 CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
 CONFIG_CMD_UIMAGE=y
+# CONFIG_CMD_BOOTU is not set
 CONFIG_CMD_RESET=y
 CONFIG_CMD_GO=y
 CONFIG_CMD_OFTREE=y
+CONFIG_CMD_MTEST=y
+CONFIG_CMD_MTEST_ALTERNATIVE=y
 CONFIG_CMD_TIMEOUT=y
 CONFIG_CMD_PARTITION=y
 CONFIG_CMD_MAGICVAR=y
 CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_SPLASH=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_UNCOMPRESS=y
 CONFIG_CMD_LED=y
@@ -66,6 +69,8 @@ CONFIG_NAND=y
 # CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_UBI=y
+CONFIG_VIDEO=y
+CONFIG_DRIVER_VIDEO_ATMEL=y
 CONFIG_MCI=y
 CONFIG_MCI_STARTUP=y
 CONFIG_MCI_ATMEL=y
@@ -75,4 +80,4 @@ CONFIG_LED_TRIGGERS=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_WRITE=y
 CONFIG_FS_FAT_LFN=y
-CONFIG_LZO_DECOMPRESS=y
+CONFIG_PNG=y
-- 
1.7.10.4


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Re: [PATCH 1/5] video: add atmel lcdc frambuffer support

[Sascha Hauer]

On Fri, Sep 21, 2012 at 02:55:29PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> This IP is present on the at91sam9 until the sam9g45, on the sam9x5 we use a
> new IP.
> 
> This driver is based on the linux one.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
>  arch/arm/mach-at91/include/mach/atmel_lcdc.h |  209 +++++++++++
>  arch/arm/mach-at91/include/mach/board.h      |    4 +
>  drivers/video/Kconfig                        |    4 +
>  drivers/video/Makefile                       |    1 +
>  drivers/video/atmel_lcdfb.c                  |  477 ++++++++++++++++++++++++++
>  5 files changed, 695 insertions(+)
>  create mode 100644 arch/arm/mach-at91/include/mach/atmel_lcdc.h
>  create mode 100644 drivers/video/atmel_lcdfb.c
> 
> diff --git a/arch/arm/mach-at91/include/mach/atmel_lcdc.h b/arch/arm/mach-at91/include/mach/atmel_lcdc.h

The register definitions should be besides the driver, not in mach.

> diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
> new file mode 100644
> index 0000000..8659836
> --- /dev/null
> +++ b/drivers/video/atmel_lcdfb.c
> @@ -0,0 +1,477 @@
> +/*
> + * Driver for AT91/AT32 LCD Controller
> + *
> + * Copyright (C) 2007 Atmel Corporation
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <io.h>
> +#include <init.h>
> +#include <linux/clk.h>
> +#include <fb.h>
> +#include <mach/atmel_lcdc.h>
> +#include <mach/hardware.h>
> +#include <mach/io.h>
> +#include <mach/cpu.h>
> +#include <errno.h>
> +#include <linux/err.h>
> +#include <malloc.h>
> +#include <asm/mmu.h>
> +
> +#define lcdc_readl(sinfo, reg)		__raw_readl((sinfo)->mmio+(reg))
> +#define lcdc_writel(sinfo, reg, val)	__raw_writel((val), (sinfo)->mmio+(reg))
> +
> +/* configurable parameters */
> +#define ATMEL_LCDC_CVAL_DEFAULT		0xc8
> +#define ATMEL_LCDC_DMA_BURST_LEN	8	/* words */
> +#define ATMEL_LCDC_FIFO_SIZE		512	/* words */
> +
> +static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
> +{
> +	clk_enable(sinfo->bus_clk);
> +	clk_enable(sinfo->lcdc_clk);
> +}
> +
> +static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
> +{
> +	clk_disable(sinfo->bus_clk);
> +	clk_disable(sinfo->lcdc_clk);
> +}
> +
> +static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
> +{
> +	unsigned long value;
> +
> +	if (!(cpu_is_at91sam9261() || cpu_is_at91sam9g10()
> +		|| cpu_is_at32ap7000()))
> +		return xres;
> +
> +	value = xres;
> +	if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
> +		/* STN display */
> +		if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR)
> +			value *= 3;
> +
> +		if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
> +		   || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
> +		      && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
> +			value = DIV_ROUND_UP(value, 4);
> +		else
> +			value = DIV_ROUND_UP(value, 8);
> +	}
> +
> +	return value;
> +}
> +
> +static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo)
> +{
> +	/* Turn off the LCD controller and the DMA controller */
> +	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
> +			sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
> +
> +	/* Wait for the LCDC core to become idle */
> +	while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
> +		mdelay(10);
> +
> +	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
> +}
> +
> +static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo)
> +{
> +	atmel_lcdfb_stop_nowait(sinfo);
> +
> +	/* Wait for DMA engine to become idle... */
> +	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
> +		mdelay(10);
> +}
> +
> +static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
> +{
> +	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
> +	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
> +		(sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
> +		| ATMEL_LCDC_PWR);
> +}
> +
> +/**
> + * @param fb_info Framebuffer information
> + */
> +static void atmel_lcdc_enable_controller(struct fb_info *fb_info)
> +{
> +	struct atmel_lcdfb_info *sinfo = fb_info->priv;
> +
> +	if (sinfo->atmel_lcdfb_power_control)
> +		sinfo->atmel_lcdfb_power_control(1);
> +}
> +
> +/**
> + * @param fb_info Framebuffer information
> + */
> +static void atmel_lcdc_disable_controller(struct fb_info *fb_info)
> +{
> +	struct atmel_lcdfb_info *sinfo = fb_info->priv;
> +
> +	if (sinfo->atmel_lcdfb_power_control)
> +		sinfo->atmel_lcdfb_power_control(0);
> +}
> +
> +static void atmel_lcdfb_update_dma(struct fb_info *info)
> +{
> +	struct atmel_lcdfb_info *sinfo = info->priv;
> +	unsigned long dma_addr;
> +
> +	dma_addr = (unsigned long)info->screen_base;
> +
> +	dma_addr &= ~3UL;
> +
> +	/* Set framebuffer DMA base address and pixel offset */
> +	lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
> +}
> +
> +static void atmel_lcdfb_set_par(struct fb_info *info)
> +{
> +	struct atmel_lcdfb_info *sinfo = info->priv;
> +	struct fb_videomode *mode = info->mode;
> +	unsigned long clk_value_khz;
> +	unsigned long value;
> +	unsigned long pix_factor = 2;
> +	unsigned long hozval_linesz;
> +
> +	atmel_lcdfb_stop(sinfo);
> +
> +	/* Re-initialize the DMA engine... */
> +	dev_dbg(&info->dev, "  * update DMA engine\n");
> +	atmel_lcdfb_update_dma(info);
> +
> +	/* ...set frame size and burst length = 8 words (?) */
> +	value = (mode->yres * mode->xres * info->bits_per_pixel) / 32;
> +	value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
> +	lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
> +
> +	/* Now, the LCDC core... */
> +
> +	/* Set pixel clock */
> +	if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es())
> +		pix_factor = 1;
> +
> +	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
> +
> +	value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(mode->pixclock));
> +
> +	if (value < pix_factor) {
> +		dev_notice(&info->dev, "Bypassing pixel clock divider\n");
> +		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
> +	} else {
> +		value = (value / pix_factor) - 1;
> +		dev_dbg(&info->dev, "  * programming CLKVAL = 0x%08lx\n",
> +				value);
> +		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
> +				value << ATMEL_LCDC_CLKVAL_OFFSET);
> +		mode->pixclock =
> +			KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
> +		dev_dbg(&info->dev, "  updated pixclk:     %lu KHz\n",
> +					PICOS2KHZ(mode->pixclock));
> +	}
> +
> +	/* Initialize control register 2 */
> +	value = sinfo->default_lcdcon2;
> +
> +	if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
> +		value |= ATMEL_LCDC_INVLINE_INVERTED;
> +	if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
> +		value |= ATMEL_LCDC_INVFRAME_INVERTED;
> +
> +	switch (info->bits_per_pixel) {
> +		case 1:	value |= ATMEL_LCDC_PIXELSIZE_1; break;
> +		case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
> +		case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
> +		case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
> +		case 15: /* fall through */
> +		case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
> +		case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
> +		case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
> +		default: BUG(); break;
> +	}
> +	dev_dbg(&info->dev, "  * LCDCON2 = %08lx\n", value);
> +	lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
> +
> +	/* Vertical timing */
> +	value = (mode->vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
> +	value |= mode->upper_margin << ATMEL_LCDC_VBP_OFFSET;
> +	value |= mode->lower_margin;
> +	dev_dbg(&info->dev, "  * LCDTIM1 = %08lx\n", value);
> +	lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
> +
> +	/* Horizontal timing */
> +	value = (mode->right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
> +	value |= (mode->hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
> +	value |= (mode->left_margin - 1);
> +	dev_dbg(&info->dev, "  * LCDTIM2 = %08lx\n", value);
> +	lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
> +
> +	/* Horizontal value (aka line size) */
> +	hozval_linesz = compute_hozval(mode->xres,
> +					lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
> +
> +	/* Display size */
> +	value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
> +	value |= mode->yres - 1;
> +	dev_dbg(&info->dev, "  * LCDFRMCFG = %08lx\n", value);
> +	lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
> +
> +	/* FIFO Threshold: Use formula from data sheet */
> +	value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
> +	lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
> +
> +	/* Toggle LCD_MODE every frame */
> +	lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
> +
> +	/* Disable all interrupts */
> +	lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
> +
> +	/* Enable FIFO & DMA errors */
> +	lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
> +
> +	/* ...wait for DMA engine to become idle... */
> +	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
> +		mdelay(10);
> +
> +	atmel_lcdfb_start(sinfo);
> +
> +	dev_dbg(&info->dev, "  * DONE\n");
> +}
> +
> +static int atmel_lcdfb_check_var(struct fb_info *info)
> +{
> +	struct device_d *dev = &info->dev;
> +	struct atmel_lcdfb_info *sinfo = info->priv;
> +	struct fb_videomode *mode = info->mode;
> +	unsigned long clk_value_khz;
> +
> +	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
> +
> +	dev_dbg(dev, "%s:\n", __func__);
> +
> +	if (!(mode->pixclock && info->bits_per_pixel)) {
> +		dev_err(dev, "needed value not specified\n");
> +		return -EINVAL;
> +	}
> +
> +	dev_dbg(dev, "  resolution: %ux%u\n", mode->xres, mode->yres);
> +	dev_dbg(dev, "  pixclk:     %lu KHz\n", PICOS2KHZ(mode->pixclock));
> +	dev_dbg(dev, "  bpp:        %u\n", info->bits_per_pixel);
> +	dev_dbg(dev, "  clk:        %lu KHz\n", clk_value_khz);
> +
> +	if (PICOS2KHZ(mode->pixclock) > clk_value_khz) {
> +		dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(mode->pixclock));
> +		return -EINVAL;
> +	}
> +
> +	/* Saturate vertical and horizontal timings at maximum values */
> +	mode->vsync_len = min_t(u32, mode->vsync_len,
> +			(ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
> +	mode->upper_margin = min_t(u32, mode->upper_margin,
> +			ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
> +	mode->lower_margin = min_t(u32, mode->lower_margin,
> +			ATMEL_LCDC_VFP);
> +	mode->right_margin = min_t(u32, mode->right_margin,
> +			(ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
> +	mode->hsync_len = min_t(u32, mode->hsync_len,
> +			(ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
> +	mode->left_margin = min_t(u32, mode->left_margin,
> +			ATMEL_LCDC_HBP + 1);
> +
> +	/* Some parameters can't be zero */
> +	mode->vsync_len = max_t(u32, mode->vsync_len, 1);
> +	mode->right_margin = max_t(u32, mode->right_margin, 1);
> +	mode->hsync_len = max_t(u32, mode->hsync_len, 1);
> +	mode->left_margin = max_t(u32, mode->left_margin, 1);
> +
> +	switch (info->bits_per_pixel) {
> +	case 1:
> +	case 2:
> +	case 4:
> +	case 8:
> +		info->red.offset = info->green.offset = info->blue.offset = 0;
> +		info->red.length = info->green.length = info->blue.length
> +			= info->bits_per_pixel;
> +		break;
> +	case 16:
> +		if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
> +			/* RGB:565 mode */
> +			info->red.offset = 11;
> +			info->blue.offset = 0;
> +		} else {
> +			/* BGR:565 mode */
> +			info->red.offset = 0;
> +			info->blue.offset = 11;
> +		}
> +		info->green.offset = 5;
> +		info->green.length = 6;
> +		info->red.length = info->blue.length = 5;
> +		break;
> +	case 32:
> +		info->transp.offset = 24;
> +		info->transp.length = 8;
> +		/* fall through */
> +	case 24:
> +		if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
> +			/* RGB:888 mode */
> +			info->red.offset = 16;
> +			info->blue.offset = 0;
> +		} else {
> +			/* BGR:888 mode */
> +			info->red.offset = 0;
> +			info->blue.offset = 16;
> +		}
> +		info->green.offset = 8;
> +		info->red.length = info->green.length = info->blue.length = 8;
> +		break;
> +	default:
> +		dev_err(dev, "color depth %d not supported\n",
> +					info->bits_per_pixel);
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
> +static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
> +{
> +	struct fb_info *info = &sinfo->info;
> +	struct fb_videomode *mode = info->mode;
> +	unsigned int smem_len;
> +
> +	free(info->screen_base);
> +
> +	smem_len = (mode->xres * mode->yres
> +		    * ((info->bits_per_pixel + 7) / 8));
> +	smem_len = max(smem_len, sinfo->smem_len);
> +
> +	info->screen_base = dma_alloc_coherent(smem_len);
> +
> +	if (!info->screen_base)
> +		return -ENOMEM;
> +
> +	memset(info->screen_base, 0, smem_len);
> +
> +	return 0;
> +}
> +
> +/**
> + * Prepare the video hardware for a specified video mode
> + * @param fb_info Framebuffer information
> + * @param mode The video mode description to initialize
> + * @return 0 on success
> + */
> +static int atmel_lcdc_activate_var(struct fb_info *info)
> +{
> +	struct atmel_lcdfb_info *sinfo = info->priv;
> +	unsigned long value;
> +	int ret;
> +
> +	ret = atmel_lcdfb_alloc_video_memory(sinfo);
> +	if (ret)
> +		return ret;
> +
> +	atmel_lcdfb_set_par(info);
> +
> +	/* Set contrast */
> +	value = ATMEL_LCDC_PS_DIV8 |
> +		ATMEL_LCDC_POL_POSITIVE |
> +		ATMEL_LCDC_ENA_PWMENABLE;
> +	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, value);
> +	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
> +
> +	return atmel_lcdfb_check_var(info);
> +}
> +
> +/*
> + * There is only one video hardware instance available.
> + * It makes no sense to dynamically allocate this data
> + */
> +static struct fb_ops atmel_lcdc_ops = {
> +	.fb_activate_var = atmel_lcdc_activate_var,
> +	.fb_enable = atmel_lcdc_enable_controller,
> +	.fb_disable = atmel_lcdc_disable_controller,
> +};
> +
> +static int atmel_lcdc_probe(struct device_d *hw_dev)
> +{
> +	struct atmel_lcdfb_info *sinfo = hw_dev->platform_data;
> +	int ret = 0;
> +	struct fb_info *info;
> +
> +	if (!sinfo)
> +		return -ENODEV;
> +
> +	sinfo->mmio = dev_request_mem_region(hw_dev, 0);
> +
> +	/* just init */
> +	info = &sinfo->info;

No. Separate your platform data from the driver private data.

> +	info->priv = sinfo;
> +	info->fbops = &atmel_lcdc_ops,	

Trailing whitespace

> +	info->mode = &info->mode_list[0];
> +	info->xres = info->mode->xres;
> +	info->yres = info->mode->yres;
> +	info->bits_per_pixel = sinfo->default_bpp;
> +
> +	/* Enable LCDC Clocks */
> +	sinfo->bus_clk = clk_get(hw_dev, "hck1");
> +	if (IS_ERR(sinfo->bus_clk)) {
> +		ret = PTR_ERR(sinfo->bus_clk);
> +		goto err;
> +	}
> +	sinfo->lcdc_clk = clk_get(hw_dev, "lcdc_clk");
> +	if (IS_ERR(sinfo->lcdc_clk)) {
> +		ret = PTR_ERR(sinfo->lcdc_clk);
> +		goto put_bus_clk;
> +	}
> +
> +	atmel_lcdfb_start_clock(sinfo);

This should be in .fb_enable.

> +
> +	ret = register_framebuffer(info);
> +	if (ret != 0) {
> +		dev_err(hw_dev, "Failed to register framebuffer\n");
> +		goto stop_clk;
> +	}
> +
> +	return ret;
> +
> +stop_clk:
> +	atmel_lcdfb_stop_clock(sinfo);
> +	clk_put(sinfo->lcdc_clk);
> +put_bus_clk:
> +	clk_put(sinfo->bus_clk);
> +err:
> +	return ret;
> +}
> +
> +static struct driver_d atmel_lcdc_driver = {
> +	.name	= "atmel_lcdfb",
> +	.probe	= atmel_lcdc_probe,
> +};
> +
> +static int atmel_lcdc_init(void)
> +{
> +	return register_driver(&atmel_lcdc_driver);
> +}
> +device_initcall(atmel_lcdc_init);
> -- 
> 1.7.10.4
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
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> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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Re: [PATCH 1/5] video: add atmel lcdc frambuffer support

[Jean-Christophe PLAGNIOL-VILLARD]

On 12:34 Sat 22 Sep     , Sascha Hauer wrote:
> On Fri, Sep 21, 2012 at 02:55:29PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > This IP is present on the at91sam9 until the sam9g45, on the sam9x5 we use a
> > new IP.
> > 
> > This driver is based on the linux one.
> > 
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> > Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
> > ---
> >  arch/arm/mach-at91/include/mach/atmel_lcdc.h |  209 +++++++++++
> >  arch/arm/mach-at91/include/mach/board.h      |    4 +
> >  drivers/video/Kconfig                        |    4 +
> >  drivers/video/Makefile                       |    1 +
> >  drivers/video/atmel_lcdfb.c                  |  477 ++++++++++++++++++++++++++
> >  5 files changed, 695 insertions(+)
> >  create mode 100644 arch/arm/mach-at91/include/mach/atmel_lcdc.h
> >  create mode 100644 drivers/video/atmel_lcdfb.c
> > 
> > diff --git a/arch/arm/mach-at91/include/mach/atmel_lcdc.h b/arch/arm/mach-at91/include/mach/atmel_lcdc.h
> 
> The register definitions should be besides the driver, not in mach.
can not  as we need the register for the board setting I can do as in linux we
put the header in include/video

Best Regards,
J.
> 

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Re: [PATCH 1/5] video: add atmel lcdc frambuffer support

[Jean-Christophe PLAGNIOL-VILLARD]

On 12:34 Sat 22 Sep     , Sascha Hauer wrote:
> On Fri, Sep 21, 2012 at 02:55:29PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > This IP is present on the at91sam9 until the sam9g45, on the sam9x5 we use a
> > new IP.
> > 
> > This driver is based on the linux one.
> > 
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> > Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
> > ---
> >  arch/arm/mach-at91/include/mach/atmel_lcdc.h |  209 +++++++++++
> >  arch/arm/mach-at91/include/mach/board.h      |    4 +
> >  drivers/video/Kconfig                        |    4 +
> >  drivers/video/Makefile                       |    1 +
> >  drivers/video/atmel_lcdfb.c                  |  477 ++++++++++++++++++++++++++
> >  5 files changed, 695 insertions(+)
> >  create mode 100644 arch/arm/mach-at91/include/mach/atmel_lcdc.h
> >  create mode 100644 drivers/video/atmel_lcdfb.c
> > 
> > diff --git a/arch/arm/mach-at91/include/mach/atmel_lcdc.h b/arch/arm/mach-at91/include/mach/atmel_lcdc.h
> 
> The register definitions should be besides the driver, not in mach.
> 
> > diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
> > new file mode 100644
> > index 0000000..8659836
> > --- /dev/null
> > +++ b/drivers/video/atmel_lcdfb.c
> > @@ -0,0 +1,477 @@
> > +/*
> > + * Driver for AT91/AT32 LCD Controller
> > + *
> > + * Copyright (C) 2007 Atmel Corporation
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <io.h>
> > +#include <init.h>
> > +#include <linux/clk.h>
> > +#include <fb.h>
> > +#include <mach/atmel_lcdc.h>
> > +#include <mach/hardware.h>
> > +#include <mach/io.h>
> > +#include <mach/cpu.h>
> > +#include <errno.h>
> > +#include <linux/err.h>
> > +#include <malloc.h>
> > +#include <asm/mmu.h>
> > +
> > +#define lcdc_readl(sinfo, reg)		__raw_readl((sinfo)->mmio+(reg))
> > +#define lcdc_writel(sinfo, reg, val)	__raw_writel((val), (sinfo)->mmio+(reg))
> > +
> > +/* configurable parameters */
> > +#define ATMEL_LCDC_CVAL_DEFAULT		0xc8
> > +#define ATMEL_LCDC_DMA_BURST_LEN	8	/* words */
> > +#define ATMEL_LCDC_FIFO_SIZE		512	/* words */
> > +
> > +static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
> > +{
> > +	clk_enable(sinfo->bus_clk);
> > +	clk_enable(sinfo->lcdc_clk);
> > +}
> > +
> > +static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
> > +{
> > +	clk_disable(sinfo->bus_clk);
> > +	clk_disable(sinfo->lcdc_clk);
> > +}
> > +
> > +static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
> > +{
> > +	unsigned long value;
> > +
> > +	if (!(cpu_is_at91sam9261() || cpu_is_at91sam9g10()
> > +		|| cpu_is_at32ap7000()))
> > +		return xres;
> > +
> > +	value = xres;
> > +	if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
> > +		/* STN display */
> > +		if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR)
> > +			value *= 3;
> > +
> > +		if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
> > +		   || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
> > +		      && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
> > +			value = DIV_ROUND_UP(value, 4);
> > +		else
> > +			value = DIV_ROUND_UP(value, 8);
> > +	}
> > +
> > +	return value;
> > +}
> > +
> > +static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo)
> > +{
> > +	/* Turn off the LCD controller and the DMA controller */
> > +	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
> > +			sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
> > +
> > +	/* Wait for the LCDC core to become idle */
> > +	while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
> > +		mdelay(10);
> > +
> > +	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
> > +}
> > +
> > +static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo)
> > +{
> > +	atmel_lcdfb_stop_nowait(sinfo);
> > +
> > +	/* Wait for DMA engine to become idle... */
> > +	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
> > +		mdelay(10);
> > +}
> > +
> > +static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
> > +{
> > +	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
> > +	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
> > +		(sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
> > +		| ATMEL_LCDC_PWR);
> > +}
> > +
> > +/**
> > + * @param fb_info Framebuffer information
> > + */
> > +static void atmel_lcdc_enable_controller(struct fb_info *fb_info)
> > +{
> > +	struct atmel_lcdfb_info *sinfo = fb_info->priv;
> > +
> > +	if (sinfo->atmel_lcdfb_power_control)
> > +		sinfo->atmel_lcdfb_power_control(1);
> > +}
> > +
> > +/**
> > + * @param fb_info Framebuffer information
> > + */
> > +static void atmel_lcdc_disable_controller(struct fb_info *fb_info)
> > +{
> > +	struct atmel_lcdfb_info *sinfo = fb_info->priv;
> > +
> > +	if (sinfo->atmel_lcdfb_power_control)
> > +		sinfo->atmel_lcdfb_power_control(0);
> > +}
> > +
> > +static void atmel_lcdfb_update_dma(struct fb_info *info)
> > +{
> > +	struct atmel_lcdfb_info *sinfo = info->priv;
> > +	unsigned long dma_addr;
> > +
> > +	dma_addr = (unsigned long)info->screen_base;
> > +
> > +	dma_addr &= ~3UL;
> > +
> > +	/* Set framebuffer DMA base address and pixel offset */
> > +	lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
> > +}
> > +
> > +static void atmel_lcdfb_set_par(struct fb_info *info)
> > +{
> > +	struct atmel_lcdfb_info *sinfo = info->priv;
> > +	struct fb_videomode *mode = info->mode;
> > +	unsigned long clk_value_khz;
> > +	unsigned long value;
> > +	unsigned long pix_factor = 2;
> > +	unsigned long hozval_linesz;
> > +
> > +	atmel_lcdfb_stop(sinfo);
> > +
> > +	/* Re-initialize the DMA engine... */
> > +	dev_dbg(&info->dev, "  * update DMA engine\n");
> > +	atmel_lcdfb_update_dma(info);
> > +
> > +	/* ...set frame size and burst length = 8 words (?) */
> > +	value = (mode->yres * mode->xres * info->bits_per_pixel) / 32;
> > +	value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
> > +	lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
> > +
> > +	/* Now, the LCDC core... */
> > +
> > +	/* Set pixel clock */
> > +	if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es())
> > +		pix_factor = 1;
> > +
> > +	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
> > +
> > +	value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(mode->pixclock));
> > +
> > +	if (value < pix_factor) {
> > +		dev_notice(&info->dev, "Bypassing pixel clock divider\n");
> > +		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
> > +	} else {
> > +		value = (value / pix_factor) - 1;
> > +		dev_dbg(&info->dev, "  * programming CLKVAL = 0x%08lx\n",
> > +				value);
> > +		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
> > +				value << ATMEL_LCDC_CLKVAL_OFFSET);
> > +		mode->pixclock =
> > +			KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
> > +		dev_dbg(&info->dev, "  updated pixclk:     %lu KHz\n",
> > +					PICOS2KHZ(mode->pixclock));
> > +	}
> > +
> > +	/* Initialize control register 2 */
> > +	value = sinfo->default_lcdcon2;
> > +
> > +	if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
> > +		value |= ATMEL_LCDC_INVLINE_INVERTED;
> > +	if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
> > +		value |= ATMEL_LCDC_INVFRAME_INVERTED;
> > +
> > +	switch (info->bits_per_pixel) {
> > +		case 1:	value |= ATMEL_LCDC_PIXELSIZE_1; break;
> > +		case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
> > +		case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
> > +		case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
> > +		case 15: /* fall through */
> > +		case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
> > +		case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
> > +		case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
> > +		default: BUG(); break;
> > +	}
> > +	dev_dbg(&info->dev, "  * LCDCON2 = %08lx\n", value);
> > +	lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
> > +
> > +	/* Vertical timing */
> > +	value = (mode->vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
> > +	value |= mode->upper_margin << ATMEL_LCDC_VBP_OFFSET;
> > +	value |= mode->lower_margin;
> > +	dev_dbg(&info->dev, "  * LCDTIM1 = %08lx\n", value);
> > +	lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
> > +
> > +	/* Horizontal timing */
> > +	value = (mode->right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
> > +	value |= (mode->hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
> > +	value |= (mode->left_margin - 1);
> > +	dev_dbg(&info->dev, "  * LCDTIM2 = %08lx\n", value);
> > +	lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
> > +
> > +	/* Horizontal value (aka line size) */
> > +	hozval_linesz = compute_hozval(mode->xres,
> > +					lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
> > +
> > +	/* Display size */
> > +	value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
> > +	value |= mode->yres - 1;
> > +	dev_dbg(&info->dev, "  * LCDFRMCFG = %08lx\n", value);
> > +	lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
> > +
> > +	/* FIFO Threshold: Use formula from data sheet */
> > +	value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
> > +	lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
> > +
> > +	/* Toggle LCD_MODE every frame */
> > +	lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
> > +
> > +	/* Disable all interrupts */
> > +	lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
> > +
> > +	/* Enable FIFO & DMA errors */
> > +	lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
> > +
> > +	/* ...wait for DMA engine to become idle... */
> > +	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
> > +		mdelay(10);
> > +
> > +	atmel_lcdfb_start(sinfo);
> > +
> > +	dev_dbg(&info->dev, "  * DONE\n");
> > +}
> > +
> > +static int atmel_lcdfb_check_var(struct fb_info *info)
> > +{
> > +	struct device_d *dev = &info->dev;
> > +	struct atmel_lcdfb_info *sinfo = info->priv;
> > +	struct fb_videomode *mode = info->mode;
> > +	unsigned long clk_value_khz;
> > +
> > +	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
> > +
> > +	dev_dbg(dev, "%s:\n", __func__);
> > +
> > +	if (!(mode->pixclock && info->bits_per_pixel)) {
> > +		dev_err(dev, "needed value not specified\n");
> > +		return -EINVAL;
> > +	}
> > +
> > +	dev_dbg(dev, "  resolution: %ux%u\n", mode->xres, mode->yres);
> > +	dev_dbg(dev, "  pixclk:     %lu KHz\n", PICOS2KHZ(mode->pixclock));
> > +	dev_dbg(dev, "  bpp:        %u\n", info->bits_per_pixel);
> > +	dev_dbg(dev, "  clk:        %lu KHz\n", clk_value_khz);
> > +
> > +	if (PICOS2KHZ(mode->pixclock) > clk_value_khz) {
> > +		dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(mode->pixclock));
> > +		return -EINVAL;
> > +	}
> > +
> > +	/* Saturate vertical and horizontal timings at maximum values */
> > +	mode->vsync_len = min_t(u32, mode->vsync_len,
> > +			(ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
> > +	mode->upper_margin = min_t(u32, mode->upper_margin,
> > +			ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
> > +	mode->lower_margin = min_t(u32, mode->lower_margin,
> > +			ATMEL_LCDC_VFP);
> > +	mode->right_margin = min_t(u32, mode->right_margin,
> > +			(ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
> > +	mode->hsync_len = min_t(u32, mode->hsync_len,
> > +			(ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
> > +	mode->left_margin = min_t(u32, mode->left_margin,
> > +			ATMEL_LCDC_HBP + 1);
> > +
> > +	/* Some parameters can't be zero */
> > +	mode->vsync_len = max_t(u32, mode->vsync_len, 1);
> > +	mode->right_margin = max_t(u32, mode->right_margin, 1);
> > +	mode->hsync_len = max_t(u32, mode->hsync_len, 1);
> > +	mode->left_margin = max_t(u32, mode->left_margin, 1);
> > +
> > +	switch (info->bits_per_pixel) {
> > +	case 1:
> > +	case 2:
> > +	case 4:
> > +	case 8:
> > +		info->red.offset = info->green.offset = info->blue.offset = 0;
> > +		info->red.length = info->green.length = info->blue.length
> > +			= info->bits_per_pixel;
> > +		break;
> > +	case 16:
> > +		if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
> > +			/* RGB:565 mode */
> > +			info->red.offset = 11;
> > +			info->blue.offset = 0;
> > +		} else {
> > +			/* BGR:565 mode */
> > +			info->red.offset = 0;
> > +			info->blue.offset = 11;
> > +		}
> > +		info->green.offset = 5;
> > +		info->green.length = 6;
> > +		info->red.length = info->blue.length = 5;
> > +		break;
> > +	case 32:
> > +		info->transp.offset = 24;
> > +		info->transp.length = 8;
> > +		/* fall through */
> > +	case 24:
> > +		if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
> > +			/* RGB:888 mode */
> > +			info->red.offset = 16;
> > +			info->blue.offset = 0;
> > +		} else {
> > +			/* BGR:888 mode */
> > +			info->red.offset = 0;
> > +			info->blue.offset = 16;
> > +		}
> > +		info->green.offset = 8;
> > +		info->red.length = info->green.length = info->blue.length = 8;
> > +		break;
> > +	default:
> > +		dev_err(dev, "color depth %d not supported\n",
> > +					info->bits_per_pixel);
> > +		return -EINVAL;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
> > +{
> > +	struct fb_info *info = &sinfo->info;
> > +	struct fb_videomode *mode = info->mode;
> > +	unsigned int smem_len;
> > +
> > +	free(info->screen_base);
> > +
> > +	smem_len = (mode->xres * mode->yres
> > +		    * ((info->bits_per_pixel + 7) / 8));
> > +	smem_len = max(smem_len, sinfo->smem_len);
> > +
> > +	info->screen_base = dma_alloc_coherent(smem_len);
> > +
> > +	if (!info->screen_base)
> > +		return -ENOMEM;
> > +
> > +	memset(info->screen_base, 0, smem_len);
> > +
> > +	return 0;
> > +}
> > +
> > +/**
> > + * Prepare the video hardware for a specified video mode
> > + * @param fb_info Framebuffer information
> > + * @param mode The video mode description to initialize
> > + * @return 0 on success
> > + */
> > +static int atmel_lcdc_activate_var(struct fb_info *info)
> > +{
> > +	struct atmel_lcdfb_info *sinfo = info->priv;
> > +	unsigned long value;
> > +	int ret;
> > +
> > +	ret = atmel_lcdfb_alloc_video_memory(sinfo);
> > +	if (ret)
> > +		return ret;
> > +
> > +	atmel_lcdfb_set_par(info);
> > +
> > +	/* Set contrast */
> > +	value = ATMEL_LCDC_PS_DIV8 |
> > +		ATMEL_LCDC_POL_POSITIVE |
> > +		ATMEL_LCDC_ENA_PWMENABLE;
> > +	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, value);
> > +	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
> > +
> > +	return atmel_lcdfb_check_var(info);
> > +}
> > +
> > +/*
> > + * There is only one video hardware instance available.
> > + * It makes no sense to dynamically allocate this data
> > + */
> > +static struct fb_ops atmel_lcdc_ops = {
> > +	.fb_activate_var = atmel_lcdc_activate_var,
> > +	.fb_enable = atmel_lcdc_enable_controller,
> > +	.fb_disable = atmel_lcdc_disable_controller,
> > +};
> > +
> > +static int atmel_lcdc_probe(struct device_d *hw_dev)
> > +{
> > +	struct atmel_lcdfb_info *sinfo = hw_dev->platform_data;
> > +	int ret = 0;
> > +	struct fb_info *info;
> > +
> > +	if (!sinfo)
> > +		return -ENODEV;
> > +
> > +	sinfo->mmio = dev_request_mem_region(hw_dev, 0);
> > +
> > +	/* just init */
> > +	info = &sinfo->info;
> 
> No. Separate your platform data from the driver private data.
> 
> > +	info->priv = sinfo;
> > +	info->fbops = &atmel_lcdc_ops,	
> 
> Trailing whitespace
> 
> > +	info->mode = &info->mode_list[0];
> > +	info->xres = info->mode->xres;
> > +	info->yres = info->mode->yres;
> > +	info->bits_per_pixel = sinfo->default_bpp;
> > +
> > +	/* Enable LCDC Clocks */
> > +	sinfo->bus_clk = clk_get(hw_dev, "hck1");
> > +	if (IS_ERR(sinfo->bus_clk)) {
> > +		ret = PTR_ERR(sinfo->bus_clk);
> > +		goto err;
> > +	}
> > +	sinfo->lcdc_clk = clk_get(hw_dev, "lcdc_clk");
> > +	if (IS_ERR(sinfo->lcdc_clk)) {
> > +		ret = PTR_ERR(sinfo->lcdc_clk);
> > +		goto put_bus_clk;
> > +	}
> > +
> > +	atmel_lcdfb_start_clock(sinfo);
> 
> This should be in .fb_enable.
need the clock always enable

Best Regards,
J.

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[PATCH 0/5 v2] at91 framebuffer support

[Jean-Christophe PLAGNIOL-VILLARD]

Hi,

	v2:
	 - mode header in include/video
	 - allocation info in driver

	The following patch serie add the support of the Framebuffer on at91
	sam9261/sam9263 and sam9g45. The sam9x5 series is not yet supported as
	they use an other IP.

	And enable it on sam0m10g45ek (9263ek and 9261ek will be availlable
	later).

	This is based on the next branch

The following changes since commit 6392955f283389fa4fecb0e2d5d1837bcb83f480:

  Merge branch 'for-next/testing-menu' into next (2012-09-20 23:11:42 +0200)

are available in the git repository at:


  git://git.jcrosoft.org/barebox.git delivery/atmel_fb

for you to fetch changes up to a60a81609fdc332ca8b84d2b8633dc59f8aacbc8:

  at91sam9m10g45ek: add lcdc support (2012-09-21 20:49:25 +0800)

----------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD (5):
      video: add atmel lcdc frambuffer support
      at91sam9263: add atmel lcdc frambuffer support
      at91sam9261: add atmel lcdc frambuffer support
      at91sam9g45: add atmel lcdc frambuffer support
      at91sam9m10g45ek: add lcdc support

 arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board |    7 +++
 arch/arm/boards/at91sam9m10g45ek/env/splash.png     |  Bin 0 -> 22747 bytes
 arch/arm/boards/at91sam9m10g45ek/init.c             |   35 +++++++++++++
 arch/arm/configs/at91sam9m10g45ek_defconfig         |   11 ++--
 arch/arm/mach-at91/at91sam9261.c                    |    1 +
 arch/arm/mach-at91/at91sam9261_devices.c            |   51 ++++++++++++++++++
 arch/arm/mach-at91/at91sam9263.c                    |    1 +
 arch/arm/mach-at91/at91sam9263_devices.c            |   40 +++++++++++++++
 arch/arm/mach-at91/at91sam9g45.c                    |    1 +
 arch/arm/mach-at91/at91sam9g45_devices.c            |   49 ++++++++++++++++++
 arch/arm/mach-at91/include/mach/atmel_lcdc.h        |  209 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-at91/include/mach/board.h             |    4 ++
 drivers/video/Kconfig                               |    4 ++
 drivers/video/Makefile                              |    1 +
 drivers/video/atmel_lcdfb.c                         |  477 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 15 files changed, 888 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/boards/at91sam9m10g45ek/env/splash.png
 create mode 100644 arch/arm/mach-at91/include/mach/atmel_lcdc.h
 create mode 100644 drivers/video/atmel_lcdfb.c

Best Regards,
J.

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[PATCH 1/5] video: add atmel lcdc frambuffer support

[Jean-Christophe PLAGNIOL-VILLARD]

This IP is present on the at91sam9 until the sam9g45, on the sam9x5 we use a
new IP.

This driver is based on the linux one.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/mach-at91/include/mach/board.h |    4 +
 drivers/video/Kconfig                   |    4 +
 drivers/video/Makefile                  |    1 +
 drivers/video/atmel_lcdfb.c             |  480 +++++++++++++++++++++++++++++++
 include/video/atmel_lcdc.h              |  211 ++++++++++++++
 5 files changed, 700 insertions(+)
 create mode 100644 drivers/video/atmel_lcdfb.c
 create mode 100644 include/video/atmel_lcdc.h

diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 670c73d..dccc37a 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -23,6 +23,8 @@
 #include <net.h>
 #include <spi/spi.h>
 #include <linux/mtd/mtd.h>
+#include <fb.h>
+#include <video/atmel_lcdc.h>
 
  /* USB Host */
 struct at91_usbh_data {
@@ -154,4 +156,6 @@ struct at91_spi_platform_data {
 };
 
 void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata);
+
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
 #endif
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 519cdbf..38dbb7a 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -5,6 +5,10 @@ menuconfig VIDEO
 
 if VIDEO
 
+config DRIVER_VIDEO_ATMEL
+	bool "Atmel LCDC framebuffer driver"
+	depends on ARCH_AT91
+
 config DRIVER_VIDEO_IMX
 	bool "i.MX framebuffer driver"
 	depends on ARCH_IMX1 || ARCH_IMX21 || ARCH_IMX25 || ARCH_IMX27
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 913c78d..dcadcf6 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_DRIVER_VIDEO_IMX) += imx.o
 obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
 obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
 obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
+obj-$(CONFIG_DRIVER_VIDEO_ATMEL) += atmel_lcdfb.o
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
new file mode 100644
index 0000000..cdd3c37
--- /dev/null
+++ b/drivers/video/atmel_lcdfb.c
@@ -0,0 +1,480 @@
+/*
+ * Driver for AT91/AT32 LCD Controller
+ *
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <io.h>
+#include <init.h>
+#include <linux/clk.h>
+#include <fb.h>
+#include <video/atmel_lcdc.h>
+#include <mach/hardware.h>
+#include <mach/io.h>
+#include <mach/cpu.h>
+#include <errno.h>
+#include <linux/err.h>
+#include <malloc.h>
+#include <asm/mmu.h>
+
+#define lcdc_readl(sinfo, reg)		__raw_readl((sinfo)->mmio+(reg))
+#define lcdc_writel(sinfo, reg, val)	__raw_writel((val), (sinfo)->mmio+(reg))
+
+/* configurable parameters */
+#define ATMEL_LCDC_CVAL_DEFAULT		0xc8
+#define ATMEL_LCDC_DMA_BURST_LEN	8	/* words */
+#define ATMEL_LCDC_FIFO_SIZE		512	/* words */
+
+static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
+{
+	clk_enable(sinfo->bus_clk);
+	clk_enable(sinfo->lcdc_clk);
+}
+
+static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
+{
+	clk_disable(sinfo->bus_clk);
+	clk_disable(sinfo->lcdc_clk);
+}
+
+static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
+{
+	unsigned long value;
+
+	if (!(cpu_is_at91sam9261() || cpu_is_at91sam9g10()
+		|| cpu_is_at32ap7000()))
+		return xres;
+
+	value = xres;
+	if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
+		/* STN display */
+		if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR)
+			value *= 3;
+
+		if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
+		   || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
+		      && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
+			value = DIV_ROUND_UP(value, 4);
+		else
+			value = DIV_ROUND_UP(value, 8);
+	}
+
+	return value;
+}
+
+static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo)
+{
+	/* Turn off the LCD controller and the DMA controller */
+	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
+			sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
+
+	/* Wait for the LCDC core to become idle */
+	while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
+		mdelay(10);
+
+	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
+}
+
+static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo)
+{
+	atmel_lcdfb_stop_nowait(sinfo);
+
+	/* Wait for DMA engine to become idle... */
+	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
+		mdelay(10);
+}
+
+static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
+{
+	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
+	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
+		(sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
+		| ATMEL_LCDC_PWR);
+}
+
+/**
+ * @param fb_info Framebuffer information
+ */
+static void atmel_lcdc_enable_controller(struct fb_info *fb_info)
+{
+	struct atmel_lcdfb_info *sinfo = fb_info->priv;
+
+	if (sinfo->atmel_lcdfb_power_control)
+		sinfo->atmel_lcdfb_power_control(1);
+}
+
+/**
+ * @param fb_info Framebuffer information
+ */
+static void atmel_lcdc_disable_controller(struct fb_info *fb_info)
+{
+	struct atmel_lcdfb_info *sinfo = fb_info->priv;
+
+	if (sinfo->atmel_lcdfb_power_control)
+		sinfo->atmel_lcdfb_power_control(0);
+}
+
+static void atmel_lcdfb_update_dma(struct fb_info *info)
+{
+	struct atmel_lcdfb_info *sinfo = info->priv;
+	unsigned long dma_addr;
+
+	dma_addr = (unsigned long)info->screen_base;
+
+	dma_addr &= ~3UL;
+
+	/* Set framebuffer DMA base address and pixel offset */
+	lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
+}
+
+static void atmel_lcdfb_set_par(struct fb_info *info)
+{
+	struct atmel_lcdfb_info *sinfo = info->priv;
+	struct fb_videomode *mode = info->mode;
+	unsigned long clk_value_khz;
+	unsigned long value;
+	unsigned long pix_factor = 2;
+	unsigned long hozval_linesz;
+
+	atmel_lcdfb_stop(sinfo);
+
+	/* Re-initialize the DMA engine... */
+	dev_dbg(&info->dev, "  * update DMA engine\n");
+	atmel_lcdfb_update_dma(info);
+
+	/* ...set frame size and burst length = 8 words (?) */
+	value = (mode->yres * mode->xres * info->bits_per_pixel) / 32;
+	value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
+	lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
+
+	/* Now, the LCDC core... */
+
+	/* Set pixel clock */
+	if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es())
+		pix_factor = 1;
+
+	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
+
+	value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(mode->pixclock));
+
+	if (value < pix_factor) {
+		dev_notice(&info->dev, "Bypassing pixel clock divider\n");
+		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
+	} else {
+		value = (value / pix_factor) - 1;
+		dev_dbg(&info->dev, "  * programming CLKVAL = 0x%08lx\n",
+				value);
+		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
+				value << ATMEL_LCDC_CLKVAL_OFFSET);
+		mode->pixclock =
+			KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
+		dev_dbg(&info->dev, "  updated pixclk:     %lu KHz\n",
+					PICOS2KHZ(mode->pixclock));
+	}
+
+	/* Initialize control register 2 */
+	value = sinfo->default_lcdcon2;
+
+	if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
+		value |= ATMEL_LCDC_INVLINE_INVERTED;
+	if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
+		value |= ATMEL_LCDC_INVFRAME_INVERTED;
+
+	switch (info->bits_per_pixel) {
+		case 1:	value |= ATMEL_LCDC_PIXELSIZE_1; break;
+		case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
+		case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
+		case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
+		case 15: /* fall through */
+		case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
+		case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
+		case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
+		default: BUG(); break;
+	}
+	dev_dbg(&info->dev, "  * LCDCON2 = %08lx\n", value);
+	lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
+
+	/* Vertical timing */
+	value = (mode->vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
+	value |= mode->upper_margin << ATMEL_LCDC_VBP_OFFSET;
+	value |= mode->lower_margin;
+	dev_dbg(&info->dev, "  * LCDTIM1 = %08lx\n", value);
+	lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
+
+	/* Horizontal timing */
+	value = (mode->right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
+	value |= (mode->hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
+	value |= (mode->left_margin - 1);
+	dev_dbg(&info->dev, "  * LCDTIM2 = %08lx\n", value);
+	lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
+
+	/* Horizontal value (aka line size) */
+	hozval_linesz = compute_hozval(mode->xres,
+					lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
+
+	/* Display size */
+	value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
+	value |= mode->yres - 1;
+	dev_dbg(&info->dev, "  * LCDFRMCFG = %08lx\n", value);
+	lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
+
+	/* FIFO Threshold: Use formula from data sheet */
+	value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
+	lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
+
+	/* Toggle LCD_MODE every frame */
+	lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
+
+	/* Disable all interrupts */
+	lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
+
+	/* Enable FIFO & DMA errors */
+	lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
+
+	/* ...wait for DMA engine to become idle... */
+	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
+		mdelay(10);
+
+	atmel_lcdfb_start(sinfo);
+
+	dev_dbg(&info->dev, "  * DONE\n");
+}
+
+static int atmel_lcdfb_check_var(struct fb_info *info)
+{
+	struct device_d *dev = &info->dev;
+	struct atmel_lcdfb_info *sinfo = info->priv;
+	struct fb_videomode *mode = info->mode;
+	unsigned long clk_value_khz;
+
+	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
+
+	dev_dbg(dev, "%s:\n", __func__);
+
+	if (!(mode->pixclock && info->bits_per_pixel)) {
+		dev_err(dev, "needed value not specified\n");
+		return -EINVAL;
+	}
+
+	dev_dbg(dev, "  resolution: %ux%u\n", mode->xres, mode->yres);
+	dev_dbg(dev, "  pixclk:     %lu KHz\n", PICOS2KHZ(mode->pixclock));
+	dev_dbg(dev, "  bpp:        %u\n", info->bits_per_pixel);
+	dev_dbg(dev, "  clk:        %lu KHz\n", clk_value_khz);
+
+	if (PICOS2KHZ(mode->pixclock) > clk_value_khz) {
+		dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(mode->pixclock));
+		return -EINVAL;
+	}
+
+	/* Saturate vertical and horizontal timings at maximum values */
+	mode->vsync_len = min_t(u32, mode->vsync_len,
+			(ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
+	mode->upper_margin = min_t(u32, mode->upper_margin,
+			ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
+	mode->lower_margin = min_t(u32, mode->lower_margin,
+			ATMEL_LCDC_VFP);
+	mode->right_margin = min_t(u32, mode->right_margin,
+			(ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
+	mode->hsync_len = min_t(u32, mode->hsync_len,
+			(ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
+	mode->left_margin = min_t(u32, mode->left_margin,
+			ATMEL_LCDC_HBP + 1);
+
+	/* Some parameters can't be zero */
+	mode->vsync_len = max_t(u32, mode->vsync_len, 1);
+	mode->right_margin = max_t(u32, mode->right_margin, 1);
+	mode->hsync_len = max_t(u32, mode->hsync_len, 1);
+	mode->left_margin = max_t(u32, mode->left_margin, 1);
+
+	switch (info->bits_per_pixel) {
+	case 1:
+	case 2:
+	case 4:
+	case 8:
+		info->red.offset = info->green.offset = info->blue.offset = 0;
+		info->red.length = info->green.length = info->blue.length
+			= info->bits_per_pixel;
+		break;
+	case 16:
+		if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
+			/* RGB:565 mode */
+			info->red.offset = 11;
+			info->blue.offset = 0;
+		} else {
+			/* BGR:565 mode */
+			info->red.offset = 0;
+			info->blue.offset = 11;
+		}
+		info->green.offset = 5;
+		info->green.length = 6;
+		info->red.length = info->blue.length = 5;
+		break;
+	case 32:
+		info->transp.offset = 24;
+		info->transp.length = 8;
+		/* fall through */
+	case 24:
+		if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
+			/* RGB:888 mode */
+			info->red.offset = 16;
+			info->blue.offset = 0;
+		} else {
+			/* BGR:888 mode */
+			info->red.offset = 0;
+			info->blue.offset = 16;
+		}
+		info->green.offset = 8;
+		info->red.length = info->green.length = info->blue.length = 8;
+		break;
+	default:
+		dev_err(dev, "color depth %d not supported\n",
+					info->bits_per_pixel);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
+{
+	struct fb_info *info = sinfo->info;
+	struct fb_videomode *mode = info->mode;
+	unsigned int smem_len;
+
+	free(info->screen_base);
+
+	smem_len = (mode->xres * mode->yres
+		    * ((info->bits_per_pixel + 7) / 8));
+	smem_len = max(smem_len, sinfo->smem_len);
+
+	info->screen_base = dma_alloc_coherent(smem_len);
+
+	if (!info->screen_base)
+		return -ENOMEM;
+
+	memset(info->screen_base, 0, smem_len);
+
+	return 0;
+}
+
+/**
+ * Prepare the video hardware for a specified video mode
+ * @param fb_info Framebuffer information
+ * @param mode The video mode description to initialize
+ * @return 0 on success
+ */
+static int atmel_lcdc_activate_var(struct fb_info *info)
+{
+	struct atmel_lcdfb_info *sinfo = info->priv;
+	unsigned long value;
+	int ret;
+
+	ret = atmel_lcdfb_alloc_video_memory(sinfo);
+	if (ret)
+		return ret;
+
+	atmel_lcdfb_set_par(info);
+
+	/* Set contrast */
+	value = ATMEL_LCDC_PS_DIV8 |
+		ATMEL_LCDC_POL_POSITIVE |
+		ATMEL_LCDC_ENA_PWMENABLE;
+	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, value);
+	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
+
+	return atmel_lcdfb_check_var(info);
+}
+
+/*
+ * There is only one video hardware instance available.
+ * It makes no sense to dynamically allocate this data
+ */
+static struct fb_ops atmel_lcdc_ops = {
+	.fb_activate_var = atmel_lcdc_activate_var,
+	.fb_enable = atmel_lcdc_enable_controller,
+	.fb_disable = atmel_lcdc_disable_controller,
+};
+
+static int atmel_lcdc_probe(struct device_d *hw_dev)
+{
+	struct atmel_lcdfb_info *sinfo = hw_dev->platform_data;
+	int ret = 0;
+	struct fb_info *info;
+
+	if (!sinfo)
+		return -ENODEV;
+
+	sinfo->mmio = dev_request_mem_region(hw_dev, 0);
+
+	/* just init */
+	info = xzalloc(sizeof(struct fb_info));
+	sinfo->info = info;
+	info->priv = sinfo;
+	info->fbops = &atmel_lcdc_ops;
+	info->mode_list = sinfo->mode_list;
+	info->num_modes = sinfo->num_modes;
+	info->mode = &info->mode_list[0];
+	info->xres = info->mode->xres;
+	info->yres = info->mode->yres;
+	info->bits_per_pixel = sinfo->default_bpp;
+
+	/* Enable LCDC Clocks */
+	sinfo->bus_clk = clk_get(hw_dev, "hck1");
+	if (IS_ERR(sinfo->bus_clk)) {
+		ret = PTR_ERR(sinfo->bus_clk);
+		goto err;
+	}
+	sinfo->lcdc_clk = clk_get(hw_dev, "lcdc_clk");
+	if (IS_ERR(sinfo->lcdc_clk)) {
+		ret = PTR_ERR(sinfo->lcdc_clk);
+		goto put_bus_clk;
+	}
+
+	atmel_lcdfb_start_clock(sinfo);
+
+	ret = register_framebuffer(info);
+	if (ret != 0) {
+		dev_err(hw_dev, "Failed to register framebuffer\n");
+		goto stop_clk;
+	}
+
+	return ret;
+
+stop_clk:
+	atmel_lcdfb_stop_clock(sinfo);
+	clk_put(sinfo->lcdc_clk);
+put_bus_clk:
+	clk_put(sinfo->bus_clk);
+err:
+	return ret;
+}
+
+static struct driver_d atmel_lcdc_driver = {
+	.name	= "atmel_lcdfb",
+	.probe	= atmel_lcdc_probe,
+};
+
+static int atmel_lcdc_init(void)
+{
+	return register_driver(&atmel_lcdc_driver);
+}
+device_initcall(atmel_lcdc_init);
diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
new file mode 100644
index 0000000..1b3005f
--- /dev/null
+++ b/include/video/atmel_lcdc.h
@@ -0,0 +1,211 @@
+/*
+ *  Header file for AT91/AT32 LCD Controller
+ *
+ *  Data structure and register user interface
+ *
+ *  Copyright (C) 2007 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ATMEL_LCDC_H__
+#define __ATMEL_LCDC_H__
+
+/* Way LCD wires are connected to the chip:
+ * Some Atmel chips use BGR color mode (instead of standard RGB)
+ * A swapped wiring onboard can bring to RGB mode.
+ */
+#define ATMEL_LCDC_WIRING_BGR	0
+#define ATMEL_LCDC_WIRING_RGB	1
+#define ATMEL_LCDC_WIRING_RGB555	2
+
+
+ /* LCD Controller info data structure, stored in device platform_data */
+struct atmel_lcdfb_info {
+	struct fb_info		*info;
+	void __iomem		*mmio;
+	struct device_d		*device;
+
+	unsigned int		guard_time;
+	unsigned int		smem_len;
+	struct clk		*bus_clk;
+	struct clk		*lcdc_clk;
+
+	bool			lcdcon_is_backlight;
+	bool			lcdcon_pol_negative;
+	u8			saved_lcdcon;
+
+	u8			default_bpp;
+	u8			lcd_wiring_mode;
+	unsigned int		default_lcdcon2;
+	unsigned int		default_dmacon;
+	void (*atmel_lcdfb_power_control)(int on);
+	struct fb_videomode	*mode_list;
+	unsigned		num_modes;
+	u32			pseudo_palette[16];
+};
+
+#define ATMEL_LCDC_DMABADDR1	0x00
+#define ATMEL_LCDC_DMABADDR2	0x04
+#define ATMEL_LCDC_DMAFRMPT1	0x08
+#define ATMEL_LCDC_DMAFRMPT2	0x0c
+#define ATMEL_LCDC_DMAFRMADD1	0x10
+#define ATMEL_LCDC_DMAFRMADD2	0x14
+
+#define ATMEL_LCDC_DMAFRMCFG	0x18
+#define	ATMEL_LCDC_FRSIZE	(0x7fffff <<  0)
+#define	ATMEL_LCDC_BLENGTH_OFFSET	24
+#define	ATMEL_LCDC_BLENGTH	(0x7f     << ATMEL_LCDC_BLENGTH_OFFSET)
+
+#define ATMEL_LCDC_DMACON	0x1c
+#define	ATMEL_LCDC_DMAEN	(0x1 << 0)
+#define	ATMEL_LCDC_DMARST	(0x1 << 1)
+#define	ATMEL_LCDC_DMABUSY	(0x1 << 2)
+#define		ATMEL_LCDC_DMAUPDT	(0x1 << 3)
+#define		ATMEL_LCDC_DMA2DEN	(0x1 << 4)
+
+#define ATMEL_LCDC_DMA2DCFG	0x20
+#define		ATMEL_LCDC_ADDRINC_OFFSET	0
+#define		ATMEL_LCDC_ADDRINC		(0xffff)
+#define		ATMEL_LCDC_PIXELOFF_OFFSET	24
+#define		ATMEL_LCDC_PIXELOFF		(0x1f << 24)
+
+#define ATMEL_LCDC_LCDCON1	0x0800
+#define	ATMEL_LCDC_BYPASS	(1     <<  0)
+#define	ATMEL_LCDC_CLKVAL_OFFSET	12
+#define	ATMEL_LCDC_CLKVAL	(0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
+#define	ATMEL_LCDC_LINCNT	(0x7ff << 21)
+
+#define ATMEL_LCDC_LCDCON2	0x0804
+#define	ATMEL_LCDC_DISTYPE	(3 << 0)
+#define		ATMEL_LCDC_DISTYPE_STNMONO	(0 << 0)
+#define		ATMEL_LCDC_DISTYPE_STNCOLOR	(1 << 0)
+#define		ATMEL_LCDC_DISTYPE_TFT		(2 << 0)
+#define	ATMEL_LCDC_SCANMOD	(1 << 2)
+#define		ATMEL_LCDC_SCANMOD_SINGLE	(0 << 2)
+#define		ATMEL_LCDC_SCANMOD_DUAL		(1 << 2)
+#define	ATMEL_LCDC_IFWIDTH	(3 << 3)
+#define		ATMEL_LCDC_IFWIDTH_4		(0 << 3)
+#define		ATMEL_LCDC_IFWIDTH_8		(1 << 3)
+#define		ATMEL_LCDC_IFWIDTH_16		(2 << 3)
+#define	ATMEL_LCDC_PIXELSIZE	(7 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_1		(0 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_2		(1 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_4		(2 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_8		(3 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_16		(4 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_24		(5 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_32		(6 << 5)
+#define	ATMEL_LCDC_INVVD	(1 << 8)
+#define		ATMEL_LCDC_INVVD_NORMAL		(0 << 8)
+#define		ATMEL_LCDC_INVVD_INVERTED	(1 << 8)
+#define	ATMEL_LCDC_INVFRAME	(1 << 9 )
+#define		ATMEL_LCDC_INVFRAME_NORMAL	(0 << 9)
+#define		ATMEL_LCDC_INVFRAME_INVERTED	(1 << 9)
+#define	ATMEL_LCDC_INVLINE	(1 << 10)
+#define		ATMEL_LCDC_INVLINE_NORMAL	(0 << 10)
+#define		ATMEL_LCDC_INVLINE_INVERTED	(1 << 10)
+#define	ATMEL_LCDC_INVCLK	(1 << 11)
+#define		ATMEL_LCDC_INVCLK_NORMAL	(0 << 11)
+#define		ATMEL_LCDC_INVCLK_INVERTED	(1 << 11)
+#define	ATMEL_LCDC_INVDVAL	(1 << 12)
+#define		ATMEL_LCDC_INVDVAL_NORMAL	(0 << 12)
+#define		ATMEL_LCDC_INVDVAL_INVERTED	(1 << 12)
+#define	ATMEL_LCDC_CLKMOD	(1 << 15)
+#define		ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY	(0 << 15)
+#define		ATMEL_LCDC_CLKMOD_ALWAYSACTIVE	(1 << 15)
+#define	ATMEL_LCDC_MEMOR	(1 << 31)
+#define		ATMEL_LCDC_MEMOR_BIG		(0 << 31)
+#define		ATMEL_LCDC_MEMOR_LITTLE		(1 << 31)
+
+#define ATMEL_LCDC_TIM1		0x0808
+#define	ATMEL_LCDC_VFP		(0xffU <<  0)
+#define	ATMEL_LCDC_VBP_OFFSET		8
+#define	ATMEL_LCDC_VBP		(0xffU <<  ATMEL_LCDC_VBP_OFFSET)
+#define	ATMEL_LCDC_VPW_OFFSET		16
+#define	ATMEL_LCDC_VPW		(0x3fU << ATMEL_LCDC_VPW_OFFSET)
+#define	ATMEL_LCDC_VHDLY_OFFSET		24
+#define	ATMEL_LCDC_VHDLY	(0xfU  << ATMEL_LCDC_VHDLY_OFFSET)
+
+#define ATMEL_LCDC_TIM2		0x080c
+#define	ATMEL_LCDC_HBP		(0xffU  <<  0)
+#define	ATMEL_LCDC_HPW_OFFSET		8
+#define	ATMEL_LCDC_HPW		(0x3fU  <<  ATMEL_LCDC_HPW_OFFSET)
+#define	ATMEL_LCDC_HFP_OFFSET		21
+#define	ATMEL_LCDC_HFP		(0x7ffU << ATMEL_LCDC_HFP_OFFSET)
+
+#define ATMEL_LCDC_LCDFRMCFG	0x0810
+#define	ATMEL_LCDC_LINEVAL	(0x7ff <<  0)
+#define	ATMEL_LCDC_HOZVAL_OFFSET	21
+#define	ATMEL_LCDC_HOZVAL	(0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
+
+#define ATMEL_LCDC_FIFO		0x0814
+#define	ATMEL_LCDC_FIFOTH	(0xffff)
+
+#define ATMEL_LCDC_MVAL		0x0818
+
+#define ATMEL_LCDC_DP1_2	0x081c
+#define ATMEL_LCDC_DP4_7	0x0820
+#define ATMEL_LCDC_DP3_5	0x0824
+#define ATMEL_LCDC_DP2_3	0x0828
+#define ATMEL_LCDC_DP5_7	0x082c
+#define ATMEL_LCDC_DP3_4	0x0830
+#define ATMEL_LCDC_DP4_5	0x0834
+#define ATMEL_LCDC_DP6_7	0x0838
+#define	ATMEL_LCDC_DP1_2_VAL	(0xff)
+#define	ATMEL_LCDC_DP4_7_VAL	(0xfffffff)
+#define	ATMEL_LCDC_DP3_5_VAL	(0xfffff)
+#define	ATMEL_LCDC_DP2_3_VAL	(0xfff)
+#define	ATMEL_LCDC_DP5_7_VAL	(0xfffffff)
+#define	ATMEL_LCDC_DP3_4_VAL	(0xffff)
+#define	ATMEL_LCDC_DP4_5_VAL	(0xfffff)
+#define	ATMEL_LCDC_DP6_7_VAL	(0xfffffff)
+
+#define ATMEL_LCDC_PWRCON	0x083c
+#define	ATMEL_LCDC_PWR		(1    <<  0)
+#define	ATMEL_LCDC_GUARDT_OFFSET	1
+#define	ATMEL_LCDC_GUARDT	(0x7f <<  ATMEL_LCDC_GUARDT_OFFSET)
+#define	ATMEL_LCDC_BUSY		(1    << 31)
+
+#define ATMEL_LCDC_CONTRAST_CTR	0x0840
+#define	ATMEL_LCDC_PS		(3 << 0)
+#define		ATMEL_LCDC_PS_DIV1		(0 << 0)
+#define		ATMEL_LCDC_PS_DIV2		(1 << 0)
+#define		ATMEL_LCDC_PS_DIV4		(2 << 0)
+#define		ATMEL_LCDC_PS_DIV8		(3 << 0)
+#define	ATMEL_LCDC_POL		(1 << 2)
+#define		ATMEL_LCDC_POL_NEGATIVE		(0 << 2)
+#define		ATMEL_LCDC_POL_POSITIVE		(1 << 2)
+#define	ATMEL_LCDC_ENA		(1 << 3)
+#define		ATMEL_LCDC_ENA_PWMDISABLE	(0 << 3)
+#define		ATMEL_LCDC_ENA_PWMENABLE	(1 << 3)
+
+#define ATMEL_LCDC_CONTRAST_VAL	0x0844
+#define	ATMEL_LCDC_CVAL	(0xff)
+
+#define ATMEL_LCDC_IER		0x0848
+#define ATMEL_LCDC_IDR		0x084c
+#define ATMEL_LCDC_IMR		0x0850
+#define ATMEL_LCDC_ISR		0x0854
+#define ATMEL_LCDC_ICR		0x0858
+#define	ATMEL_LCDC_LNI		(1 << 0)
+#define	ATMEL_LCDC_LSTLNI	(1 << 1)
+#define	ATMEL_LCDC_EOFI		(1 << 2)
+#define	ATMEL_LCDC_UFLWI	(1 << 4)
+#define	ATMEL_LCDC_OWRI		(1 << 5)
+#define	ATMEL_LCDC_MERI		(1 << 6)
+
+#define ATMEL_LCDC_LUT(n)	(0x0c00 + ((n)*4))
+
+#endif /* __ATMEL_LCDC_H__ */
-- 
1.7.10.4


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[PATCH 2/5] at91sam9263: add atmel lcdc frambuffer support

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/mach-at91/at91sam9263.c         |    1 +
 arch/arm/mach-at91/at91sam9263_devices.c |   40 ++++++++++++++++++++++++++++++
 2 files changed, 41 insertions(+)

diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index b3116d3..4f987d8 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -168,6 +168,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
+	CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb0", &lcdc_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index e686480..ba0b0b2 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -218,6 +218,46 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata)
 void __init at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {}
 #endif
 
+
+/* --------------------------------------------------------------------
+ *  LCD Controller
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_DRIVER_VIDEO_ATMEL)
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
+{
+	BUG_ON(!data);
+
+	at91_set_A_periph(AT91_PIN_PC1, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PC2, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDDEN */
+	at91_set_B_periph(AT91_PIN_PB9, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PC8, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PC9, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PC10, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PC11, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PC14, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
+	at91_set_A_periph(AT91_PIN_PC22, 0);	/* LCDD18 */
+	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD19 */
+	at91_set_A_periph(AT91_PIN_PC24, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD21 */
+	at91_set_A_periph(AT91_PIN_PC26, 0);	/* LCDD22 */
+	at91_set_A_periph(AT91_PIN_PC27, 0);	/* LCDD23 */
+
+	add_generic_device("atmel_lcdfb", 0, NULL, AT91SAM9263_LCDC_BASE, SZ_4K,
+			   IORESOURCE_MEM, data);
+}
+#else
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
+#endif
+
 resource_size_t __init at91_configure_dbgu(void)
 {
 	at91_set_A_periph(AT91_PIN_PC30, 0);		/* DRXD */
-- 
1.7.10.4


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