[PATCH 02/14] ARM i.MX35: give register base addresses a proper MX35_ prefix

[Sascha Hauer <s.hauer@pengutronix.de>]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c  |  100 ++++++------
 arch/arm/boards/eukrea_cpuimx35/lowlevel.c         |   24 +--
 arch/arm/boards/freescale-mx35-3-stack/3stack.c    |   78 +++++-----
 .../boards/freescale-mx35-3-stack/lowlevel_init.S  |    6 +-
 arch/arm/boards/guf-cupid/board.c                  |   74 ++++-----
 arch/arm/boards/guf-cupid/lowlevel.c               |   28 ++--
 arch/arm/boards/pcm043/lowlevel.c                  |   26 ++--
 arch/arm/boards/pcm043/pcm043.c                    |   78 +++++-----
 arch/arm/mach-imx/imx35.c                          |   14 +-
 arch/arm/mach-imx/include/mach/devices-imx35.h     |   34 ++--
 arch/arm/mach-imx/include/mach/imx35-regs.h        |  162 ++++++++++++++------
 arch/arm/mach-imx/speed-imx35.c                    |   30 ++--
 12 files changed, 368 insertions(+), 286 deletions(-)

diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
index 3c7fb69..53cc428 100644
--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
+++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
@@ -97,21 +97,21 @@ static void imx35_usb_init(void)
 	unsigned int tmp;
 
 	/* Host 1 */
-	tmp = readl(IMX_OTG_BASE + 0x600);
+	tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x600);
 	tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
 		MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
 	tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT;
 	tmp |= MX35_H1_USBTE_BIT | MX35_H1_PM_BIT | MX35_H1_TLL_BIT ;
 	tmp |= MX35_H1_IPPUE_DOWN_BIT;
-	writel(tmp, IMX_OTG_BASE + 0x600);
+	writel(tmp, MX35_USB_OTG_BASE_ADDR + 0x600);
 
-	tmp = readl(IMX_OTG_BASE + 0x584);
+	tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x584);
 	tmp |= 3 << 30;
-	writel(tmp, IMX_OTG_BASE + 0x584);
+	writel(tmp, MX35_USB_OTG_BASE_ADDR + 0x584);
 
 	/* Set to Host mode */
-	tmp = readl(IMX_OTG_BASE + 0x5a8);
-	writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
+	tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x5a8);
+	writel(tmp | 0x3, MX35_USB_OTG_BASE_ADDR + 0x5a8);
 }
 #endif
 
@@ -124,7 +124,7 @@ static struct fsl_usb2_platform_data usb_pdata = {
 
 static int eukrea_cpuimx35_mem_init(void)
 {
-	arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
+	arm_add_mem_device("ram0", MX35_CSD0_BASE_ADDR, 128 * 1024 * 1024);
 
 	return 0;
 }
@@ -216,13 +216,13 @@ static int eukrea_cpuimx35_devices_init(void)
 
 #ifdef CONFIG_USB
 	imx35_usb_init();
-	add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
+	add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX35_USB_HS_BASE_ADDR, NULL);
 #endif
 #ifdef CONFIG_USB_GADGET
 	/* Workaround ENGcm09152 */
-	tmp = readl(IMX_OTG_BASE + 0x608);
-	writel(tmp | (1 << 23), IMX_OTG_BASE + 0x608);
-	add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, IMX_OTG_BASE, 0x200,
+	tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x608);
+	writel(tmp | (1 << 23), MX35_USB_OTG_BASE_ADDR + 0x608);
+	add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, MX35_USB_OTG_BASE_ADDR, 0x200,
 			   IORESOURCE_MEM, &usb_pdata);
 #endif
 	armlinux_set_bootparams((void *)0x80000100);
@@ -246,70 +246,70 @@ static int eukrea_cpuimx35_core_init(void)
 	u32 reg;
 
 	/* enable clock for I2C1, SDHC1, USB and FEC */
-	reg = readl(IMX_CCM_BASE + CCM_CGR1);
+	reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1);
 	reg |= 0x3 << CCM_CGR1_FEC_SHIFT;
 	reg |= 0x3 << CCM_CGR1_SDHC1_SHIFT;
 	reg |= 0x3 << CCM_CGR1_I2C1_SHIFT,
-	reg = writel(reg, IMX_CCM_BASE + CCM_CGR1);
-	reg = readl(IMX_CCM_BASE + CCM_CGR2);
+	reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR1);
+	reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR2);
 	reg |= 0x3 << CCM_CGR2_USB_SHIFT;
-	reg = writel(reg, IMX_CCM_BASE + CCM_CGR2);
+	reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR2);
 
 	/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
 	/*
 	 * Set all MPROTx to be non-bufferable, trusted for R/W,
 	 * not forced to user-mode.
 	 */
-	writel(0x77777777, IMX_AIPS1_BASE);
-	writel(0x77777777, IMX_AIPS1_BASE + 0x4);
-	writel(0x77777777, IMX_AIPS2_BASE);
-	writel(0x77777777, IMX_AIPS2_BASE + 0x4);
+	writel(0x77777777, MX35_AIPS1_BASE_ADDR);
+	writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
+	writel(0x77777777, MX35_AIPS2_BASE_ADDR);
+	writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
 
 	/*
 	 * Clear the on and off peripheral modules Supervisor Protect bit
 	 * for SDMA to access them. Did not change the AIPS control registers
 	 * (offset 0x20) access type
 	 */
-	writel(0x0, IMX_AIPS1_BASE + 0x40);
-	writel(0x0, IMX_AIPS1_BASE + 0x44);
-	writel(0x0, IMX_AIPS1_BASE + 0x48);
-	writel(0x0, IMX_AIPS1_BASE + 0x4C);
-	reg = readl(IMX_AIPS1_BASE + 0x50);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
+	reg = readl(MX35_AIPS1_BASE_ADDR + 0x50);
 	reg &= 0x00FFFFFF;
-	writel(reg, IMX_AIPS1_BASE + 0x50);
+	writel(reg, MX35_AIPS1_BASE_ADDR + 0x50);
 
-	writel(0x0, IMX_AIPS2_BASE + 0x40);
-	writel(0x0, IMX_AIPS2_BASE + 0x44);
-	writel(0x0, IMX_AIPS2_BASE + 0x48);
-	writel(0x0, IMX_AIPS2_BASE + 0x4C);
-	reg = readl(IMX_AIPS2_BASE + 0x50);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
+	reg = readl(MX35_AIPS2_BASE_ADDR + 0x50);
 	reg &= 0x00FFFFFF;
-	writel(reg, IMX_AIPS2_BASE + 0x50);
+	writel(reg, MX35_AIPS2_BASE_ADDR + 0x50);
 
 	/* MAX (Multi-Layer AHB Crossbar Switch) setup */
 
 	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
 #define MAX_PARAM1 0x00302154
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x000); /* for S0 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
 
 	/* SGPCR - always park on last master */
-	writel(0x10, IMX_MAX_BASE + 0x10);	/* for S0 */
-	writel(0x10, IMX_MAX_BASE + 0x110);	/* for S1 */
-	writel(0x10, IMX_MAX_BASE + 0x210);	/* for S2 */
-	writel(0x10, IMX_MAX_BASE + 0x310);	/* for S3 */
-	writel(0x10, IMX_MAX_BASE + 0x410);	/* for S4 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x10);	/* for S0 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x110);	/* for S1 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x210);	/* for S2 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x310);	/* for S3 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x410);	/* for S4 */
 
 	/* MGPCR - restore default values */
-	writel(0x0, IMX_MAX_BASE + 0x800);	/* for M0 */
-	writel(0x0, IMX_MAX_BASE + 0x900);	/* for M1 */
-	writel(0x0, IMX_MAX_BASE + 0xa00);	/* for M2 */
-	writel(0x0, IMX_MAX_BASE + 0xb00);	/* for M3 */
-	writel(0x0, IMX_MAX_BASE + 0xc00);	/* for M4 */
-	writel(0x0, IMX_MAX_BASE + 0xd00);	/* for M5 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0x800);	/* for M0 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0x900);	/* for M1 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xa00);	/* for M2 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xb00);	/* for M3 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xc00);	/* for M4 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xd00);	/* for M5 */
 
 	/*
 	 * M3IF Control Register (M3IFCTL)
@@ -324,7 +324,7 @@ static int eukrea_cpuimx35_core_init(void)
 	 *                                                       ------------
 	 *                                                        0x00000040
 	 */
-	writel(0x40, IMX_M3IF_BASE);
+	writel(0x40, MX35_M3IF_BASE_ADDR);
 
 	return 0;
 }
@@ -345,10 +345,10 @@ static int do_cpufreq(int argc, char *argv[])
 
 	switch (freq) {
 	case 399:
-		writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL);
+		writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL);
 		break;
 	case 532:
-		writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL);
+		writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
 		break;
 	default:
 		return COMMAND_ERROR_USAGE;
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
index b421dfc..60a438a 100644
--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
@@ -40,10 +40,10 @@ static void __bare_init __naked insdram(void)
 	uint32_t r;
 
 	/* Speed up NAND controller by adjusting the NFC divider */
-	r = readl(IMX_CCM_BASE + CCM_PDR4);
+	r = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
 	r &= ~(0xf << 28);
 	r |= 0x1 << 28;
-	writel(r, IMX_CCM_BASE + CCM_PDR4);
+	writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4);
 
 	/* setup a stack to be able to call imx_nand_load_image() */
 	r = STACK_BASE + STACK_SIZE - 12;
@@ -58,7 +58,7 @@ static void __bare_init __naked insdram(void)
 void __bare_init __naked board_init_lowlevel(void)
 {
 	uint32_t r, s;
-	unsigned long ccm_base = IMX_CCM_BASE;
+	unsigned long ccm_base = MX35_CCM_BASE_ADDR;
 #ifdef CONFIG_NAND_IMX_BOOT
 	unsigned int *trg, *src;
 	int i;
@@ -125,9 +125,9 @@ void __bare_init __naked board_init_lowlevel(void)
 	r |= 0x03000000;
 	writel(r, ccm_base + CCM_CGR2);
 
-	r = readl(IMX_L2CC_BASE + L2X0_AUX_CTRL);
+	r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
 	r |= 0x1000;
-	writel(r, IMX_L2CC_BASE + L2X0_AUX_CTRL);
+	writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
 
 	/* Skip SDRAM initialization if we run from RAM */
 	r = get_pc();
@@ -143,22 +143,22 @@ void __bare_init __naked board_init_lowlevel(void)
 
 	writel(0x0009572B, ESDCFG0);
 	writel(0x92220000, ESDCTL0);
-	writeb(0xda, IMX_SDRAM_CS0 + 0x400);
+	writeb(0xda, MX35_CSD0_BASE_ADDR + 0x400);
 	writel(0xA2220000, ESDCTL0);
-	writeb(0xda, IMX_SDRAM_CS0);
-	writeb(0xda, IMX_SDRAM_CS0);
+	writeb(0xda, MX35_CSD0_BASE_ADDR);
+	writeb(0xda, MX35_CSD0_BASE_ADDR);
 	writel(0xB2220000, ESDCTL0);
-	writeb(0xda, IMX_SDRAM_CS0 + 0x33);
-	writeb(0xda, IMX_SDRAM_CS0 + 0x2000000);
+	writeb(0xda, MX35_CSD0_BASE_ADDR + 0x33);
+	writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000);
 	writel(0x82228080, ESDCTL0);
 
 #ifdef CONFIG_NAND_IMX_BOOT
 	/* skip NAND boot if not running from NFC space */
 	r = get_pc();
-	if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
+	if (r < MX35_NFC_BASE_ADDR || r > MX35_NFC_BASE_ADDR + 0x800)
 		board_init_lowlevel_return();
 
-	src = (unsigned int *)IMX_NFC_BASE;
+	src = (unsigned int *)MX35_NFC_BASE_ADDR;
 	trg = (unsigned int *)_text;
 
 	/* Move ourselves out of NFC SRAM */
diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
index 199841f..3d4a9cf 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
@@ -128,8 +128,8 @@ static void set_board_rev(int rev)
 
 static int f3s_mem_init(void)
 {
-	arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
-	arm_add_mem_device("ram1", IMX_SDRAM_CS1, 128 * 1024 * 1024);
+	arm_add_mem_device("ram0", MX35_CSD0_BASE_ADDR, 128 * 1024 * 1024);
+	arm_add_mem_device("ram1", MX35_CSD1_BASE_ADDR, 128 * 1024 * 1024);
 
 	return 0;
 }
@@ -144,7 +144,7 @@ static int f3s_devices_init(void)
 	writel(0x10000d03, CSCR_L(0));
 	writel(0x00720900, CSCR_A(0));
 
-	reg = readl(IMX_CCM_BASE + CCM_RCSR);
+	reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
 	/* some fuses provide us vital information about connected hardware */
 	if (reg & 0x20000000)
 		nand_info.width = 2;	/* 16 bit */
@@ -155,7 +155,7 @@ static int f3s_devices_init(void)
 	 * This platform supports NOR and NAND
 	 */
 	imx35_add_nand(&nand_info);
-	add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, 64 * 1024 * 1024, 0);
+	add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 64 * 1024 * 1024, 0);
 
 	switch ((reg >> 25) & 0x3) {
 	case 0x01:		/* NAND is the source */
@@ -178,7 +178,7 @@ static int f3s_devices_init(void)
 	imx35_add_i2c0(NULL);
 
 	imx35_add_fec(&fec_info);
-	add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL,	IMX_CS5_BASE, IMX_CS5_RANGE,
+	add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL,	MX35_CS5_BASE_ADDR, MX35_CS5_SIZE,
 			IORESOURCE_MEM, NULL);
 
 	imx35_add_mmc0(NULL);
@@ -283,66 +283,66 @@ static int f3s_core_init(void)
 	writel(0x22220A00, CSCR_A(5));
 
 	/* enable clock for I2C1 and FEC */
-	reg = readl(IMX_CCM_BASE + CCM_CGR1);
+	reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1);
 	reg |= 0x3 << CCM_CGR1_FEC_SHIFT;
 	reg |= 0x3 << CCM_CGR1_I2C1_SHIFT;
-	reg = writel(reg, IMX_CCM_BASE + CCM_CGR1);
+	reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR1);
 
 	/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
 	/*
 	 * Set all MPROTx to be non-bufferable, trusted for R/W,
 	 * not forced to user-mode.
 	 */
-	writel(0x77777777, IMX_AIPS1_BASE);
-	writel(0x77777777, IMX_AIPS1_BASE + 0x4);
-	writel(0x77777777, IMX_AIPS2_BASE);
-	writel(0x77777777, IMX_AIPS2_BASE + 0x4);
+	writel(0x77777777, MX35_AIPS1_BASE_ADDR);
+	writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
+	writel(0x77777777, MX35_AIPS2_BASE_ADDR);
+	writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
 
 	/*
 	 * Clear the on and off peripheral modules Supervisor Protect bit
 	 * for SDMA to access them. Did not change the AIPS control registers
 	 * (offset 0x20) access type
 	 */
-	writel(0x0, IMX_AIPS1_BASE + 0x40);
-	writel(0x0, IMX_AIPS1_BASE + 0x44);
-	writel(0x0, IMX_AIPS1_BASE + 0x48);
-	writel(0x0, IMX_AIPS1_BASE + 0x4C);
-	reg = readl(IMX_AIPS1_BASE + 0x50);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
+	reg = readl(MX35_AIPS1_BASE_ADDR + 0x50);
 	reg &= 0x00FFFFFF;
-	writel(reg, IMX_AIPS1_BASE + 0x50);
+	writel(reg, MX35_AIPS1_BASE_ADDR + 0x50);
 
-	writel(0x0, IMX_AIPS2_BASE + 0x40);
-	writel(0x0, IMX_AIPS2_BASE + 0x44);
-	writel(0x0, IMX_AIPS2_BASE + 0x48);
-	writel(0x0, IMX_AIPS2_BASE + 0x4C);
-	reg = readl(IMX_AIPS2_BASE + 0x50);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
+	reg = readl(MX35_AIPS2_BASE_ADDR + 0x50);
 	reg &= 0x00FFFFFF;
-	writel(reg, IMX_AIPS2_BASE + 0x50);
+	writel(reg, MX35_AIPS2_BASE_ADDR + 0x50);
 
 	/* MAX (Multi-Layer AHB Crossbar Switch) setup */
 
 	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
 #define MAX_PARAM1 0x00302154
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x000); /* for S0 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
 
 	/* SGPCR - always park on last master */
-	writel(0x10, IMX_MAX_BASE + 0x10);	/* for S0 */
-	writel(0x10, IMX_MAX_BASE + 0x110);	/* for S1 */
-	writel(0x10, IMX_MAX_BASE + 0x210);	/* for S2 */
-	writel(0x10, IMX_MAX_BASE + 0x310);	/* for S3 */
-	writel(0x10, IMX_MAX_BASE + 0x410);	/* for S4 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x10);	/* for S0 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x110);	/* for S1 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x210);	/* for S2 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x310);	/* for S3 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x410);	/* for S4 */
 
 	/* MGPCR - restore default values */
-	writel(0x0, IMX_MAX_BASE + 0x800);	/* for M0 */
-	writel(0x0, IMX_MAX_BASE + 0x900);	/* for M1 */
-	writel(0x0, IMX_MAX_BASE + 0xa00);	/* for M2 */
-	writel(0x0, IMX_MAX_BASE + 0xb00);	/* for M3 */
-	writel(0x0, IMX_MAX_BASE + 0xc00);	/* for M4 */
-	writel(0x0, IMX_MAX_BASE + 0xd00);	/* for M5 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0x800);	/* for M0 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0x900);	/* for M1 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xa00);	/* for M2 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xb00);	/* for M3 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xc00);	/* for M4 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xd00);	/* for M5 */
 
 	return 0;
 }
diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
index d1be7e8..f5f0998 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
@@ -52,7 +52,7 @@ CCM_PDR0_W:		.word	0x00001000
 MPCTL_PARAM_399_W:	.word	MPCTL_PARAM_399
 MPCTL_PARAM_532_W:	.word	MPCTL_PARAM_532
 PPCTL_PARAM_W:		.word	PPCTL_PARAM_300
-CCM_BASE_ADDR_W:	.word	IMX_CCM_BASE
+CCM_BASE_ADDR_W:	.word	MX35_CCM_BASE_ADDR
 
 .globl board_init_lowlevel
 board_init_lowlevel:
@@ -155,8 +155,8 @@ board_init_lowlevel:
 #ifdef CONFIG_NAND_IMX_BOOT
 	ldr	sp, =STACK_BASE + STACK_SIZE - 12		/* Setup a temporary stack in SDRAM */
 
-	ldr	r0, =IMX_NFC_BASE		/* start of NFC SRAM */
-	ldr	r2, =IMX_NFC_BASE + 0x800	/* end of NFC SRAM */
+	ldr	r0, =MX35_NFC_BASE_ADDR		/* start of NFC SRAM */
+	ldr	r2, =MX35_NFC_BASE_ADDR + 0x800	/* end of NFC SRAM */
 
 	/* skip NAND boot if not running from NFC space */
 	cmp	pc, r0
diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c
index d5f2291..977d71c 100644
--- a/arch/arm/boards/guf-cupid/board.c
+++ b/arch/arm/boards/guf-cupid/board.c
@@ -95,7 +95,7 @@ static struct imx_ipu_fb_platform_data ipu_fb_data = {
 
 static int cupid_mem_init(void)
 {
-	arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
+	arm_add_mem_device("ram0", MX35_CSD0_BASE_ADDR, 128 * 1024 * 1024);
 
 	return 0;
 }
@@ -116,7 +116,7 @@ static int cupid_devices_init(void)
 	gpio_direction_output(GPIO_LCD_ENABLE, 0);
 	gpio_direction_output(GPIO_LCD_BACKLIGHT, 0);
 
-	reg = readl(IMX_CCM_BASE + CCM_RCSR);
+	reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
 	/* some fuses provide us vital information about connected hardware */
 	if (reg & 0x20000000)
 		nand_info.width = 2;    /* 16 bit */
@@ -250,56 +250,56 @@ static int cupid_core_setup(void)
 	 * Set all MPROTx to be non-bufferable, trusted for R/W,
 	 * not forced to user-mode.
 	 */
-	writel(0x77777777, IMX_AIPS1_BASE);
-	writel(0x77777777, IMX_AIPS1_BASE + 0x4);
-	writel(0x77777777, IMX_AIPS2_BASE);
-	writel(0x77777777, IMX_AIPS2_BASE + 0x4);
+	writel(0x77777777, MX35_AIPS1_BASE_ADDR);
+	writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
+	writel(0x77777777, MX35_AIPS2_BASE_ADDR);
+	writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
 
 	/*
 	 * Clear the on and off peripheral modules Supervisor Protect bit
 	 * for SDMA to access them. Did not change the AIPS control registers
 	 * (offset 0x20) access type
 	 */
-	writel(0x0, IMX_AIPS1_BASE + 0x40);
-	writel(0x0, IMX_AIPS1_BASE + 0x44);
-	writel(0x0, IMX_AIPS1_BASE + 0x48);
-	writel(0x0, IMX_AIPS1_BASE + 0x4C);
-	tmp = readl(IMX_AIPS1_BASE + 0x50);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
+	tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50);
 	tmp &= 0x00FFFFFF;
-	writel(tmp, IMX_AIPS1_BASE + 0x50);
+	writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50);
 
-	writel(0x0, IMX_AIPS2_BASE + 0x40);
-	writel(0x0, IMX_AIPS2_BASE + 0x44);
-	writel(0x0, IMX_AIPS2_BASE + 0x48);
-	writel(0x0, IMX_AIPS2_BASE + 0x4C);
-	tmp = readl(IMX_AIPS2_BASE + 0x50);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
+	tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50);
 	tmp &= 0x00FFFFFF;
-	writel(tmp, IMX_AIPS2_BASE + 0x50);
+	writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50);
 
 	/* MAX (Multi-Layer AHB Crossbar Switch) setup */
 
 	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
 #define MAX_PARAM1 0x00302154
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x0);   /* for S0 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0);   /* for S0 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
 
 	/* SGPCR - always park on last master */
-	writel(0x10, IMX_MAX_BASE + 0x10);	/* for S0 */
-	writel(0x10, IMX_MAX_BASE + 0x110);	/* for S1 */
-	writel(0x10, IMX_MAX_BASE + 0x210);	/* for S2 */
-	writel(0x10, IMX_MAX_BASE + 0x310);	/* for S3 */
-	writel(0x10, IMX_MAX_BASE + 0x410);	/* for S4 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x10);	/* for S0 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x110);	/* for S1 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x210);	/* for S2 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x310);	/* for S3 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x410);	/* for S4 */
 
 	/* MGPCR - restore default values */
-	writel(0x0, IMX_MAX_BASE + 0x800);	/* for M0 */
-	writel(0x0, IMX_MAX_BASE + 0x900);	/* for M1 */
-	writel(0x0, IMX_MAX_BASE + 0xa00);	/* for M2 */
-	writel(0x0, IMX_MAX_BASE + 0xb00);	/* for M3 */
-	writel(0x0, IMX_MAX_BASE + 0xc00);	/* for M4 */
-	writel(0x0, IMX_MAX_BASE + 0xd00);	/* for M5 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0x800);	/* for M0 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0x900);	/* for M1 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xa00);	/* for M2 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xb00);	/* for M3 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xc00);	/* for M4 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xd00);	/* for M5 */
 
 	writel(0x0000DCF6, CSCR_U(0)); /* CS0: NOR Flash */
 	writel(0x444A4541, CSCR_L(0));
@@ -318,7 +318,7 @@ static int cupid_core_setup(void)
 	 *                                                       ------------
 	 *                                                        0x00000040
 	 */
-	writel(0x40, IMX_M3IF_BASE);
+	writel(0x40, MX35_M3IF_BASE_ADDR);
 
 	return 0;
 }
@@ -339,10 +339,10 @@ static int do_cpufreq(int argc, char *argv[])
 
 	switch (freq) {
 	case 399:
-		writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL);
+		writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL);
 		break;
 	case 532:
-		writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL);
+		writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
 		break;
 	default:
 		return COMMAND_ERROR_USAGE;
diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c
index 0f7d753..0160144 100644
--- a/arch/arm/boards/guf-cupid/lowlevel.c
+++ b/arch/arm/boards/guf-cupid/lowlevel.c
@@ -47,10 +47,10 @@ static void __bare_init __naked insdram(void)
 	uint32_t r;
 
 	/* Speed up NAND controller by adjusting the NFC divider */
-	r = readl(IMX_CCM_BASE + CCM_PDR4);
+	r = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
 	r &= ~(0xf << 28);
 	r |= 0x1 << 28;
-	writel(r, IMX_CCM_BASE + CCM_PDR4);
+	writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4);
 
 	/* setup a stack to be able to call imx_nand_load_image() */
 	r = STACK_BASE + STACK_SIZE - 12;
@@ -65,7 +65,7 @@ static void __bare_init __naked insdram(void)
 static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_addr)
 {
 	volatile int loop;
-	void *r9 = (void *)IMX_SDRAM_CS0;
+	void *r9 = (void *)MX35_CSD0_BASE_ADDR;
 	u32 r11 = 0xda; /* dummy constant */
 	u32 r1, r0;
 
@@ -246,7 +246,7 @@ void __bare_init __naked board_init_lowlevel(void)
 
 #define	WDOG_WMCR 0x8
 	/* silence reset WDOG */
-	writew(0, IMX_WDOG_BASE + WDOG_WMCR);
+	writew(0, MX35_WDOG_BASE_ADDR + WDOG_WMCR);
 
 	/* Skip SDRAM initialization if we run from RAM */
 	r0 = get_pc();
@@ -296,27 +296,27 @@ void __bare_init __naked board_init_lowlevel(void)
 	/* Configure clocks */
 
 	/* setup cpu/bus clocks */
-	writel(0x003f4208, IMX_CCM_BASE + CCM_CCMR);
+	writel(0x003f4208, MX35_CCM_BASE_ADDR + CCM_CCMR);
 
 	/* configure MPLL */
-	writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL);
+	writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
 
 	/* configure PPLL */
-	writel(PPCTL_PARAM_300, IMX_CCM_BASE + CCM_PPCTL);
+	writel(PPCTL_PARAM_300, MX35_CCM_BASE_ADDR + CCM_PPCTL);
 
 	/* configure core dividers */
 	r0 = PDR0_CCM_PER_AHB(1) | PDR0_HSP_PODF(2);
 
-	writel(r0, IMX_CCM_BASE + CCM_PDR0);
+	writel(r0, MX35_CCM_BASE_ADDR + CCM_PDR0);
 
 	/* configure clock-gates */
-	r0 = readl(IMX_CCM_BASE + CCM_CGR0);
+	r0 = readl(MX35_CCM_BASE_ADDR + CCM_CGR0);
 	r0 |= 0x00300000;
-	writel(r0, IMX_CCM_BASE + CCM_CGR0);
+	writel(r0, MX35_CCM_BASE_ADDR + CCM_CGR0);
 
-	r0 = readl(IMX_CCM_BASE + CCM_CGR1);
+	r0 = readl(MX35_CCM_BASE_ADDR + CCM_CGR1);
 	r0 |= 0x00000c03;
-	writel(r0, IMX_CCM_BASE + CCM_CGR1);
+	writel(r0, MX35_CCM_BASE_ADDR + CCM_CGR1);
 
 	/* Configure SDRAM */
 	/* Try 32-Bit 256 MB DDR memory */
@@ -326,10 +326,10 @@ void __bare_init __naked board_init_lowlevel(void)
 #ifdef CONFIG_NAND_IMX_BOOT
 	/* skip NAND boot if not running from NFC space */
 	r0 = get_pc();
-	if (r0 < IMX_NFC_BASE || r0 > IMX_NFC_BASE + 0x800)
+	if (r0 < MX35_NFC_BASE_ADDR || r0 > MX35_NFC_BASE_ADDR + 0x800)
 		board_init_lowlevel_return();
 
-	src = (unsigned int *)IMX_NFC_BASE;
+	src = (unsigned int *)MX35_NFC_BASE_ADDR;
 	trg = (unsigned int *)_text;
 
 	/* Move ourselves out of NFC SRAM */
diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c
index 32d12dd..cff7330 100644
--- a/arch/arm/boards/pcm043/lowlevel.c
+++ b/arch/arm/boards/pcm043/lowlevel.c
@@ -45,10 +45,10 @@ static void __bare_init __naked insdram(void)
 	uint32_t r;
 
 	/* Speed up NAND controller by adjusting the NFC divider */
-	r = readl(IMX_CCM_BASE + CCM_PDR4);
+	r = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
 	r &= ~(0xf << 28);
 	r |= 0x1 << 28;
-	writel(r, IMX_CCM_BASE + CCM_PDR4);
+	writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4);
 
 	/* setup a stack to be able to call imx_nand_load_image() */
 	r = STACK_BASE + STACK_SIZE - 12;
@@ -63,8 +63,8 @@ static void __bare_init __naked insdram(void)
 void __bare_init __naked board_init_lowlevel(void)
 {
 	uint32_t r, s;
-	unsigned long ccm_base = IMX_CCM_BASE;
-	unsigned long iomuxc_base = IMX_IOMUXC_BASE;
+	unsigned long ccm_base = MX35_CCM_BASE_ADDR;
+	unsigned long iomuxc_base = MX35_IOMUXC_BASE_ADDR;
 #ifdef CONFIG_NAND_IMX_BOOT
 	unsigned int *trg, *src;
 	int i;
@@ -115,7 +115,7 @@ void __bare_init __naked board_init_lowlevel(void)
 	writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL);
 
 	/* Check silicon revision and use 532MHz if >=2.1 */
-	r = readl(IMX_IIM_BASE + 0x24);
+	r = readl(MX35_IIM_BASE_ADDR + 0x24);
 	if (r >= IMX35_CHIP_REVISION_2_1)
 		writel(CCM_PDR0_532, ccm_base + CCM_PDR0);
 	else
@@ -130,9 +130,9 @@ void __bare_init __naked board_init_lowlevel(void)
 	r |= 0x00000003;
 	writel(r, ccm_base + CCM_CGR1);
 
-	r = readl(IMX_L2CC_BASE + L2X0_AUX_CTRL);
+	r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
 	r |= 0x1000;
-	writel(r, IMX_L2CC_BASE + L2X0_AUX_CTRL);
+	writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
 
 	/* Skip SDRAM initialization if we run from RAM */
 	r = get_pc();
@@ -158,7 +158,7 @@ void __bare_init __naked board_init_lowlevel(void)
 	/* select Precharge-All mode */
 	writel(0x92220000, ESDCTL0);
 	/* Precharge-All */
-	writel(0x12345678, IMX_SDRAM_CS0 + 0x400);
+	writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400);
 
 	/* select Load-Mode-Register mode */
 	writel(0xB8001000, ESDCTL0);
@@ -174,13 +174,13 @@ void __bare_init __naked board_init_lowlevel(void)
 	/* select Precharge-All mode */
 	writel(0x92220000, ESDCTL0);
 	/* Precharge-All */
-	writel(0x12345678, IMX_SDRAM_CS0 + 0x400);
+	writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400);
 
 	/* select Manual-Refresh mode */
 	writel(0xA2220000, ESDCTL0);
 	/* Manual-Refresh 2 times */
-	writel(0x87654321, IMX_SDRAM_CS0);
-	writel(0x87654321, IMX_SDRAM_CS0);
+	writel(0x87654321, MX35_CSD0_BASE_ADDR);
+	writel(0x87654321, MX35_CSD0_BASE_ADDR);
 
 	/* select Load-Mode-Register mode */
 	writel(0xB2220000, ESDCTL0);
@@ -205,10 +205,10 @@ void __bare_init __naked board_init_lowlevel(void)
 #ifdef CONFIG_NAND_IMX_BOOT
 	/* skip NAND boot if not running from NFC space */
 	r = get_pc();
-	if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
+	if (r < MX35_NFC_BASE_ADDR || r > MX35_NFC_BASE_ADDR + 0x800)
 		board_init_lowlevel_return();
 
-	src = (unsigned int *)IMX_NFC_BASE;
+	src = (unsigned int *)MX35_NFC_BASE_ADDR;
 	trg = (unsigned int *)_text;
 
 	/* Move ourselves out of NFC SRAM */
diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c
index 3170161..3b4ec77 100644
--- a/arch/arm/boards/pcm043/pcm043.c
+++ b/arch/arm/boards/pcm043/pcm043.c
@@ -93,13 +93,13 @@ static struct fb_videomode pcm043_fb_mode[] = {
 static struct imx_ipu_fb_platform_data ipu_fb_data = {
 	.mode			= pcm043_fb_mode,
 	.num_modes		= ARRAY_SIZE(pcm043_fb_mode),
-	.framebuffer_ovl	= (void *) (IMX_SDRAM_CS0 + SZ_128M - SZ_1M),
+	.framebuffer_ovl	= (void *) (MX35_CSD0_BASE_ADDR + SZ_128M - SZ_1M),
 	.bpp			= 16,
 };
 
 static int pcm043_mem_init(void)
 {
-	arm_add_mem_device("ram0", IMX_SDRAM_CS0, SZ_128M);
+	arm_add_mem_device("ram0", MX35_CSD0_BASE_ADDR, SZ_128M);
 
 	return 0;
 }
@@ -128,7 +128,7 @@ static int imx35_devices_init(void)
 
 	led_gpio_register(&led0);
 
-	reg = readl(IMX_CCM_BASE + CCM_RCSR);
+	reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
 	/* some fuses provide us vital information about connected hardware */
 	if (reg & 0x20000000)
 		nand_info.width = 2;    /* 16 bit */
@@ -144,7 +144,7 @@ static int imx35_devices_init(void)
 	 * Up to 32MiB NOR type flash, connected to
 	 * CS line 0, data width is 16 bit
 	 */
-	add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, 32 * 1024 * 1024, 0);
+	add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 32 * 1024 * 1024, 0);
 
 	if ((reg & 0xc00) == 0x800) {   /* reset mode: external boot */
 		switch ( (reg >> 25) & 0x3) {
@@ -224,56 +224,56 @@ static int pcm043_core_setup(void)
 	 * Set all MPROTx to be non-bufferable, trusted for R/W,
 	 * not forced to user-mode.
 	 */
-	writel(0x77777777, IMX_AIPS1_BASE);
-	writel(0x77777777, IMX_AIPS1_BASE + 0x4);
-	writel(0x77777777, IMX_AIPS2_BASE);
-	writel(0x77777777, IMX_AIPS2_BASE + 0x4);
+	writel(0x77777777, MX35_AIPS1_BASE_ADDR);
+	writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
+	writel(0x77777777, MX35_AIPS2_BASE_ADDR);
+	writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
 
 	/*
 	 * Clear the on and off peripheral modules Supervisor Protect bit
 	 * for SDMA to access them. Did not change the AIPS control registers
 	 * (offset 0x20) access type
 	 */
-	writel(0x0, IMX_AIPS1_BASE + 0x40);
-	writel(0x0, IMX_AIPS1_BASE + 0x44);
-	writel(0x0, IMX_AIPS1_BASE + 0x48);
-	writel(0x0, IMX_AIPS1_BASE + 0x4C);
-	tmp = readl(IMX_AIPS1_BASE + 0x50);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
+	tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50);
 	tmp &= 0x00FFFFFF;
-	writel(tmp, IMX_AIPS1_BASE + 0x50);
+	writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50);
 
-	writel(0x0, IMX_AIPS2_BASE + 0x40);
-	writel(0x0, IMX_AIPS2_BASE + 0x44);
-	writel(0x0, IMX_AIPS2_BASE + 0x48);
-	writel(0x0, IMX_AIPS2_BASE + 0x4C);
-	tmp = readl(IMX_AIPS2_BASE + 0x50);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
+	tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50);
 	tmp &= 0x00FFFFFF;
-	writel(tmp, IMX_AIPS2_BASE + 0x50);
+	writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50);
 
 	/* MAX (Multi-Layer AHB Crossbar Switch) setup */
 
 	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
 #define MAX_PARAM1 0x00302154
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x0);   /* for S0 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
-	writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0);   /* for S0 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
 
 	/* SGPCR - always park on last master */
-	writel(0x10, IMX_MAX_BASE + 0x10);	/* for S0 */
-	writel(0x10, IMX_MAX_BASE + 0x110);	/* for S1 */
-	writel(0x10, IMX_MAX_BASE + 0x210);	/* for S2 */
-	writel(0x10, IMX_MAX_BASE + 0x310);	/* for S3 */
-	writel(0x10, IMX_MAX_BASE + 0x410);	/* for S4 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x10);	/* for S0 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x110);	/* for S1 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x210);	/* for S2 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x310);	/* for S3 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x410);	/* for S4 */
 
 	/* MGPCR - restore default values */
-	writel(0x0, IMX_MAX_BASE + 0x800);	/* for M0 */
-	writel(0x0, IMX_MAX_BASE + 0x900);	/* for M1 */
-	writel(0x0, IMX_MAX_BASE + 0xa00);	/* for M2 */
-	writel(0x0, IMX_MAX_BASE + 0xb00);	/* for M3 */
-	writel(0x0, IMX_MAX_BASE + 0xc00);	/* for M4 */
-	writel(0x0, IMX_MAX_BASE + 0xd00);	/* for M5 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0x800);	/* for M0 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0x900);	/* for M1 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xa00);	/* for M2 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xb00);	/* for M3 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xc00);	/* for M4 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xd00);	/* for M5 */
 
 	/*
 	 * M3IF Control Register (M3IFCTL)
@@ -288,7 +288,7 @@ static int pcm043_core_setup(void)
 	 *                                                       ------------
 	 *                                                        0x00000040
 	 */
-	writel(0x40, IMX_M3IF_BASE);
+	writel(0x40, MX35_M3IF_BASE_ADDR);
 
 	return 0;
 }
@@ -309,10 +309,10 @@ static int do_cpufreq(int argc, char *argv[])
 
 	switch (freq) {
 	case 399:
-		writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL);
+		writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL);
 		break;
 	case 532:
-		writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL);
+		writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
 		break;
 	default:
 		return COMMAND_ERROR_USAGE;
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index 579e148..2e94f17 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -22,7 +22,7 @@
 int imx_silicon_revision()
 {
 	uint32_t reg;
-	reg = readl(IMX_IIM_BASE + IIM_SREV);
+	reg = readl(MX35_IIM_BASE_ADDR + IIM_SREV);
 	/* 0×00 = TO 1.0, First silicon */
 	reg += IMX_CHIP_REV_1_0;
 
@@ -41,7 +41,7 @@ int imx_silicon_revision()
 
 static int imx35_l2_fix(void)
 {
-	writel(0x515, IMX_CLKCTL_BASE + L2_MEM_VAL);
+	writel(0x515, MX35_CLKCTL_BASE_ADDR + L2_MEM_VAL);
 
 	return 0;
 }
@@ -49,13 +49,13 @@ core_initcall(imx35_l2_fix);
 
 static int imx35_init(void)
 {
-	add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
+	add_generic_device("imx_iim", 0, NULL, MX35_IIM_BASE_ADDR, SZ_4K,
 			IORESOURCE_MEM, NULL);
 
-	add_generic_device("imx31-gpt", 0, NULL, 0x53f90000, 0x100, IORESOURCE_MEM, NULL);
-	add_generic_device("imx31-gpio", 0, NULL, 0x53fcc000, 0x1000, IORESOURCE_MEM, NULL);
-	add_generic_device("imx31-gpio", 1, NULL, 0x53fd0000, 0x1000, IORESOURCE_MEM, NULL);
-	add_generic_device("imx31-gpio", 2, NULL, 0x53fa4000, 0x1000, IORESOURCE_MEM, NULL);
+	add_generic_device("imx31-gpt", 0, NULL, MX35_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+	add_generic_device("imx-gpio", 0, NULL, MX35_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+	add_generic_device("imx-gpio", 1, NULL, MX35_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+	add_generic_device("imx-gpio", 2, NULL, MX35_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
 
 	return 0;
 }
diff --git a/arch/arm/mach-imx/include/mach/devices-imx35.h b/arch/arm/mach-imx/include/mach/devices-imx35.h
index 9ecaa35..27c49e7 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx35.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx35.h
@@ -3,60 +3,70 @@
 
 static inline struct device_d *imx35_add_i2c0(struct i2c_platform_data *pdata)
 {
-	return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata);
+	return imx_add_i2c((void *)MX35_I2C1_BASE_ADDR, 0, pdata);
 }
 
 static inline struct device_d *imx35_add_i2c1(struct i2c_platform_data *pdata)
 {
-	return imx_add_i2c((void *)IMX_I2C2_BASE, 1, pdata);
+	return imx_add_i2c((void *)MX35_I2C2_BASE_ADDR, 1, pdata);
 }
 
 static inline struct device_d *imx35_add_i2c2(struct i2c_platform_data *pdata)
 {
-	return imx_add_i2c((void *)IMX_I2C3_BASE, 2, pdata);
+	return imx_add_i2c((void *)MX35_I2C3_BASE_ADDR, 2, pdata);
 }
 
 static inline struct device_d *imx35_add_spi0(struct spi_imx_master *pdata)
 {
-	return imx_add_spi((void *)IMX_CSPI1_BASE, 0, pdata);
+	return imx_add_spi((void *)MX35_CSPI1_BASE_ADDR, 0, pdata);
+}
+
+static inline struct device_d *imx35_add_spi(struct spi_imx_master *pdata)
+{
+	return imx_add_spi((void *)MX35_CSPI2_BASE_ADDR, 1, pdata);
 }
 
 static inline struct device_d *imx35_add_uart0(void)
 {
-	return imx_add_uart((void *)IMX_UART1_BASE, 0);
+	return imx_add_uart((void *)MX35_UART1_BASE_ADDR, 0);
 }
 
 static inline struct device_d *imx35_add_uart1(void)
 {
-	return imx_add_uart((void *)IMX_UART2_BASE, 1);
+	return imx_add_uart((void *)MX35_UART2_BASE_ADDR, 1);
+}
+
+static inline struct device_d *imx35_add_uart2(void)
+{
+	return imx_add_uart((void *)MX35_UART3_BASE_ADDR, 2);
 }
 
 static inline struct device_d *imx35_add_nand(struct imx_nand_platform_data *pdata)
 {
-	return imx_add_nand((void *)IMX_NFC_BASE, pdata);
+	return imx_add_nand((void *)MX35_NFC_BASE_ADDR, pdata);
 }
 
 static inline struct device_d *imx35_add_fb(struct imx_ipu_fb_platform_data *pdata)
 {
-	return imx_add_ipufb((void *)IMX_IPU_BASE, pdata);
+	return imx_add_ipufb((void *)MX35_IPU_CTRL_BASE_ADDR, pdata);
 }
 
 static inline struct device_d *imx35_add_fec(struct fec_platform_data *pdata)
 {
-	return imx_add_fec((void *)IMX_FEC_BASE, pdata);
+	return imx_add_fec((void *)MX35_FEC_BASE_ADDR, pdata);
 }
 
 static inline struct device_d *imx35_add_mmc0(struct esdhc_platform_data *pdata)
 {
-	return imx_add_esdhc((void *)IMX_SDHC1_BASE, 0, pdata);
+	return imx_add_esdhc((void *)MX35_ESDHC1_BASE_ADDR, 0, pdata);
 }
 
 static inline struct device_d *imx35_add_mmc1(struct esdhc_platform_data *pdata)
 {
-	return imx_add_esdhc((void *)IMX_SDHC2_BASE, 1, pdata);
+	return imx_add_esdhc((void *)MX35_ESDHC2_BASE_ADDR, 1, pdata);
 }
 
 static inline struct device_d *imx35_add_mmc2(struct esdhc_platform_data *pdata)
 {
-	return imx_add_esdhc((void *)IMX_SDHC3_BASE, 2, pdata);
+	return imx_add_esdhc((void *)MX35_ESDHC3_BASE_ADDR, 2, pdata);
 }
diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h
index 5a4ab90..0a4f423 100644
--- a/arch/arm/mach-imx/include/mach/imx35-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx35-regs.h
@@ -19,6 +19,8 @@
 #ifndef __ASM_ARCH_MX35_REGS_H
 #define __ASM_ARCH_MX35_REGS_H
 
+#include <sizes.h>
+
 /*
  * sanity check
  */
@@ -26,32 +28,121 @@
 # error "Please do not include directly. Use imx-regs.h instead."
 #endif
 
-#define IMX_L2CC_BASE		0x30000000
-#define IMX_CLKCTL_BASE		0x43F0C000
-#define IMX_UART1_BASE		0x43F90000
-#define IMX_UART2_BASE		0x43F94000
-#define IMX_TIM1_BASE		0x53F90000
-#define IMX_IOMUXC_BASE		0x43FAC000
-#define IMX_WDT_BASE		0x53FDC000
-#define IMX_MAX_BASE		0x43F04000
-#define IMX_ESD_BASE		0xb8001000
-#define IMX_AIPS1_BASE		0x43F00000
-#define IMX_AIPS2_BASE		0x53F00000
-#define IMX_CCM_BASE		0x53F80000
-#define IMX_IIM_BASE		0x53FF0000
-#define IMX_M3IF_BASE		0xB8003000
-#define IMX_NFC_BASE		0xBB000000
-#define IMX_FEC_BASE		0x50038000
-#define IMX_I2C1_BASE		0x43F80000
-#define IMX_I2C2_BASE		0x43F98000
-#define IMX_I2C3_BASE		0x43F84000
-#define IMX_CSPI1_BASE		0x43FA4000
-#define IMX_SDHC1_BASE		0x53FB4000
-#define IMX_SDHC2_BASE		0x53FB8000
-#define IMX_SDHC3_BASE		0x53FBC000
-#define IMX_IPU_BASE		0x53FC0000
-#define IMX_OTG_BASE		0x53FF4000
-#define IMX_WDOG_BASE		0x53fdc000
+#define MX35_IRAM_BASE_ADDR		0x10000000	/* internal ram */
+#define MX35_IRAM_SIZE			SZ_128K
+
+#define MX35_L2CC_BASE_ADDR		0x30000000
+#define MX35_L2CC_SIZE			SZ_1M
+
+#define MX35_AIPS1_BASE_ADDR		0x43f00000
+#define MX35_AIPS1_SIZE			SZ_1M
+#define MX35_MAX_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x04000)
+#define MX35_EVTMON_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x08000)
+#define MX35_CLKCTL_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x0c000)
+#define MX35_ETB_SLOT4_BASE_ADDR		(MX35_AIPS1_BASE_ADDR + 0x10000)
+#define MX35_ETB_SLOT5_BASE_ADDR		(MX35_AIPS1_BASE_ADDR + 0x14000)
+#define MX35_ECT_CTIO_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x18000)
+#define MX35_I2C1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x80000)
+#define MX35_I2C3_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x84000)
+#define MX35_UART1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x90000)
+#define MX35_UART2_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x94000)
+#define MX35_I2C2_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x98000)
+#define MX35_OWIRE_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x9c000)
+#define MX35_SSI1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xa0000)
+#define MX35_CSPI1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xa4000)
+#define MX35_KPP_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xa8000)
+#define MX35_IOMUXC_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xac000)
+#define MX35_ECT_IP1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xb8000)
+#define MX35_ECT_IP2_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xbc000)
+
+#define MX35_SPBA0_BASE_ADDR		0x50000000
+#define MX35_SPBA0_SIZE			SZ_1M
+#define MX35_UART3_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x0c000)
+#define MX35_CSPI2_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x10000)
+#define MX35_SSI2_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x14000)
+#define MX35_ATA_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x20000)
+#define MX35_MSHC1_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x24000)
+#define MX35_FEC_BASE_ADDR		0x50038000
+#define MX35_SPBA_CTRL_BASE_ADDR		(MX35_SPBA0_BASE_ADDR + 0x3c000)
+
+#define MX35_AIPS2_BASE_ADDR		0x53f00000
+#define MX35_AIPS2_SIZE			SZ_1M
+#define MX35_CCM_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0x80000)
+#define MX35_GPT1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0x90000)
+#define MX35_EPIT1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0x94000)
+#define MX35_EPIT2_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0x98000)
+#define MX35_GPIO3_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xa4000)
+#define MX35_SCC_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xac000)
+#define MX35_RNGA_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xb0000)
+#define MX35_ESDHC1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xb4000)
+#define MX35_ESDHC2_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xb8000)
+#define MX35_ESDHC3_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xbc000)
+#define MX35_IPU_CTRL_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xc0000)
+#define MX35_AUDMUX_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xc4000)
+#define MX35_GPIO1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xcc000)
+#define MX35_GPIO2_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xd0000)
+#define MX35_SDMA_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xd4000)
+#define MX35_RTC_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xd8000)
+#define MX35_WDOG_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xdc000)
+#define MX35_PWM_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xe0000)
+#define MX35_CAN1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xe4000)
+#define MX35_CAN2_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xe8000)
+#define MX35_RTIC_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xec000)
+#define MX35_IIM_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xf0000)
+#define MX35_USB_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xf4000)
+#define MX35_USB_OTG_BASE_ADDR			(MX35_USB_BASE_ADDR + 0x0000)
+
+/*
+ * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
+ * HS.  When host support was implemented only a preliminary document was
+ * available, which told 0x400.  This works fine.
+ */
+#define MX35_USB_HS_BASE_ADDR			(MX35_USB_BASE_ADDR + 0x0400)
+
+#define MX35_ROMP_BASE_ADDR		0x60000000
+#define MX35_ROMP_SIZE			SZ_1M
+
+#define MX35_AVIC_BASE_ADDR		0x68000000
+#define MX35_AVIC_SIZE			SZ_1M
+
+/*
+ * Memory regions and CS
+ */
+#define MX35_IPU_MEM_BASE_ADDR		0x70000000
+#define MX35_CSD0_BASE_ADDR		0x80000000
+#define MX35_CSD1_BASE_ADDR		0x90000000
+
+#define MX35_CS0_BASE_ADDR		0xa0000000
+#define MX35_CS1_BASE_ADDR		0xa8000000
+#define MX35_CS2_BASE_ADDR		0xb0000000
+#define MX35_CS3_BASE_ADDR		0xb2000000
+
+#define MX35_CS4_BASE_ADDR		0xb4000000
+#define MX35_CS4_SIZE			SZ_32M
+
+#define MX35_CS5_BASE_ADDR		0xb6000000
+#define MX35_CS5_SIZE			SZ_32M
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define MX35_X_MEMC_BASE_ADDR		0xb8000000
+#define MX35_X_MEMC_SIZE		SZ_64K
+#define MX35_ESDCTL_BASE_ADDR			(MX35_X_MEMC_BASE_ADDR + 0x1000)
+#define MX35_WEIM_BASE_ADDR			(MX35_X_MEMC_BASE_ADDR + 0x2000)
+#define MX35_M3IF_BASE_ADDR			(MX35_X_MEMC_BASE_ADDR + 0x3000)
+#define MX35_EMI_CTL_BASE_ADDR			(MX35_X_MEMC_BASE_ADDR + 0x4000)
+#define MX35_PCMCIA_CTL_BASE_ADDR		MX35_EMI_CTL_BASE_ADDR
+
+#define MX35_NFC_BASE_ADDR		0xbb000000
+#define MX35_PCMCIA_MEM_BASE_ADDR	0xbc000000
+
+/* FIXME: Get rid of these */
+#define IMX_WDT_BASE	MX35_WDOG_BASE_ADDR
+#define IMX_TIM1_BASE	MX35_GPT1_BASE_ADDR
+#define IMX_ESD_BASE	MX35_ESDCTL_BASE_ADDR
+#define IMX_IOMUXC_BASE	MX35_IOMUXC_BASE_ADDR
+#define IMX_CCM_BASE	MX35_CCM_BASE_ADDR
 
 /*
  * Clock Controller Module (CCM)
@@ -88,25 +179,6 @@
 #define PDR0_AUTO_CON		(1 << 0)
 #define PDR0_PER_SEL		(1 << 26)
 
-/*
- * Adresses and ranges of the external chip select lines
- */
-#define IMX_CS0_BASE	0xA0000000
-#define IMX_CS0_RANGE	(128 * 1024 * 1024)
-#define IMX_CS1_BASE	0xA8000000
-#define IMX_CS1_RANGE	(128 * 1024 * 1024)
-#define IMX_CS2_BASE	0xB0000000
-#define IMX_CS2_RANGE	(32 * 1024 * 1024)
-#define IMX_CS3_BASE	0xB2000000
-#define IMX_CS3_RANGE	(32 * 1024 * 1024)
-#define IMX_CS4_BASE	0xB4000000
-#define IMX_CS4_RANGE	(32 * 1024 * 1024)
-#define IMX_CS5_BASE	0xB6000000
-#define IMX_CS5_RANGE	(32 * 1024 * 1024)
-
-#define IMX_SDRAM_CS0  0x80000000
-#define IMX_SDRAM_CS1  0x90000000
-
 #define WEIM_BASE 0xb8002000
 #define CSCR_U(x)     (WEIM_BASE + (x) * 0x10)
 #define CSCR_L(x)     (WEIM_BASE + 4 + (x) * 0x10)
diff --git a/arch/arm/mach-imx/speed-imx35.c b/arch/arm/mach-imx/speed-imx35.c
index a4e0120..a8063f2 100644
--- a/arch/arm/mach-imx/speed-imx35.c
+++ b/arch/arm/mach-imx/speed-imx35.c
@@ -21,13 +21,13 @@
 
 unsigned long imx_get_mpllclk(void)
 {
-	ulong mpctl = readl(IMX_CCM_BASE + CCM_MPCTL);
+	ulong mpctl = readl(MX35_CCM_BASE_ADDR + CCM_MPCTL);
 	return imx_decode_pll(mpctl, CONFIG_MX35_HCLK_FREQ);
 }
 
 static unsigned long imx_get_ppllclk(void)
 {
-	ulong ppctl = readl(IMX_CCM_BASE + CCM_PPCTL);
+	ulong ppctl = readl(MX35_CCM_BASE_ADDR + CCM_PPCTL);
 	return imx_decode_pll(ppctl, CONFIG_MX35_HCLK_FREQ);
 }
 
@@ -56,7 +56,7 @@ static struct arm_ahb_div clk_consumer[] = {
 
 static unsigned long imx_get_armclk(void)
 {
-	unsigned long pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
+	unsigned long pdr0 = readl(MX35_CCM_BASE_ADDR + CCM_PDR0);
 	struct arm_ahb_div *aad;
 	unsigned long fref = imx_get_mpllclk();
 
@@ -70,7 +70,7 @@ static unsigned long imx_get_armclk(void)
 
 unsigned long imx_get_ahbclk(void)
 {
-	unsigned long pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
+	unsigned long pdr0 = readl(MX35_CCM_BASE_ADDR + CCM_PDR0);
 	struct arm_ahb_div *aad;
 	unsigned long fref = imx_get_mpllclk();
 
@@ -100,8 +100,8 @@ static unsigned long get_6_div(unsigned long in)
 
 static unsigned long imx_get_ipg_perclk(void)
 {
-	ulong pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
-	ulong pdr4 = readl(IMX_CCM_BASE + CCM_PDR4);
+	ulong pdr0 = readl(MX35_CCM_BASE_ADDR + CCM_PDR0);
+	ulong pdr4 = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
 	ulong div;
 	ulong fref;
 
@@ -129,7 +129,7 @@ unsigned long imx_get_gptclk(void)
  */
 unsigned long imx_get_lcdclk(void)
 {
-	unsigned long hsp_podf = (readl(IMX_CCM_BASE + CCM_PDR0) >> 20) & 0x03;
+	unsigned long hsp_podf = (readl(MX35_CCM_BASE_ADDR + CCM_PDR0) >> 20) & 0x03;
 	unsigned long base_clk = imx_get_armclk();
 
 	if (base_clk > 400 * 1000 * 1000) {
@@ -156,8 +156,8 @@ unsigned long imx_get_lcdclk(void)
 
 unsigned long imx_get_uartclk(void)
 {
-	unsigned long pdr3 = readl(IMX_CCM_BASE + CCM_PDR3);
-	unsigned long pdr4 = readl(IMX_CCM_BASE + CCM_PDR4);
+	unsigned long pdr3 = readl(MX35_CCM_BASE_ADDR + CCM_PDR3);
+	unsigned long pdr4 = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
 	unsigned long div = get_3_3_div(pdr4 >> 10);
 
 	if (pdr3 & (1 << 14))
@@ -169,7 +169,7 @@ unsigned long imx_get_uartclk(void)
 /* mmc0 clk only */
 unsigned long imx_get_mmcclk(void)
 {
-	unsigned long pdr3 = readl(IMX_CCM_BASE + CCM_PDR3);
+	unsigned long pdr3 = readl(MX35_CCM_BASE_ADDR + CCM_PDR3);
 	unsigned long div = get_6_div(pdr3);
 
 	if (pdr3 & (1 << 6))
@@ -213,7 +213,7 @@ void imx_dump_clocks(void)
  */
 int imx_clko_set_div(int num, int div)
 {
-	unsigned long cosr = readl(IMX_CCM_BASE + CCM_COSR);
+	unsigned long cosr = readl(MX35_CCM_BASE_ADDR + CCM_COSR);
 
 	if (num != 1)
 		return -ENODEV;
@@ -224,7 +224,7 @@ int imx_clko_set_div(int num, int div)
 	cosr &= ~(0x3f << 10);
 	cosr |= div << 10;
 
-	writel(cosr, IMX_CCM_BASE + CCM_COSR);
+	writel(cosr, MX35_CCM_BASE_ADDR + CCM_COSR);
 
 	return div + 1;
 }
@@ -234,14 +234,14 @@ int imx_clko_set_div(int num, int div)
  */
 void imx_clko_set_src(int num, int src)
 {
-	unsigned long cosr = readl(IMX_CCM_BASE + CCM_COSR);
+	unsigned long cosr = readl(MX35_CCM_BASE_ADDR + CCM_COSR);
 
 	if (num != 1)
 		return;
 
 	if (src < 0) {
 		cosr &= ~(1 << 5);
-		writel(cosr, IMX_CCM_BASE + CCM_COSR);
+		writel(cosr, MX35_CCM_BASE_ADDR + CCM_COSR);
 		return;
 	}
 
@@ -250,6 +250,6 @@ void imx_clko_set_src(int num, int src)
 	cosr &= ~(1 << 6);
 	cosr |= src & 0x1f;
 
-	writel(cosr, IMX_CCM_BASE + CCM_COSR);
+	writel(cosr, MX35_CCM_BASE_ADDR + CCM_COSR);
 }
 
-- 
1.7.10.4


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