* [PATCH 01/23] err.h: introduce IS_ERR_OR_NULL
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 02/23] clk clkdev: Add clkdev matching based on physbase Sascha Hauer
` (21 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Copied from Linux.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/linux/err.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/linux/err.h b/include/linux/err.h
index e0d8d2d..19fb70d 100644
--- a/include/linux/err.h
+++ b/include/linux/err.h
@@ -34,6 +34,11 @@ static inline long IS_ERR(const void *ptr)
return IS_ERR_VALUE((unsigned long)ptr);
}
+static inline long __must_check IS_ERR_OR_NULL(const void *ptr)
+{
+ return !ptr || IS_ERR_VALUE((unsigned long)ptr);
+}
+
/**
* ERR_CAST - Explicitly cast an error-valued pointer to another pointer type
* @ptr: The pointer to cast.
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 02/23] clk clkdev: Add clkdev matching based on physbase
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
2012-09-24 11:04 ` [PATCH 01/23] err.h: introduce IS_ERR_OR_NULL Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-26 16:02 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-24 11:04 ` [PATCH 03/23] clk: initial common clk support Sascha Hauer
` (20 subsequent siblings)
22 siblings, 1 reply; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Most clock/device associations can be done based on the physical
base address of the corresponding device. So instead of depending
on string matching add an optional possibility to associate a clock
lookups with physical addresses. This also has the advantage that
the lookups for devicetree based devices can be identical to the
platform based devices.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clk/clkdev.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
include/linux/clkdev.h | 3 +++
2 files changed, 50 insertions(+)
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 717fea5..40bc006 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -62,6 +62,32 @@ static struct clk *clk_find(const char *dev_id, const char *con_id)
return clk;
}
+static struct clk *clk_find_physbase(struct device_d *dev, const char *con_id)
+{
+ struct clk_lookup *p;
+ unsigned long start;
+
+ if (!dev || !dev->resource)
+ return ERR_PTR(-ENOSYS);
+
+ start = dev->resource[0].start;
+
+ list_for_each_entry(p, &clocks, node) {
+ if (!p->physbase)
+ continue;
+ if (p->physbase != start)
+ continue;
+ if (p->con_id) {
+ if (!con_id || strcmp(p->con_id, con_id))
+ continue;
+ return p->clk;
+ }
+ return p->clk;
+ }
+ return ERR_PTR(-ENOSYS);
+
+}
+
struct clk *clk_get_sys(const char *dev_id, const char *con_id)
{
struct clk *clk;
@@ -77,6 +103,11 @@ EXPORT_SYMBOL(clk_get_sys);
struct clk *clk_get(struct device_d *dev, const char *con_id)
{
const char *dev_id = dev ? dev_name(dev) : NULL;
+ struct clk *clk;
+
+ clk = clk_find_physbase(dev, con_id);
+ if (!IS_ERR(clk))
+ return clk;
return clk_get_sys(dev_id, con_id);
}
@@ -166,3 +197,19 @@ void clkdev_drop(struct clk_lookup *cl)
kfree(cl);
}
EXPORT_SYMBOL(clkdev_drop);
+
+int clkdev_add_physbase(struct clk *clk, unsigned long base, const char *id)
+{
+ struct clk_lookup *cl;
+
+ cl = xzalloc(sizeof(*cl));
+
+ cl->clk = clk;
+ cl->con_id = id;
+ cl->physbase = base;
+
+ clkdev_add(cl);
+
+ return 0;
+}
+EXPORT_SYMBOL(clkdev_add_physbase);
diff --git a/include/linux/clkdev.h b/include/linux/clkdev.h
index d2eca99..d2f0d89 100644
--- a/include/linux/clkdev.h
+++ b/include/linux/clkdev.h
@@ -19,6 +19,7 @@ struct device_d;
struct clk_lookup {
struct list_head node;
+ unsigned long physbase;
const char *dev_id;
const char *con_id;
struct clk *clk;
@@ -33,6 +34,8 @@ void clkdev_drop(struct clk_lookup *cl);
void clkdev_add_table(struct clk_lookup *, size_t);
int clk_add_alias(const char *, const char *, char *, struct device_d *);
+int clkdev_add_physbase(struct clk *clk, unsigned long base, const char *id);
+
#define CLKDEV_DEV_ID(_id, _clk) \
{ \
.dev_id = _id, \
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 02/23] clk clkdev: Add clkdev matching based on physbase
2012-09-24 11:04 ` [PATCH 02/23] clk clkdev: Add clkdev matching based on physbase Sascha Hauer
@ 2012-09-26 16:02 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-26 17:25 ` Sascha Hauer
0 siblings, 1 reply; 34+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-26 16:02 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 13:04 Mon 24 Sep , Sascha Hauer wrote:
> Most clock/device associations can be done based on the physical
> base address of the corresponding device. So instead of depending
> on string matching add an optional possibility to associate a clock
> lookups with physical addresses. This also has the advantage that
> the lookups for devicetree based devices can be identical to the
> platform based devices.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> drivers/clk/clkdev.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
> include/linux/clkdev.h | 3 +++
> 2 files changed, 50 insertions(+)
>
> diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
> index 717fea5..40bc006 100644
> --- a/drivers/clk/clkdev.c
> +++ b/drivers/clk/clkdev.c
> @@ -62,6 +62,32 @@ static struct clk *clk_find(const char *dev_id, const char *con_id)
> return clk;
> }
>
> +static struct clk *clk_find_physbase(struct device_d *dev, const char *con_id)
> +{
> + struct clk_lookup *p;
> + unsigned long start;
> +
> + if (!dev || !dev->resource)
> + return ERR_PTR(-ENOSYS);
this is broken
clk_get_sys(NULL, "toto") is a valid call
Best Regars,
J.
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^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 02/23] clk clkdev: Add clkdev matching based on physbase
2012-09-26 16:02 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-09-26 17:25 ` Sascha Hauer
2012-09-26 18:53 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-26 19:08 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 2 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-26 17:25 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Wed, Sep 26, 2012 at 06:02:39PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 13:04 Mon 24 Sep , Sascha Hauer wrote:
> > Most clock/device associations can be done based on the physical
> > base address of the corresponding device. So instead of depending
> > on string matching add an optional possibility to associate a clock
> > lookups with physical addresses. This also has the advantage that
> > the lookups for devicetree based devices can be identical to the
> > platform based devices.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > drivers/clk/clkdev.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
> > include/linux/clkdev.h | 3 +++
> > 2 files changed, 50 insertions(+)
> >
> > diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
> > index 717fea5..40bc006 100644
> > --- a/drivers/clk/clkdev.c
> > +++ b/drivers/clk/clkdev.c
> > @@ -62,6 +62,32 @@ static struct clk *clk_find(const char *dev_id, const char *con_id)
> > return clk;
> > }
> >
> > +static struct clk *clk_find_physbase(struct device_d *dev, const char *con_id)
> > +{
> > + struct clk_lookup *p;
> > + unsigned long start;
> > +
> > + if (!dev || !dev->resource)
> > + return ERR_PTR(-ENOSYS);
> this is broken
>
> clk_get_sys(NULL, "toto") is a valid call
clk_get_sys never calls clk_find_physbase. clk_get(NULL, "toto") will
call clk_find_physbase in which case clk_find_physbase returns -ENOSYS
and clk_get falls back to clk_get_sys just as it did before.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 02/23] clk clkdev: Add clkdev matching based on physbase
2012-09-26 17:25 ` Sascha Hauer
@ 2012-09-26 18:53 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-26 19:09 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-26 19:08 ` Jean-Christophe PLAGNIOL-VILLARD
1 sibling, 1 reply; 34+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-26 18:53 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 19:25 Wed 26 Sep , Sascha Hauer wrote:
> On Wed, Sep 26, 2012 at 06:02:39PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 13:04 Mon 24 Sep , Sascha Hauer wrote:
> > > Most clock/device associations can be done based on the physical
> > > base address of the corresponding device. So instead of depending
> > > on string matching add an optional possibility to associate a clock
> > > lookups with physical addresses. This also has the advantage that
> > > the lookups for devicetree based devices can be identical to the
> > > platform based devices.
> > >
> > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > ---
> > > drivers/clk/clkdev.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
> > > include/linux/clkdev.h | 3 +++
> > > 2 files changed, 50 insertions(+)
> > >
> > > diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
> > > index 717fea5..40bc006 100644
> > > --- a/drivers/clk/clkdev.c
> > > +++ b/drivers/clk/clkdev.c
> > > @@ -62,6 +62,32 @@ static struct clk *clk_find(const char *dev_id, const char *con_id)
> > > return clk;
> > > }
> > >
> > > +static struct clk *clk_find_physbase(struct device_d *dev, const char *con_id)
> > > +{
> > > + struct clk_lookup *p;
> > > + unsigned long start;
> > > +
> > > + if (!dev || !dev->resource)
> > > + return ERR_PTR(-ENOSYS);
> > this is broken
> >
> > clk_get_sys(NULL, "toto") is a valid call
>
> clk_get_sys never calls clk_find_physbase. clk_get(NULL, "toto") will
> call clk_find_physbase in which case clk_find_physbase returns -ENOSYS
> and clk_get falls back to clk_get_sys just as it did before.
it's clk_get (NULL, "toto)
that fail which is basilcally used on at91
and a device without resources cannot get it's clock
Best Regards,
J.
>
> Sascha
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 02/23] clk clkdev: Add clkdev matching based on physbase
2012-09-26 18:53 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-09-26 19:09 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 34+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-26 19:09 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 20:53 Wed 26 Sep , Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 19:25 Wed 26 Sep , Sascha Hauer wrote:
> > On Wed, Sep 26, 2012 at 06:02:39PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > On 13:04 Mon 24 Sep , Sascha Hauer wrote:
> > > > Most clock/device associations can be done based on the physical
> > > > base address of the corresponding device. So instead of depending
> > > > on string matching add an optional possibility to associate a clock
> > > > lookups with physical addresses. This also has the advantage that
> > > > the lookups for devicetree based devices can be identical to the
> > > > platform based devices.
> > > >
> > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > > ---
> > > > drivers/clk/clkdev.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
> > > > include/linux/clkdev.h | 3 +++
> > > > 2 files changed, 50 insertions(+)
> > > >
> > > > diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
> > > > index 717fea5..40bc006 100644
> > > > --- a/drivers/clk/clkdev.c
> > > > +++ b/drivers/clk/clkdev.c
> > > > @@ -62,6 +62,32 @@ static struct clk *clk_find(const char *dev_id, const char *con_id)
> > > > return clk;
> > > > }
> > > >
> > > > +static struct clk *clk_find_physbase(struct device_d *dev, const char *con_id)
> > > > +{
> > > > + struct clk_lookup *p;
> > > > + unsigned long start;
> > > > +
> > > > + if (!dev || !dev->resource)
> > > > + return ERR_PTR(-ENOSYS);
> > > this is broken
> > >
> > > clk_get_sys(NULL, "toto") is a valid call
> >
> > clk_get_sys never calls clk_find_physbase. clk_get(NULL, "toto") will
> > call clk_find_physbase in which case clk_find_physbase returns -ENOSYS
> > and clk_get falls back to clk_get_sys just as it did before.
> it's clk_get (NULL, "toto)
>
> that fail which is basilcally used on at91
>
> and a device without resources cannot get it's clock
ignore this
Best Regards,
J.
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^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 02/23] clk clkdev: Add clkdev matching based on physbase
2012-09-26 17:25 ` Sascha Hauer
2012-09-26 18:53 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-09-26 19:08 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-26 21:31 ` Sascha Hauer
1 sibling, 1 reply; 34+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-26 19:08 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 19:25 Wed 26 Sep , Sascha Hauer wrote:
> On Wed, Sep 26, 2012 at 06:02:39PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 13:04 Mon 24 Sep , Sascha Hauer wrote:
> > > Most clock/device associations can be done based on the physical
> > > base address of the corresponding device. So instead of depending
> > > on string matching add an optional possibility to associate a clock
> > > lookups with physical addresses. This also has the advantage that
> > > the lookups for devicetree based devices can be identical to the
> > > platform based devices.
> > >
> > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > ---
> > > drivers/clk/clkdev.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
> > > include/linux/clkdev.h | 3 +++
> > > 2 files changed, 50 insertions(+)
> > >
> > > diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
> > > index 717fea5..40bc006 100644
> > > --- a/drivers/clk/clkdev.c
> > > +++ b/drivers/clk/clkdev.c
> > > @@ -62,6 +62,32 @@ static struct clk *clk_find(const char *dev_id, const char *con_id)
> > > return clk;
> > > }
> > >
> > > +static struct clk *clk_find_physbase(struct device_d *dev, const char *con_id)
> > > +{
> > > + struct clk_lookup *p;
> > > + unsigned long start;
> > > +
> > > + if (!dev || !dev->resource)
> > > + return ERR_PTR(-ENOSYS);
> > this is broken
> >
> > clk_get_sys(NULL, "toto") is a valid call
>
> clk_get_sys never calls clk_find_physbase. clk_get(NULL, "toto") will
> call clk_find_physbase in which case clk_find_physbase returns -ENOSYS
> and clk_get falls back to clk_get_sys just as it did before.
I check one stuff
what will return the new clk_get for this
clk_get("dev0", "con0");
where we have
clkdev0 {
.devid = "dev0"
.physbase = 0x100
.clk =clk0
}
clkdev1 {
.devid = "dev0"
.conid = "con0"
.physbase = 0x100
.clk = clk1
}
clkdev2 {
.devid = "dev1"
.conid = "con0"
.clk =clk0
.physbase = 0x0
}
register in this order clkdev0 then clkdev1
it will return clkdev0
register in this order clkdev1 then clkdev0
it will return clkdev1
we need to manage the mach best as done in clk_get_sys
then we can nor register a dev with physbase at 0x0
valid on ARM
phybase need to be at ~0 for invalid
Best Regards,
J.
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^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 02/23] clk clkdev: Add clkdev matching based on physbase
2012-09-26 19:08 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-09-26 21:31 ` Sascha Hauer
0 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-26 21:31 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Wed, Sep 26, 2012 at 09:08:41PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > >
> > > clk_get_sys(NULL, "toto") is a valid call
> >
> > clk_get_sys never calls clk_find_physbase. clk_get(NULL, "toto") will
> > call clk_find_physbase in which case clk_find_physbase returns -ENOSYS
> > and clk_get falls back to clk_get_sys just as it did before.
> I check one stuff
>
> what will return the new clk_get for this
>
> clk_get("dev0", "con0");
>
> where we have
>
> clkdev0 {
> .devid = "dev0"
> .physbase = 0x100
You should either use physbase or devid, not both.
> .clk =clk0
> }
>
> clkdev1 {
> .devid = "dev0"
> .conid = "con0"
> .physbase = 0x100
> .clk = clk1
> }
>
> clkdev2 {
> .devid = "dev1"
> .conid = "con0"
> .clk =clk0
> .physbase = 0x0
> }
>
> register in this order clkdev0 then clkdev1
>
> it will return clkdev0
>
> register in this order clkdev1 then clkdev0
>
> it will return clkdev1
Try the attached fixup patch.
>
> we need to manage the mach best as done in clk_get_sys
>
> then we can nor register a dev with physbase at 0x0
>
Also fixed.
8<------------------------------------------------------
From 4b773f9c7202639d1b110773b5628820091a7e07 Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Wed, 26 Sep 2012 23:12:56 +0200
Subject: [PATCH] fixup! clk clkdev: Add clkdev matching based on physbase
When iterating over clk_lookups, we cannot return the current
clk when the lookup does not have a con_id. Instead we have
to iterate further until we can make sure that we do not have
a lookup for which both con_id and dev_id match
Also, to make sure to initialize a clk_lookup->physbase to
~0 when a dev_id is given. ~0 makes for a better invalid
physbase, NULL may be a valid device address.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clk/clkdev.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 40bc006..1ae822f 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -66,6 +66,7 @@ static struct clk *clk_find_physbase(struct device_d *dev, const char *con_id)
{
struct clk_lookup *p;
unsigned long start;
+ struct clk *clk = ERR_PTR(-ENOSYS);
if (!dev || !dev->resource)
return ERR_PTR(-ENOSYS);
@@ -73,7 +74,7 @@ static struct clk *clk_find_physbase(struct device_d *dev, const char *con_id)
start = dev->resource[0].start;
list_for_each_entry(p, &clocks, node) {
- if (!p->physbase)
+ if (p->physbase == ~0)
continue;
if (p->physbase != start)
continue;
@@ -82,9 +83,10 @@ static struct clk *clk_find_physbase(struct device_d *dev, const char *con_id)
continue;
return p->clk;
}
- return p->clk;
+ clk = p->clk;
}
- return ERR_PTR(-ENOSYS);
+
+ return clk;
}
@@ -121,6 +123,9 @@ EXPORT_SYMBOL(clk_put);
void clkdev_add(struct clk_lookup *cl)
{
+ if (cl->dev_id)
+ cl->physbase = ~0;
+
list_add_tail(&cl->node, &clocks);
}
EXPORT_SYMBOL(clkdev_add);
@@ -128,6 +133,8 @@ EXPORT_SYMBOL(clkdev_add);
void __init clkdev_add_table(struct clk_lookup *cl, size_t num)
{
while (num--) {
+ if (cl->dev_id)
+ cl->physbase = ~0;
list_add_tail(&cl->node, &clocks);
cl++;
}
@@ -151,6 +158,7 @@ struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
if (!cla)
return NULL;
+ cla->cl.physbase = ~0;
cla->cl.clk = clk;
if (con_id) {
strlcpy(cla->con_id, con_id, sizeof(cla->con_id));
--
1.7.10.4
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 03/23] clk: initial common clk support
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
2012-09-24 11:04 ` [PATCH 01/23] err.h: introduce IS_ERR_OR_NULL Sascha Hauer
2012-09-24 11:04 ` [PATCH 02/23] clk clkdev: Add clkdev matching based on physbase Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 04/23] commands: Add clk commands Sascha Hauer
` (19 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
This adds barebox common clk support loosely based on the Kernel common
clk support. differences are:
- barebox does not need prepare/unprepare
- no parent rate propagation for set_rate
- struct clk is not really encapsulated from the drivers
Along with the clk support we have support for some basic clk building
blocks:
- clk-fixed
- clk-fixed-factor
- clk-mux
- clk-divider
clk-fixed and clk-fixed-factor are completely generic, clk-mux and clk-divider
are currently the way i.MX muxes/dividers are implemented.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clk/Kconfig | 3 +
drivers/clk/Makefile | 2 +-
drivers/clk/clk-divider.c | 98 ++++++++++++++++++
drivers/clk/clk-fixed-factor.c | 63 +++++++++++
drivers/clk/clk-fixed.c | 55 ++++++++++
drivers/clk/clk-mux.c | 77 ++++++++++++++
drivers/clk/clk.c | 224 ++++++++++++++++++++++++++++++++++++++++
include/linux/clk.h | 42 ++++++++
8 files changed, 563 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/clk-divider.c
create mode 100644 drivers/clk/clk-fixed-factor.c
create mode 100644 drivers/clk/clk-fixed.c
create mode 100644 drivers/clk/clk-mux.c
create mode 100644 drivers/clk/clk.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4168c88..66c1c46 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -2,3 +2,6 @@
config CLKDEV_LOOKUP
bool
select HAVE_CLK
+
+config COMMON_CLK
+ bool
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 07613fa..39a75a4 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,2 +1,2 @@
-
+obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed.o clk-divider.o clk-fixed-factor.o clk-mux.o
obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
new file mode 100644
index 0000000..58a7ea5
--- /dev/null
+++ b/drivers/clk/clk-divider.c
@@ -0,0 +1,98 @@
+/*
+ * clk-divider.c - generic barebox clock support. Based on Linux clk support
+ *
+ * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <common.h>
+#include <io.h>
+#include <malloc.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+struct clk_divider {
+ struct clk clk;
+ u8 shift;
+ u8 width;
+ void __iomem *reg;
+ const char *parent;
+};
+
+static int clk_divider_set_rate(struct clk *clk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_divider *div = container_of(clk, struct clk_divider, clk);
+ unsigned int val, divval;
+
+ if (rate > parent_rate)
+ rate = parent_rate;
+ if (!rate)
+ rate = 1;
+
+ divval = DIV_ROUND_UP(parent_rate, rate);
+
+ if (divval > (1 << div->width))
+ divval = 1 << (div->width);
+
+ divval--;
+
+ val = readl(div->reg);
+ val &= ~(((1 << div->width) - 1) << div->shift);
+ val |= divval << div->shift;
+ writel(val, div->reg);
+
+ return 0;
+}
+
+static unsigned long clk_divider_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_divider *div = container_of(clk, struct clk_divider, clk);
+ unsigned int val;
+
+ val = readl(div->reg) >> div->shift;
+ val &= (1 << div->width) - 1;
+
+ val++;
+
+ return parent_rate / val;
+}
+
+struct clk_ops clk_divider_ops = {
+ .set_rate = clk_divider_set_rate,
+ .recalc_rate = clk_divider_recalc_rate,
+};
+
+struct clk *clk_divider(const char *name, const char *parent,
+ void __iomem *reg, u8 shift, u8 width)
+{
+ struct clk_divider *div = xzalloc(sizeof(*div));
+ int ret;
+
+ div->shift = shift;
+ div->reg = reg;
+ div->width = width;
+ div->parent = parent;
+ div->clk.ops = &clk_divider_ops;
+ div->clk.name = name;
+ div->clk.parent_names = &div->parent;
+ div->clk.num_parents = 1;
+
+ ret = clk_register(&div->clk);
+ if (ret) {
+ free(div);
+ return ERR_PTR(ret);
+ }
+
+ return &div->clk;
+}
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
new file mode 100644
index 0000000..52e7c16
--- /dev/null
+++ b/drivers/clk/clk-fixed-factor.c
@@ -0,0 +1,63 @@
+/*
+ * clk-fixed-factor.c - generic barebox clock support. Based on Linux clk support
+ *
+ * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <common.h>
+#include <io.h>
+#include <malloc.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+struct clk_fixed_factor {
+ struct clk clk;
+ int mult;
+ int div;
+ const char *parent;
+};
+
+static unsigned long clk_fixed_factor_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_fixed_factor *f = container_of(clk, struct clk_fixed_factor, clk);
+
+ return (parent_rate / f->div) * f->mult;
+}
+
+struct clk_ops clk_fixed_factor_ops = {
+ .recalc_rate = clk_fixed_factor_recalc_rate,
+};
+
+struct clk *clk_fixed_factor(const char *name,
+ const char *parent, unsigned int mult, unsigned int div)
+{
+ struct clk_fixed_factor *f = xzalloc(sizeof(*f));
+ int ret;
+
+ f->mult = mult;
+ f->div = div;
+ f->parent = parent;
+ f->clk.ops = &clk_fixed_factor_ops;
+ f->clk.name = name;
+ f->clk.parent_names = &f->parent;
+ f->clk.num_parents = 1;
+
+ ret = clk_register(&f->clk);
+ if (ret) {
+ free(f);
+ return ERR_PTR(ret);
+ }
+
+ return &f->clk;
+}
diff --git a/drivers/clk/clk-fixed.c b/drivers/clk/clk-fixed.c
new file mode 100644
index 0000000..fa89cb2
--- /dev/null
+++ b/drivers/clk/clk-fixed.c
@@ -0,0 +1,55 @@
+/*
+ * clk-fixed.c - generic barebox clock support. Based on Linux clk support
+ *
+ * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <common.h>
+#include <malloc.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+struct clk_fixed {
+ struct clk clk;
+ unsigned long rate;
+};
+
+static unsigned long clk_fixed_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_fixed *fix = container_of(clk, struct clk_fixed, clk);
+
+ return fix->rate;
+}
+
+struct clk_ops clk_fixed_ops = {
+ .recalc_rate = clk_fixed_recalc_rate,
+};
+
+struct clk *clk_fixed(const char *name, int rate)
+{
+ struct clk_fixed *fix = xzalloc(sizeof *fix);
+ int ret;
+
+ fix->rate = rate;
+ fix->clk.ops = &clk_fixed_ops;
+ fix->clk.name = name;
+
+ ret = clk_register(&fix->clk);
+ if (ret) {
+ free(fix);
+ return ERR_PTR(ret);
+ }
+
+ return &fix->clk;
+}
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
new file mode 100644
index 0000000..1794380
--- /dev/null
+++ b/drivers/clk/clk-mux.c
@@ -0,0 +1,77 @@
+/*
+ * clk-mux.c - generic barebox clock support. Based on Linux clk support
+ *
+ * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <common.h>
+#include <io.h>
+#include <malloc.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+struct clk_mux {
+ struct clk clk;
+ void __iomem *reg;
+ int shift;
+ int width;
+};
+
+static int clk_mux_get_parent(struct clk *clk)
+{
+ struct clk_mux *m = container_of(clk, struct clk_mux, clk);
+ int idx = readl(m->reg) >> m->shift & ((1 << m->width) - 1);
+
+ return idx;
+}
+
+static int clk_mux_set_parent(struct clk *clk, u8 idx)
+{
+ struct clk_mux *m = container_of(clk, struct clk_mux, clk);
+ u32 val;
+
+ val = readl(m->reg);
+ val &= ~(((1 << m->width) - 1) << m->shift);
+ val |= idx << m->shift;
+ writel(val, m->reg);
+
+ return 0;
+}
+
+struct clk_ops clk_mux_ops = {
+ .get_parent = clk_mux_get_parent,
+ .set_parent = clk_mux_set_parent,
+};
+
+struct clk *clk_mux(const char *name, void __iomem *reg,
+ u8 shift, u8 width, const char **parents, int num_parents)
+{
+ struct clk_mux *m = xzalloc(sizeof(*m));
+ int ret;
+
+ m->reg = reg;
+ m->shift = shift;
+ m->width = width;
+ m->clk.ops = &clk_mux_ops;
+ m->clk.name = name;
+ m->clk.parent_names = parents;
+ m->clk.num_parents = num_parents;
+
+ ret = clk_register(&m->clk);
+ if (ret) {
+ free(m);
+ return ERR_PTR(ret);
+ }
+
+ return &m->clk;
+}
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
new file mode 100644
index 0000000..bf61e5d
--- /dev/null
+++ b/drivers/clk/clk.c
@@ -0,0 +1,224 @@
+/*
+ * clk.c - generic barebox clock support. Based on Linux clk support
+ *
+ * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <common.h>
+#include <errno.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+static LIST_HEAD(clks);
+
+static int clk_parent_enable(struct clk *clk)
+{
+ struct clk *parent = clk_get_parent(clk);
+
+ if (!IS_ERR_OR_NULL(parent))
+ return clk_enable(parent);
+
+ return 0;
+}
+
+static void clk_parent_disable(struct clk *clk)
+{
+ struct clk *parent = clk_get_parent(clk);
+
+ if (!IS_ERR_OR_NULL(parent))
+ clk_disable(parent);
+}
+
+int clk_enable(struct clk *clk)
+{
+ int ret;
+
+ if (!clk->enable_count) {
+ ret = clk_parent_enable(clk);
+ if (ret)
+ return ret;
+
+ if (clk->ops->enable) {
+ ret = clk->ops->enable(clk);
+ if (ret) {
+ clk_parent_disable(clk);
+ return ret;
+ }
+ }
+ }
+
+ clk->enable_count++;
+
+ return 0;
+}
+
+void clk_disable(struct clk *clk)
+{
+ if (!clk->enable_count)
+ return;
+
+ clk->enable_count--;
+
+ if (!clk->enable_count) {
+ if (clk->ops->disable)
+ clk->ops->disable(clk);
+
+ clk_parent_disable(clk);
+ }
+}
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ struct clk *parent;
+ unsigned long parent_rate = 0;
+
+ parent = clk_get_parent(clk);
+ if (!IS_ERR_OR_NULL(parent))
+ parent_rate = clk_get_rate(parent);
+
+ if (clk->ops->recalc_rate)
+ return clk->ops->recalc_rate(clk, parent_rate);
+
+ return parent_rate;
+}
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+ return clk_get_rate(clk);
+}
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *parent;
+ unsigned long parent_rate = 0;
+
+ parent = clk_get_parent(clk);
+ if (parent)
+ parent_rate = clk_get_rate(parent);
+
+ if (clk->ops->set_rate)
+ return clk->ops->set_rate(clk, rate, parent_rate);
+
+ return -ENOSYS;
+}
+
+struct clk *clk_lookup(const char *name)
+{
+ struct clk *c;
+
+ if (!name)
+ return ERR_PTR(-ENODEV);
+
+ list_for_each_entry(c, &clks, list) {
+ if (!strcmp(c->name, name))
+ return c;
+ }
+
+ return ERR_PTR(-ENODEV);
+}
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ int i;
+
+ if (!clk->num_parents)
+ return -EINVAL;
+ if (!clk->ops->set_parent)
+ return -EINVAL;
+
+ for (i = 0; i < clk->num_parents; i++) {
+ if (IS_ERR_OR_NULL(clk->parents[i]))
+ clk->parents[i] = clk_lookup(clk->parent_names[i]);
+
+ if (!IS_ERR_OR_NULL(clk->parents[i]))
+ if (clk->parents[i] == parent)
+ break;
+ }
+
+ if (i == clk->num_parents)
+ return -EINVAL;
+
+ return clk->ops->set_parent(clk, i);
+}
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+ int idx;
+
+ if (!clk->num_parents)
+ return ERR_PTR(-ENODEV);
+
+ if (clk->num_parents != 1) {
+ if (!clk->ops->get_parent)
+ return ERR_PTR(-EINVAL);
+
+ idx = clk->ops->get_parent(clk);
+
+ if (idx >= clk->num_parents)
+ return ERR_PTR(-ENODEV);
+ } else {
+ idx = 0;
+ }
+
+ if (IS_ERR_OR_NULL(clk->parents[idx]))
+ clk->parents[idx] = clk_lookup(clk->parent_names[idx]);
+
+ return clk->parents[idx];
+}
+
+int clk_register(struct clk *clk)
+{
+ clk->parents = xzalloc(sizeof(struct clk *) * clk->num_parents);
+
+ list_add_tail(&clk->list, &clks);
+
+ return 0;
+}
+
+static void dump_one(struct clk *clk, int verbose, int indent)
+{
+ struct clk *c;
+
+ printf("%*s%s (rate %ld, %sabled)\n", indent * 4, "", clk->name, clk_get_rate(clk),
+ clk->enable_count ? "en" : "dis");
+ if (verbose) {
+
+ if (clk->num_parents > 1) {
+ int i;
+ printf("%*s`---- possible parents: ", indent * 4, "");
+ for (i = 0; i < clk->num_parents; i++)
+ printf("%s ", clk->parent_names[i]);
+ printf("\n");
+ }
+ }
+
+ list_for_each_entry(c, &clks, list) {
+ struct clk *parent = clk_get_parent(c);
+
+ if (parent == clk) {
+ dump_one(c, verbose, indent + 1);
+ }
+ }
+}
+
+void clk_dump(int verbose)
+{
+ struct clk *c;
+
+ list_for_each_entry(c, &clks, list) {
+ struct clk *parent = clk_get_parent(c);
+
+ if (IS_ERR_OR_NULL(parent))
+ dump_one(c, verbose, 0);
+ }
+}
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 1478c97..09e5656 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -155,4 +155,46 @@ struct clk *clk_get_sys(const char *dev_id, const char *con_id);
int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
struct device_d *dev);
+#ifdef CONFIG_COMMON_CLK
+struct clk_ops {
+ int (*enable)(struct clk *clk);
+ void (*disable)(struct clk *clk);
+ int (*is_enabled)(struct clk *clk);
+ unsigned long (*recalc_rate)(struct clk *clk,
+ unsigned long parent_rate);
+ long (*round_rate)(struct clk *clk, unsigned long,
+ unsigned long *);
+ int (*set_parent)(struct clk *clk, u8 index);
+ int (*get_parent)(struct clk *clk);
+ int (*set_rate)(struct clk *clk, unsigned long,
+ unsigned long);
+};
+
+struct clk {
+ const struct clk_ops *ops;
+ int enable_count;
+ struct list_head list;
+ const char *name;
+ const char **parent_names;
+ int num_parents;
+
+ struct clk **parents;
+};
+
+struct clk *clk_fixed(const char *name, int rate);
+struct clk *clk_divider(const char *name, const char *parent,
+ void __iomem *reg, u8 shift, u8 width);
+struct clk *clk_fixed_factor(const char *name,
+ const char *parent, unsigned int mult, unsigned int div);
+struct clk *clk_mux(const char *name, void __iomem *reg,
+ u8 shift, u8 width, const char **parents, int num_parents);
+
+int clk_register(struct clk *clk);
+
+struct clk *clk_lookup(const char *name);
+
+void clk_dump(int verbose);
+
+#endif
+
#endif
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 04/23] commands: Add clk commands
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (2 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 03/23] clk: initial common clk support Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 05/23] ARM i.MX: initial clk support Sascha Hauer
` (18 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
This adds some basic commands to manupulate clocks on the command
line. Right now we have:
- clk_set_parent
- clk_set_rate
- clk_enable
- clk_disable
- clk_dump
The commands work based on the clock name, otherwise they behave like
the Linux Kernel C functions. clk_dump will dump the clocktree to the
console.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
commands/Kconfig | 8 ++++
commands/Makefile | 1 +
commands/clk.c | 133 +++++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 142 insertions(+)
create mode 100644 commands/clk.c
diff --git a/commands/Kconfig b/commands/Kconfig
index 930a9b1..7969937 100644
--- a/commands/Kconfig
+++ b/commands/Kconfig
@@ -605,6 +605,14 @@ config CMD_USB
help
The usb command allows to rescan for USB devices.
+config CMD_CLK
+ tristate
+ depends on COMMON_CLK
+ prompt "clock manipulation commands"
+ help
+ Say yes here to get clk_set_rate, clk_set_parent and clk_dump
+ commands to manipulate clocks on your system.
+
menuconfig CMD_WD
bool
depends on WATCHDOG
diff --git a/commands/Makefile b/commands/Makefile
index 24bf46a..7a36f60 100644
--- a/commands/Makefile
+++ b/commands/Makefile
@@ -74,3 +74,4 @@ obj-$(CONFIG_CMD_BASENAME) += basename.o
obj-$(CONFIG_CMD_DIRNAME) += dirname.o
obj-$(CONFIG_CMD_READLINK) += readlink.o
obj-$(CONFIG_CMD_LN) += ln.o
+obj-$(CONFIG_CMD_CLK) += clk.o
diff --git a/commands/clk.c b/commands/clk.c
new file mode 100644
index 0000000..5cde3ca
--- /dev/null
+++ b/commands/clk.c
@@ -0,0 +1,133 @@
+#include <common.h>
+#include <command.h>
+#include <getopt.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+static int do_clk_enable(int argc, char *argv[])
+{
+ struct clk *clk;
+
+ if (argc != 2)
+ return COMMAND_ERROR_USAGE;
+
+ clk = clk_lookup(argv[1]);
+
+ return clk_enable(clk);
+}
+
+BAREBOX_CMD_HELP_START(clk_enable)
+BAREBOX_CMD_HELP_USAGE("clk_enable <clk>\n")
+BAREBOX_CMD_HELP_SHORT("enable <clk>\n")
+BAREBOX_CMD_HELP_END
+
+BAREBOX_CMD_START(clk_enable)
+ .cmd = do_clk_enable,
+ .usage = "enable a clock",
+ BAREBOX_CMD_HELP(cmd_clk_enable_help)
+BAREBOX_CMD_END
+
+static int do_clk_disable(int argc, char *argv[])
+{
+ struct clk *clk;
+
+ if (argc != 2)
+ return COMMAND_ERROR_USAGE;
+
+ clk = clk_lookup(argv[1]);
+
+ clk_disable(clk);
+
+ return 0;
+}
+
+BAREBOX_CMD_HELP_START(clk_disable)
+BAREBOX_CMD_HELP_USAGE("clk_disable <clk>\n")
+BAREBOX_CMD_HELP_SHORT("disable <clk>\n")
+BAREBOX_CMD_HELP_END
+
+BAREBOX_CMD_START(clk_disable)
+ .cmd = do_clk_disable,
+ .usage = "disable a clock",
+ BAREBOX_CMD_HELP(cmd_clk_disable_help)
+BAREBOX_CMD_END
+
+static int do_clk_set_rate(int argc, char *argv[])
+{
+ struct clk *clk;
+ unsigned long rate;
+
+ if (argc != 3)
+ return COMMAND_ERROR_USAGE;
+
+ clk = clk_lookup(argv[1]);
+ rate = simple_strtoul(argv[2], NULL, 0);
+
+ return clk_set_rate(clk, rate);
+}
+
+BAREBOX_CMD_HELP_START(clk_set_rate)
+BAREBOX_CMD_HELP_USAGE("clk_set_rate <clk> <rate_hz>\n")
+BAREBOX_CMD_HELP_SHORT("Set clock <clk> to <rate>\n")
+BAREBOX_CMD_HELP_END
+
+BAREBOX_CMD_START(clk_set_rate)
+ .cmd = do_clk_set_rate,
+ .usage = "set a clocks rate",
+ BAREBOX_CMD_HELP(cmd_clk_set_rate_help)
+BAREBOX_CMD_END
+
+static int do_clk_dump(int argc, char *argv[])
+{
+ int opt, verbose = 0;
+
+ while ((opt = getopt(argc, argv, "v")) > 0) {
+ switch(opt) {
+ case 'v':
+ verbose = 1;
+ break;
+ default:
+ return -EINVAL;
+
+ }
+ }
+
+ clk_dump(verbose);
+
+ return 0;
+}
+
+BAREBOX_CMD_HELP_START(clk_dump)
+BAREBOX_CMD_HELP_USAGE("clk_dump [-v]\n")
+BAREBOX_CMD_HELP_OPT ("-v", "verbose\n")
+BAREBOX_CMD_HELP_END
+
+BAREBOX_CMD_START(clk_dump)
+ .cmd = do_clk_dump,
+ .usage = "show information about registered clocks",
+ BAREBOX_CMD_HELP(cmd_clk_dump_help)
+BAREBOX_CMD_END
+
+static int do_clk_set_parent(int argc, char *argv[])
+{
+ struct clk *clk, *parent;
+
+ if (argc != 3)
+ return COMMAND_ERROR_USAGE;
+
+ clk = clk_lookup(argv[1]);
+ parent = clk_lookup(argv[2]);
+
+ return clk_set_parent(clk, parent);
+}
+
+BAREBOX_CMD_HELP_START(clk_set_parent)
+BAREBOX_CMD_HELP_USAGE("clk_set_parent <clk> <parent>\n")
+BAREBOX_CMD_HELP_SHORT("Set parent of <clk> to <parent>\n")
+BAREBOX_CMD_HELP_END
+
+BAREBOX_CMD_START(clk_set_parent)
+ .cmd = do_clk_set_parent,
+ .usage = "set a parent of a clock",
+ BAREBOX_CMD_HELP(cmd_clk_set_parent_help)
+BAREBOX_CMD_END
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 05/23] ARM i.MX: initial clk support
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (3 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 04/23] commands: Add clk commands Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 06/23] ARM i.MX27: implement " Sascha Hauer
` (17 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
This adds the basic i.MX common clk support and some pll and pfd
drivers.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/clk-pfd.c | 148 ++++++++++++
arch/arm/mach-imx/clk-pllv1.c | 94 ++++++++
arch/arm/mach-imx/clk-pllv2.c | 164 +++++++++++++
arch/arm/mach-imx/clk-pllv3.c | 386 +++++++++++++++++++++++++++++++
arch/arm/mach-imx/clk.h | 66 ++++++
arch/arm/mach-imx/include/mach/clkdev.h | 7 +
7 files changed, 866 insertions(+)
create mode 100644 arch/arm/mach-imx/clk-pfd.c
create mode 100644 arch/arm/mach-imx/clk-pllv1.c
create mode 100644 arch/arm/mach-imx/clk-pllv2.c
create mode 100644 arch/arm/mach-imx/clk-pllv3.c
create mode 100644 arch/arm/mach-imx/clk.h
create mode 100644 arch/arm/mach-imx/include/mach/clkdev.h
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 2b595bc..f6d487f 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_IMX_IIM) += iim.o
obj-$(CONFIG_NAND_IMX) += nand.o
obj-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o
pbl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o
+obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-pfd.o
obj-y += speed.o
obj-y += devices.o
obj-y += boot.o
diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c
new file mode 100644
index 0000000..8f6d5ad
--- /dev/null
+++ b/arch/arm/mach-imx/clk-pfd.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <malloc.h>
+#include <asm-generic/div64.h>
+
+#include "clk.h"
+
+/**
+ * struct clk_pfd - IMX PFD clock
+ * @clk_hw: clock source
+ * @reg: PFD register address
+ * @idx: the index of PFD encoded in the register
+ *
+ * PFD clock found on i.MX6 series. Each register for PFD has 4 clk_pfd
+ * data encoded, and member idx is used to specify the one. And each
+ * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc.
+ */
+struct clk_pfd {
+ struct clk clk;
+ void __iomem *reg;
+ u8 idx;
+ const char *parent;
+};
+
+#define to_clk_pfd(_clk) container_of(_clk, struct clk_pfd, clk)
+
+#define SET 0x4
+#define CLR 0x8
+#define OTG 0xc
+
+static int clk_pfd_enable(struct clk *clk)
+{
+ struct clk_pfd *pfd = to_clk_pfd(clk);
+ writel(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR);
+
+ return 0;
+}
+
+static void clk_pfd_disable(struct clk *clk)
+{
+ struct clk_pfd *pfd = to_clk_pfd(clk);
+
+ writel(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET);
+}
+
+static unsigned long clk_pfd_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_pfd *pfd = to_clk_pfd(clk);
+ u64 tmp = parent_rate;
+ u8 frac = (readl(pfd->reg) >> (pfd->idx * 8)) & 0x3f;
+
+ tmp *= 18;
+ do_div(tmp, frac);
+
+ return tmp;
+}
+
+static long clk_pfd_round_rate(struct clk *clk, unsigned long rate,
+ unsigned long *prate)
+{
+ u64 tmp = *prate;
+ u8 frac;
+
+ tmp = tmp * 18 + rate / 2;
+ do_div(tmp, rate);
+ frac = tmp;
+ if (frac < 12)
+ frac = 12;
+ else if (frac > 35)
+ frac = 35;
+ tmp = *prate;
+ tmp *= 18;
+ do_div(tmp, frac);
+
+ return tmp;
+}
+
+static int clk_pfd_set_rate(struct clk *clk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pfd *pfd = to_clk_pfd(clk);
+ u64 tmp = parent_rate;
+ u8 frac;
+
+ tmp = tmp * 18 + rate / 2;
+ do_div(tmp, rate);
+ frac = tmp;
+ if (frac < 12)
+ frac = 12;
+ else if (frac > 35)
+ frac = 35;
+
+ writel(0x3f << (pfd->idx * 8), pfd->reg + CLR);
+ writel(frac << (pfd->idx * 8), pfd->reg + SET);
+
+ return 0;
+}
+
+static const struct clk_ops clk_pfd_ops = {
+ .enable = clk_pfd_enable,
+ .disable = clk_pfd_disable,
+ .recalc_rate = clk_pfd_recalc_rate,
+ .round_rate = clk_pfd_round_rate,
+ .set_rate = clk_pfd_set_rate,
+};
+
+struct clk *imx_clk_pfd(const char *name, const char *parent,
+ void __iomem *reg, u8 idx)
+{
+ struct clk_pfd *pfd;
+ int ret;
+
+ pfd = xzalloc(sizeof(*pfd));
+
+ pfd->reg = reg;
+ pfd->idx = idx;
+ pfd->parent = parent;
+ pfd->clk.name = name;
+ pfd->clk.ops = &clk_pfd_ops;
+ pfd->clk.parent_names = &pfd->parent;
+ pfd->clk.num_parents = 1;
+
+ ret = clk_register(&pfd->clk);
+ if (ret) {
+ free(pfd);
+ return ERR_PTR(ret);
+ }
+
+ return &pfd->clk;
+}
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
new file mode 100644
index 0000000..6785da0
--- /dev/null
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -0,0 +1,94 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <malloc.h>
+#include <asm-generic/div64.h>
+
+#include "clk.h"
+
+struct clk_pllv1 {
+ struct clk clk;
+ void __iomem *reg;
+ const char *parent;
+};
+
+static unsigned long clk_pllv1_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_pllv1 *pll = container_of(clk, struct clk_pllv1, clk);
+ unsigned long long ll;
+ int mfn_abs;
+ unsigned int mfi, mfn, mfd, pd;
+ u32 reg_val = readl(pll->reg);
+ unsigned long freq = parent_rate;
+
+ mfi = (reg_val >> 10) & 0xf;
+ mfn = reg_val & 0x3ff;
+ mfd = (reg_val >> 16) & 0x3ff;
+ pd = (reg_val >> 26) & 0xf;
+
+ mfi = mfi <= 5 ? 5 : mfi;
+
+ mfn_abs = mfn;
+
+#if !defined CONFIG_ARCH_MX1 && !defined CONFIG_ARCH_MX21
+ if (mfn >= 0x200) {
+ mfn |= 0xFFFFFE00;
+ mfn_abs = -mfn;
+ }
+#endif
+
+ freq *= 2;
+ freq /= pd + 1;
+
+ ll = (unsigned long long)freq * mfn_abs;
+
+ do_div(ll, mfd + 1);
+ if (mfn < 0)
+ ll = -ll;
+ ll = (freq * mfi) + ll;
+
+ return ll;
+}
+
+struct clk_ops clk_pllv1_ops = {
+ .recalc_rate = clk_pllv1_recalc_rate,
+};
+
+struct clk *imx_clk_pllv1(const char *name, const char *parent,
+ void __iomem *base)
+{
+ struct clk_pllv1 *pll = xzalloc(sizeof(*pll));
+ int ret;
+
+ pll->parent = parent;
+ pll->reg = base;
+ pll->clk.ops = &clk_pllv1_ops;
+ pll->clk.name = name;
+ pll->clk.parent_names = &pll->parent;
+ pll->clk.num_parents = 1;
+
+ ret = clk_register(&pll->clk);
+ if (ret) {
+ free(pll);
+ return ERR_PTR(ret);
+ }
+
+ return &pll->clk;
+}
diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c
new file mode 100644
index 0000000..6907269
--- /dev/null
+++ b/arch/arm/mach-imx/clk-pllv2.c
@@ -0,0 +1,164 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <mach/imx-regs.h>
+#include <malloc.h>
+#include <asm-generic/div64.h>
+
+#include "clk.h"
+
+/* PLL Register Offsets */
+#define MXC_PLL_DP_CTL 0x00
+#define MXC_PLL_DP_CONFIG 0x04
+#define MXC_PLL_DP_OP 0x08
+#define MXC_PLL_DP_MFD 0x0C
+#define MXC_PLL_DP_MFN 0x10
+#define MXC_PLL_DP_MFNMINUS 0x14
+#define MXC_PLL_DP_MFNPLUS 0x18
+#define MXC_PLL_DP_HFS_OP 0x1C
+#define MXC_PLL_DP_HFS_MFD 0x20
+#define MXC_PLL_DP_HFS_MFN 0x24
+#define MXC_PLL_DP_MFN_TOGC 0x28
+#define MXC_PLL_DP_DESTAT 0x2c
+
+/* PLL Register Bit definitions */
+#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
+#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
+#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
+#define MXC_PLL_DP_CTL_ADE 0x800
+#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
+#define MXC_PLL_DP_CTL_HFSM 0x80
+#define MXC_PLL_DP_CTL_PRE 0x40
+#define MXC_PLL_DP_CTL_UPEN 0x20
+#define MXC_PLL_DP_CTL_RST 0x10
+#define MXC_PLL_DP_CTL_RCP 0x8
+#define MXC_PLL_DP_CTL_PLM 0x4
+#define MXC_PLL_DP_CTL_BRM0 0x2
+#define MXC_PLL_DP_CTL_LRF 0x1
+
+#define MXC_PLL_DP_CONFIG_BIST 0x8
+#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
+#define MXC_PLL_DP_CONFIG_AREN 0x2
+#define MXC_PLL_DP_CONFIG_LDREQ 0x1
+
+#define MXC_PLL_DP_OP_MFI_OFFSET 4
+#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
+#define MXC_PLL_DP_OP_PDF_OFFSET 0
+#define MXC_PLL_DP_OP_PDF_MASK 0xF
+
+#define MXC_PLL_DP_MFD_OFFSET 0
+#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_OFFSET 0x0
+#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
+#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
+#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
+#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
+
+#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
+#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
+
+#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
+
+struct clk_pllv2 {
+ struct clk clk;
+ void __iomem *reg;
+ const char *parent;
+};
+
+static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
+ u32 dp_ctl, u32 dp_op, u32 dp_mfd, u32 dp_mfn)
+{
+ long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
+ unsigned long dbl;
+ uint64_t temp;
+
+ dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
+
+ pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
+ mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
+ mfi = (mfi <= 5) ? 5 : mfi;
+ mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
+ mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
+ /* Sign extend to 32-bits */
+ if (mfn >= 0x04000000) {
+ mfn |= 0xFC000000;
+ mfn_abs = -mfn;
+ }
+
+ ref_clk = 2 * parent_rate;
+ if (dbl != 0)
+ ref_clk *= 2;
+
+ ref_clk /= (pdf + 1);
+ temp = (u64) ref_clk * mfn_abs;
+ do_div(temp, mfd + 1);
+ if (mfn < 0)
+ temp = -temp;
+ temp = (ref_clk * mfi) + temp;
+
+ return temp;
+}
+
+static unsigned long clk_pllv2_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ u32 dp_op, dp_mfd, dp_mfn, dp_ctl;
+ void __iomem *pllbase;
+ struct clk_pllv2 *pll = container_of(clk, struct clk_pllv2, clk);
+
+ pllbase = pll->reg;
+
+ dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+ dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
+ dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
+ dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
+
+ return __clk_pllv2_recalc_rate(parent_rate, dp_ctl, dp_op, dp_mfd, dp_mfn);
+}
+
+struct clk_ops clk_pllv2_ops = {
+ .recalc_rate = clk_pllv2_recalc_rate,
+};
+
+struct clk *imx_clk_pllv2(const char *name, const char *parent,
+ void __iomem *base)
+{
+ struct clk_pllv2 *pll = xzalloc(sizeof(*pll));
+ int ret;
+
+ pll->parent = parent;
+ pll->reg = base;
+ pll->clk.ops = &clk_pllv2_ops;
+ pll->clk.name = name;
+ pll->clk.parent_names = &pll->parent;
+ pll->clk.num_parents = 1;
+
+ ret = clk_register(&pll->clk);
+ if (ret) {
+ free(pll);
+ return ERR_PTR(ret);
+ }
+
+ return &pll->clk;
+}
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
new file mode 100644
index 0000000..a99eec5
--- /dev/null
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -0,0 +1,386 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <mach/imx-regs.h>
+#include <malloc.h>
+#include <clock.h>
+#include <asm-generic/div64.h>
+
+#include "clk.h"
+
+#define PLL_NUM_OFFSET 0x10
+#define PLL_DENOM_OFFSET 0x20
+
+#define BM_PLL_POWER (0x1 << 12)
+#define BM_PLL_ENABLE (0x1 << 13)
+#define BM_PLL_BYPASS (0x1 << 16)
+#define BM_PLL_LOCK (0x1 << 31)
+
+struct clk_pllv3 {
+ struct clk clk;
+ void __iomem *base;
+ bool powerup_set;
+ u32 gate_mask;
+ u32 div_mask;
+ const char *parent;
+};
+
+#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
+
+static int clk_pllv3_enable(struct clk *clk)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ u32 val;
+ int ret;
+
+ val = readl(pll->base);
+ val &= ~BM_PLL_BYPASS;
+ if (pll->powerup_set)
+ val |= BM_PLL_POWER;
+ else
+ val &= ~BM_PLL_POWER;
+ writel(val, pll->base);
+
+ /* Wait for PLL to lock */
+ ret = wait_on_timeout(10 * MSECOND, !(readl(pll->base) & BM_PLL_LOCK));
+ if (ret)
+ return ret;
+
+ val = readl(pll->base);
+ val |= pll->gate_mask;
+ writel(val, pll->base);
+
+ return 0;
+}
+
+static void clk_pllv3_disable(struct clk *clk)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ u32 val;
+
+ val = readl(pll->base);
+ val &= ~pll->gate_mask;
+ writel(val, pll->base);
+
+ val |= BM_PLL_BYPASS;
+ if (pll->powerup_set)
+ val &= ~BM_PLL_POWER;
+ else
+ val |= BM_PLL_POWER;
+ writel(val, pll->base);
+}
+
+static unsigned long clk_pllv3_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ u32 div = readl(pll->base) & pll->div_mask;
+
+ return (div == 1) ? parent_rate * 22 : parent_rate * 20;
+}
+
+static long clk_pllv3_round_rate(struct clk *clk, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long parent_rate = *prate;
+
+ return (rate >= parent_rate * 22) ? parent_rate * 22 :
+ parent_rate * 20;
+}
+
+static int clk_pllv3_set_rate(struct clk *clk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ u32 val, div;
+
+ if (rate == parent_rate * 22)
+ div = 1;
+ else if (rate == parent_rate * 20)
+ div = 0;
+ else
+ return -EINVAL;
+
+ val = readl(pll->base);
+ val &= ~pll->div_mask;
+ val |= div;
+ writel(val, pll->base);
+
+ return 0;
+}
+
+static const struct clk_ops clk_pllv3_ops = {
+ .enable = clk_pllv3_enable,
+ .disable = clk_pllv3_disable,
+ .recalc_rate = clk_pllv3_recalc_rate,
+ .round_rate = clk_pllv3_round_rate,
+ .set_rate = clk_pllv3_set_rate,
+};
+
+static unsigned long clk_pllv3_sys_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ u32 div = readl(pll->base) & pll->div_mask;
+
+ return parent_rate * div / 2;
+}
+
+static long clk_pllv3_sys_round_rate(struct clk *clk, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long parent_rate = *prate;
+ unsigned long min_rate = parent_rate * 54 / 2;
+ unsigned long max_rate = parent_rate * 108 / 2;
+ u32 div;
+
+ if (rate > max_rate)
+ rate = max_rate;
+ else if (rate < min_rate)
+ rate = min_rate;
+ div = rate * 2 / parent_rate;
+
+ return parent_rate * div / 2;
+}
+
+static int clk_pllv3_sys_set_rate(struct clk *clk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ unsigned long min_rate = parent_rate * 54 / 2;
+ unsigned long max_rate = parent_rate * 108 / 2;
+ u32 val, div;
+
+ if (rate < min_rate || rate > max_rate)
+ return -EINVAL;
+
+ div = rate * 2 / parent_rate;
+ val = readl(pll->base);
+ val &= ~pll->div_mask;
+ val |= div;
+ writel(val, pll->base);
+
+ return 0;
+}
+
+static const struct clk_ops clk_pllv3_sys_ops = {
+ .enable = clk_pllv3_enable,
+ .disable = clk_pllv3_disable,
+ .recalc_rate = clk_pllv3_sys_recalc_rate,
+ .round_rate = clk_pllv3_sys_round_rate,
+ .set_rate = clk_pllv3_sys_set_rate,
+};
+
+static unsigned long clk_pllv3_av_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
+ u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
+ u32 div = readl(pll->base) & pll->div_mask;
+
+ return (parent_rate * div) + ((parent_rate / mfd) * mfn);
+}
+
+static long clk_pllv3_av_round_rate(struct clk *clk, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long parent_rate = *prate;
+ unsigned long min_rate = parent_rate * 27;
+ unsigned long max_rate = parent_rate * 54;
+ u32 div;
+ u32 mfn, mfd = 1000000;
+ u64 temp64;
+
+ if (rate > max_rate)
+ rate = max_rate;
+ else if (rate < min_rate)
+ rate = min_rate;
+
+ div = rate / parent_rate;
+ temp64 = (u64) (rate - div * parent_rate);
+ temp64 *= mfd;
+ do_div(temp64, parent_rate);
+ mfn = temp64;
+
+ return parent_rate * div + parent_rate / mfd * mfn;
+}
+
+static int clk_pllv3_av_set_rate(struct clk *clk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ unsigned long min_rate = parent_rate * 27;
+ unsigned long max_rate = parent_rate * 54;
+ u32 val, div;
+ u32 mfn, mfd = 1000000;
+ u64 temp64;
+
+ if (rate < min_rate || rate > max_rate)
+ return -EINVAL;
+
+ div = rate / parent_rate;
+ temp64 = (u64) (rate - div * parent_rate);
+ temp64 *= mfd;
+ do_div(temp64, parent_rate);
+ mfn = temp64;
+
+ val = readl(pll->base);
+ val &= ~pll->div_mask;
+ val |= div;
+ writel(val, pll->base);
+ writel(mfn, pll->base + PLL_NUM_OFFSET);
+ writel(mfd, pll->base + PLL_DENOM_OFFSET);
+
+ return 0;
+}
+
+static const struct clk_ops clk_pllv3_av_ops = {
+ .enable = clk_pllv3_enable,
+ .disable = clk_pllv3_disable,
+ .recalc_rate = clk_pllv3_av_recalc_rate,
+ .round_rate = clk_pllv3_av_round_rate,
+ .set_rate = clk_pllv3_av_set_rate,
+};
+
+static unsigned long clk_pllv3_enet_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ u32 div = readl(pll->base) & pll->div_mask;
+
+ switch (div) {
+ case 0:
+ return 25000000;
+ case 1:
+ return 50000000;
+ case 2:
+ return 100000000;
+ case 3:
+ return 125000000;
+ }
+
+ return 0;
+}
+
+static long clk_pllv3_enet_round_rate(struct clk *clk, unsigned long rate,
+ unsigned long *prate)
+{
+ if (rate >= 125000000)
+ rate = 125000000;
+ else if (rate >= 100000000)
+ rate = 100000000;
+ else if (rate >= 50000000)
+ rate = 50000000;
+ else
+ rate = 25000000;
+ return rate;
+}
+
+static int clk_pllv3_enet_set_rate(struct clk *clk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ u32 val, div;
+
+ switch (rate) {
+ case 25000000:
+ div = 0;
+ break;
+ case 50000000:
+ div = 1;
+ break;
+ case 100000000:
+ div = 2;
+ break;
+ case 125000000:
+ div = 3;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ val = readl(pll->base);
+ val &= ~pll->div_mask;
+ val |= div;
+ writel(val, pll->base);
+
+ return 0;
+}
+
+static const struct clk_ops clk_pllv3_enet_ops = {
+ .enable = clk_pllv3_enable,
+ .disable = clk_pllv3_disable,
+ .recalc_rate = clk_pllv3_enet_recalc_rate,
+ .round_rate = clk_pllv3_enet_round_rate,
+ .set_rate = clk_pllv3_enet_set_rate,
+};
+
+static const struct clk_ops clk_pllv3_mlb_ops = {
+ .enable = clk_pllv3_enable,
+ .disable = clk_pllv3_disable,
+};
+
+struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
+ const char *parent, void __iomem *base,
+ u32 gate_mask, u32 div_mask)
+{
+ struct clk_pllv3 *pll;
+ const struct clk_ops *ops;
+ int ret;
+
+ pll = xzalloc(sizeof(*pll));
+
+ switch (type) {
+ case IMX_PLLV3_SYS:
+ ops = &clk_pllv3_sys_ops;
+ break;
+ case IMX_PLLV3_USB:
+ ops = &clk_pllv3_ops;
+ pll->powerup_set = true;
+ break;
+ case IMX_PLLV3_AV:
+ ops = &clk_pllv3_av_ops;
+ break;
+ case IMX_PLLV3_ENET:
+ ops = &clk_pllv3_enet_ops;
+ break;
+ case IMX_PLLV3_MLB:
+ ops = &clk_pllv3_mlb_ops;
+ break;
+ default:
+ ops = &clk_pllv3_ops;
+ }
+ pll->base = base;
+ pll->gate_mask = gate_mask;
+ pll->div_mask = div_mask;
+ pll->parent = parent;
+ pll->clk.ops = ops;
+ pll->clk.name = name;
+ pll->clk.parent_names = &pll->parent;
+ pll->clk.num_parents = 1;
+
+ ret = clk_register(&pll->clk);
+ if (ret) {
+ free(pll);
+ return ERR_PTR(ret);
+ }
+
+ return &pll->clk;
+}
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
new file mode 100644
index 0000000..5024a25
--- /dev/null
+++ b/arch/arm/mach-imx/clk.h
@@ -0,0 +1,66 @@
+#ifndef __IMX_CLK_H
+#define __IMX_CLK_H
+
+static inline struct clk *imx_clk_divider(const char *name, const char *parent,
+ void __iomem *reg, u8 shift, u8 width)
+{
+ return clk_divider(name, parent, reg, shift, width);
+}
+
+static inline struct clk *imx_clk_fixed_factor(const char *name,
+ const char *parent, unsigned int mult, unsigned int div)
+{
+ return clk_fixed_factor(name, parent, mult, div);
+}
+
+static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
+ u8 shift, u8 width, const char **parents, int num_parents)
+{
+ return clk_mux(name, reg, shift, width, parents, num_parents);
+}
+
+struct clk *imx_clk_pllv1(const char *name, const char *parent,
+ void __iomem *base);
+
+struct clk *imx_clk_pllv2(const char *name, const char *parent,
+ void __iomem *base);
+
+enum imx_pllv3_type {
+ IMX_PLLV3_GENERIC,
+ IMX_PLLV3_SYS,
+ IMX_PLLV3_USB,
+ IMX_PLLV3_AV,
+ IMX_PLLV3_ENET,
+ IMX_PLLV3_MLB,
+};
+
+struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
+ const char *parent, void __iomem *base,
+ u32 gate_mask, u32 div_mask);
+
+struct clk *imx_clk_pfd(const char *name, const char *parent,
+ void __iomem *reg, u8 idx);
+
+static inline struct clk *imx_clk_busy_divider(const char *name, const char *parent,
+ void __iomem *reg, u8 shift, u8 width,
+ void __iomem *busy_reg, u8 busy_shift)
+{
+ /*
+ * For now we do not support rate setting, so just fall back to
+ * regular divider.
+ */
+ return imx_clk_divider(name, parent, reg, shift, width);
+}
+
+static inline struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
+ u8 width, void __iomem *busy_reg, u8 busy_shift,
+ const char **parents, int num_parents)
+{
+ /*
+ * For now we do not support mux switching, so just fall back to
+ * regular mux.
+ */
+ return imx_clk_mux(name, reg, shift, width, parents, num_parents);
+}
+
+#endif /* __IMX_CLK_H */
diff --git a/arch/arm/mach-imx/include/mach/clkdev.h b/arch/arm/mach-imx/include/mach/clkdev.h
new file mode 100644
index 0000000..04b37a8
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 06/23] ARM i.MX27: implement clk support
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (4 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 05/23] ARM i.MX: initial clk support Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 07/23] ARM i.MX25: Switch to common " Sascha Hauer
` (16 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/Kconfig | 2 +
arch/arm/mach-imx/Makefile | 2 +-
arch/arm/mach-imx/clk-imx27.c | 154 +++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/imx27.c | 4 +-
4 files changed, 160 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-imx/clk-imx27.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a54ad03..1cb56c5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -40,6 +40,8 @@ config ARCH_IMX
bool "Freescale iMX-based"
select GENERIC_GPIO
select GPIOLIB
+ select COMMON_CLK
+ select CLKDEV_LOOKUP
config ARCH_MXS
bool "Freescale i.MX23/28 (mxs) based"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f6d487f..74e08ad 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -3,7 +3,7 @@ obj-$(CONFIG_RESET_SOURCE) += reset_source.o
obj-$(CONFIG_ARCH_IMX1) += speed-imx1.o imx1.o iomux-v1.o
obj-$(CONFIG_ARCH_IMX25) += speed-imx25.o imx25.o iomux-v3.o
obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o
-obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o
+obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o clk-imx27.o
obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o
obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o imx5.o
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
new file mode 100644
index 0000000..74a3495
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -0,0 +1,154 @@
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <mach/imx27-regs.h>
+#include <mach/generic.h>
+
+#include "clk.h"
+
+/* Register offsets */
+#define CCM_CSCR 0x0
+#define CCM_MPCTL0 0x4
+#define CCM_MPCTL1 0x8
+#define CCM_SPCTL0 0xc
+#define CCM_SPCTL1 0x10
+#define CCM_OSC26MCTL 0x14
+#define CCM_PCDR0 0x18
+#define CCM_PCDR1 0x1c
+#define CCM_PCCR0 0x20
+#define CCM_PCCR1 0x24
+#define CCM_CCSR 0x28
+#define CCM_PMCTL 0x2c
+#define CCM_PMCOUNT 0x30
+#define CCM_WKGDCTL 0x34
+
+enum mx27_clks {
+ dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
+ per2_div, per3_div, per4_div, usb_div, cpu_sel, clko_sel, cpu_div, clko_div,
+ clko_en, clk_max
+};
+
+static struct clk *clks[clk_max];
+
+static const char *cpu_sel_clks[] = {
+ "mpll_main2",
+ "mpll",
+};
+
+static const char *clko_sel_clks[] = {
+ "ckil",
+ NULL,
+ "ckih",
+ "ckih",
+ "ckih",
+ "mpll",
+ "spll",
+ "cpu_div",
+ "ahb",
+ "ipg",
+ "per1_div",
+ "per2_div",
+ "per3_div",
+ "per4_div",
+ NULL,
+ NULL,
+ "nfc_div",
+ NULL,
+ NULL,
+ NULL,
+ "ckil",
+ "usb_div",
+ NULL,
+};
+
+static int imx27_ccm_probe(struct device_d *dev)
+{
+ void __iomem *base;
+
+ base = dev_request_mem_region(dev, 0);
+
+ writel(PCCR0_SDHC3_EN | PCCR0_SDHC2_EN | PCCR0_SDHC1_EN |
+ PCCR0_PWM_EN | PCCR0_KPP_EN | PCCR0_IIM_EN | PCCR0_I2C2_EN |
+ PCCR0_I2C1_EN | PCCR0_GPT6_EN | PCCR0_GPT5_EN | PCCR0_GPT4_EN |
+ PCCR0_GPT3_EN | PCCR0_GPT2_EN | PCCR0_GPT1_EN | PCCR0_GPIO_EN |
+ PCCR0_FEC_EN | PCCR0_CSPI3_EN | PCCR0_CSPI2_EN | PCCR0_CSPI1_EN,
+ base + CCM_PCCR0);
+
+ writel(PCCR1_NFC_BAUDEN | PCCR1_PERCLK4_EN | PCCR1_PERCLK3_EN |
+ PCCR1_PERCLK2_EN | PCCR1_PERCLK1_EN | PCCR1_HCLK_USB |
+ PCCR1_HCLK_FEC | PCCR1_HCLK_EMI | PCCR1_WDT_EN | PCCR1_USB_EN |
+ PCCR1_UART6_EN | PCCR1_UART5_EN | PCCR1_UART4_EN |
+ PCCR1_UART3_EN | PCCR1_UART2_EN | PCCR1_UART1_EN,
+ base + CCM_PCCR1);
+
+ clks[dummy] = clk_fixed("dummy", 0);
+ clks[ckih] = clk_fixed("ckih", 26000000);
+ clks[ckil] = clk_fixed("ckil", 32768);
+ clks[mpll] = imx_clk_pllv1("mpll", "ckih", base + CCM_MPCTL0);
+ clks[spll] = imx_clk_pllv1("spll", "ckih", base + CCM_SPCTL0);
+ clks[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
+
+ if (imx_silicon_revision() >= IMX27_CHIP_REVISION_2_0) {
+ clks[ahb] = imx_clk_divider("ahb", "mpll_main2", base + CCM_CSCR, 8, 2);
+ clks[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
+ } else {
+ clks[ahb] = imx_clk_divider("ahb", "mpll_main2", base + CCM_CSCR, 9, 4);
+ clks[ipg] = imx_clk_divider("ipg", "ahb", base + CCM_CSCR, 8, 1);
+ }
+
+ clks[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + CCM_PCDR0, 6, 4);
+ clks[per1_div] = imx_clk_divider("per1_div", "mpll_main2", base + CCM_PCDR1, 0, 6);
+ clks[per2_div] = imx_clk_divider("per2_div", "mpll_main2", base + CCM_PCDR1, 8, 6);
+ clks[per3_div] = imx_clk_divider("per3_div", "mpll_main2", base + CCM_PCDR1, 16, 6);
+ clks[per4_div] = imx_clk_divider("per4_div", "mpll_main2", base + CCM_PCDR1, 24, 6);
+ clks[usb_div] = imx_clk_divider("usb_div", "spll", base + CCM_CSCR, 28, 3);
+ clks[cpu_sel] = imx_clk_mux("cpu_sel", base + CCM_CSCR, 15, 1, cpu_sel_clks,
+ ARRAY_SIZE(cpu_sel_clks));
+ clks[clko_sel] = imx_clk_mux("clko_sel", base + CCM_CCSR, 0, 5, clko_sel_clks,
+ ARRAY_SIZE(clko_sel_clks));
+ if (imx_silicon_revision() >= IMX27_CHIP_REVISION_2_0)
+ clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 12, 2);
+ else
+ clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 13, 3);
+ clks[clko_div] = imx_clk_divider("clko_div", "clko_sel", base + CCM_PCDR0, 22, 3);
+
+ clkdev_add_physbase(clks[ipg], MX27_GPT1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX27_GPT2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX27_GPT3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX27_GPT4_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX27_GPT5_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX27_GPT6_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per1_div], MX27_UART1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per1_div], MX27_UART2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per1_div], MX27_UART3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per1_div], MX27_UART4_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per1_div], MX27_UART5_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per1_div], MX27_UART6_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX27_CSPI1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX27_CSPI2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX27_CSPI3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX27_I2C1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX27_I2C2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per2_div], MX27_SDHC1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per2_div], MX27_SDHC2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per2_div], MX27_SDHC3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per3_div], MX27_LCDC_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX27_FEC_BASE_ADDR, NULL);
+
+ return 0;
+}
+
+static struct driver_d imx27_ccm_driver = {
+ .probe = imx27_ccm_probe,
+ .name = "imx27-ccm",
+};
+
+static int imx27_ccm_init(void)
+{
+ return register_driver(&imx27_ccm_driver);
+}
+postcore_initcall(imx27_ccm_init);
diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c
index 0c92385..8116e6f 100644
--- a/arch/arm/mach-imx/imx27.c
+++ b/arch/arm/mach-imx/imx27.c
@@ -78,6 +78,7 @@ static int imx27_init(void)
imx27_init_max();
+ add_generic_device("imx27-ccm", 0, NULL, MX27_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpt", 0, NULL, MX27_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpio", 0, NULL, MX27_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpio", 1, NULL, MX27_GPIO2_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
@@ -85,6 +86,7 @@ static int imx27_init(void)
add_generic_device("imx1-gpio", 3, NULL, MX27_GPIO4_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpio", 4, NULL, MX27_GPIO5_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpio", 5, NULL, MX27_GPIO6_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+
return 0;
}
-console_initcall(imx27_init);
+postcore_initcall(imx27_init);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 07/23] ARM i.MX25: Switch to common clk support
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (5 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 06/23] ARM i.MX27: implement " Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 08/23] ARM i.MX5: " Sascha Hauer
` (15 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/Makefile | 2 +-
arch/arm/mach-imx/clk-imx25.c | 154 +++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/imx25.c | 3 +-
3 files changed, 157 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-imx/clk-imx25.c
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 74e08ad..4cb7011 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,7 +1,7 @@
obj-y += clocksource.o gpio.o
obj-$(CONFIG_RESET_SOURCE) += reset_source.o
obj-$(CONFIG_ARCH_IMX1) += speed-imx1.o imx1.o iomux-v1.o
-obj-$(CONFIG_ARCH_IMX25) += speed-imx25.o imx25.o iomux-v3.o
+obj-$(CONFIG_ARCH_IMX25) += speed-imx25.o imx25.o iomux-v3.o clk-imx25.o
obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o
obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o clk-imx27.o
obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
new file mode 100644
index 0000000..61033d6
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2009 by Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <mach/imx25-regs.h>
+
+#include "clk.h"
+
+#define CCM_MPCTL 0x00
+#define CCM_UPCTL 0x04
+#define CCM_CCTL 0x08
+#define CCM_CGCR0 0x0C
+#define CCM_CGCR1 0x10
+#define CCM_CGCR2 0x14
+#define CCM_PCDR0 0x18
+#define CCM_PCDR1 0x1C
+#define CCM_PCDR2 0x20
+#define CCM_PCDR3 0x24
+#define CCM_RCSR 0x28
+#define CCM_CRDR 0x2C
+#define CCM_DCVR0 0x30
+#define CCM_DCVR1 0x34
+#define CCM_DCVR2 0x38
+#define CCM_DCVR3 0x3c
+#define CCM_LTR0 0x40
+#define CCM_LTR1 0x44
+#define CCM_LTR2 0x48
+#define CCM_LTR3 0x4c
+#define CCM_MCR 0x64
+
+enum mx25_clks {
+ dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg,
+ per0_sel, per1_sel, per2_sel, per3_sel, per4_sel, per5_sel, per6_sel,
+ per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel,
+ per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5,
+ per6, per7, per8, per9, per10, per11, per12, per13, per14, per15,
+ clk_max
+};
+
+static struct clk *clks[clk_max];
+
+static const char *cpu_sel_clks[] = {
+ "mpll",
+ "mpll_cpu_3_4",
+};
+
+static const char *per_sel_clks[] = {
+ "ahb",
+ "upll",
+};
+
+static int imx25_ccm_probe(struct device_d *dev)
+{
+ void __iomem *base;
+
+ base = dev_request_mem_region(dev, 0);
+
+ writel(0x10e88578, base + CCM_CGCR0);
+ writel(0x0478e1e0, base + CCM_CGCR0);
+ writel(0x0007c400, base + CCM_CGCR0);
+
+ clks[dummy] = clk_fixed("dummy", 0);
+ clks[osc] = clk_fixed("osc", 24000000);
+ clks[mpll] = imx_clk_pllv1("mpll", "osc", base + CCM_MPCTL);
+ clks[upll] = imx_clk_pllv1("upll", "osc", base + CCM_UPCTL);
+ clks[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
+ clks[cpu_sel] = imx_clk_mux("cpu_sel", base + CCM_CCTL, 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
+ clks[cpu] = imx_clk_divider("cpu", "cpu_sel", base + CCM_CCTL, 30, 2);
+ clks[ahb] = imx_clk_divider("ahb", "cpu", base + CCM_CCTL, 28, 2);
+ clks[usb_div] = imx_clk_divider("usb_div", "upll", base + CCM_CCTL, 16, 6);
+ clks[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
+ clks[per0_sel] = imx_clk_mux("per0_sel", base + CCM_MCR, 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per1_sel] = imx_clk_mux("per1_sel", base + CCM_MCR, 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per2_sel] = imx_clk_mux("per2_sel", base + CCM_MCR, 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per3_sel] = imx_clk_mux("per3_sel", base + CCM_MCR, 3, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per4_sel] = imx_clk_mux("per4_sel", base + CCM_MCR, 4, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per5_sel] = imx_clk_mux("per5_sel", base + CCM_MCR, 5, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per6_sel] = imx_clk_mux("per6_sel", base + CCM_MCR, 6, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per7_sel] = imx_clk_mux("per7_sel", base + CCM_MCR, 7, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per8_sel] = imx_clk_mux("per8_sel", base + CCM_MCR, 8, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per9_sel] = imx_clk_mux("per9_sel", base + CCM_MCR, 9, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per10_sel] = imx_clk_mux("per10_sel", base + CCM_MCR, 10, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per11_sel] = imx_clk_mux("per11_sel", base + CCM_MCR, 11, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per12_sel] = imx_clk_mux("per12_sel", base + CCM_MCR, 12, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per13_sel] = imx_clk_mux("per13_sel", base + CCM_MCR, 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per14_sel] = imx_clk_mux("per14_sel", base + CCM_MCR, 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per15_sel] = imx_clk_mux("per15_sel", base + CCM_MCR, 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+ clks[per0] = imx_clk_divider("per0", "per0_sel", base + CCM_PCDR0, 0, 6);
+ clks[per1] = imx_clk_divider("per1", "per1_sel", base + CCM_PCDR0, 8, 6);
+ clks[per2] = imx_clk_divider("per2", "per2_sel", base + CCM_PCDR0, 16, 6);
+ clks[per3] = imx_clk_divider("per3", "per3_sel", base + CCM_PCDR0, 24, 6);
+ clks[per4] = imx_clk_divider("per4", "per4_sel", base + CCM_PCDR1, 0, 6);
+ clks[per5] = imx_clk_divider("per5", "per5_sel", base + CCM_PCDR1, 8, 6);
+ clks[per6] = imx_clk_divider("per6", "per6_sel", base + CCM_PCDR1, 16, 6);
+ clks[per7] = imx_clk_divider("per7", "per7_sel", base + CCM_PCDR1, 24, 6);
+ clks[per8] = imx_clk_divider("per8", "per8_sel", base + CCM_PCDR2, 0, 6);
+ clks[per9] = imx_clk_divider("per9", "per9_sel", base + CCM_PCDR2, 8, 6);
+ clks[per10] = imx_clk_divider("per10", "per10_sel", base + CCM_PCDR2, 16, 6);
+ clks[per11] = imx_clk_divider("per11", "per11_sel", base + CCM_PCDR2, 24, 6);
+ clks[per12] = imx_clk_divider("per12", "per12_sel", base + CCM_PCDR3, 0, 6);
+ clks[per13] = imx_clk_divider("per13", "per13_sel", base + CCM_PCDR3, 8, 6);
+ clks[per14] = imx_clk_divider("per14", "per14_sel", base + CCM_PCDR3, 16, 6);
+ clks[per15] = imx_clk_divider("per15", "per15_sel", base + CCM_PCDR3, 24, 6);
+
+ clkdev_add_physbase(clks[per15], MX25_UART1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per15], MX25_UART2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per15], MX25_UART3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per15], MX25_UART4_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per15], MX25_UART5_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX25_GPT1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX25_FEC_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX25_I2C1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX25_I2C2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX25_I2C3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX25_CSPI1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX25_CSPI2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX25_CSPI3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per3], MX25_ESDHC1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per4], MX25_ESDHC2_BASE_ADDR, NULL);
+
+ return 0;
+}
+
+static struct driver_d imx25_ccm_driver = {
+ .probe = imx25_ccm_probe,
+ .name = "imx25-ccm",
+};
+
+static int imx25_ccm_init(void)
+{
+ return register_driver(&imx25_ccm_driver);
+}
+postcore_initcall(imx25_ccm_init);
diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c
index 32c0412..5e6532a 100644
--- a/arch/arm/mach-imx/imx25.c
+++ b/arch/arm/mach-imx/imx25.c
@@ -61,6 +61,7 @@ static int imx25_init(void)
add_generic_device("imx_iim", 0, NULL, MX25_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, &imx25_iim_pdata);
+ add_generic_device("imx25-ccm", 0, NULL, MX25_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, MX25_GPT1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 0, NULL, MX25_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 1, NULL, MX25_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
@@ -69,4 +70,4 @@ static int imx25_init(void)
return 0;
}
-coredevice_initcall(imx25_init);
+postcore_initcall(imx25_init);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 08/23] ARM i.MX5: Switch to common clk support
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (6 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 07/23] ARM i.MX25: Switch to common " Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:36 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 09/23] ARM i.MX1: " Sascha Hauer
` (14 subsequent siblings)
22 siblings, 1 reply; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/Makefile | 4 +-
arch/arm/mach-imx/clk-imx5.c | 298 ++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/imx51.c | 3 +-
arch/arm/mach-imx/imx53.c | 3 +-
4 files changed, 304 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/mach-imx/clk-imx5.c
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 4cb7011..282913d 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -6,8 +6,8 @@ obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o
obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o clk-imx27.o
obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o
obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
-obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o imx5.o
-obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o imx5.o
+obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o imx5.o clk-imx5.o
+obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o imx5.o clk-imx5.o
obj-$(CONFIG_ARCH_IMX6) += speed-imx6.o imx6.o iomux-v3.o usb-imx6.o
obj-$(CONFIG_IMX_CLKO) += clko.o
obj-$(CONFIG_IMX_IIM) += iim.o
diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c
new file mode 100644
index 0000000..476ea29
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx5.c
@@ -0,0 +1,298 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <mach/imx-regs.h>
+
+#include "clk.h"
+
+/* Register addresses of CCM*/
+#define CCM_CCR 0x00
+#define CCM_CCDR 0x04
+#define CCM_CSR 0x08
+#define CCM_CCSR 0x0C
+#define CCM_CACRR 0x10
+#define CCM_CBCDR 0x14
+#define CCM_CBCMR 0x18
+#define CCM_CSCMR1 0x1C
+#define CCM_CSCMR2 0x20
+#define CCM_CSCDR1 0x24
+#define CCM_CS1CDR 0x28
+#define CCM_CS2CDR 0x2C
+#define CCM_CDCDR 0x30
+#define CCM_CHSCDR 0x34
+#define CCM_CSCDR2 0x38
+#define CCM_CSCDR3 0x3C
+#define CCM_CSCDR4 0x40
+#define CCM_CWDR 0x44
+#define CCM_CDHIPR 0x48
+#define CCM_CDCR 0x4C
+#define CCM_CTOR 0x50
+#define CCM_CLPCR 0x54
+#define CCM_CISR 0x58
+#define CCM_CIMR 0x5C
+#define CCM_CCOSR 0x60
+#define CCM_CGPR 0x64
+#define CCM_CCGR0 0x68
+#define CCM_CCGR1 0x6C
+#define CCM_CCGR2 0x70
+#define CCM_CCGR3 0x74
+#define CCM_CCGR4 0x78
+#define CCM_CCGR5 0x7C
+#define CCM_CCGR6 0x80
+#define CCM_CCGR7 0x84
+
+#define CCM_CMEOR 0x84
+
+enum imx5_clks {
+ dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
+ uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
+ emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
+ usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, lp_apm,
+ periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
+ tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
+ esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel,
+ gpc_dvfs, pll1_sw, pll2_sw,
+ pll3_sw, pll4_sw, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
+ clk_max
+};
+
+static struct clk *clks[clk_max];
+
+/* This is used multiple times */
+static const char *standard_pll_sel[] = {
+ "pll1_sw",
+ "pll2_sw",
+ "pll3_sw",
+ "lp_apm",
+};
+
+static const char *lp_apm_sel[] = {
+ "osc",
+};
+
+static const char *periph_apm_sel[] = {
+ "pll1_sw",
+ "pll3_sw",
+ "lp_apm",
+};
+
+static const char *main_bus_sel[] = {
+ "pll2_sw",
+ "periph_apm",
+};
+
+static const char *per_lp_apm_sel[] = {
+ "main_bus",
+ "lp_apm",
+};
+
+static const char *per_root_sel[] = {
+ "per_podf",
+ "ipg",
+};
+
+static const char *esdhc_c_sel[] = {
+ "esdhc_a_podf",
+ "esdhc_b_podf",
+};
+
+static const char *esdhc_d_sel[] = {
+ "esdhc_a_podf",
+ "esdhc_b_podf",
+};
+
+static const char *emi_slow_sel[] = {
+ "main_bus",
+ "ahb",
+};
+
+static const char *usb_phy_sel_str[] = {
+ "osc",
+ "usb_phy_podf",
+};
+
+static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate_ckil,
+ unsigned long rate_osc, unsigned long rate_ckih1,
+ unsigned long rate_ckih2)
+{
+ writel(0xffffffff, base + CCM_CCGR0);
+ writel(0xffffffff, base + CCM_CCGR1);
+ writel(0xffffffff, base + CCM_CCGR2);
+ writel(0xffffffff, base + CCM_CCGR3);
+ writel(0xffffffff, base + CCM_CCGR4);
+ writel(0xffffffff, base + CCM_CCGR5);
+ writel(0xffffffff, base + CCM_CCGR6);
+ writel(0xffffffff, base + CCM_CCGR7);
+
+ clks[dummy] = clk_fixed("dummy", 0);
+ clks[ckil] = clk_fixed("ckil", rate_ckil);
+ clks[osc] = clk_fixed("osc", rate_osc);
+ clks[ckih1] = clk_fixed("ckih1", rate_ckih1);
+ clks[ckih2] = clk_fixed("ckih2", rate_ckih2);
+
+ clks[lp_apm] = imx_clk_mux("lp_apm", base + CCM_CCSR, 9, 1,
+ lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
+ clks[periph_apm] = imx_clk_mux("periph_apm", base + CCM_CBCMR, 12, 2,
+ periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
+ clks[main_bus] = imx_clk_mux("main_bus", base + CCM_CBCDR, 25, 1,
+ main_bus_sel, ARRAY_SIZE(main_bus_sel));
+ clks[per_lp_apm] = imx_clk_mux("per_lp_apm", base + CCM_CBCMR, 1, 1,
+ per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
+ clks[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", base + CCM_CBCDR, 6, 2);
+ clks[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", base + CCM_CBCDR, 3, 3);
+ clks[per_podf] = imx_clk_divider("per_podf", "per_pred2", base + CCM_CBCDR, 0, 3);
+ clks[per_root] = imx_clk_mux("per_root", base + CCM_CBCMR, 0, 1,
+ per_root_sel, ARRAY_SIZE(per_root_sel));
+ clks[ahb] = imx_clk_divider("ahb", "main_bus", base + CCM_CBCDR, 10, 3);
+ clks[ipg] = imx_clk_divider("ipg", "ahb", base + CCM_CBCDR, 8, 2);
+ clks[axi_a] = imx_clk_divider("axi_a", "main_bus", base + CCM_CBCDR, 16, 3);
+ clks[axi_b] = imx_clk_divider("axi_b", "main_bus", base + CCM_CBCDR, 19, 3);
+ clks[uart_sel] = imx_clk_mux("uart_sel", base + CCM_CSCMR1, 24, 2,
+ standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+ clks[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", base + CCM_CSCDR1, 3, 3);
+ clks[uart_root] = imx_clk_divider("uart_root", "uart_pred", base + CCM_CSCDR1, 0, 3);
+
+ clks[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", base + CCM_CSCMR1, 20, 2,
+ standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+ clks[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", base + CCM_CSCMR1, 16, 2,
+ standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+ clks[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", base + CCM_CSCDR1, 16, 3);
+ clks[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", base + CCM_CSCDR1, 11, 3);
+ clks[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", base + CCM_CSCDR1, 22, 3);
+ clks[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", base + CCM_CSCDR1, 19, 3);
+ clks[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", base + CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
+ clks[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", base + CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
+
+ clks[emi_sel] = imx_clk_mux("emi_sel", base + CCM_CBCDR, 26, 1,
+ emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
+ clks[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", base + CCM_CBCDR, 22, 3);
+ clks[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", base + CCM_CBCDR, 13, 3);
+ clks[ecspi_sel] = imx_clk_mux("ecspi_sel", base + CCM_CSCMR1, 4, 2,
+ standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+ clks[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", base + CCM_CSCDR2, 25, 3);
+ clks[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", base + CCM_CSCDR2, 19, 6);
+ clks[usboh3_sel] = imx_clk_mux("usboh3_sel", base + CCM_CSCMR1, 22, 2,
+ standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+ clks[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", base + CCM_CSCDR1, 8, 3);
+ clks[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", base + CCM_CSCDR1, 6, 2);
+ clks[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", base + CCM_CDCDR, 3, 3);
+ clks[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", base + CCM_CDCDR, 0, 3);
+ clks[usb_phy_sel] = imx_clk_mux("usb_phy_sel", base + CCM_CSCMR1, 26, 1,
+ usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
+ clks[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", base + CCM_CACRR, 0, 3);
+}
+
+#ifdef CONFIG_ARCH_IMX51
+int __init mx51_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
+ unsigned long rate_ckih1, unsigned long rate_ckih2)
+{
+ clks[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX51_PLL1_BASE_ADDR);
+ clks[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX51_PLL2_BASE_ADDR);
+ clks[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX51_PLL2_BASE_ADDR);
+
+ mx5_clocks_common_init(regs, rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
+
+ clkdev_add_physbase(clks[uart_root], MX51_UART1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[uart_root], MX51_UART2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[uart_root], MX51_UART3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per_root], MX51_I2C1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per_root], MX51_I2C2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX51_GPT1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX51_CSPI_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ecspi_podf], MX51_ECSPI1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ecspi_podf], MX51_ECSPI2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX51_MXC_FEC_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[esdhc_a_podf], MX51_MMC_SDHC1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[esdhc_b_podf], MX51_MMC_SDHC2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[esdhc_c_s], MX51_MMC_SDHC3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[esdhc_d_s], MX51_MMC_SDHC4_BASE_ADDR, NULL);
+
+ return 0;
+}
+
+static int imx51_ccm_probe(struct device_d *dev)
+{
+ void __iomem *regs;
+
+ regs = dev_request_mem_region(dev, 0);
+
+ mx51_clocks_init(regs, 32768, 24000000, 22579200, 0); /* FIXME */
+
+ return 0;
+}
+
+static struct driver_d imx51_ccm_driver = {
+ .probe = imx51_ccm_probe,
+ .name = "imx51-ccm",
+};
+
+static int imx51_ccm_init(void)
+{
+ return register_driver(&imx51_ccm_driver);
+}
+postcore_initcall(imx51_ccm_init);
+#endif
+
+#ifdef CONFIG_ARCH_IMX53
+int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
+ unsigned long rate_ckih1, unsigned long rate_ckih2)
+{
+ clks[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX53_PLL1_BASE_ADDR);
+ clks[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX53_PLL2_BASE_ADDR);
+ clks[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX53_PLL3_BASE_ADDR);
+ clks[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", (void *)MX53_PLL4_BASE_ADDR);
+
+ mx5_clocks_common_init(regs, rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
+
+ clkdev_add_physbase(clks[uart_root], MX53_UART1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[uart_root], MX53_UART2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[uart_root], MX53_UART3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per_root], MX53_I2C1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per_root], MX53_I2C2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX53_GPT1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX53_CSPI_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ecspi_podf], MX53_ECSPI1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ecspi_podf], MX53_ECSPI2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX53_FEC_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[esdhc_a_podf], MX53_ESDHC1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[esdhc_c_s], MX53_ESDHC2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[esdhc_b_podf], MX53_ESDHC3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[esdhc_d_s], MX53_ESDHC4_BASE_ADDR, NULL);
+
+ return 0;
+}
+
+static int imx53_ccm_probe(struct device_d *dev)
+{
+ void __iomem *regs;
+
+ regs = dev_request_mem_region(dev, 0);
+
+ mx53_clocks_init(regs, 32768, 24000000, 22579200, 0); /* FIXME */
+
+ return 0;
+}
+
+static struct driver_d imx53_ccm_driver = {
+ .probe = imx53_ccm_probe,
+ .name = "imx53-ccm",
+};
+
+static int imx53_ccm_init(void)
+{
+ return register_driver(&imx53_ccm_driver);
+}
+postcore_initcall(imx53_ccm_init);
+#endif
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index b1eeb0c..8709c43 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -74,6 +74,7 @@ static int imx51_init(void)
add_generic_device("imx_iim", 0, NULL, MX51_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
+ add_generic_device("imx51-ccm", 0, NULL, MX51_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, MX51_GPT1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 0, NULL, MX51_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 1, NULL, MX51_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
@@ -82,7 +83,7 @@ static int imx51_init(void)
return 0;
}
-coredevice_initcall(imx51_init);
+postcore_initcall(imx51_init);
/*
* Saves the boot source media into the $barebox_loc enviroment variable
diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c
index 2d7c174..88b4274 100644
--- a/arch/arm/mach-imx/imx53.c
+++ b/arch/arm/mach-imx/imx53.c
@@ -70,6 +70,7 @@ static int imx53_init(void)
add_generic_device("imx_iim", 0, NULL, MX53_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
+ add_generic_device("imx53-ccm", 0, NULL, MX53_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, 0X53fa0000, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 0, NULL, MX53_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 1, NULL, MX53_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
@@ -81,7 +82,7 @@ static int imx53_init(void)
return 0;
}
-coredevice_initcall(imx53_init);
+postcore_initcall(imx53_init);
#define setup_pll_1000(base) imx5_setup_pll((base), 1000, ((10 << 4) + ((1 - 1) << 0)), (12 - 1), 5)
#define setup_pll_800(base) imx5_setup_pll((base), 800, ((8 << 4) + ((1 - 1) << 0)), (3 - 1), 1)
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 08/23] ARM i.MX5: Switch to common clk support
2012-09-24 11:04 ` [PATCH 08/23] ARM i.MX5: " Sascha Hauer
@ 2012-09-24 11:36 ` Sascha Hauer
0 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:36 UTC (permalink / raw)
To: barebox
On Mon, Sep 24, 2012 at 01:04:37PM +0200, Sascha Hauer wrote:
> +{
> + clks[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX51_PLL1_BASE_ADDR);
> + clks[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX51_PLL2_BASE_ADDR);
> + clks[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX51_PLL2_BASE_ADDR);
typo: Should be MX51_PLL3_BASE_ADDR. Will fix.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 09/23] ARM i.MX1: Switch to common clk support
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (7 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 08/23] ARM i.MX5: " Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 10/23] ARM i.MX31: Switch to common clk Sascha Hauer
` (13 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/Makefile | 2 +-
arch/arm/mach-imx/clk-imx1.c | 108 ++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/imx1.c | 3 +-
3 files changed, 111 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-imx/clk-imx1.c
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 282913d..994159d 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,6 +1,6 @@
obj-y += clocksource.o gpio.o
obj-$(CONFIG_RESET_SOURCE) += reset_source.o
-obj-$(CONFIG_ARCH_IMX1) += speed-imx1.o imx1.o iomux-v1.o
+obj-$(CONFIG_ARCH_IMX1) += speed-imx1.o imx1.o iomux-v1.o clk-imx1.o
obj-$(CONFIG_ARCH_IMX25) += speed-imx25.o imx25.o iomux-v3.o clk-imx25.o
obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o
obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o clk-imx27.o
diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c
new file mode 100644
index 0000000..30906bf
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx1.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <mach/imx1-regs.h>
+
+#include "clk.h"
+
+#define CCM_CSCR 0x0
+#define CCM_MPCTL0 0x4
+#define CCM_SPCTL0 0xc
+#define CCM_PCDR 0x20
+
+enum imx1_clks {
+ dummy, clk32, clk16m, clk32_premult, prem, mpll, spll, mcu,
+ fclk, hclk, clk48m, per1, per2, per3, clko, dma_gate, csi_gate,
+ mma_gate, usbd_gate, clk_max
+};
+
+static struct clk *clks[clk_max];
+
+static const char *prem_sel_clks[] = {
+ "clk32_premult",
+ "clk16m",
+};
+
+static const char *clko_sel_clks[] = {
+ "per1",
+ "hclk",
+ "clk48m",
+ "clk16m",
+ "prem",
+ "fclk",
+};
+
+int __init mx1_clocks_init(void __iomem *regs, unsigned long fref)
+{
+ clks[dummy] = clk_fixed("dummy", 0);
+ clks[clk32] = clk_fixed("clk32", fref);
+ clks[clk16m] = clk_fixed("clk16m", 16000000);
+ clks[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
+ clks[prem] = imx_clk_mux("prem", regs + CCM_CSCR, 16, 1, prem_sel_clks,
+ ARRAY_SIZE(prem_sel_clks));
+ clks[mpll] = imx_clk_pllv1("mpll", "clk32_premult", regs + CCM_MPCTL0);
+ clks[spll] = imx_clk_pllv1("spll", "prem", regs + CCM_SPCTL0);
+ clks[mcu] = imx_clk_divider("mcu", "clk32_premult", regs + CCM_CSCR, 15, 1);
+ clks[fclk] = imx_clk_divider("fclk", "mpll", regs + CCM_CSCR, 15, 1);
+ clks[hclk] = imx_clk_divider("hclk", "spll", regs + CCM_CSCR, 10, 4);
+ clks[clk48m] = imx_clk_divider("clk48m", "spll", regs + CCM_CSCR, 26, 3);
+ clks[per1] = imx_clk_divider("per1", "spll", regs + CCM_PCDR, 0, 4);
+ clks[per2] = imx_clk_divider("per2", "spll", regs + CCM_PCDR, 4, 4);
+ clks[per3] = imx_clk_divider("per3", "spll", regs + CCM_PCDR, 16, 7);
+ clks[clko] = imx_clk_mux("clko", regs + CCM_CSCR, 29, 3, clko_sel_clks,
+ ARRAY_SIZE(clko_sel_clks));
+
+ clkdev_add_physbase(clks[hclk], MX1_TIM1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[hclk], MX1_TIM2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per2], MX1_LCDC_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per1], MX1_UART1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per1], MX1_UART2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per2], MX1_CSPI1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per2], MX1_CSPI2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[hclk], MX1_I2C_BASE_ADDR, NULL);
+
+ return 0;
+}
+
+static int imx1_ccm_probe(struct device_d *dev)
+{
+ void __iomem *regs;
+
+ regs = dev_request_mem_region(dev, 0);
+
+ mx1_clocks_init(regs, 32000);
+
+ return 0;
+}
+
+static struct driver_d imx1_ccm_driver = {
+ .probe = imx1_ccm_probe,
+ .name = "imx1-ccm",
+};
+
+static int imx1_ccm_init(void)
+{
+ return register_driver(&imx1_ccm_driver);
+}
+postcore_initcall(imx1_ccm_init);
diff --git a/arch/arm/mach-imx/imx1.c b/arch/arm/mach-imx/imx1.c
index 536a9ad..790e453 100644
--- a/arch/arm/mach-imx/imx1.c
+++ b/arch/arm/mach-imx/imx1.c
@@ -25,6 +25,7 @@ void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower)
static int imx1_init(void)
{
+ add_generic_device("imx1-ccm", 0, NULL, MX1_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpt", 0, NULL, MX1_TIM1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpio", 0, NULL, MX1_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpio", 1, NULL, MX1_GPIO2_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
@@ -33,4 +34,4 @@ static int imx1_init(void)
return 0;
}
-coredevice_initcall(imx1_init);
+postcore_initcall(imx1_init);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 10/23] ARM i.MX31: Switch to common clk
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (8 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 09/23] ARM i.MX1: " Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 11/23] ARM i.MX6: " Sascha Hauer
` (12 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/Makefile | 2 +-
arch/arm/mach-imx/clk-imx31.c | 133 +++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/imx31.c | 3 +-
3 files changed, 136 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-imx/clk-imx31.c
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 994159d..db203e8 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -4,7 +4,7 @@ obj-$(CONFIG_ARCH_IMX1) += speed-imx1.o imx1.o iomux-v1.o clk-imx1.o
obj-$(CONFIG_ARCH_IMX25) += speed-imx25.o imx25.o iomux-v3.o clk-imx25.o
obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o
obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o clk-imx27.o
-obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o
+obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o clk-imx31.o
obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o imx5.o clk-imx5.o
obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o imx5.o clk-imx5.o
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
new file mode 100644
index 0000000..6c181a1
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <mach/imx31-regs.h>
+
+#include "clk.h"
+
+/* Register addresses */
+#define CCM_CCMR 0x00
+#define CCM_PDR0 0x04
+#define CCM_PDR1 0x08
+//#define CCM_RCSR 0x0C
+#define CCM_MPCTL 0x10
+#define CCM_UPCTL 0x14
+#define CCM_SRPCTL 0x18
+#define CCM_COSR 0x1C
+#define CCM_CGR0 0x20
+#define CCM_CGR1 0x24
+#define CCM_CGR2 0x28
+#define CCM_WIMR 0x2C
+#define CCM_LDC 0x30
+#define CCM_DCVR0 0x34
+#define CCM_DCVR1 0x38
+#define CCM_DCVR2 0x3C
+#define CCM_DCVR3 0x40
+#define CCM_LTR0 0x44
+#define CCM_LTR1 0x48
+#define CCM_LTR2 0x4C
+#define CCM_LTR3 0x50
+#define CCM_LTBR0 0x54
+#define CCM_LTBR1 0x58
+#define CCM_PMCR0 0x5C
+#define CCM_PMCR1 0x60
+#define CCM_PDR2 0x64
+
+enum mx31_clks {
+ ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, per_div,
+ per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
+ fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
+ iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
+ uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
+ mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate,
+ sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate,
+ uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate,
+ gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max
+};
+
+static struct clk *clks[clk_max];
+
+static const char *mcu_main_sel[] = {
+ "spll",
+ "mpll",
+};
+
+static const char *per_sel[] = {
+ "per_div",
+ "ipg",
+};
+
+static int imx31_ccm_probe(struct device_d *dev)
+{
+ void __iomem *base;
+
+ base = dev_request_mem_region(dev, 0);
+
+ writel(0xffffffff, base + CCM_CGR0);
+ writel(0xffffffff, base + CCM_CGR1);
+ writel(0xffffffff, base + CCM_CGR2);
+
+ clks[ckih] = clk_fixed("ckih", 26000000);
+ clks[ckil] = clk_fixed("ckil", 32768);
+ clks[mpll] = imx_clk_pllv1("mpll", "ckih", base + CCM_MPCTL);
+ clks[spll] = imx_clk_pllv1("spll", "ckih", base + CCM_SRPCTL);
+ clks[upll] = imx_clk_pllv1("upll", "ckih", base + CCM_UPCTL);
+ clks[mcu_main] = imx_clk_mux("mcu_main", base + CCM_PMCR0, 31, 1,
+ mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
+ clks[hsp] = imx_clk_divider("hsp", "mcu_main", base + CCM_PDR0, 11, 3);
+ clks[ahb] = imx_clk_divider("ahb", "mcu_main", base + CCM_PDR0, 3, 3);
+ clks[nfc] = imx_clk_divider("nfc", "ahb", base + CCM_PDR0, 8, 3);
+ clks[ipg] = imx_clk_divider("ipg", "ahb", base + CCM_PDR0, 6, 2);
+ clks[per_div] = imx_clk_divider("per_div", "upll", base + CCM_PDR0, 16, 5);
+ clks[per] = imx_clk_mux("per", base + CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));
+
+ clkdev_add_physbase(clks[per], MX31_UART1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per], MX31_UART2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per], MX31_UART3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per], MX31_UART4_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per], MX31_UART5_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per], MX31_I2C1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per], MX31_I2C2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per], MX31_I2C3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX31_CSPI1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX31_CSPI2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX31_CSPI3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per], MX31_SDHC1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per], MX31_SDHC2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX31_GPT1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[hsp], MX31_IPU_CTRL_BASE_ADDR, NULL);
+
+ return 0;
+}
+
+static struct driver_d imx31_ccm_driver = {
+ .probe = imx31_ccm_probe,
+ .name = "imx31-ccm",
+};
+
+static int imx31_ccm_init(void)
+{
+ return register_driver(&imx31_ccm_driver);
+}
+postcore_initcall(imx31_ccm_init);
diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c
index 11d8f49..90eee0a 100644
--- a/arch/arm/mach-imx/imx31.c
+++ b/arch/arm/mach-imx/imx31.c
@@ -31,6 +31,7 @@ static int imx31_init(void)
add_generic_device("imx_iim", 0, NULL, MX31_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-ccm", 0, NULL, MX31_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, MX31_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 0, NULL, MX31_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 1, NULL, MX31_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
@@ -38,4 +39,4 @@ static int imx31_init(void)
return 0;
}
-coredevice_initcall(imx31_init);
+postcore_initcall(imx31_init);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 11/23] ARM i.MX6: Switch to common clk
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (9 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 10/23] ARM i.MX31: Switch to common clk Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 12/23] ARM i.MX21: " Sascha Hauer
` (11 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/Makefile | 2 +-
arch/arm/mach-imx/clk-imx6.c | 306 ++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/imx6.c | 3 +-
3 files changed, 309 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-imx/clk-imx6.c
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index db203e8..9d00c56 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -8,7 +8,7 @@ obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o clk-imx31.o
obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o imx5.o clk-imx5.o
obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o imx5.o clk-imx5.o
-obj-$(CONFIG_ARCH_IMX6) += speed-imx6.o imx6.o iomux-v3.o usb-imx6.o
+obj-$(CONFIG_ARCH_IMX6) += speed-imx6.o imx6.o iomux-v3.o usb-imx6.o clk-imx6.o
obj-$(CONFIG_IMX_CLKO) += clko.o
obj-$(CONFIG_IMX_IIM) += iim.o
obj-$(CONFIG_NAND_IMX) += nand.o
diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c
new file mode 100644
index 0000000..bac35ed
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx6.c
@@ -0,0 +1,306 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <mach/imx6-regs.h>
+
+#include "clk.h"
+
+#define CCGR0 0x68
+#define CCGR1 0x6c
+#define CCGR2 0x70
+#define CCGR3 0x74
+#define CCGR4 0x78
+#define CCGR5 0x7c
+#define CCGR6 0x80
+#define CCGR7 0x84
+
+#define CLPCR 0x54
+#define BP_CLPCR_LPM 0
+#define BM_CLPCR_LPM (0x3 << 0)
+#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
+#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
+#define BM_CLPCR_SBYOS (0x1 << 6)
+#define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
+#define BM_CLPCR_VSTBY (0x1 << 8)
+#define BP_CLPCR_STBY_COUNT 9
+#define BM_CLPCR_STBY_COUNT (0x3 << 9)
+#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
+#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
+#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
+#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
+#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
+#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
+#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
+#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
+#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
+#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
+#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
+
+enum mx6q_clks {
+ dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
+ pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
+ pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
+ periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
+ esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
+ gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
+ ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
+ ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
+ ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
+ usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
+ emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
+ periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
+ asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
+ gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
+ ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
+ ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
+ ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
+ usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
+ emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
+ mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
+ can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
+ esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
+ hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
+ ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
+ mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
+ gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
+ ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
+ usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
+ pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
+ ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
+ clk_max
+};
+
+static struct clk *clks[clk_max];
+
+static const char *step_sels[] = {
+ "osc",
+ "pll2_pfd2_396m",
+};
+
+static const char *pll1_sw_sels[] = {
+ "pll1_sys",
+ "step",
+};
+
+static const char *periph_pre_sels[] = {
+ "pll2_bus",
+ "pll2_pfd2_396m",
+ "pll2_pfd0_352m",
+ "pll2_198m",
+};
+
+static const char *periph_clk2_sels[] = {
+ "pll3_usb_otg",
+ "osc",
+};
+
+static const char *periph_sels[] = {
+ "periph_pre",
+ "periph_clk2",
+};
+
+static const char *periph2_sels[] = {
+ "periph2_pre",
+ "periph2_clk2",
+};
+
+static const char *axi_sels[] = {
+ "periph",
+ "pll2_pfd2_396m",
+ "pll3_pfd1_540m",
+};
+
+static const char *usdhc_sels[] = {
+ "pll2_pfd2_396m",
+ "pll2_pfd0_352m",
+};
+
+static const char *enfc_sels[] = {
+ "pll2_pfd0_352m",
+ "pll2_bus",
+ "pll3_usb_otg",
+ "pll2_pfd2_396m",
+};
+
+static const char *emi_sels[] = {
+ "axi",
+ "pll3_usb_otg",
+ "pll2_pfd2_396m",
+ "pll2_pfd0_352m",
+};
+
+static const char *vdo_axi_sels[] = {
+ "axi",
+ "ahb",
+};
+
+static const char *cko1_sels[] = {
+ "pll3_usb_otg",
+ "pll2_bus",
+ "pll1_sys",
+ "pll5_video",
+ "dummy",
+ "axi",
+ "enfc",
+ "ipu1_di0",
+ "ipu1_di1",
+ "ipu2_di0",
+ "ipu2_di1",
+ "ahb",
+ "ipg",
+ "ipg_per",
+ "ckil",
+ "pll4_audio",
+};
+
+static int imx6_ccm_probe(struct device_d *dev)
+{
+ void __iomem *base, *anatop_base, *ccm_base;
+ unsigned long ckil_rate = 32768;
+ unsigned long ckih_rate = 0;
+ unsigned long osc_rate = 24000000;
+
+ anatop_base = (void *)MX6_ANATOP_BASE_ADDR;
+ ccm_base = dev_request_mem_region(dev, 0);
+
+ base = anatop_base;
+
+ clks[dummy] = clk_fixed("dummy", 0);
+ clks[ckil] = clk_fixed("ckil", ckil_rate);
+ clks[ckih] = clk_fixed("ckih", ckih_rate);
+ clks[osc] = clk_fixed("osc", osc_rate);
+
+ /* type name parent_name base gate_mask div_mask */
+ clks[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x2000, 0x7f);
+ clks[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x2000, 0x1);
+ clks[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x2000, 0x3);
+ clks[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x2000, 0x7f);
+ clks[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x2000, 0x7f);
+ clks[pll6_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll6_mlb", "osc", base + 0xd0, 0x2000, 0x0);
+ clks[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3);
+ clks[pll8_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll8_enet", "osc", base + 0xe0, 0x182000, 0x3);
+
+ /* name parent_name reg idx */
+ clks[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
+ clks[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
+ clks[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
+ clks[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
+ clks[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
+ clks[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
+ clks[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
+
+ /* name parent_name mult div */
+ clks[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
+ clks[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
+ clks[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
+ clks[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
+ clks[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
+
+ base = ccm_base;
+
+ /* name reg shift width parent_names num_parents */
+ clks[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
+ clks[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
+ clks[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
+ clks[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
+ clks[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
+ clks[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
+ clks[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
+ clks[usdhc1_sel] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
+ clks[usdhc2_sel] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
+ clks[usdhc3_sel] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
+ clks[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
+ clks[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
+ clks[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels));
+ clks[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_sels, ARRAY_SIZE(emi_sels));
+ clks[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
+ clks[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
+
+ /* name reg shift width busy: reg, shift parent_names num_parents */
+ clks[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
+ clks[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
+
+ /* name parent_name reg shift width */
+ clks[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
+ clks[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
+ clks[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
+ clks[ipg_per] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6);
+ clks[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6);
+ clks[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
+ clks[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
+ clks[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
+ clks[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
+ clks[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
+ clks[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
+ clks[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
+ clks[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
+ clks[emi_podf] = imx_clk_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3);
+ clks[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3);
+ clks[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
+
+ /* name parent_name reg shift width busy: reg, shift */
+ clks[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
+ clks[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
+ clks[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
+ clks[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
+ clks[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
+
+
+ clkdev_add_physbase(clks[uart_serial_podf], MX6_UART1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[uart_serial_podf], MX6_UART2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[uart_serial_podf], MX6_UART3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[uart_serial_podf], MX6_UART4_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[uart_serial_podf], MX6_UART5_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI4_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI5_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX6_GPT_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX6_ENET_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[usdhc1_podf], MX6_USDHC1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[usdhc2_podf], MX6_USDHC2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[usdhc3_podf], MX6_USDHC3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[usdhc4_podf], MX6_USDHC4_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg_per], MX6_I2C1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg_per], MX6_I2C2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg_per], MX6_I2C3_BASE_ADDR, NULL);
+
+ writel(0xffffffff, ccm_base + CCGR0);
+ writel(0xffffffff, ccm_base + CCGR1);
+ writel(0xffffffff, ccm_base + CCGR2);
+ writel(0xffffffff, ccm_base + CCGR3);
+ writel(0xffffffff, ccm_base + CCGR4);
+ writel(0xffffffff, ccm_base + CCGR5);
+ writel(0xffffffff, ccm_base + CCGR6);
+ writel(0xffffffff, ccm_base + CCGR7);
+
+ return 0;
+}
+
+static struct driver_d imx6_ccm_driver = {
+ .probe = imx6_ccm_probe,
+ .name = "imx6-ccm",
+};
+
+static int imx6_ccm_init(void)
+{
+ return register_driver(&imx6_ccm_driver);
+}
+postcore_initcall(imx6_ccm_init);
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index babf8fe..a5ec364 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -54,6 +54,7 @@ void imx6_init_lowlevel(void)
static int imx6_init(void)
{
+ add_generic_device("imx6-ccm", 0, NULL, MX6_CCM_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, 0x02098000, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 0, NULL, MX6_GPIO1_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 1, NULL, MX6_GPIO2_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
@@ -65,4 +66,4 @@ static int imx6_init(void)
return 0;
}
-coredevice_initcall(imx6_init);
+postcore_initcall(imx6_init);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 12/23] ARM i.MX21: Switch to common clk
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (10 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 11/23] ARM i.MX6: " Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 13/23] ARM i.MX35: " Sascha Hauer
` (10 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/Makefile | 2 +-
arch/arm/mach-imx/clk-imx21.c | 119 +++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/imx21.c | 1 +
3 files changed, 121 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-imx/clk-imx21.c
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 9d00c56..a06ddf5 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -2,7 +2,7 @@ obj-y += clocksource.o gpio.o
obj-$(CONFIG_RESET_SOURCE) += reset_source.o
obj-$(CONFIG_ARCH_IMX1) += speed-imx1.o imx1.o iomux-v1.o clk-imx1.o
obj-$(CONFIG_ARCH_IMX25) += speed-imx25.o imx25.o iomux-v3.o clk-imx25.o
-obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o
+obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o clk-imx21.o
obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o clk-imx27.o
obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o clk-imx31.o
obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
new file mode 100644
index 0000000..09000af
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <mach/imx21-regs.h>
+
+#include "clk.h"
+
+/* Register offsets */
+#define CCM_CSCR 0x0
+#define CCM_MPCTL0 0x4
+#define CCM_MPCTL1 0x8
+#define CCM_SPCTL0 0xc
+#define CCM_SPCTL1 0x10
+#define CCM_OSC26MCTL 0x14
+#define CCM_PCDR0 0x18
+#define CCM_PCDR1 0x1c
+#define CCM_PCCR0 0x20
+#define CCM_PCCR1 0x24
+#define CCM_CCSR 0x28
+#define CCM_PMCTL 0x2c
+#define CCM_PMCOUNT 0x30
+#define CCM_WKGDCTL 0x34
+
+enum imx21_clks {
+ ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
+ per2, per3, per4, usb_div, nfc_div, clk_max
+};
+
+static struct clk *clks[clk_max];
+
+static const char *mpll_sel_clks[] = {
+ "fpm",
+ "ckih",
+};
+
+static const char *spll_sel_clks[] = {
+ "fpm",
+ "ckih",
+};
+
+static int imx21_ccm_probe(struct device_d *dev)
+{
+ void __iomem *base;
+ unsigned long lref = 32768;
+ unsigned long href = 26000000;
+
+ base = dev_request_mem_region(dev, 0);
+
+ clks[ckil] = clk_fixed("ckil", lref);
+ clks[ckih] = clk_fixed("ckih", href);
+ clks[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
+ clks[mpll_sel] = imx_clk_mux("mpll_sel", base + CCM_CSCR, 16, 1, mpll_sel_clks,
+ ARRAY_SIZE(mpll_sel_clks));
+ clks[spll_sel] = imx_clk_mux("spll_sel", base + CCM_CSCR, 17, 1, spll_sel_clks,
+ ARRAY_SIZE(spll_sel_clks));
+ clks[mpll] = imx_clk_pllv1("mpll", "mpll_sel", base + CCM_MPCTL0);
+ clks[spll] = imx_clk_pllv1("spll", "spll_sel", base + CCM_SPCTL0);
+ clks[fclk] = imx_clk_divider("fclk", "mpll", base + CCM_CSCR, 29, 3);
+ clks[hclk] = imx_clk_divider("hclk", "fclk", base + CCM_CSCR, 10, 4);
+ clks[ipg] = imx_clk_divider("ipg", "hclk", base + CCM_CSCR, 9, 1);
+ clks[per1] = imx_clk_divider("per1", "mpll", base + CCM_PCDR1, 0, 6);
+ clks[per2] = imx_clk_divider("per2", "mpll", base + CCM_PCDR1, 8, 6);
+ clks[per3] = imx_clk_divider("per3", "mpll", base + CCM_PCDR1, 16, 6);
+ clks[per4] = imx_clk_divider("per4", "mpll", base + CCM_PCDR1, 24, 6);
+ clks[usb_div] = imx_clk_divider("usb_div", "spll", base + CCM_CSCR, 26, 3);
+ clks[nfc_div] = imx_clk_divider("nfc_div", "ipg", base + CCM_PCDR0, 12, 4);
+
+ clkdev_add_physbase(clks[ipg], MX21_GPT1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX21_GPT2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX21_GPT3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per1], MX21_UART1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per1], MX21_UART2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per1], MX21_UART3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per1], MX21_UART4_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per2], MX21_CSPI1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per2], MX21_CSPI2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX21_I2C_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX21_SDHC1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX21_SDHC2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per3], MX21_CSPI3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per3], MX21_LCDC_BASE_ADDR, NULL);
+
+ return 0;
+}
+
+static struct driver_d imx21_ccm_driver = {
+ .probe = imx21_ccm_probe,
+ .name = "imx21-ccm",
+};
+
+static int imx21_ccm_init(void)
+{
+ return register_driver(&imx21_ccm_driver);
+}
+postcore_initcall(imx21_ccm_init);
diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c
index 5448ca4..7ed0809 100644
--- a/arch/arm/mach-imx/imx21.c
+++ b/arch/arm/mach-imx/imx21.c
@@ -33,6 +33,7 @@ int imx_silicon_revision(void)
static int imx21_init(void)
{
+ add_generic_device("imx21-ccm", 0, NULL, MX21_CCM_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpt", 0, NULL, MX21_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 0, NULL, MX21_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 1, NULL, MX21_GPIO2_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 13/23] ARM i.MX35: Switch to common clk
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (11 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 12/23] ARM i.MX21: " Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 14/23] net fec: Switch to clk support Sascha Hauer
` (9 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/Makefile | 2 +-
arch/arm/mach-imx/clk-imx35.c | 186 +++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/imx35.c | 3 +-
3 files changed, 189 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-imx/clk-imx35.c
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index a06ddf5..f7a5ba4 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -5,7 +5,7 @@ obj-$(CONFIG_ARCH_IMX25) += speed-imx25.o imx25.o iomux-v3.o clk-imx25.o
obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o clk-imx21.o
obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o clk-imx27.o
obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o clk-imx31.o
-obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
+obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o clk-imx35.o
obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o imx5.o clk-imx5.o
obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o imx5.o clk-imx5.o
obj-$(CONFIG_ARCH_IMX6) += speed-imx6.o imx6.o iomux-v3.o usb-imx6.o clk-imx6.o
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
new file mode 100644
index 0000000..d9f88c2
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <mach/imx35-regs.h>
+
+#include "clk.h"
+
+#define CCM_CCMR 0x00
+#define CCM_PDR0 0x04
+#define CCM_PDR1 0x08
+#define CCM_PDR2 0x0C
+#define CCM_PDR3 0x10
+#define CCM_PDR4 0x14
+#define CCM_RCSR 0x18
+#define CCM_MPCTL 0x1C
+#define CCM_PPCTL 0x20
+#define CCM_ACMR 0x24
+#define CCM_COSR 0x28
+#define CCM_CGR0 0x2C
+#define CCM_CGR1 0x30
+#define CCM_CGR2 0x34
+#define CCM_CGR3 0x38
+
+struct arm_ahb_div {
+ unsigned char arm, ahb, sel;
+};
+
+static struct arm_ahb_div clk_consumer[] = {
+ { .arm = 1, .ahb = 4, .sel = 0},
+ { .arm = 1, .ahb = 3, .sel = 1},
+ { .arm = 2, .ahb = 2, .sel = 0},
+ { .arm = 0, .ahb = 0, .sel = 0},
+ { .arm = 0, .ahb = 0, .sel = 0},
+ { .arm = 0, .ahb = 0, .sel = 0},
+ { .arm = 4, .ahb = 1, .sel = 0},
+ { .arm = 1, .ahb = 5, .sel = 0},
+ { .arm = 1, .ahb = 8, .sel = 0},
+ { .arm = 1, .ahb = 6, .sel = 1},
+ { .arm = 2, .ahb = 4, .sel = 0},
+ { .arm = 0, .ahb = 0, .sel = 0},
+ { .arm = 0, .ahb = 0, .sel = 0},
+ { .arm = 0, .ahb = 0, .sel = 0},
+ { .arm = 4, .ahb = 2, .sel = 0},
+ { .arm = 0, .ahb = 0, .sel = 0},
+};
+
+static char hsp_div_532[] = { 4, 8, 3, 0 };
+static char hsp_div_400[] = { 3, 6, 3, 0 };
+
+enum mx35_clks {
+ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
+ arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel,
+ esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre,
+ spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre,
+ ssi2_div_post, usb_sel, usb_div, nfc_div, asrc_gate, pata_gate,
+ audmux_gate, can1_gate, can2_gate, cspi1_gate, cspi2_gate, ect_gate,
+ edio_gate, emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate,
+ esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate, gpio3_gate,
+ gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate, iomuxc_gate, ipu_gate,
+ kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate,
+ rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate,
+ ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate,
+ wdog_gate, max_gate, admux_gate, csi_gate, iim_gate, gpu2d_gate,
+ clk_max
+};
+
+static struct clk *clks[clk_max];
+
+static const char *std_sel[] = {
+ "ppll",
+ "arm",
+};
+
+static const char *ipg_per_sel[] = {
+ "ahb_per_div",
+ "arm_per_div",
+};
+
+static int imx35_ccm_probe(struct device_d *dev)
+{
+ u32 pdr0, consumer_sel, hsp_sel;
+ struct arm_ahb_div *aad;
+ unsigned char *hsp_div;
+ void __iomem *base;
+
+ base = dev_request_mem_region(dev, 0);
+
+ writel(0xffffffff, base + CCM_CGR0);
+ writel(0xffffffff, base + CCM_CGR1);
+ writel(0xffffffff, base + CCM_CGR2);
+ writel(0xffffffff, base + CCM_CGR3);
+
+ pdr0 = __raw_readl(base + CCM_PDR0);
+ consumer_sel = (pdr0 >> 16) & 0xf;
+ aad = &clk_consumer[consumer_sel];
+ if (!aad->arm) {
+ pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel);
+ /*
+ * We are basically stuck. Continue with a default entry and hope we
+ * get far enough to actually show the above message
+ */
+ aad = &clk_consumer[0];
+ }
+
+ clks[ckih] = clk_fixed("ckih", 24000000);
+ clks[mpll] = imx_clk_pllv1("mpll", "ckih", base + CCM_MPCTL);
+ clks[ppll] = imx_clk_pllv1("ppll", "ckih", base + CCM_PPCTL);
+
+ clks[mpll_075] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4);
+
+ if (aad->sel)
+ clks[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm);
+ else
+ clks[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm);
+
+ if (clk_get_rate(clks[arm]) > 400000000)
+ hsp_div = hsp_div_532;
+ else
+ hsp_div = hsp_div_400;
+
+ hsp_sel = (pdr0 >> 20) & 0x3;
+ if (!hsp_div[hsp_sel]) {
+ pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel);
+ hsp_sel = 0;
+ }
+
+ clks[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]);
+
+ clks[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb);
+ clks[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
+
+ clks[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + CCM_PDR4, 16, 6);
+ clks[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + CCM_PDR0, 12, 3);
+ clks[ipg_per] = imx_clk_mux("ipg_per", base + CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel));
+
+ clks[uart_sel] = imx_clk_mux("uart_sel", base + CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel));
+ clks[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + CCM_PDR4, 10, 6);
+
+ clks[esdhc_sel] = imx_clk_mux("esdhc_sel", base + CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
+ clks[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + CCM_PDR3, 0, 6);
+ clks[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + CCM_PDR3, 8, 6);
+ clks[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + CCM_PDR3, 16, 6);
+
+ clks[usb_sel] = imx_clk_mux("usb_sel", base + CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
+ clks[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + CCM_PDR4, 22, 6);
+
+ clkdev_add_physbase(clks[uart_div], MX35_UART1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[uart_div], MX35_UART2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[uart_div], MX35_UART3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg_per], MX35_I2C1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg_per], MX35_I2C2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg_per], MX35_I2C3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX35_CSPI1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX35_CSPI2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX35_FEC_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ipg], MX35_GPT1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[esdhc1_div], MX35_ESDHC1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[esdhc2_div], MX35_ESDHC2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[esdhc3_div], MX35_ESDHC3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[hsp], MX35_IPU_CTRL_BASE_ADDR, NULL);
+
+ return 0;
+}
+
+static struct driver_d imx35_ccm_driver = {
+ .probe = imx35_ccm_probe,
+ .name = "imx35-ccm",
+};
+
+static int imx35_ccm_init(void)
+{
+ return register_driver(&imx35_ccm_driver);
+}
+postcore_initcall(imx35_ccm_init);
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index 2a9f576..722dd4c 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -61,6 +61,7 @@ static int imx35_init(void)
add_generic_device("imx_iim", 0, NULL, MX35_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
+ add_generic_device("imx35-ccm", 0, NULL, MX35_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, MX35_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 0, NULL, MX35_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 1, NULL, MX35_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
@@ -68,4 +69,4 @@ static int imx35_init(void)
return 0;
}
-coredevice_initcall(imx35_init);
+postcore_initcall(imx35_init);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 14/23] net fec: Switch to clk support
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (12 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 13/23] ARM i.MX35: " Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-26 16:07 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-24 11:04 ` [PATCH 15/23] serial i.MX: " Sascha Hauer
` (8 subsequent siblings)
22 siblings, 1 reply; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/net/fec_imx.c | 27 ++++++++++++++++++++++++---
drivers/net/fec_imx.h | 1 +
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c
index 6acf6bd..4606558 100644
--- a/drivers/net/fec_imx.c
+++ b/drivers/net/fec_imx.c
@@ -24,6 +24,8 @@
#include <clock.h>
#include <xfuncs.h>
#include <linux/phy.h>
+#include <linux/clk.h>
+#include <linux/err.h>
#include <asm/mmu.h>
@@ -43,6 +45,19 @@ struct fec_frame {
uint8_t head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
};
+#ifdef CONFIG_COMMON_CLK
+static inline unsigned long fec_clk_get_rate(struct fec_priv *fec)
+{
+ return clk_get_rate(fec->clk);
+}
+#else
+static inline unsigned long fec_clk_get_rate(struct fec_priv *fec)
+{
+ return imx_get_fecclk();
+}
+#endif
+
+
/*
* MII-interface related functions
*/
@@ -54,7 +69,7 @@ static int fec_miibus_read(struct mii_bus *bus, int phyAddr, int regAddr)
uint32_t phy; /* convenient holder for the PHY */
uint64_t start;
- writel(((imx_get_fecclk() >> 20) / 5) << 1,
+ writel(((fec_clk_get_rate(fec) >> 20) / 5) << 1,
fec->regs + FEC_MII_SPEED);
/*
* reading from any PHY's register is done by properly
@@ -97,7 +112,7 @@ static int fec_miibus_write(struct mii_bus *bus, int phyAddr,
uint32_t phy; /* convenient holder for the PHY */
uint64_t start;
- writel(((imx_get_fecclk() >> 20) / 5) << 1,
+ writel(((fec_clk_get_rate(fec) >> 20) / 5) << 1,
fec->regs + FEC_MII_SPEED);
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
@@ -290,7 +305,7 @@ static int fec_init(struct eth_device *dev)
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
*/
- writel(((imx_get_fecclk() >> 20) / 5) << 1,
+ writel(((fec_clk_get_rate(fec) >> 20) / 5) << 1,
fec->regs + FEC_MII_SPEED);
}
@@ -628,6 +643,12 @@ static int fec_probe(struct device_d *dev)
edev->set_ethaddr = fec_set_hwaddr;
edev->parent = dev;
+#ifdef CONFIG_COMMON_CLK
+ fec->clk = clk_get(dev, NULL);
+ if (IS_ERR(fec->clk))
+ return PTR_ERR(fec->clk);
+#endif
+
fec->regs = dev_request_mem_region(dev, 0);
/* Reset chip. */
diff --git a/drivers/net/fec_imx.h b/drivers/net/fec_imx.h
index d10385a..d147dca 100644
--- a/drivers/net/fec_imx.h
+++ b/drivers/net/fec_imx.h
@@ -138,6 +138,7 @@ struct fec_priv {
u32 phy_flags;
struct mii_bus miibus;
void (*phy_init)(struct phy_device *dev);
+ struct clk *clk;
};
/**
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 14/23] net fec: Switch to clk support
2012-09-24 11:04 ` [PATCH 14/23] net fec: Switch to clk support Sascha Hauer
@ 2012-09-26 16:07 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 34+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-26 16:07 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 13:04 Mon 24 Sep , Sascha Hauer wrote:
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> drivers/net/fec_imx.c | 27 ++++++++++++++++++++++++---
> drivers/net/fec_imx.h | 1 +
> 2 files changed, 25 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c
> index 6acf6bd..4606558 100644
> --- a/drivers/net/fec_imx.c
> +++ b/drivers/net/fec_imx.c
> @@ -24,6 +24,8 @@
> #include <clock.h>
> #include <xfuncs.h>
> #include <linux/phy.h>
> +#include <linux/clk.h>
> +#include <linux/err.h>
>
> #include <asm/mmu.h>
>
> @@ -43,6 +45,19 @@ struct fec_frame {
> uint8_t head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
> };
>
> +#ifdef CONFIG_COMMON_CLK
> +static inline unsigned long fec_clk_get_rate(struct fec_priv *fec)
> +{
> + return clk_get_rate(fec->clk);
> +}
> +#else
> +static inline unsigned long fec_clk_get_rate(struct fec_priv *fec)
> +{
> + return imx_get_fecclk();
> +}
> +#endif
> +
> +
> /*
> * MII-interface related functions
> */
> @@ -54,7 +69,7 @@ static int fec_miibus_read(struct mii_bus *bus, int phyAddr, int regAddr)
> uint32_t phy; /* convenient holder for the PHY */
> uint64_t start;
>
> - writel(((imx_get_fecclk() >> 20) / 5) << 1,
> + writel(((fec_clk_get_rate(fec) >> 20) / 5) << 1,
is the rate changing?
if not put it in the fec will reduce the number function call
Best Regards,
J.
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^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 15/23] serial i.MX: Switch to clk support
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (13 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 14/23] net fec: Switch to clk support Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-26 16:08 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-24 11:04 ` [PATCH 16/23] spi " Sascha Hauer
` (7 subsequent siblings)
22 siblings, 1 reply; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/serial/serial_imx.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c
index 012ab02..e0e5b01 100644
--- a/drivers/serial/serial_imx.c
+++ b/drivers/serial/serial_imx.c
@@ -22,6 +22,8 @@
#include <malloc.h>
#include <notifier.h>
#include <io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
#define URXD0 0x0 /* Receiver Register */
#define URTX0 0x40 /* Transmitter Register */
@@ -170,16 +172,17 @@ struct imx_serial_priv {
int baudrate;
struct notifier_block notify;
void __iomem *regs;
+ struct clk *clk;
};
-static int imx_serial_reffreq(void __iomem *regs)
+static int imx_serial_reffreq(struct imx_serial_priv *priv)
{
ulong rfdiv;
- rfdiv = (readl(regs + UFCR) >> 7) & 7;
+ rfdiv = (readl(priv->regs + UFCR) >> 7) & 7;
rfdiv = rfdiv < 6 ? 6 - rfdiv : 7;
- return imx_get_uartclk() / rfdiv;
+ return clk_get_rate(priv->clk) / rfdiv;
}
/*
@@ -209,7 +212,7 @@ static int imx_serial_init_port(struct console_device *cdev)
writel(0xa81, regs + UFCR);
#ifdef ONEMS
- writel(imx_serial_reffreq(regs) / 1000, regs + ONEMS);
+ writel(imx_serial_reffreq(priv) / 1000, regs + ONEMS);
#endif
/* Enable FIFOs */
@@ -291,7 +294,7 @@ static int imx_serial_setbaudrate(struct console_device *cdev, int baudrate)
/* Set the numerator value minus one of the BRM ratio */
writel((baudrate / 100) - 1, regs + UBIR);
/* Set the denominator value minus one of the BRM ratio */
- writel((imx_serial_reffreq(regs) / 1600) - 1, regs + UBMR);
+ writel((imx_serial_reffreq(priv) / 1600) - 1, regs + UBMR);
writel(ucr1, regs + UCR1);
@@ -321,6 +324,10 @@ static int imx_serial_probe(struct device_d *dev)
cdev = &priv->cdev;
dev->priv = priv;
+ priv->clk = clk_get(dev, NULL);
+ if (IS_ERR(priv->clk))
+ return PTR_ERR(priv->clk);
+
priv->regs = dev_request_mem_region(dev, 0);
cdev->dev = dev;
cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 15/23] serial i.MX: Switch to clk support
2012-09-24 11:04 ` [PATCH 15/23] serial i.MX: " Sascha Hauer
@ 2012-09-26 16:08 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 34+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-26 16:08 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 13:04 Mon 24 Sep , Sascha Hauer wrote:
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> drivers/serial/serial_imx.c | 17 ++++++++++++-----
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c
> index 012ab02..e0e5b01 100644
> --- a/drivers/serial/serial_imx.c
> +++ b/drivers/serial/serial_imx.c
> @@ -22,6 +22,8 @@
> #include <malloc.h>
> #include <notifier.h>
> #include <io.h>
> +#include <linux/err.h>
> +#include <linux/clk.h>
>
> #define URXD0 0x0 /* Receiver Register */
> #define URTX0 0x40 /* Transmitter Register */
> @@ -170,16 +172,17 @@ struct imx_serial_priv {
> int baudrate;
> struct notifier_block notify;
> void __iomem *regs;
> + struct clk *clk;
> };
>
> -static int imx_serial_reffreq(void __iomem *regs)
> +static int imx_serial_reffreq(struct imx_serial_priv *priv)
> {
> ulong rfdiv;
>
> - rfdiv = (readl(regs + UFCR) >> 7) & 7;
> + rfdiv = (readl(priv->regs + UFCR) >> 7) & 7;
> rfdiv = rfdiv < 6 ? 6 - rfdiv : 7;
>
> - return imx_get_uartclk() / rfdiv;
> + return clk_get_rate(priv->clk) / rfdiv;
> }
>
> /*
> @@ -209,7 +212,7 @@ static int imx_serial_init_port(struct console_device *cdev)
> writel(0xa81, regs + UFCR);
>
> #ifdef ONEMS
> - writel(imx_serial_reffreq(regs) / 1000, regs + ONEMS);
> + writel(imx_serial_reffreq(priv) / 1000, regs + ONEMS);
> #endif
>
> /* Enable FIFOs */
> @@ -291,7 +294,7 @@ static int imx_serial_setbaudrate(struct console_device *cdev, int baudrate)
> /* Set the numerator value minus one of the BRM ratio */
> writel((baudrate / 100) - 1, regs + UBIR);
> /* Set the denominator value minus one of the BRM ratio */
> - writel((imx_serial_reffreq(regs) / 1600) - 1, regs + UBMR);
> + writel((imx_serial_reffreq(priv) / 1600) - 1, regs + UBMR);
>
> writel(ucr1, regs + UCR1);
>
> @@ -321,6 +324,10 @@ static int imx_serial_probe(struct device_d *dev)
> cdev = &priv->cdev;
> dev->priv = priv;
>
> + priv->clk = clk_get(dev, NULL);
> + if (IS_ERR(priv->clk))
> + return PTR_ERR(priv->clk);
you do not free the data on the error patch?
Best Regards,
J.
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^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 16/23] spi i.MX: Switch to clk support
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (14 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 15/23] serial i.MX: " Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 17/23] ARM i.MX: Switch clocksource to clk_get Sascha Hauer
` (6 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/spi/imx_spi.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c
index c3dc6cc..14d2b28 100644
--- a/drivers/spi/imx_spi.c
+++ b/drivers/spi/imx_spi.c
@@ -25,6 +25,8 @@
#include <mach/spi.h>
#include <mach/generic.h>
#include <mach/clock.h>
+#include <linux/clk.h>
+#include <linux/err.h>
#define CSPI_0_0_RXDATA 0x00
#define CSPI_0_0_TXDATA 0x04
@@ -128,6 +130,7 @@ struct imx_spi {
struct spi_master master;
int *cs_array;
void __iomem *regs;
+ struct clk *clk;
unsigned int (*xchg_single)(struct imx_spi *imx, u32 data);
void (*chipselect)(struct spi_device *spi, int active);
@@ -276,7 +279,7 @@ static void cspi_0_7_chipselect(struct spi_device *spi, int is_active)
return;
}
- reg |= spi_imx_clkdiv_2(imx_get_cspiclk(), spi->max_speed_hz) <<
+ reg |= spi_imx_clkdiv_2(clk_get_rate(imx->clk), spi->max_speed_hz) <<
CSPI_0_7_CTRL_DR_SHIFT;
reg |= (spi->bits_per_word - 1) << CSPI_0_7_CTRL_BL_SHIFT;
@@ -381,7 +384,7 @@ static void cspi_2_3_chipselect(struct spi_device *spi, int is_active)
ctrl |= CSPI_2_3_CTRL_MODE(cs);
/* set clock speed */
- ctrl |= cspi_2_3_clkdiv(imx_get_cspiclk(), spi->max_speed_hz);
+ ctrl |= cspi_2_3_clkdiv(clk_get_rate(imx->clk), spi->max_speed_hz);
/* set chip select to use */
ctrl |= CSPI_2_3_CTRL_CS(cs);
@@ -532,6 +535,7 @@ static int imx_spi_probe(struct device_d *dev)
master->setup = imx_spi_setup;
master->transfer = imx_spi_transfer;
+
if (pdata) {
master->num_chipselect = pdata->num_chipselect;
imx->cs_array = pdata->chipselect;
@@ -540,6 +544,10 @@ static int imx_spi_probe(struct device_d *dev)
imx_spi_dt_probe(imx);
}
+ imx->clk = clk_get(dev, NULL);
+ if (IS_ERR(imx->clk))
+ return PTR_ERR(imx->clk);
+
#ifdef CONFIG_DRIVER_SPI_IMX_0_0
if (cpu_is_mx27())
version = SPI_IMX_VER_0_0;
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 17/23] ARM i.MX: Switch clocksource to clk_get
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (15 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 16/23] spi " Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 18/23] mci i.MX ESDHC: Switch to clock support Sascha Hauer
` (5 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/clocksource.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c
index 2c6f6a0..df018e6 100644
--- a/arch/arm/mach-imx/clocksource.c
+++ b/arch/arm/mach-imx/clocksource.c
@@ -29,6 +29,8 @@
#include <init.h>
#include <clock.h>
#include <errno.h>
+#include <linux/clk.h>
+#include <linux/err.h>
#include <notifier.h>
#include <mach/imx-regs.h>
#include <mach/clock.h>
@@ -46,6 +48,8 @@
#define IMX31_TCTL_CLKSOURCE_IPG (1 << 6) /* Clock source bit position */
#define TCTL_TEN (1 << 0) /* Timer enable */
+static struct clk *clk_gpt;
+
struct imx_gpt_regs {
unsigned int tcn;
uint32_t tctl_val;
@@ -77,7 +81,7 @@ static struct clocksource cs = {
static int imx_clocksource_clock_change(struct notifier_block *nb, unsigned long event, void *data)
{
- cs.mult = clocksource_hz2mult(imx_get_gptclk(), cs.shift);
+ cs.mult = clocksource_hz2mult(clk_get_rate(clk_gpt), cs.shift);
return 0;
}
@@ -89,6 +93,7 @@ static int imx_gpt_probe(struct device_d *dev)
{
int i;
int ret;
+ unsigned long rate;
/* one timer is enough */
if (timer_base)
@@ -118,10 +123,18 @@ static int imx_gpt_probe(struct device_d *dev)
for (i = 0; i < 100; i++)
writel(0, timer_base + GPT_TCTL); /* We have no udelay by now */
+ clk_gpt = clk_get(dev, NULL);
+ if (IS_ERR(clk_gpt)) {
+ rate = 20000000;
+ dev_err(dev, "failed to get clock\n");
+ } else {
+ rate = clk_get_rate(clk_gpt);
+ }
+
writel(0, timer_base + GPT_TPRER);
writel(regs->tctl_val, timer_base + GPT_TCTL);
- cs.mult = clocksource_hz2mult(imx_get_gptclk(), cs.shift);
+ cs.mult = clocksource_hz2mult(rate, cs.shift);
init_clock(&cs);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 18/23] mci i.MX ESDHC: Switch to clock support
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (16 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 17/23] ARM i.MX: Switch clocksource to clk_get Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 19/23] mci i.MX: " Sascha Hauer
` (4 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/mci/imx-esdhc.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index 498578d..94ed807 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -28,6 +28,8 @@
#include <mci.h>
#include <clock.h>
#include <io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
#include <asm/mmu.h>
#include <mach/clock.h>
#include <mach/generic.h>
@@ -70,6 +72,7 @@ struct fsl_esdhc_host {
u32 no_snoop;
unsigned long cur_clock;
struct device_d *dev;
+ struct clk *clk;
};
#define to_fsl_esdhc(mci) container_of(mci, struct fsl_esdhc_host, mci)
@@ -354,7 +357,7 @@ static void set_sysctl(struct mci_host *mci, u32 clock)
int div, pre_div;
struct fsl_esdhc_host *host = to_fsl_esdhc(mci);
struct fsl_esdhc __iomem *regs = host->regs;
- int sdhc_clk = imx_get_mmcclk();
+ int sdhc_clk = clk_get_rate(host->clk);
u32 clk;
if (clock < mci->f_min)
@@ -516,11 +519,16 @@ static int fsl_esdhc_probe(struct device_d *dev)
struct mci_host *mci;
u32 caps;
int ret;
+ unsigned long rate;
struct esdhc_platform_data *pdata = dev->platform_data;
host = xzalloc(sizeof(*host));
mci = &host->mci;
+ host->clk = clk_get(dev, NULL);
+ if (IS_ERR(host->clk))
+ return PTR_ERR(host->clk);
+
host->dev = dev;
host->regs = dev_request_mem_region(dev, 0);
@@ -553,10 +561,11 @@ static int fsl_esdhc_probe(struct device_d *dev)
host->mci.init = esdhc_init;
host->mci.hw_dev = dev;
- host->mci.f_min = imx_get_mmcclk() >> 12;
+ rate = clk_get_rate(host->clk);
+ host->mci.f_min = rate >> 12;
if (host->mci.f_min < 200000)
host->mci.f_min = 200000;
- host->mci.f_max = imx_get_mmcclk();
+ host->mci.f_max = rate;
mci_register(&host->mci);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 19/23] mci i.MX: Switch to clock support
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (17 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 18/23] mci i.MX ESDHC: Switch to clock support Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 20/23] i2c " Sascha Hauer
` (3 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/mci/imx.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/mci/imx.c b/drivers/mci/imx.c
index 0e4fa66..035a3aa 100644
--- a/drivers/mci/imx.c
+++ b/drivers/mci/imx.c
@@ -25,6 +25,8 @@
#include <clock.h>
#include <init.h>
#include <driver.h>
+#include <linux/clk.h>
+#include <linux/err.h>
#include <mach/clock.h>
#include <io.h>
@@ -103,6 +105,7 @@ struct mxcmci_regs {
struct mxcmci_host {
struct mci_host mci;
struct mxcmci_regs *base;
+ struct clk *clk;
int irq;
int detect_irq;
int dma;
@@ -415,7 +418,7 @@ static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
{
unsigned int divider;
int prescaler = 0;
- unsigned long clk_in = imx_get_mmcclk();
+ unsigned long clk_in = clk_get_rate(host->clk);
while (prescaler <= 0x800) {
for (divider = 1; divider <= 0xF; divider++) {
@@ -490,9 +493,14 @@ static int mxcmci_init(struct mci_host *mci, struct device_d *dev)
static int mxcmci_probe(struct device_d *dev)
{
struct mxcmci_host *host;
+ unsigned long rate;
host = xzalloc(sizeof(*host));
+ host->clk = clk_get(dev, NULL);
+ if (IS_ERR(host->clk))
+ return PTR_ERR(host->clk);
+
host->mci.send_cmd = mxcmci_request;
host->mci.set_ios = mxcmci_set_ios;
host->mci.init = mxcmci_init;
@@ -503,8 +511,9 @@ static int mxcmci_probe(struct device_d *dev)
host->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
- host->mci.f_min = imx_get_mmcclk() >> 7;
- host->mci.f_max = imx_get_mmcclk() >> 1;
+ rate = clk_get_rate(host->clk);
+ host->mci.f_min = rate >> 7;
+ host->mci.f_max = rate >> 1;
mci_register(&host->mci);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 20/23] i2c i.MX: Switch to clock support
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (18 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 19/23] mci i.MX: " Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-26 16:10 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-24 11:04 ` [PATCH 21/23] video " Sascha Hauer
` (2 subsequent siblings)
22 siblings, 1 reply; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/i2c/busses/i2c-imx.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 2ac043b..98c06f0 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -37,7 +37,7 @@
#include <malloc.h>
#include <types.h>
#include <xfuncs.h>
-
+#include <linux/clk.h>
#include <linux/err.h>
#include <io.h>
@@ -101,6 +101,7 @@ static u16 i2c_clk_div[50][2] = {
struct fsl_i2c_struct {
void __iomem *base;
+ struct clk *clk;
struct i2c_adapter adapter;
unsigned int disable_delay;
int stopped;
@@ -109,6 +110,19 @@ struct fsl_i2c_struct {
};
#define to_fsl_i2c_struct(a) container_of(a, struct fsl_i2c_struct, adapter)
+#ifdef CONFIG_COMMON_CLK
+static inline unsigned long i2c_fsl_clk_get_rate(struct fsl_i2c_struct *i2c_fsl)
+{
+ return clk_get_rate(i2c_fsl->clk);
+}
+
+#else
+static inline unsigned long i2c_fsl_clk_get_rate(struct fsl_i2c_struct *i2c_fsl)
+{
+ return fsl_get_i2cclk();
+}
+#endif
+
#ifdef CONFIG_I2C_DEBUG
static void i2c_fsl_dump_reg(struct i2c_adapter *adapter)
{
@@ -344,7 +358,7 @@ static void i2c_fsl_set_clk(struct fsl_i2c_struct *i2c_fsl,
int i;
/* Divider value calculation */
- i2c_clk_rate = fsl_get_i2cclk();
+ i2c_clk_rate = i2c_fsl_clk_get_rate(i2c_fsl);
div = (i2c_clk_rate + rate - 1) / rate;
if (div < i2c_clk_div[0][0])
i = 0;
@@ -535,6 +549,11 @@ static int __init i2c_fsl_probe(struct device_d *pdev)
i2c_fsl = kzalloc(sizeof(struct fsl_i2c_struct), GFP_KERNEL);
+#ifdef CONFIG_COMMON_CLK
+ i2c_fsl->clk = clk_get(pdev, NULL);
+ if (IS_ERR(i2c_fsl->clk))
+ return PTR_ERR(i2c_fsl->clk);
+#endif
/* Setup i2c_fsl driver structure */
i2c_fsl->adapter.master_xfer = i2c_fsl_xfer;
i2c_fsl->adapter.nr = pdev->id;
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 20/23] i2c i.MX: Switch to clock support
2012-09-24 11:04 ` [PATCH 20/23] i2c " Sascha Hauer
@ 2012-09-26 16:10 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 34+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-26 16:10 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 13:04 Mon 24 Sep , Sascha Hauer wrote:
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> drivers/i2c/busses/i2c-imx.c | 23 +++++++++++++++++++++--
> 1 file changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
> index 2ac043b..98c06f0 100644
> --- a/drivers/i2c/busses/i2c-imx.c
> +++ b/drivers/i2c/busses/i2c-imx.c
> @@ -37,7 +37,7 @@
> #include <malloc.h>
> #include <types.h>
> #include <xfuncs.h>
> -
> +#include <linux/clk.h>
> #include <linux/err.h>
>
> #include <io.h>
> @@ -101,6 +101,7 @@ static u16 i2c_clk_div[50][2] = {
>
> struct fsl_i2c_struct {
> void __iomem *base;
> + struct clk *clk;
> struct i2c_adapter adapter;
> unsigned int disable_delay;
> int stopped;
> @@ -109,6 +110,19 @@ struct fsl_i2c_struct {
> };
> #define to_fsl_i2c_struct(a) container_of(a, struct fsl_i2c_struct, adapter)
>
> +#ifdef CONFIG_COMMON_CLK
> +static inline unsigned long i2c_fsl_clk_get_rate(struct fsl_i2c_struct *i2c_fsl)
> +{
> + return clk_get_rate(i2c_fsl->clk);
> +}
> +
> +#else
> +static inline unsigned long i2c_fsl_clk_get_rate(struct fsl_i2c_struct *i2c_fsl)
> +{
> + return fsl_get_i2cclk();
> +}
> +#endif
> +
> #ifdef CONFIG_I2C_DEBUG
> static void i2c_fsl_dump_reg(struct i2c_adapter *adapter)
> {
> @@ -344,7 +358,7 @@ static void i2c_fsl_set_clk(struct fsl_i2c_struct *i2c_fsl,
> int i;
>
> /* Divider value calculation */
> - i2c_clk_rate = fsl_get_i2cclk();
> + i2c_clk_rate = i2c_fsl_clk_get_rate(i2c_fsl);
> div = (i2c_clk_rate + rate - 1) / rate;
> if (div < i2c_clk_div[0][0])
> i = 0;
> @@ -535,6 +549,11 @@ static int __init i2c_fsl_probe(struct device_d *pdev)
>
> i2c_fsl = kzalloc(sizeof(struct fsl_i2c_struct), GFP_KERNEL);
>
> +#ifdef CONFIG_COMMON_CLK
if IS_ENABLED
> + i2c_fsl->clk = clk_get(pdev, NULL);
> + if (IS_ERR(i2c_fsl->clk))
> + return PTR_ERR(i2c_fsl->clk);
no free on the error path?
> +#endif
> /* Setup i2c_fsl driver structure */
> i2c_fsl->adapter.master_xfer = i2c_fsl_xfer;
> i2c_fsl->adapter.nr = pdev->id;
> --
> 1.7.10.4
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
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^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 21/23] video i.MX: Switch to clock support
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (19 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 20/23] i2c " Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 22/23] video i.MX IPU: " Sascha Hauer
2012-09-24 11:04 ` [PATCH 23/23] ARM i.MX: Remove old " Sascha Hauer
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/video/imx.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/video/imx.c b/drivers/video/imx.c
index 452e558..810d8e3 100644
--- a/drivers/video/imx.c
+++ b/drivers/video/imx.c
@@ -22,6 +22,8 @@
#include <malloc.h>
#include <errno.h>
#include <init.h>
+#include <linux/clk.h>
+#include <linux/err.h>
#include <mach/imx-regs.h>
#include <asm-generic/div64.h>
#include <mach/clock.h>
@@ -138,6 +140,7 @@ struct imxfb_rgb {
struct imxfb_info {
void __iomem *regs;
+ struct clk *clk;
u_int pcr;
u_int pwmr;
@@ -341,7 +344,7 @@ static int imxfb_activate_var(struct fb_info *info)
writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1),
fbi->regs + LCDC_CPOS);
- lcd_clk = imx_get_lcdclk();
+ lcd_clk = clk_get_rate(fbi->clk);
tmp = mode->pixclock * (unsigned long long)lcd_clk;
@@ -564,6 +567,10 @@ static int imxfb_probe(struct device_d *dev)
fbi = xzalloc(sizeof(*fbi));
info = &fbi->info;
+ fbi->clk = clk_get(dev, NULL);
+ if (IS_ERR(fbi->clk))
+ return PTR_ERR(fbi->clk);
+
fbi->mode = pdata->mode;
fbi->regs = dev_request_mem_region(dev, 0);
fbi->pcr = pdata->mode->pcr;
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 22/23] video i.MX IPU: Switch to clock support
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (20 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 21/23] video " Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
2012-09-24 11:04 ` [PATCH 23/23] ARM i.MX: Remove old " Sascha Hauer
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/video/imx-ipu-fb.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c
index 80236b3..6343f12 100644
--- a/drivers/video/imx-ipu-fb.c
+++ b/drivers/video/imx-ipu-fb.c
@@ -27,10 +27,12 @@
#include <errno.h>
#include <asm-generic/div64.h>
#include <mach/imx-ipu-fb.h>
-#include <mach/clock.h>
+#include <linux/clk.h>
+#include <linux/err.h>
struct ipu_fb_info {
void __iomem *regs;
+ struct clk *clk;
void (*enable)(int enable);
@@ -480,7 +482,7 @@ static int sdc_init_panel(struct fb_info *info, enum pixel_fmt pixel_fmt)
* i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
*/
pixel_clk = PICOS2KHZ(mode->pixclock) * 1000UL;
- div = imx_get_lcdclk() * 16 / pixel_clk;
+ div = clk_get_rate(fbi->clk) * 16 / pixel_clk;
if (div < 0x40) { /* Divider less than 4 */
dev_dbg(&info->dev,
@@ -986,6 +988,10 @@ static int imxfb_probe(struct device_d *dev)
fbi = xzalloc(sizeof(*fbi));
info = &fbi->info;
+ fbi->clk = clk_get(dev, NULL);
+ if (IS_ERR(fbi->clk))
+ return PTR_ERR(fbi->clk);
+
fbi->regs = dev_request_mem_region(dev, 0);
fbi->dev = dev;
fbi->enable = pdata->enable;
--
1.7.10.4
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH 23/23] ARM i.MX: Remove old clock support
2012-09-24 11:04 [PATCH] common clk support Sascha Hauer
` (21 preceding siblings ...)
2012-09-24 11:04 ` [PATCH 22/23] video i.MX IPU: " Sascha Hauer
@ 2012-09-24 11:04 ` Sascha Hauer
22 siblings, 0 replies; 34+ messages in thread
From: Sascha Hauer @ 2012-09-24 11:04 UTC (permalink / raw)
To: barebox
The old clock support is now unused. Remove it. The former i.MX clko
command is superseeded by generic clock manipulation commands.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/Kconfig | 8 -
arch/arm/mach-imx/Makefile | 20 +-
arch/arm/mach-imx/clko.c | 60 -----
arch/arm/mach-imx/clocksource.c | 1 -
arch/arm/mach-imx/include/mach/clock.h | 42 +---
arch/arm/mach-imx/speed-imx1.c | 91 -------
arch/arm/mach-imx/speed-imx21.c | 193 ---------------
arch/arm/mach-imx/speed-imx25.c | 155 ------------
arch/arm/mach-imx/speed-imx27.c | 227 ------------------
arch/arm/mach-imx/speed-imx31.c | 79 -------
arch/arm/mach-imx/speed-imx35.c | 255 --------------------
arch/arm/mach-imx/speed-imx51.c | 311 ------------------------
arch/arm/mach-imx/speed-imx53.c | 236 -------------------
arch/arm/mach-imx/speed-imx6.c | 404 --------------------------------
arch/arm/mach-imx/speed.c | 82 -------
drivers/mci/imx-esdhc.c | 1 -
drivers/serial/serial_imx.c | 1 -
drivers/spi/imx_spi.c | 1 -
drivers/video/imx.c | 1 -
19 files changed, 10 insertions(+), 2158 deletions(-)
delete mode 100644 arch/arm/mach-imx/clko.c
delete mode 100644 arch/arm/mach-imx/speed-imx1.c
delete mode 100644 arch/arm/mach-imx/speed-imx21.c
delete mode 100644 arch/arm/mach-imx/speed-imx25.c
delete mode 100644 arch/arm/mach-imx/speed-imx27.c
delete mode 100644 arch/arm/mach-imx/speed-imx31.c
delete mode 100644 arch/arm/mach-imx/speed-imx35.c
delete mode 100644 arch/arm/mach-imx/speed-imx51.c
delete mode 100644 arch/arm/mach-imx/speed-imx53.c
delete mode 100644 arch/arm/mach-imx/speed-imx6.c
delete mode 100644 arch/arm/mach-imx/speed.c
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 7ab812a..d27d4f3 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -552,14 +552,6 @@ endmenu
menu "i.MX specific settings "
-config IMX_CLKO
- bool "clko command"
- depends on ARCH_IMX21 || ARCH_IMX27 || ARCH_IMX35 || ARCH_IMX25 || ARCH_IMX51
- help
- The i.MX SoCs have a Pin which can output different reference frequencies.
- Say y here if you want to have the clko command which lets you select the
- frequency to output on this pin.
-
config IMX_IIM
tristate "IIM fusebox device"
depends on !ARCH_IMX21 && !ARCH_IMX21
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f7a5ba4..e43f92e 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,20 +1,18 @@
obj-y += clocksource.o gpio.o
obj-$(CONFIG_RESET_SOURCE) += reset_source.o
-obj-$(CONFIG_ARCH_IMX1) += speed-imx1.o imx1.o iomux-v1.o clk-imx1.o
-obj-$(CONFIG_ARCH_IMX25) += speed-imx25.o imx25.o iomux-v3.o clk-imx25.o
-obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o clk-imx21.o
-obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o clk-imx27.o
-obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o clk-imx31.o
-obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o clk-imx35.o
-obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o imx5.o clk-imx5.o
-obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o imx5.o clk-imx5.o
-obj-$(CONFIG_ARCH_IMX6) += speed-imx6.o imx6.o iomux-v3.o usb-imx6.o clk-imx6.o
-obj-$(CONFIG_IMX_CLKO) += clko.o
+obj-$(CONFIG_ARCH_IMX1) += imx1.o iomux-v1.o clk-imx1.o
+obj-$(CONFIG_ARCH_IMX25) += imx25.o iomux-v3.o clk-imx25.o
+obj-$(CONFIG_ARCH_IMX21) += imx21.o iomux-v1.o clk-imx21.o
+obj-$(CONFIG_ARCH_IMX27) += imx27.o iomux-v1.o clk-imx27.o
+obj-$(CONFIG_ARCH_IMX31) += imx31.o iomux-v2.o clk-imx31.o
+obj-$(CONFIG_ARCH_IMX35) += imx35.o iomux-v3.o clk-imx35.o
+obj-$(CONFIG_ARCH_IMX51) += imx51.o iomux-v3.o imx5.o clk-imx5.o
+obj-$(CONFIG_ARCH_IMX53) += imx53.o iomux-v3.o imx5.o clk-imx5.o
+obj-$(CONFIG_ARCH_IMX6) += imx6.o iomux-v3.o usb-imx6.o clk-imx6.o
obj-$(CONFIG_IMX_IIM) += iim.o
obj-$(CONFIG_NAND_IMX) += nand.o
obj-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o
pbl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o
obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-pfd.o
-obj-y += speed.o
obj-y += devices.o
obj-y += boot.o
diff --git a/arch/arm/mach-imx/clko.c b/arch/arm/mach-imx/clko.c
deleted file mode 100644
index aeafaa9..0000000
--- a/arch/arm/mach-imx/clko.c
+++ /dev/null
@@ -1,60 +0,0 @@
-#include <common.h>
-#include <command.h>
-#include <getopt.h>
-#include <mach/imx-regs.h>
-#include <mach/clock.h>
-
-static int do_clko(int argc, char *argv[])
-{
- int opt, div = 0, src = -2, num = 1, ret;
-
- while((opt = getopt(argc, argv, "n:d:s:")) > 0) {
- switch(opt) {
- case 'n':
- num = simple_strtoul(optarg, NULL, 0);
- break;
- case 'd':
- div = simple_strtoul(optarg, NULL, 0);
- break;
- case 's':
- src = simple_strtol(optarg, NULL, 0);
- break;
- }
- }
-
- if (div == 0 && src == -2)
- return COMMAND_ERROR_USAGE;
-
- if (src == -1) {
- imx_clko_set_src(num, -1);
- return 0;
- }
-
- if (src != -2)
- imx_clko_set_src(num, src);
-
- if (div != 0) {
- ret = imx_clko_set_div(num, div);
- if (ret < 0)
- printf("CLKO-line %i not supported.\n", num);
- else if (ret != div)
- printf("Divider limited to %d.\n", ret);
- }
-
- return 0;
-}
-
-static __maybe_unused char cmd_clko_help[] =
-"Usage: clko [OPTION]...\n"
-"Route different signals to the i.MX clko pin\n"
-" -n <num> Number of CLKO-line (Default 1)\n"
-" -d <div> Divider\n"
-" -s <source> Clock select. See Ref. Manual for valid sources. Use -1\n"
-" for disabling clock output\n";
-
-BAREBOX_CMD_START(clko)
- .cmd = do_clko,
- .usage = "Adjust CLKO setting",
- BAREBOX_CMD_HELP(cmd_clko_help)
-BAREBOX_CMD_END
-
diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c
index df018e6..9229fb7 100644
--- a/arch/arm/mach-imx/clocksource.c
+++ b/arch/arm/mach-imx/clocksource.c
@@ -33,7 +33,6 @@
#include <linux/err.h>
#include <notifier.h>
#include <mach/imx-regs.h>
-#include <mach/clock.h>
#include <io.h>
/* Part 1: Registers */
diff --git a/arch/arm/mach-imx/include/mach/clock.h b/arch/arm/mach-imx/include/mach/clock.h
index f613395..304a7c8 100644
--- a/arch/arm/mach-imx/include/mach/clock.h
+++ b/arch/arm/mach-imx/include/mach/clock.h
@@ -1,41 +1 @@
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
-
-ulong imx_get_mpllclk(void);
-
-#ifdef CONFIG_ARCH_IMX27
-ulong imx_get_armclk(void);
-#endif
-#ifdef CONFIG_ARCH_IMX1
-static inline ulong imx_get_armclk(void)
-{
- return imx_get_mpllclk();
-}
-#endif
-
-ulong imx_get_spllclk(void);
-ulong imx_get_fclk(void);
-ulong imx_get_hclk(void);
-ulong imx_get_bclk(void);
-ulong imx_get_perclk1(void);
-ulong imx_get_perclk2(void);
-ulong imx_get_perclk3(void);
-ulong imx_get_ahbclk(void);
-ulong imx_get_fecclk(void);
-ulong imx_get_gptclk(void);
-ulong imx_get_uartclk(void);
-ulong imx_get_lcdclk(void);
-ulong fsl_get_i2cclk(void);
-ulong imx_get_mmcclk(void);
-ulong imx_get_cspiclk(void);
-ulong imx_get_ipgclk(void);
-ulong imx_get_usbclk(void);
-
-int imx_clko_set_div(int num, int div);
-void imx_clko_set_src(int num, int src);
-
-void imx_dump_clocks(void);
-
-#endif /* __ASM_ARCH_CLOCK_H */
+/* nothing, but some drivers need this include */
diff --git a/arch/arm/mach-imx/speed-imx1.c b/arch/arm/mach-imx/speed-imx1.c
deleted file mode 100644
index 2b62f61..0000000
--- a/arch/arm/mach-imx/speed-imx1.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- *
- * (c) 2004 Sascha Hauer <sascha@saschahauer.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-
-#include <common.h>
-#include <mach/imx-regs.h>
-#include <mach/clock.h>
-#include <init.h>
-#include <driver.h>
-
-ulong imx_get_spllclk(void)
-{
- return imx_decode_pll(SPCTL0, CONFIG_SYSPLL_CLK_FREQ);
-}
-
-ulong imx_get_mpllclk(void)
-{
- return imx_decode_pll(MPCTL0, CONFIG_SYSPLL_CLK_FREQ);
-}
-
-ulong imx_get_fclk(void)
-{
- return (( CSCR>>15)&1) ? imx_get_mpllclk()>>1 : imx_get_mpllclk();
-}
-
-ulong imx_get_hclk(void)
-{
- u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
- return imx_get_spllclk() / bclkdiv;
-}
-
-ulong imx_get_bclk(void)
-{
- return imx_get_hclk();
-}
-
-ulong imx_get_perclk1(void)
-{
- return imx_get_spllclk() / (((PCDR) & 0xf)+1);
-}
-
-ulong imx_get_perclk2(void)
-{
- return imx_get_spllclk() / (((PCDR>>4) & 0xf)+1);
-}
-
-ulong imx_get_perclk3(void)
-{
- return imx_get_spllclk() / (((PCDR>>16) & 0x7f)+1);
-}
-
-ulong imx_get_uartclk(void)
-{
- return imx_get_perclk1();
-}
-
-ulong imx_get_gptclk(void)
-{
- return imx_get_perclk1();
-}
-
-void imx_dump_clocks(void)
-{
- printf("spll: %10ld Hz\n", imx_get_spllclk());
- printf("mpll: %10ld Hz\n", imx_get_mpllclk());
- printf("fclk: %10ld Hz\n", imx_get_fclk());
- printf("hclk: %10ld Hz\n", imx_get_hclk());
- printf("bclk: %10ld Hz\n", imx_get_bclk());
- printf("perclk1: %10ld Hz\n", imx_get_perclk1());
- printf("perclk2: %10ld Hz\n", imx_get_perclk2());
- printf("perclk3: %10ld Hz\n", imx_get_perclk3());
- printf("uart: %10ld Hz\n", imx_get_uartclk());
- printf("gpt: %10ld Hz\n", imx_get_gptclk());
-}
-
diff --git a/arch/arm/mach-imx/speed-imx21.c b/arch/arm/mach-imx/speed-imx21.c
deleted file mode 100644
index b9ecd2f..0000000
--- a/arch/arm/mach-imx/speed-imx21.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <mach/imx-regs.h>
-#include <mach/generic.h>
-#include <mach/clock.h>
-#include <init.h>
-
-#ifndef CLK32
-#define CLK32 32768
-#endif
-
-static ulong clk_in_32k(void)
-{
- return 512 * CLK32;
-}
-
-static ulong clk_in_26m(void)
-{
- if (CSCR & CSCR_OSC26M_DIV1P5) {
- /* divide by 1.5 */
- return 173333333;
- } else {
- /* divide by 1 */
- return 26000000;
- }
-}
-
-ulong imx_get_mpllclk(void)
-{
- ulong cscr = CSCR;
- ulong fref;
-
- if (cscr & CSCR_MCU_SEL)
- fref = clk_in_26m();
- else
- fref = clk_in_32k();
-
- return imx_decode_pll(MPCTL0, fref);
-}
-
-ulong imx_get_fclk(void)
-{
- ulong cscr = CSCR;
- ulong fref = imx_get_mpllclk();
- ulong div;
-
- div = ((cscr >> 29) & 0x7) + 1;
-
- return fref / div;
-}
-
-/* HCLK */
-ulong imx_get_armclk(void)
-{
- ulong cscr = CSCR;
- ulong fref = imx_get_mpllclk();
- ulong div;
-
- div = ((cscr >> 10) & 0xF) + 1;
-
- return fref / div;
-}
-
-ulong imx_get_spllclk(void)
-{
- ulong cscr = CSCR;
- ulong spctl0;
- ulong fref;
-
- if (cscr & CSCR_SP_SEL)
- fref = clk_in_26m();
- else
- fref = clk_in_32k();
-
- spctl0 = SPCTL0;
- SPCTL0 = spctl0;
- return imx_decode_pll(spctl0, fref);
-}
-
-static ulong imx_decode_perclk(ulong div)
-{
- return imx_get_mpllclk() / div;
-}
-
-static ulong imx_get_nfcclk(void)
-{
- ulong fref = imx_get_fclk();
- ulong div = ((PCDR0 >> 12) & 0xF) + 1;
- return fref / div;
-}
-
-ulong imx_get_perclk1(void)
-{
- return imx_decode_perclk((PCDR1 & 0x3f) + 1);
-}
-
-ulong imx_get_perclk2(void)
-{
- return imx_decode_perclk(((PCDR1 >> 8) & 0x3f) + 1);
-}
-
-ulong imx_get_perclk3(void)
-{
- return imx_decode_perclk(((PCDR1 >> 16) & 0x3f) + 1);
-}
-
-ulong imx_get_perclk4(void)
-{
- return imx_decode_perclk(((PCDR1 >> 24) & 0x3f) + 1);
-}
-
-ulong imx_get_uartclk(void)
-{
- return imx_get_perclk1();
-}
-
-ulong imx_get_gptclk(void)
-{
- return imx_decode_perclk((PCDR1 & 0x3f) + 1);
-}
-
-ulong imx_get_lcdclk(void)
-{
- return imx_get_perclk3();
-}
-
-void imx_dump_clocks(void)
-{
- uint32_t cid = CID;
-
- printf("chip id: [%08x]\n", cid);
- printf("mpll: %10ld Hz\n", imx_get_mpllclk());
- printf("spll: %10ld Hz\n", imx_get_spllclk());
- printf("arm: %10ld Hz\n", imx_get_armclk());
- printf("fclk: %10ld Hz\n", imx_get_fclk());
- printf("nfcclk: %10ld Hz\n", imx_get_nfcclk());
- printf("perclk1: %10ld Hz\n", imx_get_perclk1());
- printf("perclk2: %10ld Hz\n", imx_get_perclk2());
- printf("perclk3: %10ld Hz\n", imx_get_perclk3());
- printf("perclk4: %10ld Hz\n", imx_get_perclk4());
- printf("clkin26: %10ld Hz\n", clk_in_26m());
-}
-
-/*
- * Set the divider of the CLKO pin (when CLK48DIV_CLKO is chosen).
- * Returns the new divider (which may be smaller
- * than the desired one)
- */
-int imx_clko_set_div(int num, int div)
-{
- ulong pcdr;
-
- if (num != 1)
- return -ENODEV;
-
- div--;
- div &= 0x7;
-
- pcdr = PCDR0 & ~(7 << 5);
- pcdr |= div << 5;
- PCDR0 = pcdr;
-
- return div + 1;
-}
-
-/*
- * Set the clock source for the CLKO pin
- */
-void imx_clko_set_src(int num, int src)
-{
- unsigned long ccsr;
-
- if (src < 0 || num != 1) {
- return;
- }
-
- ccsr = CCSR & ~0x1f;
- ccsr |= src & 0x1f;
- CCSR = ccsr;
-}
diff --git a/arch/arm/mach-imx/speed-imx25.c b/arch/arm/mach-imx/speed-imx25.c
deleted file mode 100644
index 3c85713..0000000
--- a/arch/arm/mach-imx/speed-imx25.c
+++ /dev/null
@@ -1,155 +0,0 @@
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <mach/imx-regs.h>
-#include <io.h>
-#include <mach/clock.h>
-#include <init.h>
-
-unsigned long imx_get_mpllclk(void)
-{
- ulong mpctl = readl(MX25_CCM_BASE_ADDR + CCM_MPCTL);
- return imx_decode_pll(mpctl, CONFIG_MX25_HCLK_FREQ);
-}
-
-unsigned long imx_get_upllclk(void)
-{
- ulong ppctl = readl(MX25_CCM_BASE_ADDR + CCM_UPCTL);
- return imx_decode_pll(ppctl, CONFIG_MX25_HCLK_FREQ);
-}
-
-unsigned long imx_get_armclk(void)
-{
- unsigned long rate, cctl;
-
- cctl = readl(MX25_CCM_BASE_ADDR + CCM_CCTL);
- rate = imx_get_mpllclk();
-
- if (cctl & (1 << 14)) {
- rate *= 3;
- rate >>= 2;
- }
-
- return rate / ((cctl >> 30) + 1);
-}
-
-unsigned long imx_get_ahbclk(void)
-{
- ulong cctl = readl(MX25_CCM_BASE_ADDR + CCM_CCTL);
- return imx_get_armclk() / (((cctl >> 28) & 0x3) + 1);
-}
-
-unsigned long imx_get_ipgclk(void)
-{
- return imx_get_ahbclk() / 2;
-}
-
-unsigned long imx_get_gptclk(void)
-{
- return imx_get_ipgclk();
-}
-
-unsigned long imx_get_perclk(int per)
-{
- ulong ofs = (per & 0x3) * 8;
- ulong reg = per & ~0x3;
- ulong val = (readl(MX25_CCM_BASE_ADDR + CCM_PCDR0 + reg) >> ofs) & 0x3f;
- ulong fref;
-
- if (readl(MX25_CCM_BASE_ADDR + 0x64) & (1 << per))
- fref = imx_get_upllclk();
- else
- fref = imx_get_ahbclk();
-
- return fref / (val + 1);
-}
-
-unsigned long imx_get_uartclk(void)
-{
- return imx_get_perclk(15);
-}
-
-unsigned long imx_get_fecclk(void)
-{
- return imx_get_ipgclk();
-}
-
-unsigned long imx_get_lcdclk(void)
-{
- return imx_get_perclk(7);
-}
-
-unsigned long fsl_get_i2cclk(void)
-{
- return imx_get_perclk(6);
-}
-
-unsigned long imx_get_mmcclk(void)
-{
- return imx_get_perclk(3);
-}
-
-unsigned long imx_get_cspiclk(void)
-{
- return imx_get_ipgclk();
-}
-
-void imx_dump_clocks(void)
-{
- printf("mpll: %10ld Hz\n", imx_get_mpllclk());
- printf("upll: %10ld Hz\n", imx_get_upllclk());
- printf("arm: %10ld Hz\n", imx_get_armclk());
- printf("ahb: %10ld Hz\n", imx_get_ahbclk());
- printf("uart: %10ld Hz\n", imx_get_perclk(15));
- printf("gpt: %10ld Hz\n", imx_get_ipgclk());
- printf("nand: %10ld Hz\n", imx_get_perclk(8));
- printf("lcd: %10ld Hz\n", imx_get_perclk(7));
- printf("i2c: %10ld Hz\n", imx_get_perclk(6));
- printf("sdhc1: %10ld Hz\n", imx_get_perclk(3));
-}
-
-/*
- * Set the divider of the CLKO pin. Returns
- * the new divider (which may be smaller
- * than the desired one)
- */
-int imx_clko_set_div(int num, int div)
-{
- unsigned long mcr = readl(MX25_CCM_BASE_ADDR + 0x64);
-
- if (num != 1)
- return -ENODEV;
-
- div -= 1;
- div &= 0x3f;
-
- mcr &= ~(0x3f << 24);
- mcr |= div << 24;
-
- writel(mcr, MX25_CCM_BASE_ADDR + 0x64);
-
- return div + 1;
-}
-
-/*
- * Set the clock source for the CLKO pin
- */
-void imx_clko_set_src(int num, int src)
-{
- unsigned long mcr = readl(MX25_CCM_BASE_ADDR + 0x64);
-
- if (num != 1)
- return;
-
- if (src < 0) {
- mcr &= ~(1 << 30);
- writel(mcr, MX25_CCM_BASE_ADDR + 0x64);
- return;
- }
-
- mcr |= 1 << 30;
- mcr &= ~(0xf << 20);
- mcr |= (src & 0xf) << 20;
-
- writel(mcr, MX25_CCM_BASE_ADDR + 0x64);
-}
-
diff --git a/arch/arm/mach-imx/speed-imx27.c b/arch/arm/mach-imx/speed-imx27.c
deleted file mode 100644
index 33ec448..0000000
--- a/arch/arm/mach-imx/speed-imx27.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <mach/imx-regs.h>
-#include <mach/generic.h>
-#include <mach/clock.h>
-#include <init.h>
-
-#ifndef CLK32
-#define CLK32 32000
-#endif
-
-static ulong clk_in_32k(void)
-{
- return 1024 * CLK32;
-}
-
-static ulong clk_in_26m(void)
-{
- if (CSCR & CSCR_OSC26M_DIV1P5) {
- /* divide by 1.5 */
- return 173333333;
- } else {
- /* divide by 1 */
- return 26000000;
- }
-}
-
-ulong imx_get_mpllclk(void)
-{
- ulong cscr = CSCR;
- ulong fref;
-
- if (cscr & CSCR_MCU_SEL)
- fref = clk_in_26m();
- else
- fref = clk_in_32k();
-
- return imx_decode_pll(MPCTL0, fref);
-}
-
-ulong imx_get_armclk(void)
-{
- ulong cscr = CSCR;
- ulong fref = imx_get_mpllclk();
- ulong div;
-
- if (!(cscr & CSCR_ARM_SRC_MPLL) &&
- (imx_silicon_revision() != IMX27_CHIP_REVISION_1_0))
- fref = (fref * 2) / 3;
-
- div = ((cscr >> 12) & 0x3) + 1;
-
- return fref / div;
-}
-
-ulong imx_get_ahbclk(void)
-{
- ulong cscr = CSCR;
- ulong fref = imx_get_mpllclk();
- ulong div;
-
- if (imx_silicon_revision() == IMX27_CHIP_REVISION_1_0)
- div = ((cscr >> 9) & 0xf) + 1;
- else
- div = ((cscr >> 8) & 0x3) + 1;
-
- return ((fref * 2) / 3) / div;
-}
-
-ulong imx_get_ipgclk(void)
-{
- ulong clk = imx_get_ahbclk();
-
- return clk >> 1;
-}
-
-ulong imx_get_fecclk(void)
-{
- return imx_get_ipgclk();
-}
-
-ulong imx_get_spllclk(void)
-{
- ulong cscr = CSCR;
- ulong spctl0;
- ulong fref;
-
- if (cscr & CSCR_SP_SEL)
- fref = clk_in_26m();
- else
- fref = clk_in_32k();
-
- spctl0 = SPCTL0;
- SPCTL0 = spctl0;
- return imx_decode_pll(spctl0, fref);
-}
-
-static ulong imx_decode_perclk(ulong div)
-{
- if (imx_silicon_revision() == IMX27_CHIP_REVISION_1_0)
- return imx_get_mpllclk() / div;
- else
- return (imx_get_mpllclk() * 2) / (div * 3);
-}
-
-ulong imx_get_perclk1(void)
-{
- return imx_decode_perclk((PCDR1 & 0x3f) + 1);
-}
-
-ulong imx_get_perclk2(void)
-{
- return imx_decode_perclk(((PCDR1 >> 8) & 0x3f) + 1);
-}
-
-ulong imx_get_perclk3(void)
-{
- return imx_decode_perclk(((PCDR1 >> 16) & 0x3f) + 1);
-}
-
-ulong imx_get_perclk4(void)
-{
- return imx_decode_perclk(((PCDR1 >> 24) & 0x3f) + 1);
-}
-
-ulong imx_get_uartclk(void)
-{
- return imx_get_perclk1();
-}
-
-ulong imx_get_gptclk(void)
-{
- return imx_decode_perclk((PCDR1 & 0x3f) + 1);
-}
-
-ulong imx_get_lcdclk(void)
-{
- return imx_get_perclk3();
-}
-
-ulong fsl_get_i2cclk(void)
-{
- return imx_get_ipgclk();
-}
-
-ulong imx_get_mmcclk(void)
-{
- return imx_get_perclk2();
-}
-
-void imx_dump_clocks(void)
-{
- uint32_t cid = CID;
-
- printf("chip id: [%d,%03x,%d,%03x]\n",
- (cid >> 28) & 0xf, (cid >> 16) & 0xfff,
- (cid >> 12) & 0xf, (cid >> 0) & 0xfff);
-
- printf("mpll: %10ld Hz\n", imx_get_mpllclk());
- printf("spll: %10ld Hz\n", imx_get_spllclk());
- printf("arm: %10ld Hz\n", imx_get_armclk());
- printf("perclk1: %10ld Hz\n", imx_get_perclk1());
- printf("perclk2: %10ld Hz\n", imx_get_perclk2());
- printf("perclk3: %10ld Hz\n", imx_get_perclk3());
- printf("perclk4: %10ld Hz\n", imx_get_perclk4());
- printf("clkin26: %10ld Hz\n", clk_in_26m());
- printf("ahb: %10ld Hz\n", imx_get_ahbclk());
- printf("ipg: %10ld Hz\n", imx_get_ipgclk());
-}
-
-/*
- * Set the divider of the CLKO pin. Returns
- * the new divider (which may be smaller
- * than the desired one)
- */
-int imx_clko_set_div(int num, int div)
-{
- ulong pcdr;
-
- if (num != 1)
- return -ENODEV;
-
- div--;
- div &= 0x7;
-
- pcdr = PCDR0 & ~(7 << 22);
- pcdr |= div << 22;
- PCDR0 = pcdr;
-
- return div + 1;
-}
-
-/*
- * Set the clock source for the CLKO pin
- */
-void imx_clko_set_src(int num, int src)
-{
- unsigned long ccsr;
-
- if (num != 1)
- return;
-
- if (src < 0) {
- PCDR0 &= ~(1 << 25);
- return;
- }
-
- ccsr = CCSR & ~0x1f;
- ccsr |= src & 0x1f;
- CCSR = ccsr;
-
- PCDR0 |= (1 << 25);
-}
-
diff --git a/arch/arm/mach-imx/speed-imx31.c b/arch/arm/mach-imx/speed-imx31.c
deleted file mode 100644
index f8f73c1..0000000
--- a/arch/arm/mach-imx/speed-imx31.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <io.h>
-#include <mach/imx-regs.h>
-#include <mach/clock.h>
-#include <init.h>
-
-ulong imx_get_mpl_dpdgck_clk(void)
-{
- ulong infreq;
-
- if ((readl(MX31_CCM_BASE_ADDR + CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
- infreq = CONFIG_MX31_CLK32 * 1024;
- else
- infreq = CONFIG_MX31_HCLK_FREQ;
-
- return imx_decode_pll(readl(MX31_CCM_BASE_ADDR + CCM_MPCTL), infreq);
-}
-
-ulong imx_get_mcu_main_clk(void)
-{
- /* For now we assume mpl_dpdgck_clk == mcu_main_clk
- * which should be correct for most boards
- */
- return imx_get_mpl_dpdgck_clk();
-}
-
-/**
- * Calculate the current pixel clock speed (aka HSP or IPU)
- * @return 0 on failure or current frequency in Hz
- */
-ulong imx_get_lcdclk(void)
-{
- ulong hsp_podf = (readl(MX31_CCM_BASE_ADDR + CCM_PDR0) >> 11) & 0x03;
- ulong base_clk = imx_get_mcu_main_clk();
-
- return base_clk / (hsp_podf + 1);
-}
-
-ulong imx_get_perclk1(void)
-{
- u32 freq = imx_get_mcu_main_clk();
- u32 pdr0 = readl(MX31_CCM_BASE_ADDR + CCM_PDR0);
-
- freq /= ((pdr0 >> 3) & 0x7) + 1;
- freq /= ((pdr0 >> 6) & 0x3) + 1;
-
- return freq;
-}
-
-void imx_dump_clocks(void)
-{
- ulong cpufreq = imx_get_mcu_main_clk();
- printf("mx31 cpu clock: %ldMHz\n",cpufreq / 1000000);
- printf("ipg clock : %ldHz\n", imx_get_perclk1());
-}
-
-ulong imx_get_uartclk(void)
-{
- return imx_get_perclk1();
-}
-
-ulong imx_get_gptclk(void)
-{
- return imx_get_perclk1();
-}
-
diff --git a/arch/arm/mach-imx/speed-imx35.c b/arch/arm/mach-imx/speed-imx35.c
deleted file mode 100644
index a8063f2..0000000
--- a/arch/arm/mach-imx/speed-imx35.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <mach/imx-regs.h>
-#include <io.h>
-#include <mach/clock.h>
-#include <mach/generic.h>
-#include <init.h>
-
-unsigned long imx_get_mpllclk(void)
-{
- ulong mpctl = readl(MX35_CCM_BASE_ADDR + CCM_MPCTL);
- return imx_decode_pll(mpctl, CONFIG_MX35_HCLK_FREQ);
-}
-
-static unsigned long imx_get_ppllclk(void)
-{
- ulong ppctl = readl(MX35_CCM_BASE_ADDR + CCM_PPCTL);
- return imx_decode_pll(ppctl, CONFIG_MX35_HCLK_FREQ);
-}
-
-struct arm_ahb_div {
- unsigned char arm, ahb, sel;
-};
-
-static struct arm_ahb_div clk_consumer[] = {
- { .arm = 1, .ahb = 4, .sel = 0},
- { .arm = 1, .ahb = 3, .sel = 1},
- { .arm = 2, .ahb = 2, .sel = 0},
- { .arm = 0, .ahb = 0, .sel = 0},
- { .arm = 0, .ahb = 0, .sel = 0},
- { .arm = 0, .ahb = 0, .sel = 0},
- { .arm = 4, .ahb = 1, .sel = 0},
- { .arm = 1, .ahb = 5, .sel = 0},
- { .arm = 1, .ahb = 8, .sel = 0},
- { .arm = 1, .ahb = 6, .sel = 1},
- { .arm = 2, .ahb = 4, .sel = 0},
- { .arm = 0, .ahb = 0, .sel = 0},
- { .arm = 0, .ahb = 0, .sel = 0},
- { .arm = 0, .ahb = 0, .sel = 0},
- { .arm = 4, .ahb = 2, .sel = 0},
- { .arm = 0, .ahb = 0, .sel = 0},
-};
-
-static unsigned long imx_get_armclk(void)
-{
- unsigned long pdr0 = readl(MX35_CCM_BASE_ADDR + CCM_PDR0);
- struct arm_ahb_div *aad;
- unsigned long fref = imx_get_mpllclk();
-
- /* consumer path is selected */
- aad = &clk_consumer[(pdr0 >> 16) & 0xf];
- if (aad->sel)
- fref = fref * 3 / 4;
-
- return fref / aad->arm;
-}
-
-unsigned long imx_get_ahbclk(void)
-{
- unsigned long pdr0 = readl(MX35_CCM_BASE_ADDR + CCM_PDR0);
- struct arm_ahb_div *aad;
- unsigned long fref = imx_get_mpllclk();
-
- aad = &clk_consumer[(pdr0 >> 16) & 0xf];
- if (aad->sel)
- fref = fref * 3 / 4;
-
- return fref / aad->ahb;
-}
-
-unsigned long imx_get_ipgclk(void)
-{
- ulong clk = imx_get_ahbclk();
-
- return clk >> 1;
-}
-
-static unsigned long get_3_3_div(unsigned long in)
-{
- return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1);
-}
-
-static unsigned long get_6_div(unsigned long in)
-{
- return ((in & 0x3f) + 1);
-}
-
-static unsigned long imx_get_ipg_perclk(void)
-{
- ulong pdr0 = readl(MX35_CCM_BASE_ADDR + CCM_PDR0);
- ulong pdr4 = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
- ulong div;
- ulong fref;
-
- if (pdr0 & PDR0_PER_SEL) {
- /* perclk from arm high frequency clock and synched with AHB clki */
- fref = imx_get_armclk();
- div = get_3_3_div((pdr4 >> 16));
- } else {
- /* perclk from AHB divided clock */
- fref = imx_get_ahbclk();
- div = ((pdr0 >> 12) & 0x7) + 1;
- }
-
- return fref / div;
-}
-
-unsigned long imx_get_gptclk(void)
-{
- return imx_get_ipgclk();
-}
-
-/**
- * Calculate the current pixel clock speed (aka HSP or IPU)
- * @return 0 on failure or current frequency in Hz
- */
-unsigned long imx_get_lcdclk(void)
-{
- unsigned long hsp_podf = (readl(MX35_CCM_BASE_ADDR + CCM_PDR0) >> 20) & 0x03;
- unsigned long base_clk = imx_get_armclk();
-
- if (base_clk > 400 * 1000 * 1000) {
- switch(hsp_podf) {
- case 0:
- return base_clk >> 2;
- case 1:
- return base_clk >> 3;
- case 2:
- return base_clk / 3;
- }
- } else {
- switch(hsp_podf) {
- case 0:
- case 2:
- return base_clk / 3;
- case 1:
- return base_clk / 6;
- }
- }
-
- return 0;
-}
-
-unsigned long imx_get_uartclk(void)
-{
- unsigned long pdr3 = readl(MX35_CCM_BASE_ADDR + CCM_PDR3);
- unsigned long pdr4 = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
- unsigned long div = get_3_3_div(pdr4 >> 10);
-
- if (pdr3 & (1 << 14))
- return imx_get_armclk() / div;
- else
- return imx_get_ppllclk() / div;
-}
-
-/* mmc0 clk only */
-unsigned long imx_get_mmcclk(void)
-{
- unsigned long pdr3 = readl(MX35_CCM_BASE_ADDR + CCM_PDR3);
- unsigned long div = get_6_div(pdr3);
-
- if (pdr3 & (1 << 6))
- return imx_get_armclk() / div;
- else
- return imx_get_ppllclk() / div;
-}
-
-ulong imx_get_fecclk(void)
-{
- return imx_get_ipgclk();
-}
-
-ulong fsl_get_i2cclk(void)
-{
- return imx_get_ipg_perclk();
-}
-
-unsigned long imx_get_cspiclk(void)
-{
- return imx_get_ipgclk();
-}
-
-void imx_dump_clocks(void)
-{
- printf("mpll: %10ld Hz\n", imx_get_mpllclk());
- printf("ppll: %10ld Hz\n", imx_get_ppllclk());
- printf("arm: %10ld Hz\n", imx_get_armclk());
- printf("gpt: %10ld Hz\n", imx_get_gptclk());
- printf("ahb: %10ld Hz\n", imx_get_ahbclk());
- printf("ipg: %10ld Hz\n", imx_get_ipgclk());
- printf("ipg_per: %10ld Hz\n", imx_get_ipg_perclk());
- printf("uart: %10ld Hz\n", imx_get_uartclk());
- printf("sdhc1: %10ld Hz\n", imx_get_mmcclk());
-}
-
-/*
- * Set the divider of the CLKO pin. Returns
- * the new divider (which may be smaller
- * than the desired one)
- */
-int imx_clko_set_div(int num, int div)
-{
- unsigned long cosr = readl(MX35_CCM_BASE_ADDR + CCM_COSR);
-
- if (num != 1)
- return -ENODEV;
-
- div -= 1;
- div &= 0x3f;
-
- cosr &= ~(0x3f << 10);
- cosr |= div << 10;
-
- writel(cosr, MX35_CCM_BASE_ADDR + CCM_COSR);
-
- return div + 1;
-}
-
-/*
- * Set the clock source for the CLKO pin
- */
-void imx_clko_set_src(int num, int src)
-{
- unsigned long cosr = readl(MX35_CCM_BASE_ADDR + CCM_COSR);
-
- if (num != 1)
- return;
-
- if (src < 0) {
- cosr &= ~(1 << 5);
- writel(cosr, MX35_CCM_BASE_ADDR + CCM_COSR);
- return;
- }
-
- cosr |= 1 << 5;
- cosr &= ~0x1f;
- cosr &= ~(1 << 6);
- cosr |= src & 0x1f;
-
- writel(cosr, MX35_CCM_BASE_ADDR + CCM_COSR);
-}
-
diff --git a/arch/arm/mach-imx/speed-imx51.c b/arch/arm/mach-imx/speed-imx51.c
deleted file mode 100644
index 3903afc..0000000
--- a/arch/arm/mach-imx/speed-imx51.c
+++ /dev/null
@@ -1,311 +0,0 @@
-#include <common.h>
-#include <io.h>
-#include <asm-generic/div64.h>
-#include <asm-generic/errno.h>
-#include <mach/imx51-regs.h>
-#include <mach/clock.h>
-#include <mach/clock-imx51_53.h>
-
-static u32 ccm_readl(u32 ofs)
-{
- return readl(IOMEM(MX51_CCM_BASE_ADDR) + ofs);
-}
-
-static void ccm_writel(u32 val, u32 ofs)
-{
- writel(val, MX51_CCM_BASE_ADDR + ofs);
-}
-
-static unsigned long ckil_get_rate(void)
-{
- return 32768;
-}
-
-static unsigned long osc_get_rate(void)
-{
- return 24000000;
-}
-
-static unsigned long fpm_get_rate(void)
-{
- return ckil_get_rate() * 512;
-}
-
-static unsigned long lp_apm_get_rate(void)
-{
- if (ccm_readl(MX5_CCM_CCSR) & MX5_CCM_CCSR_LP_APM_SEL)
- return fpm_get_rate();
- else
- return osc_get_rate();
-}
-
-static unsigned long pll_get_rate(void __iomem *pllbase)
-{
- long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
- unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
- u64 temp;
- unsigned long parent_rate;
-
- dp_ctl = readl(pllbase + MX5_PLL_DP_CTL);
-
- if ((dp_ctl & MX5_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
- parent_rate = fpm_get_rate();
- else
- parent_rate = osc_get_rate();
-
- pll_hfsm = dp_ctl & MX5_PLL_DP_CTL_HFSM;
- dbl = dp_ctl & MX5_PLL_DP_CTL_DPDCK0_2_EN;
-
- if (pll_hfsm == 0) {
- dp_op = readl(pllbase + MX5_PLL_DP_OP);
- dp_mfd = readl(pllbase + MX5_PLL_DP_MFD);
- dp_mfn = readl(pllbase + MX5_PLL_DP_MFN);
- } else {
- dp_op = readl(pllbase + MX5_PLL_DP_HFS_OP);
- dp_mfd = readl(pllbase + MX5_PLL_DP_HFS_MFD);
- dp_mfn = readl(pllbase + MX5_PLL_DP_HFS_MFN);
- }
- pdf = dp_op & MX5_PLL_DP_OP_PDF_MASK;
- mfi = (dp_op & MX5_PLL_DP_OP_MFI_MASK) >> MX5_PLL_DP_OP_MFI_OFFSET;
- mfi = (mfi <= 5) ? 5 : mfi;
- mfd = dp_mfd & MX5_PLL_DP_MFD_MASK;
- mfn = mfn_abs = dp_mfn & MX5_PLL_DP_MFN_MASK;
- /* Sign extend to 32-bits */
- if (mfn >= 0x04000000) {
- mfn |= 0xFC000000;
- mfn_abs = -mfn;
- }
-
- ref_clk = 2 * parent_rate;
- if (dbl != 0)
- ref_clk *= 2;
-
- ref_clk /= (pdf + 1);
- temp = (u64)ref_clk * mfn_abs;
- do_div(temp, mfd + 1);
- if (mfn < 0)
- temp = -temp;
- temp = (ref_clk * mfi) + temp;
-
- return temp;
-}
-
-static unsigned long pll1_main_get_rate(void)
-{
- return pll_get_rate((void __iomem *)MX51_PLL1_BASE_ADDR);
-}
-
-static unsigned long pll2_sw_get_rate(void)
-{
- return pll_get_rate((void __iomem *)MX51_PLL2_BASE_ADDR);
-}
-
-static unsigned long pll3_sw_get_rate(void)
-{
- return pll_get_rate((void __iomem *)MX51_PLL3_BASE_ADDR);
-}
-
-static unsigned long get_rate_select(int select,
- unsigned long (* get_rate1)(void),
- unsigned long (* get_rate2)(void),
- unsigned long (* get_rate3)(void),
- unsigned long (* get_rate4)(void))
-{
- switch (select) {
- case 0:
- return get_rate1 ? get_rate1() : 0;
- case 1:
- return get_rate2 ? get_rate2() : 0;
- case 2:
- return get_rate3 ? get_rate3() : 0;
- case 3:
- return get_rate4 ? get_rate4() : 0;
- }
-
- return 0;
-}
-
-unsigned long imx_get_uartclk(void)
-{
- u32 reg, prediv, podf;
- unsigned long parent_rate;
-
- reg = ccm_readl(MX5_CCM_CSCMR1);
- reg &= MX5_CCM_CSCMR1_UART_CLK_SEL_MASK;
- reg >>= MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
-
- parent_rate = get_rate_select(reg,
- pll1_main_get_rate,
- pll2_sw_get_rate,
- pll3_sw_get_rate,
- lp_apm_get_rate);
-
- reg = ccm_readl(MX5_CCM_CSCDR1);
- prediv = ((reg & MX5_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
- MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
- podf = ((reg & MX5_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
- MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
-
- return parent_rate / (prediv * podf);
-}
-
-unsigned long imx_get_ahbclk(void)
-{
- u32 reg, div;
-
- reg = ccm_readl(MX5_CCM_CBCDR);
- div = ((reg >> 10) & 0x7) + 1;
-
- return pll2_sw_get_rate() / div;
-}
-
-unsigned long imx_get_ipgclk(void)
-{
- u32 reg, div;
-
- reg = ccm_readl(MX5_CCM_CBCDR);
- div = ((reg >> 8) & 0x3) + 1;
-
- return imx_get_ahbclk() / div;
-}
-
-unsigned long imx_get_gptclk(void)
-{
- return imx_get_ipgclk();
-}
-
-unsigned long imx_get_fecclk(void)
-{
- return imx_get_ipgclk();
-}
-
-unsigned long fsl_get_i2cclk(void)
-{
- return imx_get_ipgclk();
-}
-
-unsigned long imx_get_mmcclk(void)
-{
- u32 reg, prediv, podf, rate;
-
- reg = ccm_readl(MX5_CCM_CSCMR1);
- reg &= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK;
- reg >>= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
- rate = get_rate_select(reg,
- pll1_main_get_rate,
- pll2_sw_get_rate,
- pll3_sw_get_rate,
- lp_apm_get_rate);
-
- reg = ccm_readl(MX5_CCM_CSCDR1);
- prediv = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
- MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1;
- podf = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >>
- MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1;
-
- return rate / (prediv * podf);
-}
-
-unsigned long imx_get_usbclk(void)
-{
- u32 reg, prediv, podf, rate;
-
- reg = ccm_readl(MX5_CCM_CSCMR1);
- reg &= MX5_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
- reg >>= MX5_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
- rate = get_rate_select(reg,
- pll1_main_get_rate,
- pll2_sw_get_rate,
- pll3_sw_get_rate,
- lp_apm_get_rate);
-
- reg = ccm_readl(MX5_CCM_CSCDR1);
- prediv = ((reg & MX5_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
- MX5_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
- podf = ((reg & MX5_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
- MX5_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
-
- return rate / (prediv * podf);
-}
-
-unsigned long imx_get_cspiclk(void)
-{
- return 166000000; /* FIXME: bogus value */
-}
-
-/*
- * Set the divider of the CLKO pin. Returns
- * the new divider (which may be smaller
- * than the desired one)
- */
-int imx_clko_set_div(int num, int div)
-{
- u32 ccosr = ccm_readl(MX5_CCM_CCOSR);
-
- div--;
-
- switch (num) {
- case 1:
- div &= 0x7;
- ccosr &= ~(0x7 << 4);
- ccosr |= div << 4;
- ccm_writel(ccosr, MX5_CCM_CCOSR);
- break;
- case 2:
- div &= 0x7;
- ccosr &= ~(0x7 << 21);
- ccosr |= div << 21;
- ccm_writel(ccosr, MX5_CCM_CCOSR);
- break;
- default:
- return -ENODEV;
- }
-
- return div + 1;
-}
-
-/*
- * Set the clock source for the CLKO pin
- */
-void imx_clko_set_src(int num, int src)
-{
- u32 ccosr = ccm_readl(MX5_CCM_CCOSR);
-
- switch (num) {
- case 1:
- if (src < 0) {
- ccosr &= ~(1 << 7);
- break;
- }
- ccosr &= ~0xf;
- ccosr |= src & 0xf;
- ccosr |= 1 << 7;
- break;
- case 2:
- if (src < 0) {
- ccosr &= ~(1 << 24);
- break;
- }
- ccosr &= ~(0x1f << 16);
- ccosr |= (src & 0x1f) << 16;
- ccosr |= 1 << 24;
- break;
- default:
- return;
- }
-
- ccm_writel(ccosr, MX5_CCM_CCOSR);
-}
-
-void imx_dump_clocks(void)
-{
- printf("pll1: %ld\n", pll1_main_get_rate());
- printf("pll2: %ld\n", pll2_sw_get_rate());
- printf("pll3: %ld\n", pll3_sw_get_rate());
- printf("lp_apm: %ld\n", lp_apm_get_rate());
- printf("uart: %ld\n", imx_get_uartclk());
- printf("ipg: %ld\n", imx_get_ipgclk());
- printf("fec: %ld\n", imx_get_fecclk());
- printf("gpt: %ld\n", imx_get_gptclk());
- printf("usb: %ld\n", imx_get_usbclk());
-}
diff --git a/arch/arm/mach-imx/speed-imx53.c b/arch/arm/mach-imx/speed-imx53.c
deleted file mode 100644
index b1ba5fd..0000000
--- a/arch/arm/mach-imx/speed-imx53.c
+++ /dev/null
@@ -1,236 +0,0 @@
-#include <common.h>
-#include <io.h>
-#include <asm-generic/div64.h>
-#include <mach/imx-regs.h>
-#include <mach/clock.h>
-#include "mach/clock-imx51_53.h"
-
-static u32 ccm_readl(u32 ofs)
-{
- return readl(MX53_CCM_BASE_ADDR + ofs);
-}
-
-static unsigned long ckil_get_rate(void)
-{
- return 32768;
-}
-
-static unsigned long osc_get_rate(void)
-{
- return 24000000;
-}
-
-static unsigned long fpm_get_rate(void)
-{
- return ckil_get_rate() * 512;
-}
-
-static unsigned long pll_get_rate(void __iomem *pllbase)
-{
- long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
- unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
- u64 temp;
- unsigned long parent_rate;
-
- dp_ctl = readl(pllbase + MX5_PLL_DP_CTL);
-
- if ((dp_ctl & MX5_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
- parent_rate = fpm_get_rate();
- else
- parent_rate = osc_get_rate();
-
- pll_hfsm = dp_ctl & MX5_PLL_DP_CTL_HFSM;
- dbl = dp_ctl & MX5_PLL_DP_CTL_DPDCK0_2_EN;
-
- if (pll_hfsm == 0) {
- dp_op = readl(pllbase + MX5_PLL_DP_OP);
- dp_mfd = readl(pllbase + MX5_PLL_DP_MFD);
- dp_mfn = readl(pllbase + MX5_PLL_DP_MFN);
- } else {
- dp_op = readl(pllbase + MX5_PLL_DP_HFS_OP);
- dp_mfd = readl(pllbase + MX5_PLL_DP_HFS_MFD);
- dp_mfn = readl(pllbase + MX5_PLL_DP_HFS_MFN);
- }
- pdf = dp_op & MX5_PLL_DP_OP_PDF_MASK;
- mfi = (dp_op & MX5_PLL_DP_OP_MFI_MASK) >> MX5_PLL_DP_OP_MFI_OFFSET;
- mfi = (mfi <= 5) ? 5 : mfi;
- mfd = dp_mfd & MX5_PLL_DP_MFD_MASK;
- mfn = mfn_abs = dp_mfn & MX5_PLL_DP_MFN_MASK;
- /* Sign extend to 32-bits */
- if (mfn >= 0x04000000) {
- mfn |= 0xFC000000;
- mfn_abs = -mfn;
- }
-
- ref_clk = 2 * parent_rate;
- if (dbl != 0)
- ref_clk *= 2;
-
- ref_clk /= (pdf + 1);
- temp = (u64)ref_clk * mfn_abs;
- do_div(temp, mfd + 1);
- if (mfn < 0)
- temp = -temp;
- temp = (ref_clk * mfi) + temp;
-
- return temp;
-}
-
-static unsigned long pll1_main_get_rate(void)
-{
- return pll_get_rate((void __iomem *)MX53_PLL1_BASE_ADDR);
-}
-
-static unsigned long pll2_sw_get_rate(void)
-{
- return pll_get_rate((void __iomem *)MX53_PLL2_BASE_ADDR);
-}
-
-static unsigned long pll3_sw_get_rate(void)
-{
- return pll_get_rate((void __iomem *)MX53_PLL3_BASE_ADDR);
-}
-
-static unsigned long pll4_sw_get_rate(void)
-{
- return pll_get_rate((void __iomem *)MX53_PLL4_BASE_ADDR);
-}
-
-static unsigned long get_rate_select(int select,
- unsigned long (* get_rate1)(void),
- unsigned long (* get_rate2)(void),
- unsigned long (* get_rate3)(void),
- unsigned long (* get_rate4)(void))
-{
- switch (select) {
- case 0:
- return get_rate1 ? get_rate1() : 0;
- case 1:
- return get_rate2 ? get_rate2() : 0;
- case 2:
- return get_rate3 ? get_rate3() : 0;
- case 3:
- return get_rate4 ? get_rate4() : 0;
- }
-
- return 0;
-}
-
-unsigned long imx_get_uartclk(void)
-{
- u32 reg, prediv, podf;
- unsigned long parent_rate;
-
- reg = ccm_readl(MX5_CCM_CSCMR1);
- reg &= MX5_CCM_CSCMR1_UART_CLK_SEL_MASK;
- reg >>= MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
-
- parent_rate = get_rate_select(reg,
- pll1_main_get_rate,
- pll2_sw_get_rate,
- pll3_sw_get_rate,
- pll4_sw_get_rate);
-
- reg = ccm_readl(MX5_CCM_CSCDR1);
- prediv = ((reg & MX5_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
- MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
- podf = ((reg & MX5_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
- MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
-
- return parent_rate / (prediv * podf);
-}
-
-unsigned long imx_get_ahbclk(void)
-{
- u32 reg, div;
-
- reg = ccm_readl(MX5_CCM_CBCDR);
- div = ((reg >> 10) & 0x7) + 1;
-
- return pll2_sw_get_rate() / div;
-}
-
-unsigned long imx_get_ipgclk(void)
-{
- u32 reg, div;
-
- reg = ccm_readl(MX5_CCM_CBCDR);
- div = ((reg >> 8) & 0x3) + 1;
-
- return imx_get_ahbclk() / div;
-}
-
-unsigned long imx_get_gptclk(void)
-{
- return imx_get_ipgclk();
-}
-
-unsigned long imx_get_fecclk(void)
-{
- return imx_get_ipgclk();
-}
-
-static unsigned long imx_get_ipg_perclk(void)
-{
- u32 reg;
-
- reg = ccm_readl(MX5_CCM_CBCDR);
- if (!(reg & MX5_CCM_CBCDR_PERIPH_CLK_SEL))
- return pll2_sw_get_rate();
- reg = ccm_readl(MX5_CCM_CBCMR);
- switch ((reg & MX5_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
- MX5_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
- case 0:
- return pll1_main_get_rate();
- case 1:
- return pll3_sw_get_rate();
- /* case 2:
- TODO : LP_APM */
- }
- return 0;
-}
-
-unsigned long fsl_get_i2cclk(void)
-{
- return imx_get_ipg_perclk();
-}
-
-unsigned long imx_get_mmcclk(void)
-{
- u32 reg, prediv, podf, rate;
-
- reg = ccm_readl(MX5_CCM_CSCMR1);
- reg &= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK;
- reg >>= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
- rate = get_rate_select(reg,
- pll1_main_get_rate,
- pll2_sw_get_rate,
- pll3_sw_get_rate,
- pll4_sw_get_rate);
-
- reg = ccm_readl(MX5_CCM_CSCDR1);
- prediv = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
- MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1;
- podf = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >>
- MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1;
-
- return rate / (prediv * podf);
-}
-
-unsigned long imx_get_cspiclk(void)
-{
- return 166000000; /* FIXME: bogus value */
-}
-
-void imx_dump_clocks(void)
-{
- printf("pll1: %ld\n", pll1_main_get_rate());
- printf("pll2: %ld\n", pll2_sw_get_rate());
- printf("pll3: %ld\n", pll3_sw_get_rate());
- printf("pll4: %ld\n", pll4_sw_get_rate());
- printf("uart: %ld\n", imx_get_uartclk());
- printf("ipg: %ld\n", imx_get_ipgclk());
- printf("fec: %ld\n", imx_get_fecclk());
- printf("gpt: %ld\n", imx_get_gptclk());
- printf("i2c: %ld\n", fsl_get_i2cclk());
-}
diff --git a/arch/arm/mach-imx/speed-imx6.c b/arch/arm/mach-imx/speed-imx6.c
deleted file mode 100644
index 645b2c9..0000000
--- a/arch/arm/mach-imx/speed-imx6.c
+++ /dev/null
@@ -1,404 +0,0 @@
-#include <common.h>
-#include <asm/io.h>
-#include <asm-generic/div64.h>
-#include <mach/imx-regs.h>
-#include <mach/clock-imx6.h>
-#include <mach/imx6-anadig.h>
-
-enum pll_clocks {
- CPU_PLL1, /* System PLL */
- BUS_PLL2, /* System Bus PLL*/
- USBOTG_PLL3, /* OTG USB PLL */
- AUD_PLL4, /* Audio PLL */
- VID_PLL5, /* Video PLL */
- MLB_PLL6, /* MLB PLL */
- USBHOST_PLL7, /* Host USB PLL */
- ENET_PLL8, /* ENET PLL */
-};
-
-#define SZ_DEC_1M 1000000
-
-/* Out-of-reset PFDs and clock source definitions */
-#define PLL2_PFD0_FREQ 352000000
-#define PLL2_PFD1_FREQ 594000000
-#define PLL2_PFD2_FREQ 400000000
-#define PLL2_PFD2_DIV_FREQ 200000000
-#define PLL3_PFD0_FREQ 720000000
-#define PLL3_PFD1_FREQ 540000000
-#define PLL3_PFD2_FREQ 508200000
-#define PLL3_PFD3_FREQ 454700000
-#define PLL3_80M 80000000
-#define PLL3_60M 60000000
-
-#define AHB_CLK_ROOT 132000000
-#define IPG_CLK_ROOT 66000000
-#define ENET_FREQ_0 25000000
-#define ENET_FREQ_1 50000000
-#define ENET_FREQ_2 100000000
-#define ENET_FREQ_3 125000000
-
-#define CONFIG_MX6_HCLK_FREQ 24000000
-
-static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
-{
- u32 div;
-
- switch (pll) {
- case CPU_PLL1:
- div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_PLL_SYS) &
- BM_ANADIG_PLL_SYS_DIV_SELECT;
- return infreq * (div >> 1);
- case BUS_PLL2:
- div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_PLL_528) &
- BM_ANADIG_PLL_528_DIV_SELECT;
- return infreq * (20 + (div << 1));
- case USBOTG_PLL3:
- div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_USB2_PLL_480_CTRL) &
- BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT;
- return infreq * (20 + (div << 1));
- case ENET_PLL8:
- div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_PLL_ENET) &
- BM_ANADIG_PLL_ENET_DIV_SELECT;
- switch (div) {
- default:
- case 0:
- return ENET_FREQ_0;
- case 1:
- return ENET_FREQ_1;
- case 2:
- return ENET_FREQ_2;
- case 3:
- return ENET_FREQ_3;
- }
- case AUD_PLL4:
- case VID_PLL5:
- case MLB_PLL6:
- case USBHOST_PLL7:
- default:
- return 0;
- }
-}
-
-static u32 __get_mcu_main_clk(void)
-{
- u32 reg, freq;
- reg = (__REG(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
- MXC_CCM_CACRR_ARM_PODF_OFFSET;
- freq = __decode_pll(CPU_PLL1, CONFIG_MX6_HCLK_FREQ);
- return freq / (reg + 1);
-}
-
-static u32 __get_periph_clk(void)
-{
- u32 reg;
- reg = __REG(MXC_CCM_CBCDR);
- if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
- reg = __REG(MXC_CCM_CBCMR);
- switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK) >>
- MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET) {
- case 0:
- return __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ);
- case 1:
- case 2:
- return CONFIG_MX6_HCLK_FREQ;
- default:
- return 0;
- }
- } else {
- reg = __REG(MXC_CCM_CBCMR);
- switch ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) >>
- MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET) {
- default:
- case 0:
- return __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ);
- case 1:
- return PLL2_PFD2_FREQ;
- case 2:
- return PLL2_PFD0_FREQ;
- case 3:
- return PLL2_PFD2_DIV_FREQ;
- }
- }
-}
-
-static u32 __get_ipg_clk(void)
-{
- u32 ahb_podf, ipg_podf;
-
- ahb_podf = __REG(MXC_CCM_CBCDR);
- ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
- MXC_CCM_CBCDR_IPG_PODF_OFFSET;
- ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
- MXC_CCM_CBCDR_AHB_PODF_OFFSET;
- return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
-}
-
-u32 imx_get_gptclk(void)
-{
- return __get_ipg_clk();
-}
-
-static u32 __get_ipg_per_clk(void)
-{
- u32 podf;
- u32 clk_root = __get_ipg_clk();
-
- podf = __REG(MXC_CCM_CSCMR1) & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
- return clk_root / (podf + 1);
-}
-
-u32 imx_get_uartclk(void)
-{
- u32 freq = PLL3_80M, reg, podf;
-
- reg = __REG(MXC_CCM_CSCDR1);
- podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
- MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
- freq /= (podf + 1);
-
- return freq;
-}
-
-static u32 __get_cspi_clk(void)
-{
- u32 freq = PLL3_60M, reg, podf;
-
- reg = __REG(MXC_CCM_CSCDR2);
- podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
- MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
- freq /= (podf + 1);
-
- return freq;
-}
-
-static u32 __get_axi_clk(void)
-{
- u32 clkroot;
- u32 cbcdr = __REG(MXC_CCM_CBCDR);
- u32 podf = (cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK) >>
- MXC_CCM_CBCDR_AXI_PODF_OFFSET;
-
- if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
- if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
- clkroot = PLL2_PFD2_FREQ;
- else
- clkroot = PLL3_PFD1_FREQ;;
- } else
- clkroot = __get_periph_clk();
-
- return clkroot / (podf + 1);
-}
-
-static u32 __get_ahb_clk(void)
-{
- u32 cbcdr = __REG(MXC_CCM_CBCDR);
- u32 podf = (cbcdr & MXC_CCM_CBCDR_AHB_PODF_MASK) \
- >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
-
- return __get_periph_clk() / (podf + 1);
-}
-
-static u32 __get_emi_slow_clk(void)
-{
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 emi_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK) >>
- MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
- u32 podf = (cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >>
- MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
-
- switch (emi_clk_sel) {
- default:
- case 0:
- return __get_axi_clk() / (podf + 1);
- case 1:
- return __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ) /
- (podf + 1);
- case 2:
- return PLL2_PFD2_FREQ / (podf + 1);
- case 3:
- return PLL2_PFD0_FREQ / (podf + 1);
- }
-}
-
-static u32 __get_nfc_clk(void)
-{
- u32 clkroot;
- u32 cs2cdr = __REG(MXC_CCM_CS2CDR);
- u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) \
- >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
- u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) \
- >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
-
- switch ((cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
- MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET) {
- default:
- case 0:
- clkroot = PLL2_PFD0_FREQ;
- break;
- case 1:
- clkroot = __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ);
- break;
- case 2:
- clkroot = __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ);
- break;
- case 3:
- clkroot = PLL2_PFD2_FREQ;
- break;
- }
-
- return clkroot / (pred+1) / (podf+1);
-}
-
-static u32 __get_ddr_clk(void)
-{
- u32 cbcdr = __REG(MXC_CCM_CBCDR);
- u32 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
- MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
-
- return __get_periph_clk() / (podf + 1);
-}
-
-static u32 __get_usdhc1_clk(void)
-{
- u32 clkroot;
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
- u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
- MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
-
- if (cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL)
- clkroot = PLL2_PFD0_FREQ;
- else
- clkroot = PLL2_PFD2_FREQ;
-
- return clkroot / (podf + 1);
-}
-
-static u32 __get_usdhc2_clk(void)
-{
- u32 clkroot;
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
- u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
- MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
-
- if (cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL)
- clkroot = PLL2_PFD0_FREQ;
- else
- clkroot = PLL2_PFD2_FREQ;
-
- return clkroot / (podf + 1);
-}
-
-static u32 __get_usdhc3_clk(void)
-{
- u32 clkroot;
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
- u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
- MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
-
- if (cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL)
- clkroot = PLL2_PFD0_FREQ;
- else
- clkroot = PLL2_PFD2_FREQ;
-
- return clkroot / (podf + 1);
-}
-
-static u32 __get_usdhc4_clk(void)
-{
- u32 clkroot;
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
- u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
- MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
-
- if (cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL)
- clkroot = PLL2_PFD0_FREQ;
- else
- clkroot = PLL2_PFD2_FREQ;
-
- return clkroot / (podf + 1);
-}
-
-u32 imx_get_mmcclk(void)
-{
- return __get_usdhc3_clk();
-}
-
-u32 imx_get_fecclk(void)
-{
- return __get_ipg_clk();
-}
-
-u32 imx_get_i2cclk(void)
-{
- return __get_ipg_per_clk();
-}
-
-u32 imx_get_cspiclk(void)
-{
- return __get_cspi_clk();
-}
-
-void imx_dump_clocks(void)
-{
- u32 freq;
-
- freq = __decode_pll(CPU_PLL1, CONFIG_MX6_HCLK_FREQ);
- printf("mx6q pll1: %d\n", freq);
- freq = __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ);
- printf("mx6q pll2: %d\n", freq);
- freq = __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ);
- printf("mx6q pll3: %d\n", freq);
- freq = __decode_pll(ENET_PLL8, CONFIG_MX6_HCLK_FREQ);
- printf("mx6q pll8: %d\n", freq);
- printf("mcu main: %d\n", __get_mcu_main_clk());
- printf("periph: %d\n", __get_periph_clk());
- printf("i2c: %d\n", __get_ipg_per_clk());
- printf("ipg: %d\n", __get_ipg_clk());
- printf("ipg per: %d\n", __get_ipg_per_clk());
- printf("cspi: %d\n", __get_cspi_clk());
- printf("axi: %d\n", __get_axi_clk());
- printf("ahb: %d\n", __get_ahb_clk());
- printf("emi slow: %d\n", __get_emi_slow_clk());
- printf("nfc: %d\n", __get_nfc_clk());
- printf("ddr: %d\n", __get_ddr_clk());
- printf("usdhc1: %d\n", __get_usdhc1_clk());
- printf("usdhc2: %d\n", __get_usdhc2_clk());
- printf("usdhc3: %d\n", __get_usdhc3_clk());
- printf("usdhc4: %d\n", __get_usdhc4_clk());
-}
-
-void imx6_ipu_clk_enable(int di)
-{
- u32 reg;
-
- if (di == 1) {
- reg = readl(MXC_CCM_CCGR3);
- reg |= 0xC033;
- writel(reg, MXC_CCM_CCGR3);
- } else {
- reg = readl(MXC_CCM_CCGR3);
- reg |= 0x300F;
- writel(reg, MXC_CCM_CCGR3);
- }
-
- reg = readl(MX6_ANATOP_BASE_ADDR + 0xF0);
- reg &= ~0x00003F00;
- reg |= 0x00001300;
- writel(reg, MX6_ANATOP_BASE_ADDR + 0xF4);
-
- reg = readl(MXC_CCM_CS2CDR);
- reg &= ~0x00007E00;
- reg |= 0x00001200;
- writel(reg, MXC_CCM_CS2CDR);
-
- reg = readl(MXC_CCM_CSCMR2);
- reg |= 0x00000C00;
- writel(reg, MXC_CCM_CSCMR2);
-
- reg = 0x0002A953;
- writel(reg, MXC_CCM_CHSCDR);
-}
diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c
deleted file mode 100644
index c86ad71..0000000
--- a/arch/arm/mach-imx/speed.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- *
- * (c) 2004 Sascha Hauer <sascha@saschahauer.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <asm-generic/div64.h>
-#include <common.h>
-#include <command.h>
-#include <complete.h>
-#include <mach/clock.h>
-
-/*
- * get the system pll clock in Hz
- *
- * mfi + mfn / (mfd +1)
- * f = 2 * f_ref * --------------------
- * pd + 1
- */
-unsigned int imx_decode_pll(unsigned int reg_val, unsigned int freq)
-{
- unsigned long long ll;
- int mfn_abs;
- unsigned int mfi, mfn, mfd, pd;
-
- mfi = (reg_val >> 10) & 0xf;
- mfn = reg_val & 0x3ff;
- mfd = (reg_val >> 16) & 0x3ff;
- pd = (reg_val >> 26) & 0xf;
-
- mfi = mfi <= 5 ? 5 : mfi;
-
- mfn_abs = mfn;
-
-#if !defined CONFIG_ARCH_MX1 && !defined CONFIG_ARCH_MX21
- if (mfn >= 0x200) {
- mfn |= 0xFFFFFE00;
- mfn_abs = -mfn;
- }
-#endif
-
- freq *= 2;
- freq /= pd + 1;
-
- ll = (unsigned long long)freq * mfn_abs;
-
- do_div(ll, mfd + 1);
- if (mfn < 0)
- ll = -ll;
- ll = (freq * mfi) + ll;
-
- return ll;
-}
-
-extern void imx_dump_clocks(void);
-
-static int do_clocks(int argc, char *argv[])
-{
- imx_dump_clocks();
-
- return 0;
-}
-
-BAREBOX_CMD_START(dump_clocks)
- .cmd = do_clocks,
- .usage = "show clock frequencies",
- BAREBOX_CMD_COMPLETE(empty_complete)
-BAREBOX_CMD_END
-
diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index 94ed807..7fed935 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -31,7 +31,6 @@
#include <linux/clk.h>
#include <linux/err.h>
#include <asm/mmu.h>
-#include <mach/clock.h>
#include <mach/generic.h>
#include <mach/esdhc.h>
#include <gpio.h>
diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c
index e0e5b01..a58d820 100644
--- a/drivers/serial/serial_imx.c
+++ b/drivers/serial/serial_imx.c
@@ -16,7 +16,6 @@
#include <common.h>
#include <mach/imx-regs.h>
-#include <mach/clock.h>
#include <driver.h>
#include <init.h>
#include <malloc.h>
diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c
index 14d2b28..ca7ba01 100644
--- a/drivers/spi/imx_spi.c
+++ b/drivers/spi/imx_spi.c
@@ -24,7 +24,6 @@
#include <gpio.h>
#include <mach/spi.h>
#include <mach/generic.h>
-#include <mach/clock.h>
#include <linux/clk.h>
#include <linux/err.h>
diff --git a/drivers/video/imx.c b/drivers/video/imx.c
index 810d8e3..7ddc2f1 100644
--- a/drivers/video/imx.c
+++ b/drivers/video/imx.c
@@ -26,7 +26,6 @@
#include <linux/err.h>
#include <mach/imx-regs.h>
#include <asm-generic/div64.h>
-#include <mach/clock.h>
#define LCDC_SSA 0x00
--
1.7.10.4
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