* [PATCH 1/8] ARM i.MX27: Use standard IMX_CHIP_REV_* defines
2012-10-05 10:53 [PATCH] i.MX SoC work Sascha Hauer
@ 2012-10-05 10:53 ` Sascha Hauer
2012-10-05 10:53 ` [PATCH 2/8] ARM i.MX: streamline imx_silicon_revision Sascha Hauer
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2012-10-05 10:53 UTC (permalink / raw)
To: barebox
We have IMX_CHIP_REV_* defines which are used for most i.MX SoCs.
Use them for i.MX27 aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/clk-imx27.c | 4 ++--
arch/arm/mach-imx/imx27.c | 15 ++++++++++++++-
arch/arm/mach-imx/include/mach/generic.h | 2 --
arch/arm/mach-imx/include/mach/imx-regs.h | 1 +
4 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index abfde0f..74d70db 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -92,7 +92,7 @@ static int imx27_ccm_probe(struct device_d *dev)
clks[spll] = imx_clk_pllv1("spll", "ckih", base + CCM_SPCTL0);
clks[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
- if (imx_silicon_revision() >= IMX27_CHIP_REVISION_2_0) {
+ if (imx_silicon_revision() >= IMX_CHIP_REV_2_0) {
clks[ahb] = imx_clk_divider("ahb", "mpll_main2", base + CCM_CSCR, 8, 2);
clks[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
} else {
@@ -110,7 +110,7 @@ static int imx27_ccm_probe(struct device_d *dev)
ARRAY_SIZE(cpu_sel_clks));
clks[clko_sel] = imx_clk_mux("clko_sel", base + CCM_CCSR, 0, 5, clko_sel_clks,
ARRAY_SIZE(clko_sel_clks));
- if (imx_silicon_revision() >= IMX27_CHIP_REVISION_2_0)
+ if (imx_silicon_revision() >= IMX_CHIP_REV_2_0)
clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 12, 2);
else
clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 13, 3);
diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c
index 8116e6f..cd429d0 100644
--- a/arch/arm/mach-imx/imx27.c
+++ b/arch/arm/mach-imx/imx27.c
@@ -20,7 +20,20 @@
int imx_silicon_revision(void)
{
- return CID >> 28;
+ uint32_t val;
+
+ val = readl(MX27_SYSCTRL_BASE_ADDR);
+
+ switch (val >> 28) {
+ case 0:
+ return IMX_CHIP_REV_1_0;
+ case 1:
+ return IMX_CHIP_REV_2_0;
+ case 2:
+ return IMX_CHIP_REV_2_1;
+ default:
+ return IMX_CHIP_REV_UNKNOWN;
+ }
}
void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index 99f3012..018ea91 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -1,7 +1,5 @@
int imx_silicon_revision(void);
-#define IMX27_CHIP_REVISION_1_0 0
-#define IMX27_CHIP_REVISION_2_0 1
u64 imx_uid(void);
diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h
index 235bac3..2b836c9 100644
--- a/arch/arm/mach-imx/include/mach/imx-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx-regs.h
@@ -115,5 +115,6 @@
#define IMX_CHIP_REV_3_0 0x30
#define IMX_CHIP_REV_3_1 0x31
#define IMX_CHIP_REV_3_2 0x32
+#define IMX_CHIP_REV_UNKNOWN 0xff
#endif /* _IMX_REGS_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 2/8] ARM i.MX: streamline imx_silicon_revision
2012-10-05 10:53 [PATCH] i.MX SoC work Sascha Hauer
2012-10-05 10:53 ` [PATCH 1/8] ARM i.MX27: Use standard IMX_CHIP_REV_* defines Sascha Hauer
@ 2012-10-05 10:53 ` Sascha Hauer
2012-10-05 10:53 ` [PATCH 3/8] ARM i.MX1: move iomux definitions to separate header file Sascha Hauer
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2012-10-05 10:53 UTC (permalink / raw)
To: barebox
All i.MX SoCs now use the same imx_silicon_revision() function to get
the revision. Add a separate header file for it and a common function
used on all SoCs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/ccxmx51/ccxmx51.c | 1 +
arch/arm/boards/freescale-mx35-3-stack/3stack.c | 1 +
arch/arm/boards/freescale-mx51-pdk/board.c | 1 +
arch/arm/boards/freescale-mx53-loco/board.c | 1 +
arch/arm/mach-imx/Makefile | 2 +-
arch/arm/mach-imx/clk-imx27.c | 1 +
arch/arm/mach-imx/imx.c | 27 +++++++++++++++++++++++
arch/arm/mach-imx/imx21.c | 8 -------
arch/arm/mach-imx/imx27.c | 24 +++++++++++++++-----
arch/arm/mach-imx/imx35.c | 7 ++++--
arch/arm/mach-imx/imx51.c | 15 ++++++-------
arch/arm/mach-imx/imx53.c | 15 ++++++-------
arch/arm/mach-imx/include/mach/generic.h | 2 --
arch/arm/mach-imx/include/mach/imx-regs.h | 14 ------------
arch/arm/mach-imx/include/mach/revision.h | 22 ++++++++++++++++++
15 files changed, 92 insertions(+), 49 deletions(-)
create mode 100644 arch/arm/mach-imx/imx.c
create mode 100644 arch/arm/mach-imx/include/mach/revision.h
diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c
index 0b450d6..b391df1 100644
--- a/arch/arm/boards/ccxmx51/ccxmx51.c
+++ b/arch/arm/boards/ccxmx51/ccxmx51.c
@@ -45,6 +45,7 @@
#include <mach/iim.h>
#include <mach/clock-imx51_53.h>
#include <mach/imx5.h>
+#include <mach/revision.h>
#include "ccxmx51.h"
diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
index 9a01424..1a5bf5b 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
@@ -47,6 +47,7 @@
#include <mach/imx-ipu-fb.h>
#include <mach/generic.h>
#include <mach/devices-imx35.h>
+#include <mach/revision.h>
#include <i2c/i2c.h>
#include <mfd/mc13xxx.h>
diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c
index 3a8e5ea..61e635a 100644
--- a/arch/arm/boards/freescale-mx51-pdk/board.c
+++ b/arch/arm/boards/freescale-mx51-pdk/board.c
@@ -37,6 +37,7 @@
#include <mach/generic.h>
#include <mach/iomux-mx51.h>
#include <mach/devices-imx51.h>
+#include <mach/revision.h>
#include <mach/iim.h>
static struct fec_platform_data fec_info = {
diff --git a/arch/arm/boards/freescale-mx53-loco/board.c b/arch/arm/boards/freescale-mx53-loco/board.c
index 0d71555..8e9b030 100644
--- a/arch/arm/boards/freescale-mx53-loco/board.c
+++ b/arch/arm/boards/freescale-mx53-loco/board.c
@@ -35,6 +35,7 @@
#include <mach/imx-nand.h>
#include <mach/iim.h>
#include <mach/imx5.h>
+#include <mach/revision.h>
#include <i2c/i2c.h>
#include <mfd/mc34708.h>
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index e43f92e..54703f3 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -14,5 +14,5 @@ obj-$(CONFIG_NAND_IMX) += nand.o
obj-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o
pbl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o
obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-pfd.o
-obj-y += devices.o
+obj-y += devices.o imx.o
obj-y += boot.o
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 74d70db..e406228 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -7,6 +7,7 @@
#include <linux/err.h>
#include <mach/imx27-regs.h>
#include <mach/generic.h>
+#include <mach/revision.h>
#include "clk.h"
diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
new file mode 100644
index 0000000..1bc6e23
--- /dev/null
+++ b/arch/arm/mach-imx/imx.c
@@ -0,0 +1,27 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <mach/revision.h>
+
+static int __imx_silicon_revision = IMX_CHIP_REV_UNKNOWN;
+
+int imx_silicon_revision(void)
+{
+ return __imx_silicon_revision;
+}
+
+void imx_set_silicon_revision(int revision)
+{
+ __imx_silicon_revision = revision;
+}
diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c
index 7ed0809..58895da 100644
--- a/arch/arm/mach-imx/imx21.c
+++ b/arch/arm/mach-imx/imx21.c
@@ -23,14 +23,6 @@ void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower)
writel(lower, MX21_EIM_BASE_ADDR + 4 + cs * 8);
}
-int imx_silicon_revision(void)
-{
- // Known values:
- // 0x101D101D : mask set ID 0M55B
- // 0x201D101D : mask set ID 1M55B or M55B
- return CID;
-}
-
static int imx21_init(void)
{
add_generic_device("imx21-ccm", 0, NULL, MX21_CCM_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c
index cd429d0..3d7b21d 100644
--- a/arch/arm/mach-imx/imx27.c
+++ b/arch/arm/mach-imx/imx27.c
@@ -12,28 +12,38 @@
*/
#include <common.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/weim.h>
#include <sizes.h>
+#include <mach/revision.h>
#include <init.h>
#include <io.h>
-int imx_silicon_revision(void)
+static int imx27_silicon_revision(void)
{
uint32_t val;
+ int rev;
val = readl(MX27_SYSCTRL_BASE_ADDR);
switch (val >> 28) {
case 0:
- return IMX_CHIP_REV_1_0;
+ rev = IMX_CHIP_REV_1_0;
+ break;
case 1:
- return IMX_CHIP_REV_2_0;
+ rev = IMX_CHIP_REV_2_0;
+ break;
case 2:
- return IMX_CHIP_REV_2_1;
+ rev = IMX_CHIP_REV_2_1;
+ break;
default:
- return IMX_CHIP_REV_UNKNOWN;
+ rev = IMX_CHIP_REV_UNKNOWN;
+ break;
}
+
+ imx_set_silicon_revision(rev);
+
+ return 0;
}
void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
@@ -86,6 +96,8 @@ static void imx27_init_max(void)
static int imx27_init(void)
{
+ imx27_silicon_revision();
+
add_generic_device("imx_iim", 0, NULL, MX27_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index 722dd4c..1575d54 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -18,6 +18,7 @@
#include <mach/weim.h>
#include <mach/imx-regs.h>
#include <mach/iim.h>
+#include <mach/revision.h>
#include <mach/generic.h>
void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
@@ -28,14 +29,14 @@ void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
writel(additional, MX35_WEIM_BASE_ADDR + (cs * 0x10) + 0x8);
}
-int imx_silicon_revision()
+static void imx35_silicon_revision(void)
{
uint32_t reg;
reg = readl(MX35_IIM_BASE_ADDR + IIM_SREV);
/* 0×00 = TO 1.0, First silicon */
reg += IMX_CHIP_REV_1_0;
- return (reg & 0xFF);
+ imx_set_silicon_revision(reg & 0xFF);
}
/*
@@ -58,6 +59,8 @@ core_initcall(imx35_l2_fix);
static int imx35_init(void)
{
+ imx35_silicon_revision();
+
add_generic_device("imx_iim", 0, NULL, MX35_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index 8709c43..3850001 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -18,21 +18,17 @@
#include <io.h>
#include <mach/imx5.h>
#include <mach/imx-regs.h>
+#include <mach/revision.h>
#include <mach/clock-imx51_53.h>
#define SI_REV 0x48
-static u32 mx51_silicon_revision;
static char *mx51_rev_string = "unknown";
-int imx_silicon_revision(void)
-{
- return mx51_silicon_revision;
-}
-
-static int query_silicon_revision(void)
+static int imx51_silicon_revision(void)
{
void __iomem *rom = MX51_IROM_BASE_ADDR;
+ u32 mx51_silicon_revision;
u32 rev;
rev = readl(rom + SI_REV);
@@ -57,9 +53,10 @@ static int query_silicon_revision(void)
mx51_silicon_revision = 0;
}
+ imx_set_silicon_revision(mx51_silicon_revision);
+
return 0;
}
-core_initcall(query_silicon_revision);
static int imx51_print_silicon_rev(void)
{
@@ -71,6 +68,8 @@ device_initcall(imx51_print_silicon_rev);
static int imx51_init(void)
{
+ imx51_silicon_revision();
+
add_generic_device("imx_iim", 0, NULL, MX51_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c
index 88b4274..4aa3f61 100644
--- a/arch/arm/mach-imx/imx53.c
+++ b/arch/arm/mach-imx/imx53.c
@@ -18,22 +18,18 @@
#include <sizes.h>
#include <mach/imx5.h>
#include <mach/imx-regs.h>
+#include <mach/revision.h>
#include <mach/clock-imx51_53.h>
#define SI_REV 0x48
-static u32 mx53_silicon_revision;
static char *mx53_rev_string = "unknown";
-int imx_silicon_revision(void)
-{
- return mx53_silicon_revision;
-}
-
-static int query_silicon_revision(void)
+static int imx53_silicon_revision(void)
{
void __iomem *rom = MX53_IROM_BASE_ADDR;
u32 rev;
+ u32 mx53_silicon_revision;
rev = readl(rom + SI_REV);
switch (rev) {
@@ -53,9 +49,10 @@ static int query_silicon_revision(void)
mx53_silicon_revision = 0;
}
+ imx_set_silicon_revision(mx53_silicon_revision);
+
return 0;
}
-core_initcall(query_silicon_revision);
static int imx53_print_silicon_rev(void)
{
@@ -67,6 +64,8 @@ device_initcall(imx53_print_silicon_rev);
static int imx53_init(void)
{
+ imx53_silicon_revision();
+
add_generic_device("imx_iim", 0, NULL, MX53_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index 018ea91..691a146 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -1,6 +1,4 @@
-int imx_silicon_revision(void);
-
u64 imx_uid(void);
diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h
index 2b836c9..08ee957 100644
--- a/arch/arm/mach-imx/include/mach/imx-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx-regs.h
@@ -103,18 +103,4 @@
#define GPIO_GIUS (1<<16)
-/* silicon revisions */
-#define IMX_CHIP_REV_1_0 0x10
-#define IMX_CHIP_REV_1_1 0x11
-#define IMX_CHIP_REV_1_2 0x12
-#define IMX_CHIP_REV_1_3 0x13
-#define IMX_CHIP_REV_2_0 0x20
-#define IMX_CHIP_REV_2_1 0x21
-#define IMX_CHIP_REV_2_2 0x22
-#define IMX_CHIP_REV_2_3 0x23
-#define IMX_CHIP_REV_3_0 0x30
-#define IMX_CHIP_REV_3_1 0x31
-#define IMX_CHIP_REV_3_2 0x32
-#define IMX_CHIP_REV_UNKNOWN 0xff
-
#endif /* _IMX_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/revision.h b/arch/arm/mach-imx/include/mach/revision.h
new file mode 100644
index 0000000..b6b06ef
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/revision.h
@@ -0,0 +1,22 @@
+#ifndef __MACH_REVISION_H__
+#define __MACH_REVISION_H__
+
+/* silicon revisions */
+#define IMX_CHIP_REV_1_0 0x10
+#define IMX_CHIP_REV_1_1 0x11
+#define IMX_CHIP_REV_1_2 0x12
+#define IMX_CHIP_REV_1_3 0x13
+#define IMX_CHIP_REV_2_0 0x20
+#define IMX_CHIP_REV_2_1 0x21
+#define IMX_CHIP_REV_2_2 0x22
+#define IMX_CHIP_REV_2_3 0x23
+#define IMX_CHIP_REV_3_0 0x30
+#define IMX_CHIP_REV_3_1 0x31
+#define IMX_CHIP_REV_3_2 0x32
+#define IMX_CHIP_REV_UNKNOWN 0xff
+
+int imx_silicon_revision(void);
+
+void imx_set_silicon_revision(int revision);
+
+#endif /* __MACH_REVISION_H__ */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 3/8] ARM i.MX1: move iomux definitions to separate header file
2012-10-05 10:53 [PATCH] i.MX SoC work Sascha Hauer
2012-10-05 10:53 ` [PATCH 1/8] ARM i.MX27: Use standard IMX_CHIP_REV_* defines Sascha Hauer
2012-10-05 10:53 ` [PATCH 2/8] ARM i.MX: streamline imx_silicon_revision Sascha Hauer
@ 2012-10-05 10:53 ` Sascha Hauer
2012-10-05 10:53 ` [PATCH 4/8] ARM i.MX boards: Use IMX_GPIO_NR Sascha Hauer
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2012-10-05 10:53 UTC (permalink / raw)
To: barebox
Just like we have a separate file for the other i.MX SoCs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/scb9328/scb9328.c | 1 +
arch/arm/mach-imx/include/mach/imx1-regs.h | 130 ---------------------------
arch/arm/mach-imx/include/mach/iomux-mx1.h | 133 ++++++++++++++++++++++++++++
3 files changed, 134 insertions(+), 130 deletions(-)
create mode 100644 arch/arm/mach-imx/include/mach/iomux-mx1.h
diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c
index c83132a..1a85554 100644
--- a/arch/arm/boards/scb9328/scb9328.c
+++ b/arch/arm/boards/scb9328/scb9328.c
@@ -29,6 +29,7 @@
#include <fcntl.h>
#include <dm9000.h>
#include <led.h>
+#include <mach/iomux-mx1.h>
#include <mach/devices-imx1.h>
static struct dm9000_platform_data dm9000_data = {
diff --git a/arch/arm/mach-imx/include/mach/imx1-regs.h b/arch/arm/mach-imx/include/mach/imx1-regs.h
index cb60c84..a4d1690 100644
--- a/arch/arm/mach-imx/include/mach/imx1-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx1-regs.h
@@ -86,134 +86,4 @@
#define CSCR_MPLL_RESTART (1<<21)
-/* assignements for GPIO alternate/primary functions */
-
-/* FIXME: This list is not completed. The correct directions are
- * missing on some (many) pins
- */
-#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 )
-#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
-#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
-#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
-#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
-#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
-#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
-#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
-#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
-#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
-#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
-#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
-#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
-#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
-#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
-#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
-#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
-#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
-#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
-#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
-#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
-#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 )
-#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
-#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
-#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
-#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
-#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
-#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
-#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
-#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
-#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
-#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
-#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
-#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
-#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
-#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
-#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
-#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
-#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
-#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
-#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
-#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
-#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
-#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
-#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
-#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
-#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
-#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
-#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
-#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
-#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 )
-#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
-#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 )
-#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
-#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 )
-#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
-#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
-#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
-#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
-#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
-#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
-#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
-#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
-#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
-#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
-#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
-#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
-#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
-#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
-#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
-#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
-#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
-#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
-#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
-#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
-#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
-#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
-#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
-#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
-#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
-#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
-#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
-#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
-#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
-#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
-#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
-#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
-#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
-#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
-#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
-#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
-#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
-#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 )
-#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
-#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
-#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 )
-#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
-#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
-#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
-#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
-#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
-#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
-#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
-#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
-#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
-#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
-#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
-#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
-#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
-#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
-#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
-#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
-#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
-#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
-#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
-#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
-#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
-#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
-#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
-#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
-#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
-#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
-#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
-#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 )
-
#endif /* _IMX1_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx1.h b/arch/arm/mach-imx/include/mach/iomux-mx1.h
new file mode 100644
index 0000000..11e48b1
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/iomux-mx1.h
@@ -0,0 +1,133 @@
+#ifndef __MACH_IOMUX_MX1_H
+#define __MACH_IOMUX_MX1_H
+
+/*
+ * FIXME: This list is not completed. The correct directions are
+ * missing on some (many) pins
+ */
+#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 )
+#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
+#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
+#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
+#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
+#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
+#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
+#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
+#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
+#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
+#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
+#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
+#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
+#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
+#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
+#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
+#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
+#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
+#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
+#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
+#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
+#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 )
+#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
+#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
+#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
+#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
+#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
+#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
+#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
+#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
+#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
+#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
+#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
+#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
+#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
+#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
+#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
+#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
+#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
+#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
+#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
+#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
+#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
+#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
+#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
+#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
+#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
+#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
+#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
+#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
+#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 )
+#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
+#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 )
+#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
+#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 )
+#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
+#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
+#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
+#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
+#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
+#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
+#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
+#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
+#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
+#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
+#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
+#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
+#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
+#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
+#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
+#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
+#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
+#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
+#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
+#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
+#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
+#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
+#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
+#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
+#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
+#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
+#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
+#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
+#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
+#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
+#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
+#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
+#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
+#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
+#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
+#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
+#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
+#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 )
+#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
+#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
+#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 )
+#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
+#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
+#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
+#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
+#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
+#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
+#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
+#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
+#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
+#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
+#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
+#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
+#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
+#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
+#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
+#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
+#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
+#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
+#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
+#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
+#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
+#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
+#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
+#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
+#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
+#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
+#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
+#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 )
+
+#endif /* __MACH_IOMUX_MX1_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 4/8] ARM i.MX boards: Use IMX_GPIO_NR
2012-10-05 10:53 [PATCH] i.MX SoC work Sascha Hauer
` (2 preceding siblings ...)
2012-10-05 10:53 ` [PATCH 3/8] ARM i.MX1: move iomux definitions to separate header file Sascha Hauer
@ 2012-10-05 10:53 ` Sascha Hauer
2012-10-05 10:53 ` [PATCH 5/8] ARM i.MX iomux-v1: Add separate header file Sascha Hauer
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2012-10-05 10:53 UTC (permalink / raw)
To: barebox
Rather than GPIO_PORT* which will vanish.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/freescale-mx6-sabrelite/board.c | 2 +-
arch/arm/boards/karo-tx25/board.c | 10 +++++-----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c b/arch/arm/boards/freescale-mx6-sabrelite/board.c
index 25402d7..cbfa3b4 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/board.c
+++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c
@@ -200,7 +200,7 @@ static inline int imx6_iim_register_fec_ethaddr(void)
return 0;
}
-static int sabrelite_spi_cs[] = {GPIO_PORTC + 19};
+static int sabrelite_spi_cs[] = {IMX_GPIO_NR(3, 19)};
static struct spi_imx_master sabrelite_spi_0_data = {
.chipselect = sabrelite_spi_cs,
diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c
index 5413ea8..82d5eb5 100644
--- a/arch/arm/boards/karo-tx25/board.c
+++ b/arch/arm/boards/karo-tx25/board.c
@@ -75,8 +75,8 @@ static iomux_v3_cfg_t karo_tx25_padsd_fec[] = {
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
};
-#define TX25_FEC_PWR_GPIO (GPIO_PORTD | 9)
-#define TX25_FEC_RST_GPIO (GPIO_PORTD | 7)
+#define TX25_FEC_PWR_GPIO IMX_GPIO_NR(4, 9)
+#define TX25_FEC_RST_GPIO IMX_GPIO_NR(4, 7)
static void noinline gpio_fec_active(void)
{
@@ -217,9 +217,9 @@ static struct imx_fb_videomode stk5_fb_mode = {
.pcr = PCR_TFT | PCR_COLOR | PCR_FLMPOL | PCR_LPPOL | PCR_SCLK_SEL,
};
-#define STK5_LCD_BACKLIGHT_GPIO (GPIO_PORTA | 26)
-#define STK5_LCD_RESET_GPIO (GPIO_PORTB | 4)
-#define STK5_LCD_POWER_GPIO (GPIO_PORTB | 5)
+#define STK5_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 26)
+#define STK5_LCD_RESET_GPIO IMX_GPIO_NR(2, 4)
+#define STK5_LCD_POWER_GPIO IMX_GPIO_NR(2, 5)
static void tx25_fb_enable(int enable)
{
--
1.7.10.4
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^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 5/8] ARM i.MX iomux-v1: Add separate header file
2012-10-05 10:53 [PATCH] i.MX SoC work Sascha Hauer
` (3 preceding siblings ...)
2012-10-05 10:53 ` [PATCH 4/8] ARM i.MX boards: Use IMX_GPIO_NR Sascha Hauer
@ 2012-10-05 10:53 ` Sascha Hauer
2012-10-05 10:53 ` [PATCH 6/8] ARM i.MX: Turn iomux-v2 into driver Sascha Hauer
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2012-10-05 10:53 UTC (permalink / raw)
To: barebox
- Add a separate header file for the iomux-v1 just like done for
iomux-v3.
- initialize iomux from SoC code so that we do not depend on IMX_GPIO_BASE
anymore.
- define registers as offset to the base rather than absolute addresses
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/imx1.c | 3 +
arch/arm/mach-imx/imx21.c | 3 +
arch/arm/mach-imx/imx27.c | 3 +
arch/arm/mach-imx/include/mach/imx-regs.h | 42 ---------
arch/arm/mach-imx/include/mach/iomux-mx21.h | 1 +
arch/arm/mach-imx/include/mach/iomux-mx27.h | 1 +
arch/arm/mach-imx/include/mach/iomux-v1.h | 48 +++++++++++
arch/arm/mach-imx/iomux-v1.c | 123 +++++++++++++++++----------
8 files changed, 135 insertions(+), 89 deletions(-)
create mode 100644 arch/arm/mach-imx/include/mach/iomux-v1.h
diff --git a/arch/arm/mach-imx/imx1.c b/arch/arm/mach-imx/imx1.c
index 790e453..747ec09 100644
--- a/arch/arm/mach-imx/imx1.c
+++ b/arch/arm/mach-imx/imx1.c
@@ -16,6 +16,7 @@
#include <io.h>
#include <mach/imx-regs.h>
#include <mach/weim.h>
+#include <mach/iomux-v1.h>
void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower)
{
@@ -25,6 +26,8 @@ void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower)
static int imx1_init(void)
{
+ imx_iomuxv1_init((void *)MX1_GPIO1_BASE_ADDR);
+
add_generic_device("imx1-ccm", 0, NULL, MX1_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpt", 0, NULL, MX1_TIM1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpio", 0, NULL, MX1_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c
index 58895da..55216dc 100644
--- a/arch/arm/mach-imx/imx21.c
+++ b/arch/arm/mach-imx/imx21.c
@@ -16,6 +16,7 @@
#include <io.h>
#include <mach/imx-regs.h>
#include <mach/weim.h>
+#include <mach/iomux-v1.h>
void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower)
{
@@ -25,6 +26,8 @@ void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower)
static int imx21_init(void)
{
+ imx_iomuxv1_init((void *)MX21_GPIO1_BASE_ADDR);
+
add_generic_device("imx21-ccm", 0, NULL, MX21_CCM_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpt", 0, NULL, MX21_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 0, NULL, MX21_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c
index 3d7b21d..d1aa213 100644
--- a/arch/arm/mach-imx/imx27.c
+++ b/arch/arm/mach-imx/imx27.c
@@ -14,6 +14,7 @@
#include <common.h>
#include <mach/imx27-regs.h>
#include <mach/weim.h>
+#include <mach/iomux-v1.h>
#include <sizes.h>
#include <mach/revision.h>
#include <init.h>
@@ -98,6 +99,8 @@ static int imx27_init(void)
{
imx27_silicon_revision();
+ imx_iomuxv1_init((void *)MX27_GPIO1_BASE_ADDR);
+
add_generic_device("imx_iim", 0, NULL, MX27_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h
index 08ee957..4acee24 100644
--- a/arch/arm/mach-imx/include/mach/imx-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx-regs.h
@@ -61,46 +61,4 @@
/* range e.g. GPIO_1_5 is gpio 5 under linux */
#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
-#define GPIO_PIN_MASK 0x1f
-
-#define GPIO_PORT_SHIFT 5
-#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
-
-#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
-#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
-#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
-#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
-#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
-#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
-
-#define GPIO_OUT (1 << 8)
-#define GPIO_IN (0 << 8)
-#define GPIO_PUEN (1 << 9)
-
-#define GPIO_PF (1 << 10)
-#define GPIO_AF (1 << 11)
-
-#define GPIO_OCR_SHIFT 12
-#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
-#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
-#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
-#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
-#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
-
-#define GPIO_AOUT_SHIFT 14
-#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
-
-#define GPIO_BOUT_SHIFT 16
-#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
-
-#define GPIO_GIUS (1<<16)
-
#endif /* _IMX_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx21.h b/arch/arm/mach-imx/include/mach/iomux-mx21.h
index 482c4f2..203190d 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx21.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx21.h
@@ -13,6 +13,7 @@
#ifndef __MACH_IOMUX_MX21_H__
#define __MACH_IOMUX_MX21_H__
+#include <mach/iomux-v1.h>
#include <mach/iomux-mx2x.h>
/* Primary GPIO pin functions */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx27.h b/arch/arm/mach-imx/include/mach/iomux-mx27.h
index ff9d657..7d24967 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx27.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx27.h
@@ -15,6 +15,7 @@
#ifndef __MACH_IOMUX_MX27_H__
#define __MACH_IOMUX_MX27_H__
+#include <mach/iomux-v1.h>
#include <mach/iomux-mx2x.h>
/* Primary GPIO pin functions */
diff --git a/arch/arm/mach-imx/include/mach/iomux-v1.h b/arch/arm/mach-imx/include/mach/iomux-v1.h
new file mode 100644
index 0000000..55fbcdb
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/iomux-v1.h
@@ -0,0 +1,48 @@
+#ifndef __MACH_IOMUX_V1_H__
+#define __MACH_IOMUX_V1_H__
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
+
+#define GPIO_OUT (1 << 8)
+#define GPIO_IN (0 << 8)
+#define GPIO_PUEN (1 << 9)
+
+#define GPIO_PF (1 << 10)
+#define GPIO_AF (1 << 11)
+
+#define GPIO_OCR_SHIFT 12
+#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
+#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
+#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
+#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
+#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
+
+#define GPIO_AOUT_SHIFT 14
+#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
+
+#define GPIO_BOUT_SHIFT 16
+#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
+
+#define GPIO_GIUS (1 << 16)
+
+void imx_iomuxv1_init(void __iomem *base);
+
+#endif /* __MACH_IOMUX_V1_H__ */
diff --git a/arch/arm/mach-imx/iomux-v1.c b/arch/arm/mach-imx/iomux-v1.c
index f2dfdb3..f8f9061 100644
--- a/arch/arm/mach-imx/iomux-v1.c
+++ b/arch/arm/mach-imx/iomux-v1.c
@@ -1,5 +1,6 @@
#include <common.h>
-#include <mach/imx-regs.h>
+#include <io.h>
+#include <mach/iomux-v1.h>
/*
* GPIO Module and I/O Multiplexer
@@ -8,23 +9,25 @@
* i.MX1 and i.MXL: 0 <= x <= 3
* i.MX27 : 0 <= x <= 5
*/
-#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 7) << 8)
-#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 7) << 8)
-#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 7) << 8)
-#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 7) << 8)
-#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 7) << 8)
-#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 7) << 8)
-#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 7) << 8)
-#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 7) << 8)
-#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 7) << 8)
-#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 7) << 8)
-#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 7) << 8)
-#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 7) << 8)
-#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 7) << 8)
-#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 7) << 8)
-#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 7) << 8)
-#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 7) << 8)
-#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 7) << 8)
+#define DDIR 0x00
+#define OCR1 0x04
+#define OCR2 0x08
+#define ICONFA1 0x0c
+#define ICONFA2 0x10
+#define ICONFB1 0x14
+#define ICONFB2 0x18
+#define DR 0x1c
+#define GIUS 0x20
+#define SSR 0x24
+#define ICR1 0x28
+#define ICR2 0x2c
+#define IMR 0x30
+#define ISR 0x34
+#define GPR 0x38
+#define SWR 0x3c
+#define PUEN 0x40
+
+static void __iomem *iomuxv1_base;
void imx_gpio_mode(int gpio_mode)
{
@@ -33,55 +36,81 @@ void imx_gpio_mode(int gpio_mode)
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
- unsigned int tmp;
+ void __iomem *portbase = iomuxv1_base + port * 0x100;
+ uint32_t val;
+
+ if (!iomuxv1_base)
+ return;
/* Pullup enable */
- if(gpio_mode & GPIO_PUEN)
- PUEN(port) |= (1 << pin);
+ val = readl(portbase + PUEN);
+ if (gpio_mode & GPIO_PUEN)
+ val |= (1 << pin);
else
- PUEN(port) &= ~(1 << pin);
+ val &= ~(1 << pin);
+ writel(val, portbase + PUEN);
/* Data direction */
- if(gpio_mode & GPIO_OUT)
- DDIR(port) |= 1 << pin;
+ val = readl(portbase + DDIR);
+ if (gpio_mode & GPIO_OUT)
+ val |= 1 << pin;
else
- DDIR(port) &= ~(1 << pin);
+ val &= ~(1 << pin);
+ writel(val, portbase + DDIR);
/* Primary / alternate function */
- if(gpio_mode & GPIO_AF)
- GPR(port) |= (1 << pin);
+ val = readl(portbase + GPR);
+ if (gpio_mode & GPIO_AF)
+ val |= (1 << pin);
else
- GPR(port) &= ~(1 << pin);
+ val &= ~(1 << pin);
+ writel(val, portbase + GPR);
/* use as gpio? */
- if(!(gpio_mode & (GPIO_PF | GPIO_AF)))
- GIUS(port) |= (1 << pin);
+ val = readl(portbase + GIUS);
+ if (!(gpio_mode & (GPIO_PF | GPIO_AF)))
+ val |= (1 << pin);
else
- GIUS(port) &= ~(1 << pin);
+ val &= ~(1 << pin);
+ writel(val, portbase + GIUS);
/* Output / input configuration */
if (pin < 16) {
- tmp = OCR1(port);
- tmp &= ~(3 << (pin * 2));
- tmp |= (ocr << (pin * 2));
- OCR1(port) = tmp;
+ val = readl(portbase + OCR1);
+ val &= ~(3 << (pin * 2));
+ val |= (ocr << (pin * 2));
+ writel(val, portbase + OCR1);
+
+ val = readl(portbase + ICONFA1);
+ val &= ~(3 << (pin * 2));
+ val |= aout << (pin * 2);
+ writel(val, portbase + ICONFA1);
- ICONFA1(port) &= ~(3 << (pin * 2));
- ICONFA1(port) |= aout << (pin * 2);
- ICONFB1(port) &= ~(3 << (pin * 2));
- ICONFB1(port) |= bout << (pin * 2);
+ val = readl(portbase + ICONFB1);
+ val &= ~(3 << (pin * 2));
+ val |= bout << (pin * 2);
+ writel(val, portbase + ICONFB1);
} else {
pin -= 16;
- tmp = OCR2(port);
- tmp &= ~(3 << (pin * 2));
- tmp |= (ocr << (pin * 2));
- OCR2(port) = tmp;
+ val = readl(portbase + OCR2);
+ val &= ~(3 << (pin * 2));
+ val |= (ocr << (pin * 2));
+ writel(val, portbase + OCR2);
- ICONFA2(port) &= ~(3 << (pin * 2));
- ICONFA2(port) |= aout << (pin * 2);
- ICONFB2(port) &= ~(3 << (pin * 2));
- ICONFB2(port) |= bout << (pin * 2);
+ val = readl(portbase + ICONFA2);
+ val &= ~(3 << (pin * 2));
+ val |= aout << (pin * 2);
+ writel(val, portbase + ICONFA2);
+
+ val = readl(portbase + ICONFB2);
+ val &= ~(3 << (pin * 2));
+ val |= bout << (pin * 2);
+ writel(val, portbase + ICONFB2);
}
}
+void imx_iomuxv1_init(void __iomem *base)
+{
+ iomuxv1_base = base;
+}
--
1.7.10.4
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^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 6/8] ARM i.MX: Turn iomux-v2 into driver
2012-10-05 10:53 [PATCH] i.MX SoC work Sascha Hauer
` (4 preceding siblings ...)
2012-10-05 10:53 ` [PATCH 5/8] ARM i.MX iomux-v1: Add separate header file Sascha Hauer
@ 2012-10-05 10:53 ` Sascha Hauer
2012-10-05 10:53 ` [PATCH 7/8] ARM i.MX: Turn iomux-v3 " Sascha Hauer
2012-10-05 10:53 ` [PATCH 8/8] ARM i.MX: rework bootsource setting Sascha Hauer
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2012-10-05 10:53 UTC (permalink / raw)
To: barebox
To get proper resources allocated for it and to get rid of IOMUXC_BASE
usage.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/imx31.c | 1 +
arch/arm/mach-imx/iomux-v2.c | 66 +++++++++++++++++++++++++++++++++++-------
2 files changed, 57 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c
index 90eee0a..d4955bf 100644
--- a/arch/arm/mach-imx/imx31.c
+++ b/arch/arm/mach-imx/imx31.c
@@ -31,6 +31,7 @@ static int imx31_init(void)
add_generic_device("imx_iim", 0, NULL, MX31_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-iomux", 0, NULL, MX31_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-ccm", 0, NULL, MX31_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, MX31_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 0, NULL, MX31_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/iomux-v2.c b/arch/arm/mach-imx/iomux-v2.c
index 08af54c..dbbb8a2 100644
--- a/arch/arm/mach-imx/iomux-v2.c
+++ b/arch/arm/mach-imx/iomux-v2.c
@@ -16,19 +16,22 @@
#include <common.h>
#include <io.h>
-#include <mach/imx-regs.h>
+#include <init.h>
#include <mach/iomux-mx31.h>
/*
* IOMUX register (base) addresses
*/
-#define IOMUXINT_OBS1 (IOMUXC_BASE + 0x000)
-#define IOMUXINT_OBS2 (IOMUXC_BASE + 0x004)
-#define IOMUXGPR (IOMUXC_BASE + 0x008)
-#define IOMUXSW_MUX_CTL (IOMUXC_BASE + 0x00C)
-#define IOMUXSW_PAD_CTL (IOMUXC_BASE + 0x154)
+#define IOMUXINT_OBS1 0x000
+#define IOMUXINT_OBS2 0x004
+#define IOMUXGPR 0x008
+#define IOMUXSW_MUX_CTL 0x00C
+#define IOMUXSW_PAD_CTL 0x154
#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
+
+static void __iomem *base;
+
/*
* set the mode for a IOMUX pin.
*/
@@ -37,7 +40,10 @@ int imx_iomux_mode(unsigned int pin_mode)
u32 field, l, mode, ret = 0;
void __iomem *reg;
- reg = (void *)(IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK));
+ if (!base)
+ return -EINVAL;
+
+ reg = base + IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
field = pin_mode & 0x3;
mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
@@ -61,8 +67,11 @@ void imx_iomux_set_pad(enum iomux_pins pin, u32 config)
u32 field, l;
void __iomem *reg;
+ if (!base)
+ return;
+
pin &= IOMUX_PADNUM_MASK;
- reg = (void *)(IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4);
+ reg = base + IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
field = (pin + 2) % 3;
pr_debug("%s: reg offset = 0x%x, field = %d\n",
@@ -83,14 +92,51 @@ void imx_iomux_set_gpr(enum iomux_gp_func gp, int en)
{
u32 l;
- l = readl(IOMUXGPR);
+ if (!base)
+ return;
+
+ l = readl(base + IOMUXGPR);
if (en)
l |= gp;
else
l &= ~gp;
- writel(l, IOMUXGPR);
+ writel(l, base + IOMUXGPR);
}
EXPORT_SYMBOL(mxc_iomux_set_gpr);
+static int imx_iomux_probe(struct device_d *dev)
+{
+ base = dev_request_mem_region(dev, 0);
+
+ return 0;
+}
+static __maybe_unused struct of_device_id imx_iomux_dt_ids[] = {
+ {
+ .compatible = "fsl,imx31-iomux",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_device_id imx_iomux_ids[] = {
+ {
+ .name = "imx31-iomux",
+ }, {
+ /* sentinel */
+ },
+};
+
+static struct driver_d imx_iomux_driver = {
+ .name = "imx-iomuxv2",
+ .probe = imx_iomux_probe,
+ .of_compatible = DRV_OF_COMPAT(imx_iomux_dt_ids),
+ .id_table = imx_iomux_ids,
+};
+
+static int imx_iomux_init(void)
+{
+ return platform_driver_register(&imx_iomux_driver);
+}
+postcore_initcall(imx_iomux_init);
--
1.7.10.4
_______________________________________________
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 7/8] ARM i.MX: Turn iomux-v3 into driver
2012-10-05 10:53 [PATCH] i.MX SoC work Sascha Hauer
` (5 preceding siblings ...)
2012-10-05 10:53 ` [PATCH 6/8] ARM i.MX: Turn iomux-v2 into driver Sascha Hauer
@ 2012-10-05 10:53 ` Sascha Hauer
2012-10-05 10:53 ` [PATCH 8/8] ARM i.MX: rework bootsource setting Sascha Hauer
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2012-10-05 10:53 UTC (permalink / raw)
To: barebox
To get proper resources allocated for it and to get rid of IMX_IOMUXC_BASE
usage.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/imx35.c | 1 +
arch/arm/mach-imx/imx51.c | 1 +
arch/arm/mach-imx/imx53.c | 1 +
arch/arm/mach-imx/imx6.c | 1 +
arch/arm/mach-imx/iomux-v3.c | 42 +++++++++++++++++++++++++++++++++++++++++-
5 files changed, 45 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index 1575d54..bb93c37 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -64,6 +64,7 @@ static int imx35_init(void)
add_generic_device("imx_iim", 0, NULL, MX35_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
+ add_generic_device("imx-iomuxv3", 0, NULL, MX35_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx35-ccm", 0, NULL, MX35_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, MX35_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 0, NULL, MX35_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index 3850001..81e6211 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -73,6 +73,7 @@ static int imx51_init(void)
add_generic_device("imx_iim", 0, NULL, MX51_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
+ add_generic_device("imx-iomuxv3", 0, NULL, MX51_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx51-ccm", 0, NULL, MX51_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, MX51_GPT1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 0, NULL, MX51_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c
index 4aa3f61..569d8f4 100644
--- a/arch/arm/mach-imx/imx53.c
+++ b/arch/arm/mach-imx/imx53.c
@@ -69,6 +69,7 @@ static int imx53_init(void)
add_generic_device("imx_iim", 0, NULL, MX53_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
+ add_generic_device("imx-iomuxv3", 0, NULL, MX53_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx53-ccm", 0, NULL, MX53_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, 0X53fa0000, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 0, NULL, MX53_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index a5ec364..fef6832 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -54,6 +54,7 @@ void imx6_init_lowlevel(void)
static int imx6_init(void)
{
+ add_generic_device("imx-iomuxv3", 0, NULL, MX6_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx6-ccm", 0, NULL, MX6_CCM_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, 0x02098000, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 0, NULL, MX6_GPIO1_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
index 948b610..9153ead 100644
--- a/arch/arm/mach-imx/iomux-v3.c
+++ b/arch/arm/mach-imx/iomux-v3.c
@@ -15,11 +15,12 @@
*
*/
#include <common.h>
+#include <init.h>
#include <io.h>
#include <mach/iomux-v3.h>
#include <mach/imx-regs.h>
-static void __iomem *base = (void *)IMX_IOMUXC_BASE;
+static void __iomem *base;
/*
* configures a single pad in the iomuxer
@@ -33,6 +34,9 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+ if (!base)
+ return -EINVAL;
+
debug("%s: mux 0x%08x -> 0x%04x pad: 0x%08x -> 0x%04x sel_inp: 0x%08x -> 0x%04x\n",
__func__, mux_mode, mux_ctrl_ofs, pad_ctrl, pad_ctrl_ofs, sel_input,
sel_input_ofs);
@@ -66,3 +70,39 @@ int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
return 0;
}
EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
+
+static int imx_iomux_probe(struct device_d *dev)
+{
+ base = dev_request_mem_region(dev, 0);
+
+ return 0;
+}
+
+static __maybe_unused struct of_device_id imx_iomux_dt_ids[] = {
+ {
+ .compatible = "fsl,imx35-iomux",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_device_id imx_iomux_ids[] = {
+ {
+ .name = "imx35-iomux",
+ }, {
+ /* sentinel */
+ },
+};
+
+static struct driver_d imx_iomux_driver = {
+ .name = "imx-iomuxv3",
+ .probe = imx_iomux_probe,
+ .of_compatible = DRV_OF_COMPAT(imx_iomux_dt_ids),
+ .id_table = imx_iomux_ids,
+};
+
+static int imx_iomux_init(void)
+{
+ return platform_driver_register(&imx_iomux_driver);
+}
+postcore_initcall(imx_iomux_init);
--
1.7.10.4
_______________________________________________
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 8/8] ARM i.MX: rework bootsource setting
2012-10-05 10:53 [PATCH] i.MX SoC work Sascha Hauer
` (6 preceding siblings ...)
2012-10-05 10:53 ` [PATCH 7/8] ARM i.MX: Turn iomux-v3 " Sascha Hauer
@ 2012-10-05 10:53 ` Sascha Hauer
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2012-10-05 10:53 UTC (permalink / raw)
To: barebox
This moves the known i.MX bootsource settings to a single file
so that the code can be shared. Also we add a enum for the different
boot sources so that it can be used in C Code and not only on the shell.
The pcm038 board is changed to use it instead of digging in the registers
manually.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/pcm038/pcm038.c | 8 +-
arch/arm/mach-imx/boot.c | 178 +++++++++++++++++++--------
arch/arm/mach-imx/imx25.c | 7 ++
arch/arm/mach-imx/imx35.c | 6 +
arch/arm/mach-imx/imx51.c | 67 ----------
arch/arm/mach-imx/include/mach/generic.h | 17 +++
arch/arm/mach-imx/include/mach/imx27-regs.h | 10 --
7 files changed, 158 insertions(+), 135 deletions(-)
diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c
index 58b1ec9..ec4ffd7 100644
--- a/arch/arm/boards/pcm038/pcm038.c
+++ b/arch/arm/boards/pcm038/pcm038.c
@@ -39,6 +39,7 @@
#include <mach/devices-imx27.h>
#include <mach/iim.h>
#include <mfd/mc13xxx.h>
+#include <mach/generic.h>
#include "pll.h"
@@ -302,11 +303,8 @@ static int pcm038_devices_init(void)
*/
imx27_add_fec(&fec_info);
- switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
- case GPCR_BOOT_8BIT_NAND_2k:
- case GPCR_BOOT_16BIT_NAND_2k:
- case GPCR_BOOT_16BIT_NAND_512:
- case GPCR_BOOT_8BIT_NAND_512:
+ switch (imx_bootsource()) {
+ case bootsource_nand:
devfs_add_partition("nand0", 0x00000, 0x80000,
DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index 11c688e..409c237 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -17,9 +17,64 @@
#include <magicvar.h>
#include <io.h>
-#include <mach/imx-regs.h>
+#include <mach/generic.h>
+
+static const char *bootsource_str[] = {
+ [bootsource_unknown] = "unknown",
+ [bootsource_nand] = "nand",
+ [bootsource_nor] = "nor",
+ [bootsource_mmc] = "mmc",
+ [bootsource_i2c] = "i2c",
+ [bootsource_spi] = "spi",
+ [bootsource_serial] = "serial",
+ [bootsource_onenand] = "onenand",
+};
+
+static enum imx_bootsource bootsource;
+
+void imx_set_bootsource(enum imx_bootsource src)
+{
+ if (src >= ARRAY_SIZE(bootsource_str))
+ src = bootsource_unknown;
+
+ bootsource = src;
+
+ setenv("barebox_loc", bootsource_str[src]);
+ export("barebox_loc");
+}
+
+enum imx_bootsource imx_bootsource(void)
+{
+ return bootsource;
+}
+
+BAREBOX_MAGICVAR(barebox_loc, "The source barebox has been booted from");
+
+/* [CTRL][TYPE] */
+static const enum imx_bootsource locations[4][4] = {
+ { /* CTRL = WEIM */
+ bootsource_nor,
+ bootsource_unknown,
+ bootsource_onenand,
+ bootsource_unknown,
+ }, { /* CTRL == NAND */
+ bootsource_nand,
+ bootsource_nand,
+ bootsource_nand,
+ bootsource_nand,
+ }, { /* CTRL == ATA, (imx35 only) */
+ bootsource_unknown,
+ bootsource_unknown, /* might be p-ata */
+ bootsource_unknown,
+ bootsource_unknown,
+ }, { /* CTRL == expansion */
+ bootsource_mmc, /* note imx25 could also be: movinand, ce-ata */
+ bootsource_unknown,
+ bootsource_i2c,
+ bootsource_spi,
+ }
+};
-#if defined(CONFIG_ARCH_IMX25) || defined(CONFIG_ARCH_IMX35)
/*
* Saves the boot source media into the $barebox_loc enviroment variable
*
@@ -38,43 +93,14 @@
* Note also that I suspect that the boot source pins are only sampled at
* power up.
*/
-static int imx_25_35_boot_save_loc(void)
+int imx_25_35_boot_save_loc(unsigned int ctrl, unsigned int type)
{
const char *bareboxloc = NULL;
- uint32_t reg;
- unsigned int ctrl, type;
+ enum imx_bootsource src;
- /* [CTRL][TYPE] */
- const char *const locations[4][4] = {
- { /* CTRL = WEIM */
- "nor",
- NULL,
- "onenand",
- NULL,
- }, { /* CTRL == NAND */
- "nand",
- "nand",
- "nand",
- "nand",
- }, { /* CTRL == ATA, (imx35 only) */
- NULL,
- NULL, /* might be p-ata */
- NULL,
- NULL,
- }, { /* CTRL == expansion */
- "mmc", /* note imx25 could also be: movinand, ce-ata */
- NULL,
- "i2c",
- "spi",
- }
- };
-
- reg = readl(IMX_CCM_BASE + CCM_RCSR);
- ctrl = (reg >> CCM_RCSR_MEM_CTRL_SHIFT) & 0x3;
- type = (reg >> CCM_RCSR_MEM_TYPE_SHIFT) & 0x3;
-
- bareboxloc = locations[ctrl][type];
+ src = locations[ctrl][type];
+ imx_set_bootsource(src);
if (bareboxloc) {
setenv("barebox_loc", bareboxloc);
export("barebox_loc");
@@ -82,32 +108,78 @@ static int imx_25_35_boot_save_loc(void)
return 0;
}
-coredevice_initcall(imx_25_35_boot_save_loc);
-#endif
-#if defined(CONFIG_ARCH_IMX27)
-static int imx_27_boot_save_loc(void)
+#define IMX27_SYSCTRL_GPCR 0x18
+#define IMX27_GPCR_BOOT_SHIFT 16
+#define IMX27_GPCR_BOOT_MASK (0xf << IMX27_GPCR_BOOT_SHIFT)
+#define IMX27_GPCR_BOOT_UART_USB 0
+#define IMX27_GPCR_BOOT_8BIT_NAND_2k 2
+#define IMX27_GPCR_BOOT_16BIT_NAND_2k 3
+#define IMX27_GPCR_BOOT_16BIT_NAND_512 4
+#define IMX27_GPCR_BOOT_16BIT_CS0 5
+#define IMX27_GPCR_BOOT_32BIT_CS0 6
+#define IMX27_GPCR_BOOT_8BIT_NAND_512 7
+
+void imx_27_boot_save_loc(void __iomem *sysctrl_base)
{
- switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
- case GPCR_BOOT_UART_USB:
- setenv("barebox_loc", "serial");
+ enum imx_bootsource src;
+ uint32_t val;
+
+ val = readl(sysctrl_base + IMX27_SYSCTRL_GPCR);
+ val &= IMX27_GPCR_BOOT_MASK;
+ val >>= IMX27_GPCR_BOOT_SHIFT;
+
+ switch (val) {
+ case IMX27_GPCR_BOOT_UART_USB:
+ src = bootsource_serial;
break;
- case GPCR_BOOT_8BIT_NAND_2k:
- case GPCR_BOOT_16BIT_NAND_2k:
- case GPCR_BOOT_16BIT_NAND_512:
- case GPCR_BOOT_8BIT_NAND_512:
- setenv("barebox_loc", "nand");
+ case IMX27_GPCR_BOOT_8BIT_NAND_2k:
+ case IMX27_GPCR_BOOT_16BIT_NAND_2k:
+ case IMX27_GPCR_BOOT_16BIT_NAND_512:
+ case IMX27_GPCR_BOOT_8BIT_NAND_512:
+ src = bootsource_nand;
break;
default:
- setenv("barebox_loc", "nor");
+ src = bootsource_nor;
break;
}
- export("barebox_loc");
+ imx_set_bootsource(src);
+}
+
+#define IMX51_SRC_SBMR 0x4
+#define IMX51_SBMR_BT_MEM_TYPE_SHIFT 7
+#define IMX51_SBMR_BT_MEM_CTL_SHIFT 0
+#define IMX51_SBMR_BMOD_SHIFT 14
+
+int imx51_boot_save_loc(void __iomem *src_base)
+{
+ enum imx_bootsource src = bootsource_unknown;
+ uint32_t reg;
+ unsigned int ctrl, type;
+
+ reg = readl(src_base + IMX51_SRC_SBMR);
+
+ switch ((reg >> IMX51_SBMR_BMOD_SHIFT) & 0x3) {
+ case 0:
+ case 2:
+ /* internal boot */
+ ctrl = (reg >> IMX51_SBMR_BT_MEM_CTL_SHIFT) & 0x3;
+ type = (reg >> IMX51_SBMR_BT_MEM_TYPE_SHIFT) & 0x3;
+
+ src = locations[ctrl][type];
+ break;
+ case 1:
+ /* reserved */
+ src = bootsource_unknown;
+ break;
+ case 3:
+ src = bootsource_serial;
+ break;
+
+ }
+
+ imx_set_bootsource(src);
return 0;
}
-coredevice_initcall(imx_27_boot_save_loc);
-#endif
-
-BAREBOX_MAGICVAR(barebox_loc, "The source barebox has been booted from");
diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c
index 5e6532a..87c23ec 100644
--- a/arch/arm/mach-imx/imx25.c
+++ b/arch/arm/mach-imx/imx25.c
@@ -17,6 +17,7 @@
#include <mach/iim.h>
#include <io.h>
#include <mach/weim.h>
+#include <mach/generic.h>
#include <sizes.h>
void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
@@ -58,6 +59,12 @@ static struct imx_iim_platform_data imx25_iim_pdata = {
static int imx25_init(void)
{
+ uint32_t val;
+
+ val = readl(MX25_CCM_BASE_ADDR + CCM_RCSR);
+ imx_25_35_boot_save_loc((val >> CCM_RCSR_MEM_CTRL_SHIFT) & 0x3,
+ (val >> CCM_RCSR_MEM_TYPE_SHIFT) & 0x3);
+
add_generic_device("imx_iim", 0, NULL, MX25_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, &imx25_iim_pdata);
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index bb93c37..f89bd10 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -59,8 +59,14 @@ core_initcall(imx35_l2_fix);
static int imx35_init(void)
{
+ uint32_t val;
+
imx35_silicon_revision();
+ val = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
+ imx_25_35_boot_save_loc((val >> CCM_RCSR_MEM_CTRL_SHIFT) & 0x3,
+ (val >> CCM_RCSR_MEM_TYPE_SHIFT) & 0x3);
+
add_generic_device("imx_iim", 0, NULL, MX35_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index 81e6211..805361d 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -104,73 +104,6 @@ postcore_initcall(imx51_init);
* power up.
*/
-#define SRC_SBMR 0x4
-#define SBMR_BT_MEM_TYPE_SHIFT 7
-#define SBMR_BT_MEM_CTL_SHIFT 0
-#define SBMR_BMOD_SHIFT 14
-
-static int imx51_boot_save_loc(void)
-{
- const char *bareboxloc = NULL;
- uint32_t reg;
- unsigned int ctrl, type;
-
- /* [CTRL][TYPE] */
- const char *const locations[4][4] = {
- { /* CTRL = WEIM */
- "nor",
- NULL,
- "onenand",
- NULL,
- }, { /* CTRL == NAND */
- "nand",
- "nand",
- "nand",
- "nand",
- }, { /* CTRL == reserved */
- NULL,
- NULL,
- NULL,
- NULL,
- }, { /* CTRL == expansion */
- "mmc",
- NULL,
- "i2c",
- "spi",
- }
- };
-
- reg = readl(MX51_SRC_BASE_ADDR + SRC_SBMR);
-
- switch ((reg >> SBMR_BMOD_SHIFT) & 0x3) {
- case 0:
- case 2:
- /* internal boot */
- ctrl = (reg >> SBMR_BT_MEM_CTL_SHIFT) & 0x3;
- type = (reg >> SBMR_BT_MEM_TYPE_SHIFT) & 0x3;
-
- bareboxloc = locations[ctrl][type];
- break;
- case 1:
- /* reserved */
- bareboxloc = "unknown";
- break;
- case 3:
- bareboxloc = "serial";
- break;
-
- }
-
- if (bareboxloc) {
- setenv("barebox_loc", bareboxloc);
- export("barebox_loc");
- }
-
- return 0;
-}
-
-coredevice_initcall(imx51_boot_save_loc);
-
#define setup_pll_800(base) imx5_setup_pll((base), 800, (( 8 << 4) + ((1 - 1) << 0)), ( 3 - 1), 1)
#define setup_pll_665(base) imx5_setup_pll((base), 665, (( 6 << 4) + ((1 - 1) << 0)), (96 - 1), 89)
#define setup_pll_600(base) imx5_setup_pll((base), 600, (( 6 << 4) + ((1 - 1) << 0)), ( 4 - 1), 1)
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index 691a146..7fe5810 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -1,6 +1,23 @@
u64 imx_uid(void);
+enum imx_bootsource {
+ bootsource_unknown,
+ bootsource_nand,
+ bootsource_nor,
+ bootsource_mmc,
+ bootsource_i2c,
+ bootsource_spi,
+ bootsource_serial,
+ bootsource_onenand,
+};
+
+enum imx_bootsource imx_bootsource(void);
+void imx_set_bootsource(enum imx_bootsource src);
+
+int imx_25_35_boot_save_loc(unsigned int ctrl, unsigned int type);
+void imx_27_boot_save_loc(void __iomem *sysctrl_base);
+int imx51_boot_save_loc(void __iomem *src_base);
#ifdef CONFIG_ARCH_IMX1
#define cpu_is_mx1() (1)
diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h
index 5db1a3c..e7372e4 100644
--- a/arch/arm/mach-imx/include/mach/imx27-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx27-regs.h
@@ -129,16 +129,6 @@
#define WBCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C) /* Well Bias Control Register */
#define DSCR(x) __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */
-#define GPCR_BOOT_SHIFT 16
-#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT)
-#define GPCR_BOOT_UART_USB 0
-#define GPCR_BOOT_8BIT_NAND_2k 2
-#define GPCR_BOOT_16BIT_NAND_2k 3
-#define GPCR_BOOT_16BIT_NAND_512 4
-#define GPCR_BOOT_16BIT_CS0 5
-#define GPCR_BOOT_32BIT_CS0 6
-#define GPCR_BOOT_8BIT_NAND_512 7
-
#include "esdctl.h"
/* PLL registers */
--
1.7.10.4
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