[PATCH] i.MX clk

[PATCH] i.MX clk

[Sascha Hauer]

Another round of clk patches, mostly driven by the fact that
the i.MX LCD controller does not have an enable bit. Instead
it starts once a clock is provided.

Sascha

----------------------------------------------------------------
Sascha Hauer (10):
      clk: Add clk gate support
      ARM i.MX: Add clk_gate inline function
      ARM i.MX21: Fix CSPI parent clock
      ARM i.MX21: Enable all needed clocks during startup
      ARM i.MX25: Enable all needed clocks during startup
      ARM i.MX21: Add lcdc per gate
      ARM i.MX27: Add lcdc per gate
      ARM i.MX25: Add lcdc per gate
      video i.MX: Use regular clk_[en|dis]able functions
      ARM i.MX: Enable clocks in common place

 arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c |   15 ----
 arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c |    1 -
 arch/arm/boards/guf-neso/lowlevel.c               |    2 -
 arch/arm/boards/imx21ads/imx21ads.c               |    1 -
 arch/arm/boards/pcm038/lowlevel.c                 |    2 -
 arch/arm/boards/pcm038/pcm038.c                   |    4 --
 arch/arm/boards/pcm038/pcm970.c                   |    1 -
 arch/arm/boards/phycard-i.MX27/pca100.c           |    4 --
 arch/arm/mach-imx/clk-imx21.c                     |   17 ++++-
 arch/arm/mach-imx/clk-imx25.c                     |   20 ++++--
 arch/arm/mach-imx/clk-imx27.c                     |   25 +++----
 arch/arm/mach-imx/clk.h                           |    6 ++
 arch/arm/mach-imx/clocksource.c                   |   12 ----
 drivers/clk/Makefile                              |    3 +-
 drivers/clk/clk-gate.c                            |   78 +++++++++++++++++++++
 drivers/mtd/nand/nand_imx.c                       |    6 --
 drivers/net/fec_imx.c                             |    4 +-
 drivers/video/imx.c                               |   44 ++----------
 include/linux/clk.h                               |    2 +
 19 files changed, 137 insertions(+), 110 deletions(-)
 create mode 100644 drivers/clk/clk-gate.c

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[PATCH 01/10] clk: Add clk gate support

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/Makefile   |    3 +-
 drivers/clk/clk-gate.c |   78 ++++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk.h    |    2 ++
 3 files changed, 82 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/clk-gate.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 39a75a4..3cc7163 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,2 +1,3 @@
-obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed.o clk-divider.o clk-fixed-factor.o clk-mux.o
+obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed.o clk-divider.o clk-fixed-factor.o \
+				clk-mux.o clk-gate.o
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
new file mode 100644
index 0000000..cf1bb1a
--- /dev/null
+++ b/drivers/clk/clk-gate.c
@@ -0,0 +1,78 @@
+/*
+ * clk-gate.c - generic barebox clock support. Based on Linux clk support
+ *
+ * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <common.h>
+#include <io.h>
+#include <malloc.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+struct clk_gate {
+	struct clk clk;
+	void __iomem *reg;
+	int shift;
+	const char *parent;
+};
+
+static int clk_gate_enable(struct clk *clk)
+{
+	struct clk_gate *g = container_of(clk, struct clk_gate, clk);
+	u32 val;
+
+	val = readl(g->reg);
+	val |= 1 << g->shift;
+	writel(val, g->reg);
+
+	return 0;
+}
+
+static void clk_gate_disable(struct clk *clk)
+{
+	struct clk_gate *g = container_of(clk, struct clk_gate, clk);
+	u32 val;
+
+	val = readl(g->reg);
+	val &= ~(1 << g->shift);
+	writel(val, g->reg);
+}
+
+struct clk_ops clk_gate_ops = {
+	.enable = clk_gate_enable,
+	.disable = clk_gate_disable,
+};
+
+struct clk *clk_gate(const char *name, const char *parent, void __iomem *reg,
+		u8 shift)
+{
+	struct clk_gate *g = xzalloc(sizeof(*g));
+	int ret;
+
+	g->parent = parent;
+	g->reg = reg;
+	g->shift = shift;
+	g->clk.ops = &clk_gate_ops;
+	g->clk.name = name;
+	g->clk.parent_names = &g->parent;
+	g->clk.num_parents = 1;
+
+	ret = clk_register(&g->clk);
+	if (ret) {
+		free(g);
+		return ERR_PTR(ret);
+	}
+
+	return &g->clk;
+}
diff --git a/include/linux/clk.h b/include/linux/clk.h
index e9031dd..00588bf 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -188,6 +188,8 @@ struct clk *clk_fixed_factor(const char *name,
 		const char *parent, unsigned int mult, unsigned int div);
 struct clk *clk_mux(const char *name, void __iomem *reg,
 		u8 shift, u8 width, const char **parents, u8 num_parents);
+struct clk *clk_gate(const char *name, const char *parent, void __iomem *reg,
+		u8 shift);
 
 int clk_register(struct clk *clk);
 
-- 
1.7.10.4


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[PATCH 02/10] ARM i.MX: Add clk_gate inline function

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/clk.h |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 3d79950..0f30082 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -19,6 +19,12 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
 	return clk_mux(name, reg, shift, width, parents, num_parents);
 }
 
+static inline struct clk *imx_clk_gate(const char *name, const char *parent,
+		void __iomem *reg, u8 shift)
+{
+	return clk_gate(name, parent, reg, shift);
+}
+
 struct clk *imx_clk_pllv1(const char *name, const char *parent,
 		void __iomem *base);
 
-- 
1.7.10.4


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[PATCH 03/10] ARM i.MX21: Fix CSPI parent clock

[Sascha Hauer]

It's perclk2, not perclk3

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/clk-imx21.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index 69aaa9e..32c8a4c 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -98,10 +98,10 @@ static int imx21_ccm_probe(struct device_d *dev)
 	clkdev_add_physbase(clks[per1], MX21_UART4_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[per2], MX21_CSPI1_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[per2], MX21_CSPI2_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[per2], MX21_CSPI3_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[ipg], MX21_I2C_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[ipg], MX21_SDHC1_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[ipg], MX21_SDHC2_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[per3], MX21_CSPI3_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[per3], MX21_LCDC_BASE_ADDR, NULL);
 
 	return 0;
-- 
1.7.10.4


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[PATCH 04/10] ARM i.MX21: Enable all needed clocks during startup

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/clk-imx21.c |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index 32c8a4c..cab5233 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -70,6 +70,16 @@ static int imx21_ccm_probe(struct device_d *dev)
 
 	base = dev_request_mem_region(dev, 0);
 
+	writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
+			(1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
+			(1 << 13) | (1 << 14) | (1 << 19) | (1 << 22) |
+			(1 << 24) | (1 << 26) |	(1 << 30),
+			base + CCM_PCCR0);
+
+	writel((1 << 23) | (1 << 24) | (1 << 25) | (1 << 26) | (1 << 27) |
+			(1 << 28) | (1 << 29) | (1 << 30) | (1 << 31),
+			base + CCM_PCCR1);
+
 	clks[ckil] = clk_fixed("ckil", lref);
 	clks[ckih] = clk_fixed("ckih", href);
 	clks[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
-- 
1.7.10.4


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[PATCH 05/10] ARM i.MX25: Enable all needed clocks during startup

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/clk-imx25.c |   16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 3b9588c..3a141c2 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -76,9 +76,19 @@ static int imx25_ccm_probe(struct device_d *dev)
 
 	base = dev_request_mem_region(dev, 0);
 
-	writel(0x10e88578, base + CCM_CGCR0);
-	writel(0x0478e1e0, base + CCM_CGCR0);
-	writel(0x0007c400, base + CCM_CGCR0);
+	writel((1 << 3) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 8) | (1 << 9) |
+			(1 << 10) | (1 << 15) |	(1 << 19) | (1 << 21) | (1 << 22) |
+			(1 << 22) | (1 << 23) | (1 << 24) | (1 << 28),
+			base + CCM_CGCR0);
+
+	writel((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 13) | (1 << 14) |
+			(1 << 15) | (1 << 19) | (1 << 20) | (1 << 21) | (1 << 22) |
+			(1 << 26) | (1 << 29) | (1 << 31),
+			base + CCM_CGCR1);
+
+	writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 10) | (1 << 13) | (1 << 14) |
+			(1 << 15) | (1 << 16) | (1 << 17) | (1 << 18),
+			base + CCM_CGCR2);
 
 	clks[dummy] = clk_fixed("dummy", 0);
 	clks[osc] = clk_fixed("osc", 24000000);
-- 
1.7.10.4


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[PATCH 06/10] ARM i.MX21: Add lcdc per gate

[Sascha Hauer]

This gate is used to enable/disable the lcd controller, hence we
need a gate for it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/clk-imx21.c |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index cab5233..9ef73bd 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -47,7 +47,7 @@
 
 enum imx21_clks {
 	ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
-	per2, per3, per4, usb_div, nfc_div, clk_max
+	per2, per3, per4, usb_div, nfc_div, lcdc_per_gate, clk_max
 };
 
 static struct clk *clks[clk_max];
@@ -98,6 +98,7 @@ static int imx21_ccm_probe(struct device_d *dev)
 	clks[per4] = imx_clk_divider("per4", "mpll", base + CCM_PCDR1, 24, 6);
 	clks[usb_div] = imx_clk_divider("usb_div", "spll", base + CCM_CSCR, 26, 3);
 	clks[nfc_div] = imx_clk_divider("nfc_div", "ipg", base + CCM_PCDR0, 12, 4);
+	clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per3", base + CCM_PCCR0, 18);
 
 	clkdev_add_physbase(clks[per1], MX21_GPT1_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[per1], MX21_GPT2_BASE_ADDR, NULL);
@@ -112,7 +113,7 @@ static int imx21_ccm_probe(struct device_d *dev)
 	clkdev_add_physbase(clks[ipg], MX21_I2C_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[ipg], MX21_SDHC1_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[ipg], MX21_SDHC2_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[per3], MX21_LCDC_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[lcdc_per_gate], MX21_LCDC_BASE_ADDR, NULL);
 
 	return 0;
 }
-- 
1.7.10.4


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[PATCH 07/10] ARM i.MX27: Add lcdc per gate

[Sascha Hauer]

This gate is used to enable/disable the lcd controller, hence we
need a gate for it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/clk-imx27.c |   25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index abfde0f..881be22 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -29,7 +29,7 @@
 enum mx27_clks {
 	dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
 	per2_div, per3_div, per4_div, usb_div, cpu_sel,	clko_sel, cpu_div, clko_div,
-	clko_en, clk_max
+	clko_en, lcdc_per_gate, clk_max
 };
 
 static struct clk *clks[clk_max];
@@ -72,18 +72,18 @@ static int imx27_ccm_probe(struct device_d *dev)
 	base = dev_request_mem_region(dev, 0);
 
 	writel(PCCR0_SDHC3_EN | PCCR0_SDHC2_EN | PCCR0_SDHC1_EN |
-			PCCR0_PWM_EN | PCCR0_KPP_EN | PCCR0_IIM_EN | PCCR0_I2C2_EN |
-			PCCR0_I2C1_EN | PCCR0_GPT6_EN | PCCR0_GPT5_EN | PCCR0_GPT4_EN |
-			PCCR0_GPT3_EN | PCCR0_GPT2_EN | PCCR0_GPT1_EN | PCCR0_GPIO_EN |
-			PCCR0_FEC_EN | PCCR0_CSPI3_EN | PCCR0_CSPI2_EN | PCCR0_CSPI1_EN,
+			PCCR0_PWM_EN | PCCR0_KPP_EN | PCCR0_LCDC_EN | PCCR0_IIM_EN |
+			PCCR0_I2C2_EN | PCCR0_I2C1_EN | PCCR0_GPT6_EN | PCCR0_GPT5_EN |
+			PCCR0_GPT4_EN | PCCR0_GPT3_EN | PCCR0_GPT2_EN | PCCR0_GPT1_EN |
+			PCCR0_GPIO_EN | PCCR0_FEC_EN | PCCR0_CSPI3_EN | PCCR0_CSPI2_EN |
+			PCCR0_CSPI1_EN,
 			base + CCM_PCCR0);
 
-	writel(PCCR1_NFC_BAUDEN | PCCR1_PERCLK4_EN | PCCR1_PERCLK3_EN |
-		       PCCR1_PERCLK2_EN | PCCR1_PERCLK1_EN | PCCR1_HCLK_USB |
-		       PCCR1_HCLK_FEC | PCCR1_HCLK_EMI | PCCR1_WDT_EN | PCCR1_USB_EN |
-		       PCCR1_UART6_EN | PCCR1_UART5_EN | PCCR1_UART4_EN |
-		       PCCR1_UART3_EN | PCCR1_UART2_EN | PCCR1_UART1_EN,
-		       base + CCM_PCCR1);
+	writel(PCCR1_NFC_BAUDEN | PCCR1_PERCLK4_EN | PCCR1_PERCLK2_EN | PCCR1_PERCLK1_EN |
+			PCCR1_HCLK_USB | PCCR1_HCLK_LCDC | PCCR1_HCLK_FEC | PCCR1_HCLK_EMI |
+			PCCR1_WDT_EN | PCCR1_USB_EN | PCCR1_UART6_EN | PCCR1_UART5_EN |
+			PCCR1_UART4_EN | PCCR1_UART3_EN | PCCR1_UART2_EN | PCCR1_UART1_EN,
+			base + CCM_PCCR1);
 
 	clks[dummy] = clk_fixed("dummy", 0);
 	clks[ckih] = clk_fixed("ckih", 26000000);
@@ -115,6 +115,7 @@ static int imx27_ccm_probe(struct device_d *dev)
 	else
 		clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 13, 3);
 	clks[clko_div] = imx_clk_divider("clko_div", "clko_sel", base + CCM_PCDR0, 22, 3);
+	clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per3_div", base + CCM_PCCR1, 7);
 
 	clkdev_add_physbase(clks[per1_div], MX27_GPT1_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[per1_div], MX27_GPT2_BASE_ADDR, NULL);
@@ -136,7 +137,7 @@ static int imx27_ccm_probe(struct device_d *dev)
 	clkdev_add_physbase(clks[per2_div], MX27_SDHC1_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[per2_div], MX27_SDHC2_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[per2_div], MX27_SDHC3_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[per3_div], MX27_LCDC_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[lcdc_per_gate], MX27_LCDC_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[ipg], MX27_FEC_BASE_ADDR, NULL);
 
 	return 0;
-- 
1.7.10.4


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[PATCH 08/10] ARM i.MX25: Add lcdc per gate

[Sascha Hauer]

This gate is used to enable/disable the lcd controller, hence we
need a gate for it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/clk-imx25.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 3a141c2..2587994 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -55,7 +55,7 @@ enum mx25_clks {
 	per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel,
 	per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5,
 	per6, per7, per8, per9, per10, per11, per12, per13, per14, per15,
-	clk_max
+	lcdc_per_gate, clk_max
 };
 
 static struct clk *clks[clk_max];
@@ -132,6 +132,7 @@ static int imx25_ccm_probe(struct device_d *dev)
 	clks[per13] = imx_clk_divider("per13", "per13_sel", base + CCM_PCDR3, 8, 6);
 	clks[per14] = imx_clk_divider("per14", "per14_sel", base + CCM_PCDR3, 16, 6);
 	clks[per15] = imx_clk_divider("per15", "per15_sel", base + CCM_PCDR3, 24, 6);
+	clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per7", base + CCM_CGCR0, 7);
 
 	clkdev_add_physbase(clks[per15], MX25_UART1_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[per15], MX25_UART2_BASE_ADDR, NULL);
@@ -148,6 +149,7 @@ static int imx25_ccm_probe(struct device_d *dev)
 	clkdev_add_physbase(clks[ipg], MX25_CSPI3_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[per3], MX25_ESDHC1_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[per4], MX25_ESDHC2_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[lcdc_per_gate], MX25_LCDC_BASE_ADDR, NULL);
 
 	return 0;
 }
-- 
1.7.10.4


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[PATCH 09/10] video i.MX: Use regular clk_[en|dis]able functions

[Sascha Hauer]

This controller has no enable bit. It is always on once the
pixel clock is provided. This patch switches the driver to use
regular clk functions instead of SoC specific register hacking.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/video/imx.c |   44 +++++---------------------------------------
 1 file changed, 5 insertions(+), 39 deletions(-)

diff --git a/drivers/video/imx.c b/drivers/video/imx.c
index 9406b36..ae4c671 100644
--- a/drivers/video/imx.c
+++ b/drivers/video/imx.c
@@ -252,19 +252,9 @@ static void imxfb_enable_controller(struct fb_info *info)
 	struct imxfb_info *fbi = info->priv;
 
 	writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR);
-#ifdef CONFIG_ARCH_IMX21
-	PCCR0 |= PCCR0_PERCLK3_EN | PCCR0_HCLK_LCDC_EN;
-#endif
-#ifdef CONFIG_ARCH_IMX27
-	PCCR0 |= PCCR0_LCDC_EN;
-	PCCR1 |= PCCR1_HCLK_LCDC;
-#endif
-#ifdef CONFIG_ARCH_IMX25
-	writel(readl(IMX_CCM_BASE + CCM_CGCR0) | (1 << 24) | (1 << 7),
-		IMX_CCM_BASE + CCM_CGCR0);
-	writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 29),
-		IMX_CCM_BASE + CCM_CGCR1);
-#endif
+
+	clk_enable(fbi->clk);
+
 	if (fbi->enable)
 		fbi->enable(1);
 }
@@ -277,19 +267,8 @@ static void imxfb_disable_controller(struct fb_info *info)
 		fbi->enable(0);
 
 	writel(0, fbi->regs + LCDC_RMCR);
-#ifdef CONFIG_ARCH_IMX21
-	PCCR0 &= ~(PCCR0_PERCLK3_EN | PCCR0_HCLK_LCDC_EN);
-#endif
-#ifdef CONFIG_ARCH_IMX27
-	PCCR0 &= ~PCCR0_LCDC_EN;
-	PCCR1 &= ~PCCR1_HCLK_LCDC;
-#endif
-#ifdef CONFIG_ARCH_IMX25
-	writel(readl(IMX_CCM_BASE + CCM_CGCR0) & ~((1 << 24) | (1 << 7)),
-		IMX_CCM_BASE + CCM_CGCR0);
-	writel(readl(IMX_CCM_BASE + CCM_CGCR1) & ~(1 << 29),
-		IMX_CCM_BASE + CCM_CGCR1);
-#endif
+
+	clk_disable(fbi->clk);
 }
 
 /*
@@ -541,19 +520,6 @@ static int imxfb_probe(struct device_d *dev)
 	if (!pdata)
 		return -ENODEV;
 
-#ifdef CONFIG_ARCH_IMX21
-	PCCR0 &= ~(PCCR0_PERCLK3_EN | PCCR0_HCLK_LCDC_EN);
-#endif
-#ifdef CONFIG_ARCH_IMX27
-	PCCR0 &= ~PCCR0_LCDC_EN;
-	PCCR1 &= ~PCCR1_HCLK_LCDC;
-#endif
-#ifdef CONFIG_ARCH_IMX25
-	writel(readl(IMX_CCM_BASE + CCM_CGCR0) & ~((1 << 24) | (1 << 7)),
-		IMX_CCM_BASE + CCM_CGCR0);
-	writel(readl(IMX_CCM_BASE + CCM_CGCR1) & ~(1 << 29),
-		IMX_CCM_BASE + CCM_CGCR1);
-#endif
 	if (!pdata->num_modes) {
 		dev_err(dev, "no modes. bailing out\n");
 		return -EINVAL;
-- 
1.7.10.4


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[PATCH 10/10] ARM i.MX: Enable clocks in common place

[Sascha Hauer]

On i.MX we enable all necessary clocks during startup of the clock
controller driver, so we do not need the register hacking in the drivers
anymore.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c |   15 ---------------
 arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c |    1 -
 arch/arm/boards/guf-neso/lowlevel.c               |    2 --
 arch/arm/boards/imx21ads/imx21ads.c               |    1 -
 arch/arm/boards/pcm038/lowlevel.c                 |    2 --
 arch/arm/boards/pcm038/pcm038.c                   |    4 ----
 arch/arm/boards/pcm038/pcm970.c                   |    1 -
 arch/arm/boards/phycard-i.MX27/pca100.c           |    4 ----
 arch/arm/mach-imx/clocksource.c                   |   12 ------------
 drivers/mtd/nand/nand_imx.c                       |    6 ------
 drivers/net/fec_imx.c                             |    4 +---
 11 files changed, 1 insertion(+), 51 deletions(-)

diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
index bf3cbc3..39ed3b0 100644
--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
+++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
@@ -250,18 +250,3 @@ void __bare_init nand_boot(void)
 	imx_nand_load_image(_text, barebox_image_size);
 }
 #endif
-
-static int eukrea_cpuimx25_core_init(void) {
-	/* enable UART1, FEC, SDHC, USB & I2C clock */
-	writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR0) | (1 << 6) | (1 << 23)
-		| (1 << 15) | (1 << 21) | (1 << 3) | (1 << 28),
-		MX25_CCM_BASE_ADDR + CCM_CGCR0);
-	writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR1) | (1 << 23) | (1 << 15)
-		| (1 << 13), MX25_CCM_BASE_ADDR + CCM_CGCR1);
-	writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR2) | (1 << 14),
-		MX25_CCM_BASE_ADDR + CCM_CGCR2);
-
-	return 0;
-}
-
-core_initcall(eukrea_cpuimx25_core_init);
diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
index cff4f77..57c04c4 100644
--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
+++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
@@ -194,7 +194,6 @@ static int eukrea_cpuimx27_devices_init(void)
 #endif
 	imx27_add_nand(&nand_info);
 
-	PCCR0 |= PCCR0_I2C1_EN;
 	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
 	imx27_add_i2c0(NULL);
 
diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c
index 52fe6cf..e2e3c78 100644
--- a/arch/arm/boards/guf-neso/lowlevel.c
+++ b/arch/arm/boards/guf-neso/lowlevel.c
@@ -35,8 +35,6 @@ static void __bare_init __naked insdram(void)
 {
 	uint32_t r;
 
-	PCCR1 |= PCCR1_NFC_BAUDEN;
-
 	/* setup a stack to be able to call imx_nand_load_image() */
 	r = STACK_BASE + STACK_SIZE - 12;
 	__asm__ __volatile__("mov sp, %0" : : "r"(r));
diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c
index 22406be..26604a9 100644
--- a/arch/arm/boards/imx21ads/imx21ads.c
+++ b/arch/arm/boards/imx21ads/imx21ads.c
@@ -193,7 +193,6 @@ console_initcall(mx21ads_console_init);
 #ifdef CONFIG_NAND_IMX_BOOT
 void __bare_init nand_boot(void)
 {
-	PCCR0 |= PCCR0_NFC_EN;
 	imx_nand_load_image(_text, barebox_image_size);
 	board_init_lowlevel_return();
 }
diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c
index 7ecff3a..bed1c3f 100644
--- a/arch/arm/boards/pcm038/lowlevel.c
+++ b/arch/arm/boards/pcm038/lowlevel.c
@@ -36,8 +36,6 @@ static void __bare_init __naked insdram(void)
 {
 	uint32_t r;
 
-	PCCR1 |= PCCR1_NFC_BAUDEN;
-
 	/* setup a stack to be able to call imx_nand_load_image() */
 	r = STACK_BASE + STACK_SIZE - 12;
 	__asm__ __volatile__("mov sp, %0" : : "r"(r));
diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c
index 58b1ec9..dce852b 100644
--- a/arch/arm/boards/pcm038/pcm038.c
+++ b/arch/arm/boards/pcm038/pcm038.c
@@ -281,9 +281,6 @@ static int pcm038_devices_init(void)
 	for (i = 0; i < ARRAY_SIZE(mode); i++)
 		imx_gpio_mode(mode[i]);
 
-	PCCR0 |= PCCR0_CSPI1_EN;
-	PCCR1 |= PCCR1_PERCLK2_EN;
-
 	spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
 	imx27_add_spi0(&pcm038_spi_0_data);
 
@@ -293,7 +290,6 @@ static int pcm038_devices_init(void)
 	imx27_add_nand(&nand_info);
 	imx27_add_fb(&pcm038_fb_data);
 
-	PCCR0 |= PCCR0_I2C1_EN | PCCR0_I2C2_EN;
 	imx27_add_i2c0(NULL);
 	imx27_add_i2c1(NULL);
 
diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c
index a6b6c83..5723fb3 100644
--- a/arch/arm/boards/pcm038/pcm970.c
+++ b/arch/arm/boards/pcm038/pcm970.c
@@ -162,7 +162,6 @@ static void pcm970_mmc_init(void)
 	for (i = 0; i < ARRAY_SIZE(mode); i++)
 		imx_gpio_mode(mode[i]);
 
-	PCCR0 |= PCCR0_SDHC2_EN;
 	imx27_add_mmc1(NULL);
 }
 
diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
index 45e59fb..b8abd1b 100644
--- a/arch/arm/boards/phycard-i.MX27/pca100.c
+++ b/arch/arm/boards/phycard-i.MX27/pca100.c
@@ -279,8 +279,6 @@ static int pca100_devices_init(void)
 		PD18_PF_I2C_CLK,
 	};
 
-	PCCR0 |= PCCR0_SDHC2_EN;
-
 	pca100_usb_init();
 
 	/* initizalize gpios */
@@ -292,8 +290,6 @@ static int pca100_devices_init(void)
 	imx27_add_mmc1(NULL);
 	imx27_add_fb(&pca100_fb_data);
 
-	PCCR1 |= PCCR1_PERCLK2_EN;
-
 #ifdef CONFIG_USB
 	pca100_usb_register();
 #endif
diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c
index 69a688c..31e1fdf 100644
--- a/arch/arm/mach-imx/clocksource.c
+++ b/arch/arm/mach-imx/clocksource.c
@@ -108,18 +108,6 @@ static int imx_gpt_probe(struct device_d *dev)
 	/* setup GP Timer 1 */
 	writel(TCTL_SWR, timer_base + GPT_TCTL);
 
-#ifdef CONFIG_ARCH_IMX21
-	PCCR1 |= PCCR1_GPT1_EN;
-#endif
-#ifdef CONFIG_ARCH_IMX27
-	PCCR0 |= PCCR0_GPT1_EN;
-	PCCR1 |= PCCR1_PERCLK1_EN;
-#endif
-#ifdef CONFIG_ARCH_IMX25
-	writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 19),
-		IMX_CCM_BASE + CCM_CGCR1);
-#endif
-
 	for (i = 0; i < 100; i++)
 		writel(0, timer_base + GPT_TCTL); /* We have no udelay by now */
 
diff --git a/drivers/mtd/nand/nand_imx.c b/drivers/mtd/nand/nand_imx.c
index b1b7f55..0489d09 100644
--- a/drivers/mtd/nand/nand_imx.c
+++ b/drivers/mtd/nand/nand_imx.c
@@ -1107,12 +1107,6 @@ static int __init imxnd_probe(struct device_d *dev)
 	struct nand_ecclayout *oob_smallpage, *oob_largepage, *oob_4kpage;
 	int err = 0;
 
-#ifdef CONFIG_ARCH_IMX27
-	PCCR1 |= PCCR1_NFC_BAUDEN;
-#endif
-#ifdef CONFIG_ARCH_IMX21
-	PCCR0 |= PCCR0_NFC_EN;
-#endif
 	/* Allocate memory for MTD device structure and private data */
 	host = kzalloc(sizeof(struct imx_nand_host) + NAND_MAX_PAGESIZE +
 			NAND_MAX_OOBSIZE, GFP_KERNEL);
diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c
index b95c4f0..cdb4a85 100644
--- a/drivers/net/fec_imx.c
+++ b/drivers/net/fec_imx.c
@@ -628,9 +628,7 @@ static int fec_probe(struct device_d *dev)
 	struct fec_priv *fec;
 	void *base;
 	int ret;
-#ifdef CONFIG_ARCH_IMX27
-	PCCR0 |= PCCR0_FEC_EN;
-#endif
+
 	fec = xzalloc(sizeof(*fec));
 	edev = &fec->edev;
 	dev->priv = fec;
-- 
1.7.10.4


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Re: [PATCH 05/10] ARM i.MX25: Enable all needed clocks during startup

[Roberto Nibali]

Hi

>  arch/arm/mach-imx/clk-imx25.c |   16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
> index 3b9588c..3a141c2 100644
> --- a/arch/arm/mach-imx/clk-imx25.c
> +++ b/arch/arm/mach-imx/clk-imx25.c
> @@ -76,9 +76,19 @@ static int imx25_ccm_probe(struct device_d *dev)
>
>         base = dev_request_mem_region(dev, 0);
>
> -       writel(0x10e88578, base + CCM_CGCR0);
> -       writel(0x0478e1e0, base + CCM_CGCR0);
> -       writel(0x0007c400, base + CCM_CGCR0);
> +       writel((1 << 3) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 8) | (1 << 9) |
> +                       (1 << 10) | (1 << 15) | (1 << 19) | (1 << 21) | (1 << 22) |
> +                       (1 << 22) | (1 << 23) | (1 << 24) | (1 << 28),

(1<<22) does not need to be written twice, I'm sure the bit is safe in
silicon :).

> +                       base + CCM_CGCR0);
> +
> +       writel((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 13) | (1 << 14) |
> +                       (1 << 15) | (1 << 19) | (1 << 20) | (1 << 21) | (1 << 22) |
> +                       (1 << 26) | (1 << 29) | (1 << 31),
> +                       base + CCM_CGCR1);
> +
> +       writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 10) | (1 << 13) | (1 << 14) |
> +                       (1 << 15) | (1 << 16) | (1 << 17) | (1 << 18),
> +                       base + CCM_CGCR2);

Quite a change from writing 0x15692B58 (sum) to CGCR0, enabling PER
clocks esdhc1, esdhc2, i2c, nfc, owire, sim1, ssi1, and AHB clocks
ata, emi, esdhc1, esdhc2, lcdc, sdma, usbotg, to now enabling the
following clocks:

PER: esdhc1, esdhc2, i2c, nfc, owire, pwm(!), uart (!)
AHB: emi, esdhc1, esdhc2, fec, lcdc, usbotg

Why not enable all clocks (i.e. sim1, sim2, ssi1, ssi2)? Maybe because
we have no drivers (yet)? Or does it not matter, because each platform
driver is required to set the clocks anyway in the init routine?

With regard to CGCR1 and CGCR2, the following clock outputs get
enabled (maybe for changelog):

IPG: cspi1, cspi2, cspi3, esdhc1, esdhc2, fec, gpt1, gpt2, gpt3, gpt4,
iim, LCDC_EN, pwm1, pwm2, pwm3, pwm4, spba, tsc, uart1, uart2, uart3,
uart4, uart5.

Cheers
Roberto

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Re: [PATCH 05/10] ARM i.MX25: Enable all needed clocks during startup

[Sascha Hauer]

On Mon, Oct 08, 2012 at 10:49:21PM +0200, Roberto Nibali wrote:
> Hi
> 
> >  arch/arm/mach-imx/clk-imx25.c |   16 +++++++++++++---
> >  1 file changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
> > index 3b9588c..3a141c2 100644
> > --- a/arch/arm/mach-imx/clk-imx25.c
> > +++ b/arch/arm/mach-imx/clk-imx25.c
> > @@ -76,9 +76,19 @@ static int imx25_ccm_probe(struct device_d *dev)
> >
> >         base = dev_request_mem_region(dev, 0);
> >
> > -       writel(0x10e88578, base + CCM_CGCR0);
> > -       writel(0x0478e1e0, base + CCM_CGCR0);
> > -       writel(0x0007c400, base + CCM_CGCR0);
> > +       writel((1 << 3) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 8) | (1 << 9) |
> > +                       (1 << 10) | (1 << 15) | (1 << 19) | (1 << 21) | (1 << 22) |
> > +                       (1 << 22) | (1 << 23) | (1 << 24) | (1 << 28),
> 
> (1<<22) does not need to be written twice, I'm sure the bit is safe in
> silicon :).

Sure ;) Will fix.

> 
> > +                       base + CCM_CGCR0);
> > +
> > +       writel((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 13) | (1 << 14) |
> > +                       (1 << 15) | (1 << 19) | (1 << 20) | (1 << 21) | (1 << 22) |
> > +                       (1 << 26) | (1 << 29) | (1 << 31),
> > +                       base + CCM_CGCR1);
> > +
> > +       writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 10) | (1 << 13) | (1 << 14) |
> > +                       (1 << 15) | (1 << 16) | (1 << 17) | (1 << 18),
> > +                       base + CCM_CGCR2);
> 
> Quite a change from writing 0x15692B58 (sum) to CGCR0, enabling PER
> clocks esdhc1, esdhc2, i2c, nfc, owire, sim1, ssi1, and AHB clocks
> ata, emi, esdhc1, esdhc2, lcdc, sdma, usbotg, to now enabling the
> following clocks:
> 
> PER: esdhc1, esdhc2, i2c, nfc, owire, pwm(!), uart (!)
> AHB: emi, esdhc1, esdhc2, fec, lcdc, usbotg
> 
> Why not enable all clocks (i.e. sim1, sim2, ssi1, ssi2)? Maybe because
> we have no drivers (yet)?

I really hope we do not get sound support in barebox...

> Or does it not matter, because each platform
> driver is required to set the clocks anyway in the init routine?

No, the strategy I want to follow is that we enable all necessary clocks
for barebox during startup. Barebox normally does not run long enough to
waste a significant amount og energy. The kernel will turn of the
unneeded clocks anyway, so I think it's just not worth the effort (and
binary size) to add proper clk gate support.

> 
> With regard to CGCR1 and CGCR2, the following clock outputs get
> enabled (maybe for changelog):
> 
> IPG: cspi1, cspi2, cspi3, esdhc1, esdhc2, fec, gpt1, gpt2, gpt3, gpt4,
> iim, LCDC_EN, pwm1, pwm2, pwm3, pwm4, spba, tsc, uart1, uart2, uart3,
> uart4, uart5.

Ok, can add this.

Thanks
  Sascha

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Re: [PATCH 05/10] ARM i.MX25: Enable all needed clocks during startup

[Roberto Nibali]

>> > +                       base + CCM_CGCR0);
>> > +
>> > +       writel((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 13) | (1 << 14) |
>> > +                       (1 << 15) | (1 << 19) | (1 << 20) | (1 << 21) | (1 << 22) |
>> > +                       (1 << 26) | (1 << 29) | (1 << 31),
>> > +                       base + CCM_CGCR1);
>> > +
>> > +       writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 10) | (1 << 13) | (1 << 14) |
>> > +                       (1 << 15) | (1 << 16) | (1 << 17) | (1 << 18),
>> > +                       base + CCM_CGCR2);
>>
>> Quite a change from writing 0x15692B58 (sum) to CGCR0, enabling PER
>> clocks esdhc1, esdhc2, i2c, nfc, owire, sim1, ssi1, and AHB clocks
>> ata, emi, esdhc1, esdhc2, lcdc, sdma, usbotg, to now enabling the
>> following clocks:
>>
>> PER: esdhc1, esdhc2, i2c, nfc, owire, pwm(!), uart (!)
>> AHB: emi, esdhc1, esdhc2, fec, lcdc, usbotg
>>
>> Why not enable all clocks (i.e. sim1, sim2, ssi1, ssi2)? Maybe because
>> we have no drivers (yet)?
>
> I really hope we do not get sound support in barebox...

Famous last words ... some marketing executive will find a reason to
do so in the future ;).

On a more serious note, I have in the past worked as a freelancer on a
project where they used sim1 and sim2, albeit there was no
functionality implemented into the boot loader. So I reckon your clock
enable selection is fine as is.

>> Or does it not matter, because each platform
>> driver is required to set the clocks anyway in the init routine?
>
> No, the strategy I want to follow is that we enable all necessary clocks
> for barebox during startup. Barebox normally does not run long enough to
> waste a significant amount og energy. The kernel will turn of the
> unneeded clocks anyway, so I think it's just not worth the effort (and
> binary size) to add proper clk gate support.

Fair enough.

>> IPG: cspi1, cspi2, cspi3, esdhc1, esdhc2, fec, gpt1, gpt2, gpt3, gpt4,
>> iim, LCDC_EN, pwm1, pwm2, pwm3, pwm4, spba, tsc, uart1, uart2, uart3,
>> uart4, uart5.
>
> Ok, can add this.

Cheers
Roberto

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Re: [PATCH 05/10] ARM i.MX25: Enable all needed clocks during startup

[Sascha Hauer]

On Mon, Oct 08, 2012 at 09:44:14PM +0200, Sascha Hauer wrote:
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm/mach-imx/clk-imx25.c |   16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
> index 3b9588c..3a141c2 100644
> --- a/arch/arm/mach-imx/clk-imx25.c
> +++ b/arch/arm/mach-imx/clk-imx25.c
> @@ -76,9 +76,19 @@ static int imx25_ccm_probe(struct device_d *dev)
>  
>  	base = dev_request_mem_region(dev, 0);
>  
> -	writel(0x10e88578, base + CCM_CGCR0);
> -	writel(0x0478e1e0, base + CCM_CGCR0);
> -	writel(0x0007c400, base + CCM_CGCR0);

I applied this one to master as I noticed the clk setup was broken, all
values were written to CCM_CGCR0 :(


> +	writel((1 << 3) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 8) | (1 << 9) |
> +			(1 << 10) | (1 << 15) |	(1 << 19) | (1 << 21) | (1 << 22) |
> +			(1 << 22) | (1 << 23) | (1 << 24) | (1 << 28),
> +			base + CCM_CGCR0);
> +
> +	writel((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 13) | (1 << 14) |
> +			(1 << 15) | (1 << 19) | (1 << 20) | (1 << 21) | (1 << 22) |
> +			(1 << 26) | (1 << 29) | (1 << 31),
> +			base + CCM_CGCR1);
> +
> +	writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 10) | (1 << 13) | (1 << 14) |
> +			(1 << 15) | (1 << 16) | (1 << 17) | (1 << 18),
> +			base + CCM_CGCR2);
>  
>  	clks[dummy] = clk_fixed("dummy", 0);
>  	clks[osc] = clk_fixed("osc", 24000000);
> -- 
> 1.7.10.4
> 
> 

-- 
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