* [PATCH 1/6] ARM i.MX6: fix ethernet PLL rate
2012-12-06 13:29 [PATCH] i.MX (and one generic) clock patches Sascha Hauer
@ 2012-12-06 13:29 ` Sascha Hauer
2012-12-06 13:29 ` [PATCH 2/6] ARM i.MX6: rename PLLs according to datasheet Sascha Hauer
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Sascha Hauer @ 2012-12-06 13:29 UTC (permalink / raw)
To: barebox
The ethernet PLL has a fixed frequency of 500MHz. What is adjustable
are additional dividers which we better describe separately.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/clk-pllv3.c | 63 +----------------------------------------
1 file changed, 1 insertion(+), 62 deletions(-)
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index e337e87..f400a7c 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -261,74 +261,13 @@ static const struct clk_ops clk_pllv3_av_ops = {
static unsigned long clk_pllv3_enet_recalc_rate(struct clk *clk,
unsigned long parent_rate)
{
- struct clk_pllv3 *pll = to_clk_pllv3(clk);
- u32 div = readl(pll->base) & pll->div_mask;
-
- switch (div) {
- case 0:
- return 25000000;
- case 1:
- return 50000000;
- case 2:
- return 100000000;
- case 3:
- return 125000000;
- }
-
- return 0;
-}
-
-static long clk_pllv3_enet_round_rate(struct clk *clk, unsigned long rate,
- unsigned long *prate)
-{
- if (rate >= 125000000)
- rate = 125000000;
- else if (rate >= 100000000)
- rate = 100000000;
- else if (rate >= 50000000)
- rate = 50000000;
- else
- rate = 25000000;
- return rate;
-}
-
-static int clk_pllv3_enet_set_rate(struct clk *clk, unsigned long rate,
- unsigned long parent_rate)
-{
- struct clk_pllv3 *pll = to_clk_pllv3(clk);
- u32 val, div;
-
- switch (rate) {
- case 25000000:
- div = 0;
- break;
- case 50000000:
- div = 1;
- break;
- case 100000000:
- div = 2;
- break;
- case 125000000:
- div = 3;
- break;
- default:
- return -EINVAL;
- }
-
- val = readl(pll->base);
- val &= ~pll->div_mask;
- val |= div;
- writel(val, pll->base);
-
- return 0;
+ return 500000000;
}
static const struct clk_ops clk_pllv3_enet_ops = {
.enable = clk_pllv3_enable,
.disable = clk_pllv3_disable,
.recalc_rate = clk_pllv3_enet_recalc_rate,
- .round_rate = clk_pllv3_enet_round_rate,
- .set_rate = clk_pllv3_enet_set_rate,
};
static const struct clk_ops clk_pllv3_mlb_ops = {
--
1.7.10.4
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^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 2/6] ARM i.MX6: rename PLLs according to datasheet
2012-12-06 13:29 [PATCH] i.MX (and one generic) clock patches Sascha Hauer
2012-12-06 13:29 ` [PATCH 1/6] ARM i.MX6: fix ethernet PLL rate Sascha Hauer
@ 2012-12-06 13:29 ` Sascha Hauer
2012-12-06 13:29 ` [PATCH 3/6] clk: Add clk table based divider support Sascha Hauer
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Sascha Hauer @ 2012-12-06 13:29 UTC (permalink / raw)
To: barebox
In recent reference manuals the plls were renumbered. PLL8 now is
PLL6 and vice versa. Change the code according to the reference
manual to avoid confusion.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/clk-imx6.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c
index a1da47a..e2385ad 100644
--- a/arch/arm/mach-imx/clk-imx6.c
+++ b/arch/arm/mach-imx/clk-imx6.c
@@ -81,7 +81,7 @@ enum mx6q_clks {
gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
- pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
+ pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
clk_max
};
@@ -192,9 +192,9 @@ static int imx6_ccm_probe(struct device_d *dev)
clks[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x2000, 0x3);
clks[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x2000, 0x7f);
clks[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x2000, 0x7f);
- clks[pll6_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll6_mlb", "osc", base + 0xd0, 0x2000, 0x0);
+ clks[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x2000, 0x0);
clks[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3);
- clks[pll8_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll8_enet", "osc", base + 0xe0, 0x182000, 0x3);
+ clks[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x182000, 0x3);
/* name parent_name reg idx */
clks[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 3/6] clk: Add clk table based divider support
2012-12-06 13:29 [PATCH] i.MX (and one generic) clock patches Sascha Hauer
2012-12-06 13:29 ` [PATCH 1/6] ARM i.MX6: fix ethernet PLL rate Sascha Hauer
2012-12-06 13:29 ` [PATCH 2/6] ARM i.MX6: rename PLLs according to datasheet Sascha Hauer
@ 2012-12-06 13:29 ` Sascha Hauer
2012-12-06 13:29 ` [PATCH 4/6] ARM i.MX6 pllv3: Do not use delay functions Sascha Hauer
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Sascha Hauer @ 2012-12-06 13:29 UTC (permalink / raw)
To: barebox
For easy support of table based dividers.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clk/Makefile | 2 +-
drivers/clk/clk-divider-table.c | 119 +++++++++++++++++++++++++++++++++++++++
include/linux/clk.h | 10 ++++
3 files changed, 130 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/clk-divider-table.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 3cc7163..656b859 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,3 +1,3 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed.o clk-divider.o clk-fixed-factor.o \
- clk-mux.o clk-gate.o
+ clk-mux.o clk-gate.o clk-divider-table.o
obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
diff --git a/drivers/clk/clk-divider-table.c b/drivers/clk/clk-divider-table.c
new file mode 100644
index 0000000..204e24d
--- /dev/null
+++ b/drivers/clk/clk-divider-table.c
@@ -0,0 +1,119 @@
+/*
+ * clk-divider-table.c - generic barebox clock support. Based on Linux clk support
+ *
+ * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <common.h>
+#include <io.h>
+#include <malloc.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+struct clk_divider_table {
+ struct clk clk;
+ u8 shift;
+ u8 width;
+ void __iomem *reg;
+ const char *parent;
+ const struct clk_div_table *table;
+ int table_size;
+ int max_div_index;
+};
+
+static int clk_divider_set_rate(struct clk *clk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_divider_table *div =
+ container_of(clk, struct clk_divider_table, clk);
+ unsigned int val;
+ int i, div_index = -1;
+ unsigned long best = 0;
+
+ if (rate > parent_rate)
+ rate = parent_rate;
+ if (rate < parent_rate / div->table[div->max_div_index].div)
+ rate = parent_rate / div->table[div->max_div_index].div;
+
+ for (i = 0; i < div->table_size; i++) {
+ unsigned long now = parent_rate / div->table[i].div;
+
+ if (now <= rate && now >= best) {
+ best = now;
+ div_index = i;
+ }
+ }
+
+ val = readl(div->reg);
+ val &= ~(((1 << div->width) - 1) << div->shift);
+ val |= div_index << div->shift;
+ writel(val, div->reg);
+
+ return 0;
+}
+
+static unsigned long clk_divider_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_divider_table *div =
+ container_of(clk, struct clk_divider_table, clk);
+ unsigned int val;
+
+ val = readl(div->reg) >> div->shift;
+ val &= (1 << div->width) - 1;
+
+ if (val >= div->table_size)
+ return 0;
+
+ return parent_rate / div->table[val].div;
+}
+
+struct clk_ops clk_divider_table_ops = {
+ .set_rate = clk_divider_set_rate,
+ .recalc_rate = clk_divider_recalc_rate,
+};
+
+struct clk *clk_divider_table(const char *name,
+ const char *parent, void __iomem *reg, u8 shift, u8 width,
+ const struct clk_div_table *table)
+{
+ struct clk_divider_table *div = xzalloc(sizeof(*div));
+ const struct clk_div_table *clkt;
+ int ret, max_div = 0;
+
+ div->shift = shift;
+ div->reg = reg;
+ div->width = width;
+ div->parent = parent;
+ div->clk.ops = &clk_divider_table_ops;
+ div->clk.name = name;
+ div->clk.parent_names = &div->parent;
+ div->clk.num_parents = 1;
+ div->table = table;
+
+ for (clkt = div->table; clkt->div; clkt++) {
+ if (clkt->div > max_div) {
+ max_div = clkt->div;
+ div->max_div_index = div->table_size;
+ }
+ div->table_size++;
+ }
+
+ ret = clk_register(&div->clk);
+ if (ret) {
+ free(div);
+ return ERR_PTR(ret);
+ }
+
+ return &div->clk;
+}
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 00588bf..91574f2 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -181,9 +181,19 @@ struct clk {
struct clk **parents;
};
+#define CLK_ALWAYS_ENABLED (1 << 0)
+
+struct clk_div_table {
+ unsigned int val;
+ unsigned int div;
+};
+
struct clk *clk_fixed(const char *name, int rate);
struct clk *clk_divider(const char *name, const char *parent,
void __iomem *reg, u8 shift, u8 width);
+struct clk *clk_divider_table(const char *name,
+ const char *parent, void __iomem *reg, u8 shift, u8 width,
+ const struct clk_div_table *table);
struct clk *clk_fixed_factor(const char *name,
const char *parent, unsigned int mult, unsigned int div);
struct clk *clk_mux(const char *name, void __iomem *reg,
--
1.7.10.4
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^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 4/6] ARM i.MX6 pllv3: Do not use delay functions
2012-12-06 13:29 [PATCH] i.MX (and one generic) clock patches Sascha Hauer
` (2 preceding siblings ...)
2012-12-06 13:29 ` [PATCH 3/6] clk: Add clk table based divider support Sascha Hauer
@ 2012-12-06 13:29 ` Sascha Hauer
2012-12-06 13:29 ` [PATCH 5/6] ARM i.MX6 clk: remove gate_mask from pllv3 Sascha Hauer
2012-12-06 13:29 ` [PATCH 6/6] ARM i.MX6: Add sata device Sascha Hauer
5 siblings, 0 replies; 7+ messages in thread
From: Sascha Hauer @ 2012-12-06 13:29 UTC (permalink / raw)
To: barebox
We may be called very early, before the timer is available,
so don't use it here.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/clk-pllv3.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index f400a7c..cc9621c 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -46,7 +46,7 @@ static int clk_pllv3_enable(struct clk *clk)
{
struct clk_pllv3 *pll = to_clk_pllv3(clk);
u32 val;
- int ret;
+ int timeout = 10000;
val = readl(pll->base);
val &= ~BM_PLL_BYPASS;
@@ -57,9 +57,13 @@ static int clk_pllv3_enable(struct clk *clk)
writel(val, pll->base);
/* Wait for PLL to lock */
- ret = wait_on_timeout(10 * MSECOND, !(readl(pll->base) & BM_PLL_LOCK));
- if (ret)
- return ret;
+ while (timeout--) {
+ if (readl(pll->base) & BM_PLL_LOCK)
+ break;
+ }
+
+ if (!timeout)
+ return -ETIMEDOUT;
val = readl(pll->base);
val |= pll->gate_mask;
--
1.7.10.4
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^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 5/6] ARM i.MX6 clk: remove gate_mask from pllv3
2012-12-06 13:29 [PATCH] i.MX (and one generic) clock patches Sascha Hauer
` (3 preceding siblings ...)
2012-12-06 13:29 ` [PATCH 4/6] ARM i.MX6 pllv3: Do not use delay functions Sascha Hauer
@ 2012-12-06 13:29 ` Sascha Hauer
2012-12-06 13:29 ` [PATCH 6/6] ARM i.MX6: Add sata device Sascha Hauer
5 siblings, 0 replies; 7+ messages in thread
From: Sascha Hauer @ 2012-12-06 13:29 UTC (permalink / raw)
To: barebox
Not needed as we will handle the additional gate bits as gate.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/clk-imx6.c | 18 +++++++++---------
arch/arm/mach-imx/clk-pllv3.c | 8 +++-----
arch/arm/mach-imx/clk.h | 2 +-
3 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c
index e2385ad..6f2df17 100644
--- a/arch/arm/mach-imx/clk-imx6.c
+++ b/arch/arm/mach-imx/clk-imx6.c
@@ -186,15 +186,15 @@ static int imx6_ccm_probe(struct device_d *dev)
clks[ckih] = clk_fixed("ckih", ckih_rate);
clks[osc] = clk_fixed("osc", osc_rate);
- /* type name parent_name base gate_mask div_mask */
- clks[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x2000, 0x7f);
- clks[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x2000, 0x1);
- clks[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x2000, 0x3);
- clks[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x2000, 0x7f);
- clks[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x2000, 0x7f);
- clks[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x2000, 0x0);
- clks[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3);
- clks[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x182000, 0x3);
+ /* type name parent_name base div_mask */
+ clks[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
+ clks[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
+ clks[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
+ clks[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
+ clks[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
+ clks[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0);
+ clks[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
+ clks[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
/* name parent_name reg idx */
clks[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index cc9621c..e38dcdf 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -35,7 +35,6 @@ struct clk_pllv3 {
struct clk clk;
void __iomem *base;
bool powerup_set;
- u32 gate_mask;
u32 div_mask;
const char *parent;
};
@@ -66,7 +65,7 @@ static int clk_pllv3_enable(struct clk *clk)
return -ETIMEDOUT;
val = readl(pll->base);
- val |= pll->gate_mask;
+ val |= BM_PLL_ENABLE;
writel(val, pll->base);
return 0;
@@ -78,7 +77,7 @@ static void clk_pllv3_disable(struct clk *clk)
u32 val;
val = readl(pll->base);
- val &= ~pll->gate_mask;
+ val &= ~BM_PLL_ENABLE;
writel(val, pll->base);
val |= BM_PLL_BYPASS;
@@ -281,7 +280,7 @@ static const struct clk_ops clk_pllv3_mlb_ops = {
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent, void __iomem *base,
- u32 gate_mask, u32 div_mask)
+ u32 div_mask)
{
struct clk_pllv3 *pll;
const struct clk_ops *ops;
@@ -310,7 +309,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
ops = &clk_pllv3_ops;
}
pll->base = base;
- pll->gate_mask = gate_mask;
pll->div_mask = div_mask;
pll->parent = parent;
pll->clk.ops = ops;
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 0f30082..4a7298d 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -42,7 +42,7 @@ enum imx_pllv3_type {
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent, void __iomem *base,
- u32 gate_mask, u32 div_mask);
+ u32 div_mask);
struct clk *imx_clk_pfd(const char *name, const char *parent,
void __iomem *reg, u8 idx);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 6/6] ARM i.MX6: Add sata device
2012-12-06 13:29 [PATCH] i.MX (and one generic) clock patches Sascha Hauer
` (4 preceding siblings ...)
2012-12-06 13:29 ` [PATCH 5/6] ARM i.MX6 clk: remove gate_mask from pllv3 Sascha Hauer
@ 2012-12-06 13:29 ` Sascha Hauer
5 siblings, 0 replies; 7+ messages in thread
From: Sascha Hauer @ 2012-12-06 13:29 UTC (permalink / raw)
To: barebox
This also adds and enables the clocks needed for SATA.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/clk-imx6.c | 20 ++++++++++++++++++++
arch/arm/mach-imx/include/mach/devices-imx6.h | 5 +++++
arch/arm/mach-imx/include/mach/imx6-regs.h | 2 ++
3 files changed, 27 insertions(+)
diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c
index 6f2df17..f78d3d2 100644
--- a/arch/arm/mach-imx/clk-imx6.c
+++ b/arch/arm/mach-imx/clk-imx6.c
@@ -83,6 +83,7 @@ enum mx6q_clks {
usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
+ sata_ref, pcie_ref, sata_ref_100m, pcie_ref_125m, enet_ref,
clk_max
};
@@ -169,6 +170,14 @@ static const char *cko1_sels[] = {
"pll4_audio",
};
+static struct clk_div_table clk_enet_ref_table[] = {
+ { .val = 0, .div = 20, },
+ { .val = 1, .div = 10, },
+ { .val = 2, .div = 5, },
+ { .val = 3, .div = 4, },
+ { },
+};
+
static int imx6_ccm_probe(struct device_d *dev)
{
void __iomem *base, *anatop_base, *ccm_base;
@@ -196,6 +205,13 @@ static int imx6_ccm_probe(struct device_d *dev)
clks[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
clks[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
+ clks[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
+ clks[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
+ clks[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
+ clks[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
+
+ clks[enet_ref] = clk_divider_table("enet_ref", "pll6_enet", base + 0xe0, 0, 2, clk_enet_ref_table);
+
/* name parent_name reg idx */
clks[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
clks[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
@@ -281,6 +297,7 @@ static int imx6_ccm_probe(struct device_d *dev)
clkdev_add_physbase(clks[ipg_per], MX6_I2C1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg_per], MX6_I2C2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg_per], MX6_I2C3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ahb], MX6_SATA_BASE_ADDR, NULL);
writel(0xffffffff, ccm_base + CCGR0);
writel(0xffffffff, ccm_base + CCGR1);
@@ -291,6 +308,9 @@ static int imx6_ccm_probe(struct device_d *dev)
writel(0xffffffff, ccm_base + CCGR6);
writel(0xffffffff, ccm_base + CCGR7);
+ clk_enable(clks[pll6_enet]);
+ clk_enable(clks[sata_ref_100m]);
+
return 0;
}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx6.h b/arch/arm/mach-imx/include/mach/devices-imx6.h
index f8282e7..0f17016 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx6.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx6.h
@@ -64,3 +64,8 @@ static inline struct device_d *imx6_add_i2c2(struct i2c_platform_data *pdata)
{
return imx_add_i2c((void *)MX6_I2C3_BASE_ADDR, 2, pdata);
}
+
+static inline struct device_d *imx6_add_sata(void)
+{
+ return add_generic_device("imx6-sata", 0, NULL, MX6_SATA_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+}
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
index 716e6b4..7c72cba 100644
--- a/arch/arm/mach-imx/include/mach/imx6-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
@@ -105,4 +105,6 @@
#define MX6_IP2APB_USBPHY1_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x78000)
#define MX6_IP2APB_USBPHY2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x7C000)
+#define MX6_SATA_BASE_ADDR 0x02200000
+
#endif /* __MACH_IMX6_REGS_H */
--
1.7.10.4
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