* [PATCH 1/9] ata: register disks as /dev/ata*
2012-12-06 13:34 [PATCH] AHCI support Sascha Hauer
@ 2012-12-06 13:34 ` Sascha Hauer
2012-12-06 13:34 ` [PATCH 2/9] ata: fix status flags Sascha Hauer
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2012-12-06 13:34 UTC (permalink / raw)
To: barebox
Using /dev/disk* for every type of device is not helpful. It increases
the chance that the user doesn't know which file corresponds to which
device. So rename ata device files to /dev/ata*. Also add a dev_info
about which device just has been registered.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/ata/disk_ata_drive.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/disk_ata_drive.c b/drivers/ata/disk_ata_drive.c
index 6bb72a9..303d6d0 100644
--- a/drivers/ata/disk_ata_drive.c
+++ b/drivers/ata/disk_ata_drive.c
@@ -572,12 +572,12 @@ int register_ata_drive(struct device_d *dev, struct ata_ioports *io)
#ifdef DEBUG
ata_dump_id(drive->id);
#endif
- rc = cdev_find_free_index("disk");
+ rc = cdev_find_free_index("ata");
if (rc == -1)
pr_err("Cannot find a free index for the disk node\n");
drive->blk.num_blocks = ata_id_n_sectors(drive->id);
- drive->blk.cdev.name = asprintf("disk%d", rc);
+ drive->blk.cdev.name = asprintf("ata%d", rc);
drive->blk.blockbits = SECTOR_SHIFT;
rc = blockdevice_register(&drive->blk);
@@ -586,6 +586,8 @@ int register_ata_drive(struct device_d *dev, struct ata_ioports *io)
goto on_error;
}
+ dev_info(dev, "registered /dev/%s\n", port->blk.cdev.name);
+
/* create partitions on demand */
rc = parse_partition_table(&drive->blk);
if (rc != 0)
--
1.7.10.4
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barebox@lists.infradead.org
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 2/9] ata: fix status flags
2012-12-06 13:34 [PATCH] AHCI support Sascha Hauer
2012-12-06 13:34 ` [PATCH 1/9] ata: register disks as /dev/ata* Sascha Hauer
@ 2012-12-06 13:34 ` Sascha Hauer
2012-12-06 13:34 ` [PATCH 3/9] ata: split ide sff suport to separate file Sascha Hauer
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2012-12-06 13:34 UTC (permalink / raw)
To: barebox
Some status flags are wrong, fix them. All of them are currently unused,
so no functional change included.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/ata/disk_ata_drive.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/ata/disk_ata_drive.c b/drivers/ata/disk_ata_drive.c
index 303d6d0..b65a660 100644
--- a/drivers/ata/disk_ata_drive.c
+++ b/drivers/ata/disk_ata_drive.c
@@ -61,9 +61,11 @@ struct ata_drive_access {
#define ATA_STATUS_BUSY (1 << 7)
#define ATA_STATUS_READY (1 << 6)
#define ATA_STATUS_WR_FLT (1 << 5)
-#define ATA_STATUS_DRQ (1 << 4)
-#define ATA_STATUS_CORR (1 << 3)
-#define ATA_STATUS_ERROR (1 << 1)
+#define ATA_STATUS_DSC (1 << 4)
+#define ATA_STATUS_DRQ (1 << 3)
+#define ATA_STATUS_CORR (1 << 2)
+#define ATA_STATUS_IDX (1 << 1)
+#define ATA_STATUS_ERROR (1 << 0)
/* command flags */
#define LBA_FLAG (1 << 6)
#define ATA_DEVCTL_SOFT_RESET (1 << 2)
--
1.7.10.4
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 3/9] ata: split ide sff suport to separate file
2012-12-06 13:34 [PATCH] AHCI support Sascha Hauer
2012-12-06 13:34 ` [PATCH 1/9] ata: register disks as /dev/ata* Sascha Hauer
2012-12-06 13:34 ` [PATCH 2/9] ata: fix status flags Sascha Hauer
@ 2012-12-06 13:34 ` Sascha Hauer
2012-12-06 13:34 ` [PATCH 4/9] ata: align ata command defines with kernel Sascha Hauer
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2012-12-06 13:34 UTC (permalink / raw)
To: barebox
Currently we only support oldschool IDE SFF devices. This is done
by registering a register layout struct and everything else is done
by the generic IDE SFF driver. Since modern ATA devices still use
ATA, but not the SFF interface anymore, split out the IDE SFF support
to a separate file to allow for other types of ata interfaces.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/ata/Kconfig | 6 +-
drivers/ata/Makefile | 1 +
drivers/ata/disk_ata_drive.c | 342 ++++----------------------------------
drivers/ata/ide-sff.c | 343 +++++++++++++++++++++++++++++++++++++++
drivers/ata/intf_platform_ide.c | 2 +-
drivers/ata/pata-imx.c | 2 +-
include/ata_drive.h | 42 ++++-
7 files changed, 424 insertions(+), 314 deletions(-)
create mode 100644 drivers/ata/ide-sff.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 459fac3..c66f13d 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -9,6 +9,9 @@ menuconfig DISK
if DISK
+config DISK_IDE_SFF
+ bool
+
config DISK_WRITE
select BLOCK_WRITE
bool "support writing to disk drives"
@@ -35,6 +38,7 @@ comment "interface types"
config DISK_INTF_PLATFORM_IDE
bool "Platform IDE"
select DISK_ATA
+ select DISK_IDE_SFF
help
Generic platform driver for simple IDE like interfaces to a connected
ATA device.
@@ -42,7 +46,7 @@ config DISK_INTF_PLATFORM_IDE
config DISK_PATA_IMX
bool "i.MX PATA driver"
depends on ARCH_IMX
- select DISK_ATA
+ depends on DISK_INTF_PLATFORM_IDE
help
select this to enable support for the i.MX PATA driver
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index eaeddae..e27299e 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -1,6 +1,7 @@
# drive types
obj-$(CONFIG_DISK_BIOS) += disk_bios_drive.o
+obj-$(CONFIG_DISK_IDE_SFF) += ide-sff.o
obj-$(CONFIG_DISK_ATA) += disk_ata_drive.o
# interface types
diff --git a/drivers/ata/disk_ata_drive.c b/drivers/ata/disk_ata_drive.c
index b65a660..a1df4bd 100644
--- a/drivers/ata/disk_ata_drive.c
+++ b/drivers/ata/disk_ata_drive.c
@@ -25,28 +25,6 @@
#include <ata_drive.h>
#include <disks.h>
-#define ATA_CMD_ID_DEVICE 0xEC
-#define ATA_CMD_RD_CONF 0x40
-#define ATA_CMD_RD 0x20
-#define ATA_CMD_WR 0x30
-
-#define DISK_MASTER 0
-#define DISK_SLAVE 1
-
-/* max timeout for a rotating disk in [ms] */
-#define MAX_TIMEOUT 5000
-
-/**
- * Collection of data we need to know about this drive
- */
-struct ata_drive_access {
- struct block_device blk; /**< the main device */
- struct ata_ioports *io; /**< register file */
- uint16_t id[(SECTOR_SIZE / sizeof(uint16_t))];
-};
-
-#define to_ata_drive_access(x) container_of((x), struct ata_drive_access, blk)
-
#define ata_id_u32(id,n) \
(((uint32_t) (id)[(n) + 1] << 16) | ((uint32_t) (id)[(n)]))
#define ata_id_u64(id,n) \
@@ -57,20 +35,6 @@ struct ata_drive_access {
#define ata_id_has_lba(id) ((id)[49] & (1 << 9))
-/* drive's status flags */
-#define ATA_STATUS_BUSY (1 << 7)
-#define ATA_STATUS_READY (1 << 6)
-#define ATA_STATUS_WR_FLT (1 << 5)
-#define ATA_STATUS_DSC (1 << 4)
-#define ATA_STATUS_DRQ (1 << 3)
-#define ATA_STATUS_CORR (1 << 2)
-#define ATA_STATUS_IDX (1 << 1)
-#define ATA_STATUS_ERROR (1 << 0)
-/* command flags */
-#define LBA_FLAG (1 << 6)
-#define ATA_DEVCTL_SOFT_RESET (1 << 2)
-#define ATA_DEVCTL_INTR_DISABLE (1 << 1)
-
enum {
ATA_ID_SERNO = 10,
#define ATA_ID_SERNO_LEN 20
@@ -242,225 +206,6 @@ static void ata_fix_endianess(uint16_t *buf, unsigned wds)
}
/**
- * Read the status register of the ATA drive
- * @param io Register file
- * @return Register's content
- */
-static uint8_t ata_rd_status(struct ata_ioports *io)
-{
- return readb(io->status_addr);
-}
-
-/**
- * Wait until the disk is busy or time out
- * @param io Register file
- * @param timeout Timeout in [ms]
- * @return 0 on success, -ETIMEDOUT else
- */
-static int ata_wait_busy(struct ata_ioports *io, unsigned timeout)
-{
- uint8_t status;
- uint64_t start = get_time_ns();
- uint64_t toffs = timeout * 1000 * 1000;
-
- do {
- status = ata_rd_status(io);
- if (status & ATA_STATUS_BUSY)
- return 0;
- } while (!is_timeout(start, toffs));
-
- return -ETIMEDOUT;
-}
-
-/**
- * Wait until the disk is ready again or time out
- * @param io Register file
- * @param timeout Timeout in [ms]
- * @return 0 on success, -ETIMEDOUT else
- *
- * This function is useful to check if the disk has accepted a command.
- */
-static int ata_wait_ready(struct ata_ioports *io, unsigned timeout)
-{
- uint8_t status;
- uint64_t start = get_time_ns();
- uint64_t toffs = timeout * 1000 * 1000;
-
- do {
- status = ata_rd_status(io);
- if (!(status & ATA_STATUS_BUSY)) {
- if (status & ATA_STATUS_READY)
- return 0;
- }
- } while (!is_timeout(start, toffs));
-
- return -ETIMEDOUT;
-}
-
-/**
- * Setup the sector number in LBA notation (LBA28)
- * @param io Register file
- * @param drive 0 master drive, 1 slave drive
- * @param num Sector number
- *
- * @todo LBA48 support
- */
-static int ata_set_lba_sector(struct ata_ioports *io, unsigned drive, uint64_t num)
-{
- if (num > 0x0FFFFFFF || drive > 1)
- return -EINVAL;
-
- writeb(0xA0 | LBA_FLAG | drive << 4 | num >> 24, io->device_addr);
- writeb(0x00, io->error_addr);
- writeb(0x01, io->nsect_addr);
- writeb(num, io->lbal_addr); /* 0 ... 7 */
- writeb(num >> 8, io->lbam_addr); /* 8 ... 15 */
- writeb(num >> 16, io->lbah_addr); /* 16 ... 23 */
-
- return 0;
-}
-
-/**
- * Write an ATA command into the disk
- * @param io Register file
- * @param cmd Command to write
- * @return 0 on success
- */
-static int ata_wr_cmd(struct ata_ioports *io, uint8_t cmd)
-{
- int rc;
-
- rc = ata_wait_ready(io, MAX_TIMEOUT);
- if (rc != 0)
- return rc;
-
- writeb(cmd, io->command_addr);
- return 0;
-}
-
-/**
- * Write a new value into the "device control register"
- * @param io Register file
- * @param val Value to write
- */
-static void ata_wr_dev_ctrl(struct ata_ioports *io, uint8_t val)
-{
- writeb(val, io->ctl_addr);
-}
-
-/**
- * Read one sector from the drive (always SECTOR_SIZE bytes at once)
- * @param io Register file
- * @param buf Buffer to read the data into
- */
-static void ata_rd_sector(struct ata_ioports *io, void *buf)
-{
- unsigned u = SECTOR_SIZE / sizeof(uint16_t);
- uint16_t *b = buf;
-
- if (io->dataif_be) {
- for (; u > 0; u--)
- *b++ = be16_to_cpu(readw(io->data_addr));
- } else {
- for (; u > 0; u--)
- *b++ = le16_to_cpu(readw(io->data_addr));
- }
-}
-
-/**
- * Write one sector into the drive
- * @param io Register file
- * @param buf Buffer to read the data from
- */
-static void ata_wr_sector(struct ata_ioports *io, const void *buf)
-{
- unsigned u = SECTOR_SIZE / sizeof(uint16_t);
- const uint16_t *b = buf;
-
- if (io->dataif_be) {
- for (; u > 0; u--)
- writew(cpu_to_be16(*b++), io->data_addr);
- } else {
- for (; u > 0; u--)
- writew(cpu_to_le16(*b++), io->data_addr);
- }
-}
-
-/**
- * Read the ATA disk's description info
- * @param d All we need to know about the disk
- * @return 0 on success
- */
-static int ata_get_id(struct ata_drive_access *d)
-{
- int rc;
-
- writeb(0xA0, d->io->device_addr); /* FIXME drive */
- writeb(0x00, d->io->lbal_addr);
- writeb(0x00, d->io->lbam_addr);
- writeb(0x00, d->io->lbah_addr);
-
- rc = ata_wr_cmd(d->io, ATA_CMD_ID_DEVICE);
- if (rc != 0)
- return rc;
-
- rc = ata_wait_ready(d->io, MAX_TIMEOUT);
- if (rc != 0)
- return rc;
-
- ata_rd_sector(d->io, &d->id);
-
- ata_fix_endianess(d->id, SECTOR_SIZE / sizeof(uint16_t));
-
- return ata_id_is_valid(d->id);
-}
-
-static int ata_reset(struct ata_ioports *io)
-{
- int rc;
- uint8_t reg;
-
- /* try a hard reset first (if available) */
- if (io->reset != NULL) {
- pr_debug("%s: Resetting drive...\n", __func__);
- io->reset(1);
- rc = ata_wait_busy(io, 500);
- io->reset(0);
- if (rc == 0) {
- rc = ata_wait_ready(io, MAX_TIMEOUT);
- if (rc != 0)
- return rc;
- } else {
- pr_debug("%s: Drive does not respond to RESET line. Ignored\n",
- __func__);
- }
- }
-
- /* try a soft reset */
- ata_wr_dev_ctrl(io, ATA_DEVCTL_SOFT_RESET | ATA_DEVCTL_INTR_DISABLE);
- rc = ata_wait_busy(io, MAX_TIMEOUT); /* does the drive accept the command? */
- if (rc != 0) {
- pr_debug("%s: Drive fails on soft reset\n", __func__);
- return rc;
- }
- ata_wr_dev_ctrl(io, ATA_DEVCTL_INTR_DISABLE);
- rc = ata_wait_ready(io, MAX_TIMEOUT);
- if (rc != 0) {
- pr_debug("%s: Drive fails after soft reset\n", __func__);
- return rc;
- }
-
- reg = ata_rd_status(io) & 0xf;
-
- if (reg == 0xf) {
- pr_debug("%s: Seems no drive connected!\n", __func__);
- return -ENODEV;
- }
-
- return 0;
-}
-
-/**
* Read a chunk of sectors from the drive
* @param blk All info about the block device we need
* @param buffer Buffer to read into
@@ -476,27 +221,9 @@ static int ata_reset(struct ata_ioports *io)
static int ata_read(struct block_device *blk, void *buffer, int block,
int num_blocks)
{
- int rc;
- uint64_t sector = block;
- struct ata_drive_access *drv = to_ata_drive_access(blk);
-
- while (num_blocks) {
- rc = ata_set_lba_sector(drv->io, DISK_MASTER, sector);
- if (rc != 0)
- return rc;
- rc = ata_wr_cmd(drv->io, ATA_CMD_RD);
- if (rc != 0)
- return rc;
- rc = ata_wait_ready(drv->io, MAX_TIMEOUT);
- if (rc != 0)
- return rc;
- ata_rd_sector(drv->io, buffer);
- num_blocks--;
- sector++;
- buffer += SECTOR_SIZE;
- }
+ struct ata_port *port = container_of(blk, struct ata_port, blk);
- return 0;
+ return port->ops->read(port, buffer, block, num_blocks);
}
/**
@@ -515,24 +242,9 @@ static int ata_read(struct block_device *blk, void *buffer, int block,
static int __maybe_unused ata_write(struct block_device *blk,
const void *buffer, int block, int num_blocks)
{
- int rc;
- uint64_t sector = block;
- struct ata_drive_access *drv = to_ata_drive_access(blk);
-
- while (num_blocks) {
- rc = ata_set_lba_sector(drv->io, DISK_MASTER, sector);
- if (rc != 0)
- return rc;
- rc = ata_wr_cmd(drv->io, ATA_CMD_WR);
- if (rc != 0)
- return rc;
- ata_wr_sector(drv->io, buffer);
- num_blocks--;
- sector++;
- buffer += SECTOR_SIZE;
- }
+ struct ata_port *port = container_of(blk, struct ata_port, blk);
- return 0;
+ return port->ops->write(port, buffer, block, num_blocks);
}
static struct block_device_ops ata_ops = {
@@ -548,41 +260,52 @@ static struct block_device_ops ata_ops = {
* @param io ATA register file description
* @return 0 on success
*/
-int register_ata_drive(struct device_d *dev, struct ata_ioports *io)
+int ata_port_register(struct ata_port *port)
{
int rc;
- struct ata_drive_access *drive;
+ struct ata_port_operations *ops = port->ops;
+ struct device_d *dev = port->dev;
- drive = xzalloc(sizeof(struct ata_drive_access));
+ port->id = xzalloc(SECTOR_SIZE);
- drive->io = io;
- drive->blk.dev = dev;
- drive->blk.ops = &ata_ops;
+ port->blk.dev = dev;
+ port->blk.ops = &ata_ops;
- rc = ata_reset(io);
- if (rc) {
- dev_dbg(dev, "Resetting failed\n");
- goto on_error;
+ if (ops->reset) {
+ rc = ops->reset(port);
+ if (rc) {
+ dev_dbg(dev, "Resetting failed\n");
+ goto on_error;
+ }
}
- rc = ata_get_id(drive);
+ rc = ops->read_id(port, port->id);
if (rc != 0) {
dev_dbg(dev, "Reading ID failed\n");
goto on_error;
}
+ ata_fix_endianess(port->id, SECTOR_SIZE / sizeof(uint16_t));
+
+ rc = ata_id_is_valid(port->id);
+ if (rc) {
+ dev_err(dev, "ata id invalid\n");
+ free(port->id);
+ return rc;
+ }
+
#ifdef DEBUG
- ata_dump_id(drive->id);
+ ata_dump_id(port->id);
#endif
rc = cdev_find_free_index("ata");
if (rc == -1)
pr_err("Cannot find a free index for the disk node\n");
- drive->blk.num_blocks = ata_id_n_sectors(drive->id);
- drive->blk.cdev.name = asprintf("ata%d", rc);
- drive->blk.blockbits = SECTOR_SHIFT;
+ port->blk.num_blocks = ata_id_n_sectors(port->id);
+ port->blk.cdev.name = asprintf("ata%d", rc);
+ port->blk.blockbits = SECTOR_SHIFT;
- rc = blockdevice_register(&drive->blk);
+ rc = blockdevice_register(&port->blk);
if (rc != 0) {
dev_err(dev, "Failed to register blockdevice\n");
goto on_error;
@@ -591,14 +314,13 @@ int register_ata_drive(struct device_d *dev, struct ata_ioports *io)
dev_info(dev, "registered /dev/%s\n", port->blk.cdev.name);
/* create partitions on demand */
- rc = parse_partition_table(&drive->blk);
+ rc = parse_partition_table(&port->blk);
if (rc != 0)
dev_warn(dev, "No partition table found\n");
return 0;
on_error:
- free(drive);
return rc;
}
diff --git a/drivers/ata/ide-sff.c b/drivers/ata/ide-sff.c
new file mode 100644
index 0000000..6a452d6
--- /dev/null
+++ b/drivers/ata/ide-sff.c
@@ -0,0 +1,343 @@
+#include <common.h>
+#include <ata_drive.h>
+#include <io.h>
+#include <clock.h>
+#include <disks.h>
+#include <malloc.h>
+
+/* max timeout for a rotating disk in [ms] */
+#define MAX_TIMEOUT 5000
+
+/**
+ * Collection of data we need to know about this drive
+ */
+struct ide_port {
+ struct ata_ioports *io; /**< register file */
+ struct ata_port port;
+};
+
+#define to_ata_drive_access(x) container_of((x), struct ide_port, port)
+
+#define DISK_MASTER 0
+#define DISK_SLAVE 1
+
+/**
+ * Read the status register of the ATA drive
+ * @param io Register file
+ * @return Register's content
+ */
+static uint8_t ata_rd_status(struct ide_port *ide)
+{
+ return readb(ide->io->status_addr);
+}
+
+/**
+ * Wait until the disk is busy or time out
+ * @param io Register file
+ * @param timeout Timeout in [ms]
+ * @return 0 on success, -ETIMEDOUT else
+ */
+static int ata_wait_busy(struct ide_port *ide, unsigned timeout)
+{
+ uint8_t status;
+ uint64_t start = get_time_ns();
+ uint64_t toffs = timeout * 1000 * 1000;
+
+ do {
+ status = ata_rd_status(ide);
+ if (status & ATA_STATUS_BUSY)
+ return 0;
+ } while (!is_timeout(start, toffs));
+
+ return -ETIMEDOUT;
+}
+
+/**
+ * Wait until the disk is ready again or time out
+ * @param io Register file
+ * @param timeout Timeout in [ms]
+ * @return 0 on success, -ETIMEDOUT else
+ *
+ * This function is useful to check if the disk has accepted a command.
+ */
+static int ata_wait_ready(struct ide_port *ide, unsigned timeout)
+{
+ uint8_t status;
+ uint64_t start = get_time_ns();
+ uint64_t toffs = timeout * 1000 * 1000;
+
+ do {
+ status = ata_rd_status(ide);
+ if (!(status & ATA_STATUS_BUSY)) {
+ if (status & ATA_STATUS_READY)
+ return 0;
+ }
+ } while (!is_timeout(start, toffs));
+
+ return -ETIMEDOUT;
+}
+
+/**
+ * Setup the sector number in LBA notation (LBA28)
+ * @param io Register file
+ * @param drive 0 master drive, 1 slave drive
+ * @param num Sector number
+ *
+ * @todo LBA48 support
+ */
+static int ata_set_lba_sector(struct ide_port *ide, unsigned drive, uint64_t num)
+{
+ if (num > 0x0FFFFFFF || drive > 1)
+ return -EINVAL;
+
+ writeb(0xA0 | LBA_FLAG | drive << 4 | num >> 24, ide->io->device_addr);
+ writeb(0x00, ide->io->error_addr);
+ writeb(0x01, ide->io->nsect_addr);
+ writeb(num, ide->io->lbal_addr); /* 0 ... 7 */
+ writeb(num >> 8, ide->io->lbam_addr); /* 8 ... 15 */
+ writeb(num >> 16, ide->io->lbah_addr); /* 16 ... 23 */
+
+ return 0;
+}
+
+/**
+ * Write an ATA command into the disk
+ * @param io Register file
+ * @param cmd Command to write
+ * @return 0 on success
+ */
+static int ata_wr_cmd(struct ide_port *ide, uint8_t cmd)
+{
+ int rc;
+
+ rc = ata_wait_ready(ide, MAX_TIMEOUT);
+ if (rc != 0)
+ return rc;
+
+ writeb(cmd, ide->io->command_addr);
+ return 0;
+}
+
+/**
+ * Write a new value into the "device control register"
+ * @param io Register file
+ * @param val Value to write
+ */
+static void ata_wr_dev_ctrl(struct ide_port *ide, uint8_t val)
+{
+ writeb(val, ide->io->ctl_addr);
+}
+
+/**
+ * Read one sector from the drive (always SECTOR_SIZE bytes at once)
+ * @param io Register file
+ * @param buf Buffer to read the data into
+ */
+static void ata_rd_sector(struct ide_port *ide, void *buf)
+{
+ unsigned u = SECTOR_SIZE / sizeof(uint16_t);
+ uint16_t *b = buf;
+
+ if (ide->io->dataif_be) {
+ for (; u > 0; u--)
+ *b++ = be16_to_cpu(readw(ide->io->data_addr));
+ } else {
+ for (; u > 0; u--)
+ *b++ = le16_to_cpu(readw(ide->io->data_addr));
+ }
+}
+
+/**
+ * Write one sector into the drive
+ * @param io Register file
+ * @param buf Buffer to read the data from
+ */
+static void ata_wr_sector(struct ide_port *ide, const void *buf)
+{
+ unsigned u = SECTOR_SIZE / sizeof(uint16_t);
+ const uint16_t *b = buf;
+
+ if (ide->io->dataif_be) {
+ for (; u > 0; u--)
+ writew(cpu_to_be16(*b++), ide->io->data_addr);
+ } else {
+ for (; u > 0; u--)
+ writew(cpu_to_le16(*b++), ide->io->data_addr);
+ }
+}
+
+/**
+ * Read the ATA disk's description info
+ * @param d All we need to know about the disk
+ * @return 0 on success
+ */
+static int ide_read_id(struct ata_port *port, void *buf)
+{
+ struct ide_port *ide = to_ata_drive_access(port);
+ int rc;
+
+ writeb(0xA0, ide->io->device_addr); /* FIXME drive */
+ writeb(0x00, ide->io->lbal_addr);
+ writeb(0x00, ide->io->lbam_addr);
+ writeb(0x00, ide->io->lbah_addr);
+
+ rc = ata_wr_cmd(ide, ATA_CMD_ID_DEVICE);
+ if (rc != 0)
+ return rc;
+
+ rc = ata_wait_ready(ide, MAX_TIMEOUT);
+ if (rc != 0)
+ return rc;
+
+ ata_rd_sector(ide, buf);
+
+ return 0;
+}
+
+static int ide_reset(struct ata_port *port)
+{
+ struct ide_port *ide = to_ata_drive_access(port);
+ int rc;
+ uint8_t reg;
+
+ /* try a hard reset first (if available) */
+ if (ide->io->reset != NULL) {
+ pr_debug("%s: Resetting drive...\n", __func__);
+ ide->io->reset(1);
+ rc = ata_wait_busy(ide, 500);
+ ide->io->reset(0);
+ if (rc == 0) {
+ rc = ata_wait_ready(ide, MAX_TIMEOUT);
+ if (rc != 0)
+ return rc;
+ } else {
+ pr_debug("%s: Drive does not respond to RESET line. Ignored\n",
+ __func__);
+ }
+ }
+
+ /* try a soft reset */
+ ata_wr_dev_ctrl(ide, ATA_DEVCTL_SOFT_RESET | ATA_DEVCTL_INTR_DISABLE);
+ rc = ata_wait_busy(ide, MAX_TIMEOUT); /* does the drive accept the command? */
+ if (rc != 0) {
+ pr_debug("%s: Drive fails on soft reset\n", __func__);
+ return rc;
+ }
+ ata_wr_dev_ctrl(ide, ATA_DEVCTL_INTR_DISABLE);
+ rc = ata_wait_ready(ide, MAX_TIMEOUT);
+ if (rc != 0) {
+ pr_debug("%s: Drive fails after soft reset\n", __func__);
+ return rc;
+ }
+
+ reg = ata_rd_status(ide) & 0xf;
+
+ if (reg == 0xf) {
+ pr_debug("%s: Seems no drive connected!\n", __func__);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+/**
+ * Read a chunk of sectors from the drive
+ * @param blk All info about the block device we need
+ * @param buffer Buffer to read into
+ * @param block Sector's LBA number to start read from
+ * @param num_blocks Sector count to read
+ * @return 0 on success, anything else on failure
+ *
+ * This routine expects the buffer has the correct size to store all data!
+ *
+ * @note Due to 'block' is of type 'int' only small disks can be handled!
+ * @todo Optimize the read loop
+ */
+static int ide_read(struct ata_port *port, void *buffer, unsigned int block,
+ int num_blocks)
+{
+ int rc;
+ uint64_t sector = block;
+ struct ide_port *ide = to_ata_drive_access(port);
+
+ while (num_blocks) {
+ rc = ata_set_lba_sector(ide, DISK_MASTER, sector);
+ if (rc != 0)
+ return rc;
+ rc = ata_wr_cmd(ide, ATA_CMD_RD);
+ if (rc != 0)
+ return rc;
+ rc = ata_wait_ready(ide, MAX_TIMEOUT);
+ if (rc != 0)
+ return rc;
+ ata_rd_sector(ide, buffer);
+ num_blocks--;
+ sector++;
+ buffer += SECTOR_SIZE;
+ }
+
+ return 0;
+}
+
+/**
+ * Write a chunk of sectors into the drive
+ * @param blk All info about the block device we need
+ * @param buffer Buffer to write from
+ * @param block Sector's number to start write to
+ * @param num_blocks Sector count to write
+ * @return 0 on success, anything else on failure
+ *
+ * This routine expects the buffer has the correct size to read all data!
+ *
+ * @note Due to 'block' is of type 'int' only small disks can be handled!
+ * @todo Optimize the write loop
+ */
+static int __maybe_unused ide_write(struct ata_port *port,
+ const void *buffer, unsigned int block, int num_blocks)
+{
+ int rc;
+ uint64_t sector = block;
+ struct ide_port *ide = to_ata_drive_access(port);
+
+ while (num_blocks) {
+ rc = ata_set_lba_sector(ide, DISK_MASTER, sector);
+ if (rc != 0)
+ return rc;
+ rc = ata_wr_cmd(ide, ATA_CMD_WR);
+ if (rc != 0)
+ return rc;
+ ata_wr_sector(ide, buffer);
+ num_blocks--;
+ sector++;
+ buffer += SECTOR_SIZE;
+ }
+
+ return 0;
+}
+
+static struct ata_port_operations ide_ops = {
+ .read_id = ide_read_id,
+ .read = ide_read,
+#ifdef CONFIG_BLOCK_WRITE
+ .write = ide_write,
+#endif
+ .reset = ide_reset,
+};
+
+int ide_port_register(struct device_d *dev, struct ata_ioports *io)
+{
+ struct ide_port *ide;
+ int ret;
+
+ ide = xzalloc(sizeof(*ide));
+
+ ide->io = io;
+ ide->port.ops = &ide_ops;
+
+ ret = ata_port_register(&ide->port);
+
+ if (ret)
+ free(ide);
+
+ return ret;
+}
diff --git a/drivers/ata/intf_platform_ide.c b/drivers/ata/intf_platform_ide.c
index a1840f7..6473b38 100644
--- a/drivers/ata/intf_platform_ide.c
+++ b/drivers/ata/intf_platform_ide.c
@@ -95,7 +95,7 @@ static int platform_ide_probe(struct device_d *dev)
io->reset = pdata->reset;
io->dataif_be = pdata->dataif_be;
- rc = register_ata_drive(dev, io);
+ rc = ide_port_register(dev, io);
if (rc != 0) {
dev_err(dev, "Cannot register IDE interface\n");
free(io);
diff --git a/drivers/ata/pata-imx.c b/drivers/ata/pata-imx.c
index 29531cb..202f537 100644
--- a/drivers/ata/pata-imx.c
+++ b/drivers/ata/pata-imx.c
@@ -172,7 +172,7 @@ static int imx_pata_probe(struct device_d *dev)
pata_imx_set_bus_timing(base, clk_get_rate(clk), 4);
- ret= register_ata_drive(dev, io);
+ ret= ide_port_register(dev, io);
if (ret) {
dev_err(dev, "Cannot register IDE interface: %s\n",
strerror(-ret));
diff --git a/include/ata_drive.h b/include/ata_drive.h
index cdd8049..10edd51 100644
--- a/include/ata_drive.h
+++ b/include/ata_drive.h
@@ -16,6 +16,8 @@
#ifndef ATA_DISK_H
# define ATA_DISK
+#include <block.h>
+
/* IDE register file */
#define IDE_REG_DATA 0x00
#define IDE_REG_ERR 0x01
@@ -33,6 +35,25 @@
#define IDE_REG_DEV_CTL 0x00
#define IDE_REG_DRV_ADDR 0x01
+#define ATA_CMD_ID_DEVICE 0xEC
+#define ATA_CMD_RD_CONF 0x40
+#define ATA_CMD_RD 0x20
+#define ATA_CMD_WR 0x30
+
+/* drive's status flags */
+#define ATA_STATUS_BUSY (1 << 7)
+#define ATA_STATUS_READY (1 << 6)
+#define ATA_STATUS_WR_FLT (1 << 5)
+#define ATA_STATUS_DSC (1 << 4)
+#define ATA_STATUS_DRQ (1 << 3)
+#define ATA_STATUS_CORR (1 << 2)
+#define ATA_STATUS_IDX (1 << 1)
+#define ATA_STATUS_ERROR (1 << 0)
+/* command flags */
+#define LBA_FLAG (1 << 6)
+#define ATA_DEVCTL_SOFT_RESET (1 << 2)
+#define ATA_DEVCTL_INTR_DISABLE (1 << 1)
+
/** addresses of each individual IDE drive register */
struct ata_ioports {
void __iomem *cmd_addr;
@@ -55,8 +76,27 @@ struct ata_ioports {
int dataif_be; /* true if 16 bit data register is big endian */
};
+struct ata_port;
+
+struct ata_port_operations {
+ int (*read)(struct ata_port *port, void *buf, unsigned int block, int num_blocks);
+ int (*write)(struct ata_port *port, const void *buf, unsigned int block, int num_blocks);
+ int (*read_id)(struct ata_port *port, void *buf);
+ int (*reset)(struct ata_port *port);
+};
+
+struct ata_port {
+ struct ata_port_operations *ops;
+ struct device_d *dev;
+ void *drvdata;
+ struct block_device blk;
+ uint16_t *id;
+};
+
+int ide_port_register(struct device_d *, struct ata_ioports *);
+int ata_port_register(struct ata_port *port);
+
struct device_d;
-extern int register_ata_drive(struct device_d*, struct ata_ioports*);
/**
* @file
--
1.7.10.4
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 4/9] ata: align ata command defines with kernel
2012-12-06 13:34 [PATCH] AHCI support Sascha Hauer
` (2 preceding siblings ...)
2012-12-06 13:34 ` [PATCH 3/9] ata: split ide sff suport to separate file Sascha Hauer
@ 2012-12-06 13:34 ` Sascha Hauer
2012-12-06 13:34 ` [PATCH 5/9] ata: Use dma_alloc for buffer Sascha Hauer
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2012-12-06 13:34 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/ata/ide-sff.c | 6 +++---
include/ata_drive.h | 9 +++++----
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/ata/ide-sff.c b/drivers/ata/ide-sff.c
index 6a452d6..3dd6f63 100644
--- a/drivers/ata/ide-sff.c
+++ b/drivers/ata/ide-sff.c
@@ -181,7 +181,7 @@ static int ide_read_id(struct ata_port *port, void *buf)
writeb(0x00, ide->io->lbam_addr);
writeb(0x00, ide->io->lbah_addr);
- rc = ata_wr_cmd(ide, ATA_CMD_ID_DEVICE);
+ rc = ata_wr_cmd(ide, ATA_CMD_ID_ATA);
if (rc != 0)
return rc;
@@ -264,7 +264,7 @@ static int ide_read(struct ata_port *port, void *buffer, unsigned int block,
rc = ata_set_lba_sector(ide, DISK_MASTER, sector);
if (rc != 0)
return rc;
- rc = ata_wr_cmd(ide, ATA_CMD_RD);
+ rc = ata_wr_cmd(ide, ATA_CMD_READ);
if (rc != 0)
return rc;
rc = ata_wait_ready(ide, MAX_TIMEOUT);
@@ -303,7 +303,7 @@ static int __maybe_unused ide_write(struct ata_port *port,
rc = ata_set_lba_sector(ide, DISK_MASTER, sector);
if (rc != 0)
return rc;
- rc = ata_wr_cmd(ide, ATA_CMD_WR);
+ rc = ata_wr_cmd(ide, ATA_CMD_WRITE);
if (rc != 0)
return rc;
ata_wr_sector(ide, buffer);
diff --git a/include/ata_drive.h b/include/ata_drive.h
index 10edd51..1996321 100644
--- a/include/ata_drive.h
+++ b/include/ata_drive.h
@@ -35,10 +35,11 @@
#define IDE_REG_DEV_CTL 0x00
#define IDE_REG_DRV_ADDR 0x01
-#define ATA_CMD_ID_DEVICE 0xEC
-#define ATA_CMD_RD_CONF 0x40
-#define ATA_CMD_RD 0x20
-#define ATA_CMD_WR 0x30
+#define ATA_CMD_ID_ATA 0xEC
+#define ATA_CMD_READ 0x20
+#define ATA_CMD_READ_EXT 0x25
+#define ATA_CMD_WRITE 0x30
+#define ATA_CMD_WRITE_EXT 0x35
/* drive's status flags */
#define ATA_STATUS_BUSY (1 << 7)
--
1.7.10.4
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 5/9] ata: Use dma_alloc for buffer
2012-12-06 13:34 [PATCH] AHCI support Sascha Hauer
` (3 preceding siblings ...)
2012-12-06 13:34 ` [PATCH 4/9] ata: align ata command defines with kernel Sascha Hauer
@ 2012-12-06 13:34 ` Sascha Hauer
2012-12-06 13:34 ` [PATCH 6/9] ata: Add ahci support Sascha Hauer
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2012-12-06 13:34 UTC (permalink / raw)
To: barebox
ATA devices using DMA may need a sufficiently aligned buffer, so use
dma_alloc instead of regular malloc.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/ata/disk_ata_drive.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/ata/disk_ata_drive.c b/drivers/ata/disk_ata_drive.c
index a1df4bd..923be9a 100644
--- a/drivers/ata/disk_ata_drive.c
+++ b/drivers/ata/disk_ata_drive.c
@@ -24,6 +24,7 @@
#include <block.h>
#include <ata_drive.h>
#include <disks.h>
+#include <dma.h>
#define ata_id_u32(id,n) \
(((uint32_t) (id)[(n) + 1] << 16) | ((uint32_t) (id)[(n)]))
@@ -266,7 +267,7 @@ int ata_port_register(struct ata_port *port)
struct ata_port_operations *ops = port->ops;
struct device_d *dev = port->dev;
- port->id = xzalloc(SECTOR_SIZE);
+ port->id = dma_alloc(SECTOR_SIZE);
port->blk.dev = dev;
port->blk.ops = &ata_ops;
--
1.7.10.4
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 6/9] ata: Add ahci support
2012-12-06 13:34 [PATCH] AHCI support Sascha Hauer
` (4 preceding siblings ...)
2012-12-06 13:34 ` [PATCH 5/9] ata: Use dma_alloc for buffer Sascha Hauer
@ 2012-12-06 13:34 ` Sascha Hauer
2012-12-06 13:34 ` [PATCH 7/9] mfd: Add i.MX6 iomux gpr header file Sascha Hauer
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2012-12-06 13:34 UTC (permalink / raw)
To: barebox
This adds ahci controller support based on U-Boot ahci support. Unlike
U-Boot we do not push the SCSI layer in between, but use the ata interface
directly. Tested on a Freescale i.MX53.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/ata/Kconfig | 5 +
drivers/ata/Makefile | 1 +
drivers/ata/ahci.c | 678 ++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/ata/ahci.h | 182 ++++++++++++++
4 files changed, 866 insertions(+)
create mode 100644 drivers/ata/ahci.c
create mode 100644 drivers/ata/ahci.h
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index c66f13d..3eca390 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -33,6 +33,11 @@ config DISK_ATA
help
Support for native ATA/IDE drives
+config DISK_AHCI
+ bool "AHCI support"
+ select DISK_ATA
+ select DISK_DRIVE
+
comment "interface types"
config DISK_INTF_PLATFORM_IDE
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index e27299e..7fbef32 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -3,6 +3,7 @@
obj-$(CONFIG_DISK_BIOS) += disk_bios_drive.o
obj-$(CONFIG_DISK_IDE_SFF) += ide-sff.o
obj-$(CONFIG_DISK_ATA) += disk_ata_drive.o
+obj-$(CONFIG_DISK_AHCI) += ahci.o
# interface types
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
new file mode 100644
index 0000000..14de3c5
--- /dev/null
+++ b/drivers/ata/ahci.c
@@ -0,0 +1,678 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ * Author: Jason Jin<Jason.jin@freescale.com>
+ * Zhang Wei<wei.zhang@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * with the reference on libata and ahci drvier in kernel
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <errno.h>
+#include <io.h>
+#include <malloc.h>
+#include <scsi.h>
+#include <linux/ctype.h>
+#include <disks.h>
+#include <asm/mmu.h>
+#include <ata_drive.h>
+#include <sizes.h>
+#include <clock.h>
+
+#include "ahci.h"
+
+#define AHCI_MAX_DATA_BYTE_COUNT SZ_4M
+
+/*
+ * Some controllers limit number of blocks they can read/write at once.
+ * Contemporary SSD devices work much faster if the read/write size is aligned
+ * to a power of 2.
+ */
+#define MAX_SATA_BLOCKS_READ_WRITE 0x80
+
+/* Maximum timeouts for each event */
+#define WAIT_SPINUP (10 * SECOND)
+#define WAIT_DATAIO (5 * SECOND)
+#define WAIT_FLUSH (5 * SECOND)
+#define WAIT_LINKUP (4 * MSECOND)
+
+#define ahci_port_debug(port, fmt, arg...) \
+ dev_dbg(port->ahci->dev, "port %d: " fmt, port->num, ##arg)
+
+#define ahci_port_info(port, fmt, arg...) \
+ dev_info(port->ahci->dev, "port %d: " fmt, port->num, ##arg)
+
+#define ahci_debug(ahci, fmt, arg...) \
+ dev_dbg(ahci->dev, fmt, ##arg)
+
+struct ahci_cmd_hdr {
+ u32 opts;
+ u32 status;
+ u32 tbl_addr;
+ u32 tbl_addr_hi;
+ u32 reserved[4];
+};
+
+struct ahci_sg {
+ u32 addr;
+ u32 addr_hi;
+ u32 reserved;
+ u32 flags_size;
+};
+
+static inline void ahci_iowrite(struct ahci_device *ahci, int ofs, u32 val)
+{
+ writel(val, ahci->mmio_base + ofs);
+}
+
+static inline u32 ahci_ioread(struct ahci_device *ahci, int ofs)
+{
+ return readl(ahci->mmio_base + ofs);
+}
+
+static inline void ahci_iowrite_f(struct ahci_device *ahci, int ofs, u32 val)
+{
+ writel(val, ahci->mmio_base + ofs);
+ readl(ahci->mmio_base);
+}
+
+static inline void ahci_port_write(struct ahci_port *port, int ofs, u32 val)
+{
+ writel(val, port->port_mmio + ofs);
+}
+
+static inline void ahci_port_write_f(struct ahci_port *port, int ofs, u32 val)
+{
+ writel(val, port->port_mmio + ofs);
+ readl(port->port_mmio + ofs);
+}
+
+static inline u32 ahci_port_read(struct ahci_port *port, int ofs)
+{
+ return readl(port->port_mmio + ofs);
+}
+
+static inline void __iomem *ahci_port_base(void __iomem *base, int port)
+{
+ return base + 0x100 + (port * 0x80);
+}
+
+static int ahci_link_ok(struct ahci_port *ahci_port, int verbose)
+{
+ u32 val = ahci_port_read(ahci_port, PORT_SCR_STAT) & 0xf;
+
+ if (val == 0x3)
+ return true;
+
+ if (verbose)
+ dev_err(ahci_port->ahci->dev, "port %d: no link\n", ahci_port->num);
+
+ return false;
+}
+
+static void ahci_fill_cmd_slot(struct ahci_port *ahci_port, u32 opts)
+{
+ ahci_port->cmd_slot->opts = cpu_to_le32(opts);
+ ahci_port->cmd_slot->status = 0;
+ ahci_port->cmd_slot->tbl_addr =
+ cpu_to_le32((unsigned long)ahci_port->cmd_tbl & 0xffffffff);
+ ahci_port->cmd_slot->tbl_addr_hi = 0;
+}
+
+static int ahci_fill_sg(struct ahci_port *ahci_port, const void *buf, int buf_len)
+{
+ struct ahci_sg *ahci_sg = ahci_port->cmd_tbl_sg;
+ u32 sg_count;
+
+ sg_count = ((buf_len - 1) / AHCI_MAX_DATA_BYTE_COUNT) + 1;
+ if (sg_count > AHCI_MAX_SG)
+ return -EINVAL;
+
+ while (buf_len) {
+ unsigned int now = min(AHCI_MAX_DATA_BYTE_COUNT, buf_len);
+
+ ahci_sg->addr = cpu_to_le32((u32)buf);
+ ahci_sg->addr_hi = 0;
+ ahci_sg->flags_size = cpu_to_le32(now - 1);
+
+ buf_len -= now;
+ buf += now;
+ }
+
+ return sg_count;
+}
+
+static int ahci_io(struct ahci_port *ahci_port, u8 *fis, int fis_len, void *rbuf,
+ const void *wbuf, int buf_len)
+{
+ u32 opts;
+ int sg_count;
+ int ret;
+
+ if (!ahci_link_ok(ahci_port, 1))
+ return -EIO;
+
+ if (wbuf)
+ dma_flush_range((unsigned long)wbuf, (unsigned long)wbuf + buf_len);
+
+ memcpy((unsigned char *)ahci_port->cmd_tbl, fis, fis_len);
+
+ sg_count = ahci_fill_sg(ahci_port, rbuf ? rbuf : wbuf, buf_len);
+ opts = (fis_len >> 2) | (sg_count << 16);
+ if (wbuf)
+ opts |= 1 << 6;
+ ahci_fill_cmd_slot(ahci_port, opts);
+
+ ahci_port_write_f(ahci_port, PORT_CMD_ISSUE, 1);
+
+ ret = wait_on_timeout(WAIT_DATAIO,
+ (readl(ahci_port->port_mmio + PORT_CMD_ISSUE) & 0x1) == 0);
+ if (ret)
+ return -ETIMEDOUT;
+
+ if (rbuf)
+ dma_inv_range((unsigned long)rbuf, (unsigned long)rbuf + buf_len);
+
+ return 0;
+}
+
+/*
+ * SCSI INQUIRY command operation.
+ */
+static int ahci_read_id(struct ata_port *ata, void *buf)
+{
+ struct ahci_port *ahci = container_of(ata, struct ahci_port, ata);
+ u8 fis[20];
+ int ret;
+
+ memset(fis, 0, sizeof(fis));
+
+ /* Construct the FIS */
+ fis[0] = 0x27; /* Host to device FIS. */
+ fis[1] = 1 << 7; /* Command FIS. */
+ fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
+
+ ret = ahci_io(ahci, fis, sizeof(fis), buf, NULL, SECTOR_SIZE);
+ if (ret)
+ return ret;
+
+ return ret;
+}
+
+static int ahci_rw(struct ata_port *ata, void *rbuf, const void *wbuf,
+ unsigned int block, int num_blocks)
+{
+ struct ahci_port *ahci = container_of(ata, struct ahci_port, ata);
+ u8 fis[20];
+ int ret;
+
+ memset(fis, 0, sizeof(fis));
+
+ /* Construct the FIS */
+ fis[0] = 0x27; /* Host to device FIS. */
+ fis[1] = 1 << 7; /* Command FIS. */
+ fis[2] = wbuf ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; /* Command byte. */
+
+ while (num_blocks) {
+ int now;
+
+ now = min(MAX_SATA_BLOCKS_READ_WRITE, num_blocks);
+
+ fis[4] = (block >> 0) & 0xff;
+ fis[5] = (block >> 8) & 0xff;
+ fis[6] = (block >> 16) & 0xff;
+ fis[7] = 1 << 6; /* device reg: set LBA mode */
+ fis[8] = ((block >> 24) & 0xff);
+ fis[3] = 0xe0; /* features */
+
+ /* Block (sector) count */
+ fis[12] = (now >> 0) & 0xff;
+ fis[13] = (now >> 8) & 0xff;
+
+ ret = ahci_io(ahci, fis, sizeof(fis), rbuf, wbuf, now * SECTOR_SIZE);
+ if (ret)
+ return ret;
+
+ if (rbuf)
+ rbuf += now * SECTOR_SIZE;
+ if (wbuf)
+ wbuf += now * SECTOR_SIZE;
+ num_blocks -= now;
+ block += now;
+ }
+
+ return 0;
+}
+
+static int ahci_read(struct ata_port *ata, void *buf, unsigned int block,
+ int num_blocks)
+{
+ return ahci_rw(ata, buf, NULL, block, num_blocks);
+}
+
+static int ahci_write(struct ata_port *ata, const void *buf, unsigned int block,
+ int num_blocks)
+{
+ return ahci_rw(ata, NULL, buf, block, num_blocks);
+}
+
+static struct ata_port_operations ahci_ops = {
+ .read_id = ahci_read_id,
+ .read = ahci_read,
+ .write = ahci_write,
+};
+
+static int ahci_init_port(struct ahci_port *ahci_port)
+{
+ void __iomem *port_mmio;
+ u32 val, cmd;
+ int ret;
+
+ port_mmio = ahci_port->port_mmio;
+
+ /* make sure port is not active */
+ val = ahci_port_read(ahci_port, PORT_CMD);
+ if (val & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | PORT_CMD_FIS_RX | PORT_CMD_START)) {
+ ahci_port_debug(ahci_port, "Port is active. Deactivating.\n");
+ val &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
+ PORT_CMD_FIS_RX | PORT_CMD_START);
+ ahci_port_write(ahci_port, PORT_CMD, val);
+
+ /*
+ * spec says 500 msecs for each bit, so
+ * this is slightly incorrect.
+ */
+ mdelay(500);
+ }
+
+ /*
+ * First item in chunk of DMA memory: 32-slot command table,
+ * 32 bytes each in size
+ */
+ ahci_port->cmd_slot = dma_alloc_coherent(AHCI_CMD_SLOT_SZ * 32);
+ if (!ahci_port->cmd_slot) {
+ ret = -ENOMEM;
+ goto err_alloc;
+ }
+
+ ahci_port_debug(ahci_port, "cmd_slot = 0x%x\n", (unsigned)ahci_port->cmd_slot);
+
+ /*
+ * Second item: Received-FIS area
+ */
+ ahci_port->rx_fis = (unsigned long)dma_alloc_coherent(AHCI_RX_FIS_SZ);
+ if (!ahci_port->rx_fis) {
+ ret = -ENOMEM;
+ goto err_alloc1;
+ }
+
+ /*
+ * Third item: data area for storing a single command
+ * and its scatter-gather table
+ */
+ ahci_port->cmd_tbl = dma_alloc_coherent(AHCI_CMD_TBL_SZ);
+ if (!ahci_port->cmd_tbl) {
+ ret = -ENOMEM;
+ goto err_alloc2;
+ }
+
+ memset(ahci_port->cmd_slot, 0, AHCI_CMD_SLOT_SZ * 32);
+ memset((void *)ahci_port->rx_fis, 0, AHCI_RX_FIS_SZ);
+ memset(ahci_port->cmd_tbl, 0, AHCI_CMD_TBL_SZ);
+
+ ahci_port_debug(ahci_port, "cmd_tbl_dma = 0x%p\n", ahci_port->cmd_tbl);
+
+ ahci_port->cmd_tbl_sg = ahci_port->cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
+
+ ahci_port_write_f(ahci_port, PORT_LST_ADDR, (u32)ahci_port->cmd_slot);
+ ahci_port_write_f(ahci_port, PORT_FIS_ADDR, ahci_port->rx_fis);
+
+ /*
+ * Add the spinup command to whatever mode bits may
+ * already be on in the command register.
+ */
+ cmd = ahci_port_read(ahci_port, PORT_CMD);
+ cmd |= PORT_CMD_FIS_RX;
+ cmd |= PORT_CMD_SPIN_UP;
+ cmd |= PORT_CMD_ICC_ACTIVE;
+ ahci_port_write_f(ahci_port, PORT_CMD, cmd);
+
+ mdelay(10);
+
+ cmd = ahci_port_read(ahci_port, PORT_CMD);
+ cmd |= PORT_CMD_START;
+ ahci_port_write_f(ahci_port, PORT_CMD, cmd);
+
+ /*
+ * Bring up SATA link.
+ * SATA link bringup time is usually less than 1 ms; only very
+ * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
+ */
+ ret = wait_on_timeout(WAIT_LINKUP,
+ (ahci_port_read(ahci_port, PORT_SCR_STAT) & 0xf) == 0x3);
+ if (ret) {
+ ahci_port_info(ahci_port, "SATA link timeout\n");;
+ ret = -ETIMEDOUT;
+ goto err_init;
+ }
+
+ ahci_port_info(ahci_port, "SATA link ok\n");
+
+ /* Clear error status */
+ val = ahci_port_read(ahci_port, PORT_SCR_ERR);
+ if (val)
+ ahci_port_write(ahci_port, PORT_SCR_ERR, val);
+
+ ahci_port_info(ahci_port, "Spinning up device...\n");
+
+ ret = wait_on_timeout(WAIT_SPINUP,
+ (readl(port_mmio + PORT_TFDATA) &
+ (ATA_STATUS_BUSY | ATA_STATUS_DRQ)) == 0);
+ if (ret) {
+ ahci_port_info(ahci_port, "timeout.\n");
+ ret = -ENODEV;
+ goto err_init;
+ }
+
+ ahci_port_info(ahci_port, "ok.\n");
+
+ val = ahci_port_read(ahci_port, PORT_SCR_ERR);
+
+ ahci_port_write(ahci_port, PORT_SCR_ERR, val);
+
+ /* ack any pending irq events for this port */
+ val = ahci_port_read(ahci_port, PORT_IRQ_STAT);
+ if (val)
+ ahci_port_write(ahci_port, PORT_IRQ_STAT, val);
+
+ ahci_iowrite(ahci_port->ahci, HOST_IRQ_STAT, 1 << ahci_port->num);
+
+ /* set irq mask (enables interrupts) */
+ ahci_port_write(ahci_port, PORT_IRQ_MASK, DEF_PORT_IRQ);
+
+ /* register linkup ports */
+ val = ahci_port_read(ahci_port, PORT_SCR_STAT);
+
+ ahci_port_debug(ahci_port, "status: 0x%08x\n", val);
+
+ ahci_port->ata.ops = &ahci_ops;
+
+ if ((val & 0xf) == 0x03)
+ return 0;
+
+ ret = -ENODEV;
+
+err_init:
+ dma_free_coherent(ahci_port->cmd_tbl, AHCI_CMD_TBL_SZ);
+err_alloc2:
+ dma_free_coherent((void *)ahci_port->rx_fis, AHCI_RX_FIS_SZ);
+err_alloc1:
+ dma_free_coherent(ahci_port->cmd_slot, AHCI_CMD_SLOT_SZ * 32);
+err_alloc:
+ return ret;
+}
+
+static int ahci_host_init(struct ahci_device *ahci)
+{
+ u8 *mmio = (u8 *)ahci->mmio_base;
+ u32 tmp, cap_save;
+ int i, ret;
+
+ ahci_debug(ahci, "ahci_host_init: start\n");
+
+ cap_save = readl(mmio + HOST_CAP);
+ cap_save &= ((1 << 28) | (1 << 17));
+ cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
+
+ /* global controller reset */
+ tmp = ahci_ioread(ahci, HOST_CTL);
+ if ((tmp & HOST_RESET) == 0)
+ ahci_iowrite_f(ahci, HOST_CTL, tmp | HOST_RESET);
+
+ /*
+ * reset must complete within 1 second, or
+ * the hardware should be considered fried.
+ */
+ ret = wait_on_timeout(SECOND, (readl(mmio + HOST_CTL) & HOST_RESET) == 0);
+ if (ret) {
+ ahci_debug(ahci,"controller reset failed (0x%x)\n", tmp);
+ return -ENODEV;
+ }
+
+ ahci_iowrite_f(ahci, HOST_CTL, HOST_AHCI_EN);
+ ahci_iowrite(ahci, HOST_CAP, cap_save);
+ ahci_iowrite_f(ahci, HOST_PORTS_IMPL, 0xf);
+
+ ahci->cap = ahci_ioread(ahci, HOST_CAP);
+ ahci->port_map = ahci_ioread(ahci, HOST_PORTS_IMPL);
+ ahci->n_ports = (ahci->cap & 0x1f) + 1;
+
+ ahci_debug(ahci, "cap 0x%x port_map 0x%x n_ports %d\n",
+ ahci->cap, ahci->port_map, ahci->n_ports);
+
+ for (i = 0; i < ahci->n_ports; i++) {
+ struct ahci_port *ahci_port = &ahci->ports[i];
+
+ ahci_port->num = i;
+ ahci_port->ahci = ahci;
+ ahci_port->ata.dev = ahci->dev;
+ ahci_port->port_mmio = ahci_port_base(mmio, i);
+ ret = ahci_init_port(ahci_port);
+ if (!ret)
+ ahci->link_port_map |= 1 << i;
+ }
+
+ tmp = ahci_ioread(ahci, HOST_CTL);
+ ahci_iowrite(ahci, HOST_CTL, tmp | HOST_IRQ_EN);
+ tmp = ahci_ioread(ahci, HOST_CTL);
+
+ return 0;
+}
+
+static int ahci_port_start(struct ahci_port *ahci_port, u8 port)
+{
+ if (!ahci_link_ok(ahci_port, 1))
+ return -EIO;
+
+ ahci_port_write_f(ahci_port, PORT_CMD,
+ PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
+ PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
+ PORT_CMD_START);
+
+ ata_port_register(&ahci_port->ata);
+
+ return 0;
+}
+
+static int __ahci_host_init(struct ahci_device *ahci)
+{
+ int i, rc = 0;
+ u32 linkmap;
+
+ ahci->host_flags = ATA_FLAG_SATA
+ | ATA_FLAG_NO_LEGACY
+ | ATA_FLAG_MMIO
+ | ATA_FLAG_PIO_DMA
+ | ATA_FLAG_NO_ATAPI;
+ ahci->pio_mask = 0x1f;
+ ahci->udma_mask = 0x7f; /* FIXME: assume to support UDMA6 */
+
+ /* initialize adapter */
+ rc = ahci_host_init(ahci);
+ if (rc)
+ goto err_out;
+
+ linkmap = ahci->link_port_map;
+
+ for (i = 0; i < 32; i++) {
+ if (((linkmap >> i) & 0x01)) {
+ if (ahci_port_start(&ahci->ports[i], i)) {
+ printf("Can not start port %d\n", i);
+ continue;
+ }
+ }
+ }
+err_out:
+ return rc;
+}
+
+#if 0
+/*
+ * In the general case of generic rotating media it makes sense to have a
+ * flush capability. It probably even makes sense in the case of SSDs because
+ * one cannot always know for sure what kind of internal cache/flush mechanism
+ * is embodied therein. At first it was planned to invoke this after the last
+ * write to disk and before rebooting. In practice, knowing, a priori, which
+ * is the last write is difficult. Because writing to the disk in u-boot is
+ * very rare, this flush command will be invoked after every block write.
+ */
+static int ata_io_flush(u8 port)
+{
+ u8 fis[20];
+ struct ahci_ioports *pp = &(probe_ent->port[port]);
+ volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
+ u32 cmd_fis_len = 5; /* five dwords */
+
+ /* Preset the FIS */
+ memset(fis, 0, 20);
+ fis[0] = 0x27; /* Host to device FIS. */
+ fis[1] = 1 << 7; /* Command FIS. */
+ fis[2] = ATA_CMD_FLUSH_EXT;
+
+ memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
+ ahci_fill_cmd_slot(pp, cmd_fis_len);
+ mywritel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
+
+ if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
+ WAIT_MS_FLUSH, 0x1)) {
+ debug("scsi_ahci: flush command timeout on port %d.\n", port);
+ return -EIO;
+ }
+
+ return 0;
+}
+#endif
+
+void ahci_print_info(struct ahci_device *ahci)
+{
+ u32 vers, cap, cap2, impl, speed;
+ const char *speed_s;
+ const char *scc_s;
+
+ vers = ahci_ioread(ahci, HOST_VERSION);
+ cap = ahci->cap;
+ cap2 = ahci_ioread(ahci, HOST_CAP2);
+ impl = ahci->port_map;
+
+ speed = (cap >> 20) & 0xf;
+ if (speed == 1)
+ speed_s = "1.5";
+ else if (speed == 2)
+ speed_s = "3";
+ else if (speed == 3)
+ speed_s = "6";
+ else
+ speed_s = "?";
+
+ scc_s = "SATA";
+
+ printf("AHCI %02x%02x.%02x%02x "
+ "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
+ (vers >> 24) & 0xff,
+ (vers >> 16) & 0xff,
+ (vers >> 8) & 0xff,
+ vers & 0xff,
+ ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
+
+ printf("flags: "
+ "%s%s%s%s%s%s%s"
+ "%s%s%s%s%s%s%s"
+ "%s%s%s%s%s%s\n",
+ cap & (1 << 31) ? "64bit " : "",
+ cap & (1 << 30) ? "ncq " : "",
+ cap & (1 << 28) ? "ilck " : "",
+ cap & (1 << 27) ? "stag " : "",
+ cap & (1 << 26) ? "pm " : "",
+ cap & (1 << 25) ? "led " : "",
+ cap & (1 << 24) ? "clo " : "",
+ cap & (1 << 19) ? "nz " : "",
+ cap & (1 << 18) ? "only " : "",
+ cap & (1 << 17) ? "pmp " : "",
+ cap & (1 << 16) ? "fbss " : "",
+ cap & (1 << 15) ? "pio " : "",
+ cap & (1 << 14) ? "slum " : "",
+ cap & (1 << 13) ? "part " : "",
+ cap & (1 << 7) ? "ccc " : "",
+ cap & (1 << 6) ? "ems " : "",
+ cap & (1 << 5) ? "sxs " : "",
+ cap2 & (1 << 2) ? "apst " : "",
+ cap2 & (1 << 1) ? "nvmp " : "",
+ cap2 & (1 << 0) ? "boh " : "");
+}
+
+void ahci_info(struct device_d *dev)
+{
+ struct ahci_device *ahci = dev->priv;
+
+ ahci_print_info(ahci);
+}
+
+int ahci_add_host(struct ahci_device *ahci)
+{
+ __ahci_host_init(ahci);
+
+ return 0;
+}
+
+static int ahci_probe(struct device_d *dev)
+{
+ struct ahci_device *ahci;
+ void __iomem *regs;
+ int ret;
+
+ ahci = xzalloc(sizeof(*ahci));
+
+ regs = dev_request_mem_region(dev, 0);
+
+ ahci->dev = dev;
+ ahci->mmio_base = regs;
+ dev->priv = ahci;
+
+ ret = ahci_add_host(ahci);
+ if (ret)
+ free(ahci);
+
+ return ret;
+}
+
+static struct driver_d ahci_driver = {
+ .name = "ahci",
+ .probe = ahci_probe,
+ .info = ahci_info,
+};
+
+static int ahci_init(void)
+{
+ return platform_driver_register(&ahci_driver);
+}
+
+device_initcall(ahci_init);
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
new file mode 100644
index 0000000..72e5c1a
--- /dev/null
+++ b/drivers/ata/ahci.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ * Author: Jason Jin<Jason.jin@freescale.com>
+ * Zhang Wei<wei.zhang@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#ifndef _AHCI_H_
+#define _AHCI_H_
+
+#define AHCI_PCI_BAR 0x24
+#define AHCI_MAX_SG 56 /* hardware max is 64K */
+#define AHCI_CMD_SLOT_SZ 32
+#define AHCI_MAX_CMD_SLOT 32
+#define AHCI_RX_FIS_SZ 256
+#define AHCI_CMD_TBL_HDR_SZ 0x80
+#define AHCI_CMD_TBL_CDB 0x40
+#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 32)
+#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
+ AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ)
+#define AHCI_CMD_ATAPI (1 << 5)
+#define AHCI_CMD_WRITE (1 << 6)
+#define AHCI_CMD_PREFETCH (1 << 7)
+#define AHCI_CMD_RESET (1 << 8)
+#define AHCI_CMD_CLR_BUSY (1 << 10)
+
+#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
+
+/* Global controller registers */
+#define HOST_CAP 0x00 /* host capabilities */
+#define HOST_CTL 0x04 /* global host control */
+#define HOST_IRQ_STAT 0x08 /* interrupt status */
+#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
+#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
+#define HOST_CAP2 0x24 /* host capabilities, extended */
+
+/* HOST_CTL bits */
+#define HOST_RESET (1 << 0) /* reset controller; self-clear */
+#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */
+#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */
+
+/* Registers for each SATA port */
+#define PORT_LST_ADDR 0x00 /* command list DMA addr */
+#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
+#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
+#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
+#define PORT_IRQ_STAT 0x10 /* interrupt status */
+#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
+#define PORT_CMD 0x18 /* port command */
+#define PORT_TFDATA 0x20 /* taskfile data */
+#define PORT_SIG 0x24 /* device TF signature */
+#define PORT_CMD_ISSUE 0x38 /* command issue */
+#define PORT_SCR 0x28 /* SATA phy register block */
+#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
+#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
+#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
+#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
+
+/* PORT_IRQ_{STAT,MASK} bits */
+#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
+#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
+#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
+#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
+#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
+#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
+#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
+#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
+
+#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
+#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
+#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
+#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
+#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
+#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
+#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
+#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
+#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
+
+#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \
+ | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
+
+#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \
+ | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \
+ | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \
+ | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \
+ | PORT_IRQ_D2H_REG_FIS
+
+/* PORT_CMD bits */
+#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
+#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
+#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
+#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
+#define PORT_CMD_CLO (1 << 3) /* Command list override */
+#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
+#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
+#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
+
+#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
+#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
+#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
+
+#define AHCI_MAX_PORTS 32
+
+/* SETFEATURES stuff */
+#define SETFEATURES_XFER 0x03
+#define XFER_UDMA_7 0x47
+#define XFER_UDMA_6 0x46
+#define XFER_UDMA_5 0x45
+#define XFER_UDMA_4 0x44
+#define XFER_UDMA_3 0x43
+#define XFER_UDMA_2 0x42
+#define XFER_UDMA_1 0x41
+#define XFER_UDMA_0 0x40
+#define XFER_MW_DMA_2 0x22
+#define XFER_MW_DMA_1 0x21
+#define XFER_MW_DMA_0 0x20
+#define XFER_SW_DMA_2 0x12
+#define XFER_SW_DMA_1 0x11
+#define XFER_SW_DMA_0 0x10
+#define XFER_PIO_4 0x0C
+#define XFER_PIO_3 0x0B
+#define XFER_PIO_2 0x0A
+#define XFER_PIO_1 0x09
+#define XFER_PIO_0 0x08
+#define XFER_PIO_SLOW 0x00
+
+#define ATA_FLAG_SATA (1 << 3)
+#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */
+#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */
+#define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */
+#define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */
+#define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */
+
+struct ahci_device;
+
+struct ahci_port {
+ struct ata_port ata;
+ struct ahci_device *ahci;
+ int num;
+ unsigned flags;
+ void __iomem *port_mmio;
+ struct ahci_cmd_hdr *cmd_slot;
+ struct ahci_sg *cmd_tbl_sg;
+ void *cmd_tbl;
+ u32 rx_fis;
+};
+
+struct ahci_device {
+ struct device_d *dev;
+ struct ahci_port ports[AHCI_MAX_PORTS];
+ u32 n_ports;
+ void __iomem *mmio_base;
+ u32 cap; /* cache of HOST_CAP register */
+ u32 port_map; /* cache of HOST_PORTS_IMPL reg */
+ u32 link_port_map; /* linkup port map */
+ u32 pio_mask;
+ u32 udma_mask;
+ u32 host_flags;
+};
+
+int ahci_add_host(struct ahci_device *ahci);
+void ahci_print_info(struct ahci_device *ahci);
+void ahci_info(struct device_d *dev);
+
+#endif
--
1.7.10.4
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 7/9] mfd: Add i.MX6 iomux gpr header file
2012-12-06 13:34 [PATCH] AHCI support Sascha Hauer
` (5 preceding siblings ...)
2012-12-06 13:34 ` [PATCH 6/9] ata: Add ahci support Sascha Hauer
@ 2012-12-06 13:34 ` Sascha Hauer
2012-12-06 13:34 ` [PATCH 8/9] ata: Add i.MX AHCI driver Sascha Hauer
2012-12-06 13:34 ` [PATCH 9/9] ARM i.MX5: Add SATA support Sascha Hauer
8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2012-12-06 13:34 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/mfd/imx6q-iomuxc-gpr.h | 320 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 320 insertions(+)
create mode 100644 include/mfd/imx6q-iomuxc-gpr.h
diff --git a/include/mfd/imx6q-iomuxc-gpr.h b/include/mfd/imx6q-iomuxc-gpr.h
new file mode 100644
index 0000000..db43d59
--- /dev/null
+++ b/include/mfd/imx6q-iomuxc-gpr.h
@@ -0,0 +1,320 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_IMX6Q_IOMUXC_GPR_H
+#define __LINUX_IMX6Q_IOMUXC_GPR_H
+
+#include <linux/bitops.h>
+
+#define IOMUXC_GPR0 0x00
+#define IOMUXC_GPR1 0x04
+#define IOMUXC_GPR2 0x08
+#define IOMUXC_GPR3 0x0c
+#define IOMUXC_GPR4 0x10
+#define IOMUXC_GPR5 0x14
+#define IOMUXC_GPR6 0x18
+#define IOMUXC_GPR7 0x1c
+#define IOMUXC_GPR8 0x20
+#define IOMUXC_GPR9 0x24
+#define IOMUXC_GPR10 0x28
+#define IOMUXC_GPR11 0x2c
+#define IOMUXC_GPR12 0x30
+#define IOMUXC_GPR13 0x34
+
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK (0x3 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x0 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7 (0x1 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK (0x2 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 30)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK (0x3 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED (0x0 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR (0x1 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR (0x2 << 28)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK (0x3 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED (0x0 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7 (0x1 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK (0x2 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK (0x3 << 26)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK (0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7 (0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK (0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK (0x3 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED (0x0 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2 (0x1 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK (0x2 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK (0x3 << 22)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK (0x3 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED (0x0 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2 (0x1 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK (0x2 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK (0x3 << 20)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK (0x3 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED (0x0 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1 (0x1 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK (0x2 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK (0x3 << 18)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK (0x3 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED (0x0 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1 (0x1 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK (0x2 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK (0x3 << 16)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK (0x3 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1 (0x0 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2 (0x1 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3 (0x2 << 14)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_SPDIF 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_ESAI 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK BIT(5)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_ECSPI4 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2 BIT(5)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK BIT(4)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_ECSPI4 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1 BIT(4)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK BIT(3)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_ECSPI2 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1 BIT(3)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK BIT(2)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_ECSPI1 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2 BIT(2)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK BIT(1)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_ECSPI1 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3 BIT(1)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK BIT(0)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IPU1 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX BIT(0)
+
+#define IMX6Q_GPR1_PCIE_REQ_MASK (0x3 << 30)
+#define IMX6Q_GPR1_PCIE_EXIT_L1 BIT(28)
+#define IMX6Q_GPR1_PCIE_RDY_L23 BIT(27)
+#define IMX6Q_GPR1_PCIE_ENTER_L1 BIT(26)
+#define IMX6Q_GPR1_MIPI_COLOR_SW BIT(25)
+#define IMX6Q_GPR1_DPI_OFF BIT(24)
+#define IMX6Q_GPR1_EXC_MON_MASK BIT(22)
+#define IMX6Q_GPR1_EXC_MON_OKAY 0x0
+#define IMX6Q_GPR1_EXC_MON_SLVE BIT(22)
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET 0x0
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(19)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(19)
+#define IMX6Q_GPR1_PCIE_TEST_PD BIT(18)
+#define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17)
+#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0
+#define IMX6Q_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
+#define IMX6Q_GPR1_PCIE_REF_CLK_EN BIT(16)
+#define IMX6Q_GPR1_USB_EXP_MODE BIT(15)
+#define IMX6Q_GPR1_PCIE_INT BIT(14)
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK BIT(13)
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER 0x0
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1 BIT(13)
+#define IMX6Q_GPR1_GINT BIT(12)
+#define IMX6Q_GPR1_ADDRS3_MASK (0x3 << 10)
+#define IMX6Q_GPR1_ADDRS3_32MB (0x0 << 10)
+#define IMX6Q_GPR1_ADDRS3_64MB (0x1 << 10)
+#define IMX6Q_GPR1_ADDRS3_128MB (0x2 << 10)
+#define IMX6Q_GPR1_ACT_CS3 BIT(9)
+#define IMX6Q_GPR1_ADDRS2_MASK (0x3 << 7)
+#define IMX6Q_GPR1_ACT_CS2 BIT(6)
+#define IMX6Q_GPR1_ADDRS1_MASK (0x3 << 4)
+#define IMX6Q_GPR1_ACT_CS1 BIT(3)
+#define IMX6Q_GPR1_ADDRS0_MASK (0x3 << 1)
+#define IMX6Q_GPR1_ACT_CS0 BIT(0)
+
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_MASK (0x3 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_5 (0x0 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_3 (0x1 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_4 (0x2 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_6 (0x3 << 20)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_MASK (0x7 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_0 (0x0 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_1 (0x1 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_2 (0x2 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_3 (0x3 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_4 (0x4 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_5 (0x5 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_6 (0x6 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_7 (0x7 << 16)
+#define IMX6Q_GPR2_BGREF_RRMODE_MASK BIT(15)
+#define IMX6Q_GPR2_BGREF_RRMODE_EXT_RESISTOR 0x0
+#define IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR BIT(15)
+#define IMX6Q_GPR2_DI1_VS_POLARITY_MASK BIT(10)
+#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_H 0x0
+#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L BIT(10)
+#define IMX6Q_GPR2_DI0_VS_POLARITY_MASK BIT(9)
+#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_H 0x0
+#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L BIT(9)
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_MASK BIT(8)
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_SPWG 0x0
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA BIT(8)
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_MASK BIT(7)
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_18BIT 0x0
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT BIT(7)
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_MASK BIT(6)
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_SPWG 0x0
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA BIT(6)
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_MASK BIT(5)
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_18BIT 0x0
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT BIT(5)
+#define IMX6Q_GPR2_SPLIT_MODE_EN BIT(4)
+#define IMX6Q_GPR2_CH1_MODE_MASK (0x3 << 2)
+#define IMX6Q_GPR2_CH1_MODE_DISABLE (0x0 << 2)
+#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI0 (0x1 << 2)
+#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI1 (0x3 << 2)
+#define IMX6Q_GPR2_CH0_MODE_MASK (0x3 << 0)
+#define IMX6Q_GPR2_CH0_MODE_DISABLE (0x0 << 0)
+#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI0 (0x1 << 0)
+#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI1 (0x3 << 0)
+
+#define IMX6Q_GPR3_GPU_DBG_MASK (0x3 << 29)
+#define IMX6Q_GPR3_GPU_DBG_GPU3D (0x0 << 29)
+#define IMX6Q_GPR3_GPU_DBG_GPU2D (0x1 << 29)
+#define IMX6Q_GPR3_GPU_DBG_OPENVG (0x2 << 29)
+#define IMX6Q_GPR3_BCH_WR_CACHE_CTL BIT(28)
+#define IMX6Q_GPR3_BCH_RD_CACHE_CTL BIT(27)
+#define IMX6Q_GPR3_USDHCX_WR_CACHE_CTL BIT(26)
+#define IMX6Q_GPR3_USDHCX_RD_CACHE_CTL BIT(25)
+#define IMX6Q_GPR3_OCRAM_CTL_MASK (0xf << 21)
+#define IMX6Q_GPR3_OCRAM_STATUS_MASK (0xf << 17)
+#define IMX6Q_GPR3_CORE3_DBG_ACK_EN BIT(16)
+#define IMX6Q_GPR3_CORE2_DBG_ACK_EN BIT(15)
+#define IMX6Q_GPR3_CORE1_DBG_ACK_EN BIT(14)
+#define IMX6Q_GPR3_CORE0_DBG_ACK_EN BIT(13)
+#define IMX6Q_GPR3_TZASC2_BOOT_LOCK BIT(12)
+#define IMX6Q_GPR3_TZASC1_BOOT_LOCK BIT(11)
+#define IMX6Q_GPR3_IPU_DIAG_MASK BIT(10)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_MASK (0x3 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0x0 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI1 (0x1 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0 (0x2 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1 (0x3 << 8)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_MASK (0x3 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI0 (0x0 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0 (0x2 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1 (0x3 << 4)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_MASK (0x3 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0 (0x0 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1 (0x1 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0 (0x2 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI1 (0x3 << 2)
+
+#define IMX6Q_GPR4_VDOA_WR_CACHE_SEL BIT(31)
+#define IMX6Q_GPR4_VDOA_RD_CACHE_SEL BIT(30)
+#define IMX6Q_GPR4_VDOA_WR_CACHE_VAL BIT(29)
+#define IMX6Q_GPR4_VDOA_RD_CACHE_VAL BIT(28)
+#define IMX6Q_GPR4_PCIE_WR_CACHE_SEL BIT(27)
+#define IMX6Q_GPR4_PCIE_RD_CACHE_SEL BIT(26)
+#define IMX6Q_GPR4_PCIE_WR_CACHE_VAL BIT(25)
+#define IMX6Q_GPR4_PCIE_RD_CACHE_VAL BIT(24)
+#define IMX6Q_GPR4_SDMA_STOP_ACK BIT(19)
+#define IMX6Q_GPR4_CAN2_STOP_ACK BIT(18)
+#define IMX6Q_GPR4_CAN1_STOP_ACK BIT(17)
+#define IMX6Q_GPR4_ENET_STOP_ACK BIT(16)
+#define IMX6Q_GPR4_SOC_VERSION_MASK (0xff << 8)
+#define IMX6Q_GPR4_SOC_VERSION_OFF 0x8
+#define IMX6Q_GPR4_VPU_WR_CACHE_SEL BIT(7)
+#define IMX6Q_GPR4_VPU_RD_CACHE_SEL BIT(6)
+#define IMX6Q_GPR4_VPU_P_WR_CACHE_VAL BIT(3)
+#define IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK BIT(2)
+#define IMX6Q_GPR4_IPU_WR_CACHE_CTL BIT(1)
+#define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0)
+
+#define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
+
+#define IMX6Q_GPR9_TZASC2_BYP BIT(1)
+#define IMX6Q_GPR9_TZASC1_BYP BIT(0)
+
+#define IMX6Q_GPR10_LOCK_DBG_EN BIT(29)
+#define IMX6Q_GPR10_LOCK_DBG_CLK_EN BIT(28)
+#define IMX6Q_GPR10_LOCK_SEC_ERR_RESP BIT(27)
+#define IMX6Q_GPR10_LOCK_OCRAM_TZ_ADDR (0x3f << 21)
+#define IMX6Q_GPR10_LOCK_OCRAM_TZ_EN BIT(20)
+#define IMX6Q_GPR10_LOCK_DCIC2_MUX_MASK (0x3 << 18)
+#define IMX6Q_GPR10_LOCK_DCIC1_MUX_MASK (0x3 << 16)
+#define IMX6Q_GPR10_DBG_EN BIT(13)
+#define IMX6Q_GPR10_DBG_CLK_EN BIT(12)
+#define IMX6Q_GPR10_SEC_ERR_RESP_MASK BIT(11)
+#define IMX6Q_GPR10_SEC_ERR_RESP_OKEY 0x0
+#define IMX6Q_GPR10_SEC_ERR_RESP_SLVE BIT(11)
+#define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << 5)
+#define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK (0x3 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0 (0x0 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x1 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0 (0x2 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1 (0x3 << 2)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK (0x3 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0x0 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1 (0x1 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0 (0x2 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1 (0x3 << 0)
+
+#define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27)
+#define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26)
+#define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25)
+#define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24)
+#define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
+
+#define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
+#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
+#define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28)
+#define IMX6Q_GPR13_ENET_STOP_REQ BIT(27)
+#define IMX6Q_GPR13_SATA_PHY_8_MASK (0x7 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB (0x0 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB (0x1 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB (0x2 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB (0x3 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB (0x4 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB (0x5 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB (0x6 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB (0x7 << 24)
+#define IMX6Q_GPR13_SATA_PHY_7_MASK (0x1f << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1I (0x10 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1M (0x10 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1X (0x1a << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2I (0x12 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2M (0x12 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2X (0x1a << 19)
+#define IMX6Q_GPR13_SATA_PHY_6_MASK (0x7 << 16)
+#define IMX6Q_GPR13_SATA_PHY_6_OFF 16
+#define IMX6Q_GPR13_SATA_SPEED_MASK BIT(15)
+#define IMX6Q_GPR13_SATA_SPEED_1P5G 0x0
+#define IMX6Q_GPR13_SATA_SPEED_3P0G BIT(15)
+#define IMX6Q_GPR13_SATA_PHY_5 BIT(14)
+#define IMX6Q_GPR13_SATA_PHY_4_MASK (0x7 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_16_16 (0x0 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_14_16 (0x1 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_12_16 (0x2 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_10_16 (0x3 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_9_16 (0x4 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_8_16 (0x5 << 11)
+#define IMX6Q_GPR13_SATA_PHY_3_MASK (0xf << 7)
+#define IMX6Q_GPR13_SATA_PHY_3_OFF 0x7
+#define IMX6Q_GPR13_SATA_PHY_2_MASK (0x1f << 2)
+#define IMX6Q_GPR13_SATA_PHY_2_OFF 0x2
+#define IMX6Q_GPR13_SATA_PHY_1_MASK (0x3 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_FAST (0x0 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_MED (0x1 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_SLOW (0x2 << 0)
+
+#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 8/9] ata: Add i.MX AHCI driver
2012-12-06 13:34 [PATCH] AHCI support Sascha Hauer
` (6 preceding siblings ...)
2012-12-06 13:34 ` [PATCH 7/9] mfd: Add i.MX6 iomux gpr header file Sascha Hauer
@ 2012-12-06 13:34 ` Sascha Hauer
2012-12-06 13:34 ` [PATCH 9/9] ARM i.MX5: Add SATA support Sascha Hauer
8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2012-12-06 13:34 UTC (permalink / raw)
To: barebox
This adds the glue code for the i.MX SATA controller. This controller
needs some i.MX specific setup and some SoC specific setting outside
the controller itself. The code for setting up the correct clock source
for the SATA phy has been taken from U-Boot.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/ata/Kconfig | 4 ++
drivers/ata/Makefile | 1 +
drivers/ata/sata-imx.c | 155 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 160 insertions(+)
create mode 100644 drivers/ata/sata-imx.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 3eca390..b10c5c7 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -38,6 +38,10 @@ config DISK_AHCI
select DISK_ATA
select DISK_DRIVE
+config DISK_AHCI_IMX
+ depends on DISK_AHCI
+ bool "i.MX AHCI support"
+
comment "interface types"
config DISK_INTF_PLATFORM_IDE
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 7fbef32..c444c4d 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_DISK_BIOS) += disk_bios_drive.o
obj-$(CONFIG_DISK_IDE_SFF) += ide-sff.o
obj-$(CONFIG_DISK_ATA) += disk_ata_drive.o
obj-$(CONFIG_DISK_AHCI) += ahci.o
+obj-$(CONFIG_DISK_AHCI_IMX) += sata-imx.o
# interface types
diff --git a/drivers/ata/sata-imx.c b/drivers/ata/sata-imx.c
new file mode 100644
index 0000000..fc57f5f
--- /dev/null
+++ b/drivers/ata/sata-imx.c
@@ -0,0 +1,155 @@
+#include <common.h>
+#include <ata_drive.h>
+#include <io.h>
+#include <clock.h>
+#include <disks.h>
+#include <driver.h>
+#include <init.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <malloc.h>
+#include <mach/imx53-regs.h>
+#include <mach/imx6-regs.h>
+#include <mfd/imx6q-iomuxc-gpr.h>
+#include "ahci.h"
+
+#define HOST_TIMER1MS 0xe0 /* Timer 1-ms */
+
+struct imx_ahci {
+ struct ahci_device ahci;
+ struct clk *clk;
+};
+
+struct imx_sata_data {
+ int (*init)(struct imx_ahci *imx_ahci);
+};
+
+static int imx6_sata_init(struct imx_ahci *imx_ahci)
+{
+ u32 val;
+ void __iomem *base = (void *)MX6_IOMUXC_BASE_ADDR;
+
+ val = 0x11 << IMX6Q_GPR13_SATA_PHY_2_OFF | IMX6Q_GPR13_SATA_PHY_4_9_16 |
+ IMX6Q_GPR13_SATA_SPEED_MASK | 0x3 << IMX6Q_GPR13_SATA_PHY_6_OFF |
+ IMX6Q_GPR13_SATA_PHY_7_SATA2I | IMX6Q_GPR13_SATA_PHY_8_3_0_DB;
+
+ writel(val, base + IOMUXC_GPR13);
+ writel(val | 2, base + IOMUXC_GPR13);
+
+ return 0;
+}
+
+static int imx53_sata_init(struct imx_ahci *imx_ahci)
+{
+ u32 val;
+ void __iomem *base = (void *)MX53_IIM_BASE_ADDR;
+
+ /*
+ * The clock for the external interface can be set to use internal clock
+ * if fuse bank 4, row 3, bit 2 is set.
+ * This is an undocumented feature and it was confirmed by Freescale's support:
+ * Fuses (but not pins) may be used to configure SATA clocks.
+ * Particularly the i.MX53 Fuse_Map contains the next information
+ * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
+ * '00' - 100MHz (External)
+ * '01' - 50MHz (External)
+ * '10' - 120MHz, internal (USB PHY)
+ * '11' - Reserved
+ */
+ val = readl(base + 0x180c);
+ val &= (0x3 << 1);
+ val |= (0x1 << 1);
+ writel(val, base + 0x180c);
+
+ return 0;
+}
+
+static int imx_sata_init_1ms(struct imx_ahci *imx_ahci)
+{
+ void __iomem *base = imx_ahci->ahci.mmio_base;
+ u32 val;
+
+ val = readl(base + HOST_PORTS_IMPL);
+ writel(val | 1, base + HOST_PORTS_IMPL);
+
+ val = clk_get_rate(imx_ahci->clk) / 1000;
+
+ writel(val, base + HOST_TIMER1MS);
+
+ return 0;
+}
+
+static int imx_sata_probe(struct device_d *dev)
+{
+ struct imx_ahci *imx_ahci;
+ struct imx_sata_data *data;
+ int ret;
+
+ ret = dev_get_drvdata(dev, (unsigned long *)&data);
+ if (ret)
+ return ret;
+
+ imx_ahci = xzalloc(sizeof(*imx_ahci));
+
+ imx_ahci->clk = clk_get(dev, NULL);
+ if (IS_ERR(imx_ahci->clk)) {
+ ret = PTR_ERR(imx_ahci->clk);
+ goto err_free;
+ }
+
+ imx_ahci->ahci.mmio_base = dev_request_mem_region(dev, 0);
+ if (!imx_ahci->ahci.mmio_base)
+ return -ENODEV;
+
+ data->init(imx_ahci);
+
+ imx_sata_init_1ms(imx_ahci);
+
+ imx_ahci->ahci.dev = dev;
+ dev->priv = &imx_ahci->ahci;
+
+ ret = ahci_add_host(&imx_ahci->ahci);
+ if (ret)
+ goto err_free;
+
+ return 0;
+
+err_free:
+ free(imx_ahci);
+
+ return ret;
+}
+
+struct imx_sata_data data_imx6 = {
+ .init = imx6_sata_init,
+};
+
+struct imx_sata_data data_imx53 = {
+ .init = imx53_sata_init,
+};
+
+static struct platform_device_id imx_sata_ids[] = {
+ {
+ .name = "imx6-sata",
+ .driver_data = (unsigned long)&data_imx6,
+ }, {
+ .name = "imx53-sata",
+ .driver_data = (unsigned long)&data_imx53,
+ }, {
+ /* sentinel */
+ },
+};
+
+static struct driver_d imx_sata_driver = {
+ .name = "imx-sata",
+ .probe = imx_sata_probe,
+ .info = ahci_info,
+ .id_table = imx_sata_ids,
+};
+
+static int ahci_init(void)
+{
+ return platform_driver_register(&imx_sata_driver);
+}
+
+device_initcall(ahci_init);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 9/9] ARM i.MX5: Add SATA support
2012-12-06 13:34 [PATCH] AHCI support Sascha Hauer
` (7 preceding siblings ...)
2012-12-06 13:34 ` [PATCH 8/9] ata: Add i.MX AHCI driver Sascha Hauer
@ 2012-12-06 13:34 ` Sascha Hauer
8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2012-12-06 13:34 UTC (permalink / raw)
To: barebox
Add the convenience wrappers for registering the SATA device.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/clk-imx5.c | 1 +
arch/arm/mach-imx/include/mach/devices-imx53.h | 5 +++++
arch/arm/mach-imx/include/mach/imx53-regs.h | 2 ++
3 files changed, 8 insertions(+)
diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c
index 050842d..1ff6859 100644
--- a/arch/arm/mach-imx/clk-imx5.c
+++ b/arch/arm/mach-imx/clk-imx5.c
@@ -280,6 +280,7 @@ int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigne
clkdev_add_physbase(clks[esdhc_c_s], MX53_ESDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[esdhc_b_podf], MX53_ESDHC3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[esdhc_d_s], MX53_ESDHC4_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[ahb], MX53_SATA_BASE_ADDR, NULL);
return 0;
}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx53.h b/arch/arm/mach-imx/include/mach/devices-imx53.h
index 5f967ea..a49678e 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx53.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx53.h
@@ -82,3 +82,8 @@ static inline struct device_d *imx53_add_nand(struct imx_nand_platform_data *pda
return dev;
}
+
+static inline struct device_d *imx53_add_sata(void)
+{
+ return add_generic_device("imx53-sata", 0, NULL, MX53_SATA_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+}
diff --git a/arch/arm/mach-imx/include/mach/imx53-regs.h b/arch/arm/mach-imx/include/mach/imx53-regs.h
index 8025e97..473b942 100644
--- a/arch/arm/mach-imx/include/mach/imx53-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx53-regs.h
@@ -3,6 +3,8 @@
#define MX53_IROM_BASE_ADDR 0x0
+#define MX53_SATA_BASE_ADDR 0x10000000
+
/*
* SPBA global module enabled #0
*/
--
1.7.10.4
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^ permalink raw reply [flat|nested] 10+ messages in thread