* [PATCH 01/14] ARM omap: remove unused function
2012-12-13 16:30 AM33xx support Jan Luebbe
@ 2012-12-13 16:30 ` Jan Luebbe
2012-12-13 16:30 ` [PATCH 02/14] ARM omap4: remove unused struct Jan Luebbe
` (12 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Jan Luebbe @ 2012-12-13 16:30 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/include/mach/sys_info.h | 1 -
arch/arm/mach-omap/omap3_generic.c | 19 -------------------
2 files changed, 20 deletions(-)
diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h
index e54791d..4d9b138 100644
--- a/arch/arm/mach-omap/include/mach/sys_info.h
+++ b/arch/arm/mach-omap/include/mach/sys_info.h
@@ -85,7 +85,6 @@ u32 get_cpu_rev(void);
u32 get_sdr_cs_size(u32 offset);
u32 get_sdr_cs1_base(void);
inline u32 get_sysboot_value(void);
-u32 get_gpmc0_base(void);
u32 get_base(void);
u32 running_in_flash(void);
u32 running_in_sram(void);
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index 7cfb3e4..cbac06f 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -204,25 +204,6 @@ inline u32 get_sysboot_value(void)
}
/**
- * @brief Return the current CS0 base address
- *
- * Return current address hardware will be
- * fetching from. The below effectively gives what is correct, its a bit
- * mis-leading compared to the TRM. For the most general case the mask
- * needs to be also taken into account this does work in practice.
- *
- * @return base address
- */
-u32 get_gpmc0_base(void)
-{
- u32 b;
- b = readl(GPMC_REG(CONFIG7_0));
- b &= 0x1F; /* keep base [5:0] */
- b = b << 24; /* ret 0x0b000000 */
- return b;
-}
-
-/**
* @brief Get the upper address of current execution
*
* we can use this to figure out if we are running in SRAM /
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 02/14] ARM omap4: remove unused struct
2012-12-13 16:30 AM33xx support Jan Luebbe
2012-12-13 16:30 ` [PATCH 01/14] ARM omap: remove unused function Jan Luebbe
@ 2012-12-13 16:30 ` Jan Luebbe
2012-12-13 16:30 ` [PATCH 03/14] ARM omap4: Add missing assembly protection in header file Jan Luebbe
` (11 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Jan Luebbe @ 2012-12-13 16:30 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/include/mach/omap4-silicon.h | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
index 008eafb..8ce1882 100644
--- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
@@ -153,15 +153,6 @@
#define PRM_RSTCTRL PRM_DEVICE_BASE
#define PRM_RSTCTRL_RESET 0x01
-#ifndef __ASSEMBLY__
-
-struct s32ktimer {
- unsigned char res[0x10];
- unsigned int s32k_cr; /* 0x10 */
-};
-
-#endif /* __ASSEMBLY__ */
-
/*
* Non-secure SRAM Addresses
* Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 03/14] ARM omap4: Add missing assembly protection in header file
2012-12-13 16:30 AM33xx support Jan Luebbe
2012-12-13 16:30 ` [PATCH 01/14] ARM omap: remove unused function Jan Luebbe
2012-12-13 16:30 ` [PATCH 02/14] ARM omap4: remove unused struct Jan Luebbe
@ 2012-12-13 16:30 ` Jan Luebbe
2012-12-13 16:30 ` [PATCH 04/14] ARM omap4: Add missing double include protection Jan Luebbe
` (10 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Jan Luebbe @ 2012-12-13 16:30 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/include/mach/omap4-silicon.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
index 8ce1882..127257d 100644
--- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
@@ -184,6 +184,8 @@
#define OMAP4460_ES1_0 6
#define OMAP4460_ES1_1 7
+#ifndef __ASSEMBLY__
+
struct ddr_regs {
u32 tim1;
u32 tim2;
@@ -205,3 +207,5 @@ unsigned int omap4_revision(void);
noinline int omap4_scale_vcores(unsigned vsel0_pin);
#endif
+
+#endif
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 04/14] ARM omap4: Add missing double include protection
2012-12-13 16:30 AM33xx support Jan Luebbe
` (2 preceding siblings ...)
2012-12-13 16:30 ` [PATCH 03/14] ARM omap4: Add missing assembly protection in header file Jan Luebbe
@ 2012-12-13 16:30 ` Jan Luebbe
2012-12-13 16:30 ` [PATCH 05/14] ARM omap: Make gpmc base runtime configurable Jan Luebbe
` (9 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Jan Luebbe @ 2012-12-13 16:30 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
missing in omap4-clock.h
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/include/mach/omap4-clock.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap/include/mach/omap4-clock.h b/arch/arm/mach-omap/include/mach/omap4-clock.h
index e5302d6..469c716 100644
--- a/arch/arm/mach-omap/include/mach/omap4-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap4-clock.h
@@ -1,4 +1,7 @@
- /* PRCM */
+#ifndef __MACH_OMAP4_CLOCK_H
+#define __MACH_OMAP4_CLOCK_H
+
+/* PRCM */
#define CM_SYS_CLKSEL 0x4a306110
#define CM_SYS_CLKSEL_19M2 0x4
@@ -337,3 +340,4 @@ void omap4_enable_gpio_clocks(void);
void omap4_enable_all_clocks(void);
void omap4_do_scale_tps62361(u32 reg, u32 volt_mv);
+#endif /* __MACH_OMAP4_CLOCK_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 05/14] ARM omap: Make gpmc base runtime configurable
2012-12-13 16:30 AM33xx support Jan Luebbe
` (3 preceding siblings ...)
2012-12-13 16:30 ` [PATCH 04/14] ARM omap4: Add missing double include protection Jan Luebbe
@ 2012-12-13 16:30 ` Jan Luebbe
2012-12-13 16:30 ` [PATCH 06/14] ARM omap: Make timer " Jan Luebbe
` (8 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Jan Luebbe @ 2012-12-13 16:30 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/devices-gpmc-nand.c | 2 +-
arch/arm/mach-omap/gpmc.c | 14 ++++++++++++--
arch/arm/mach-omap/include/mach/gpmc.h | 4 +++-
3 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap/devices-gpmc-nand.c b/arch/arm/mach-omap/devices-gpmc-nand.c
index 42cb1b4..b2a2b0f 100644
--- a/arch/arm/mach-omap/devices-gpmc-nand.c
+++ b/arch/arm/mach-omap/devices-gpmc-nand.c
@@ -46,7 +46,7 @@ int omap_add_gpmc_nand_device(struct gpmc_nand_platform_data *pdata)
/* Configure GPMC CS before register */
gpmc_cs_config(pdata->cs, pdata->nand_cfg);
- add_generic_device("gpmc_nand", DEVICE_ID_DYNAMIC, NULL, OMAP_GPMC_BASE,
+ add_generic_device("gpmc_nand", DEVICE_ID_DYNAMIC, NULL, (resource_size_t)omap_gpmc_base,
1024 * 4, IORESOURCE_MEM, pdata);
return 0;
diff --git a/arch/arm/mach-omap/gpmc.c b/arch/arm/mach-omap/gpmc.c
index 4cfb7cf..d2b7024 100644
--- a/arch/arm/mach-omap/gpmc.c
+++ b/arch/arm/mach-omap/gpmc.c
@@ -29,6 +29,16 @@
#include <mach/sys_info.h>
#include <mach/syslib.h>
+void __iomem *omap_gpmc_base;
+
+static int gpmc_init(void)
+{
+ omap_gpmc_base = (void *)OMAP_GPMC_BASE;
+
+ return 0;
+}
+pure_initcall(gpmc_init);
+
/**
* @brief Do a Generic initialization of GPMC. if you choose otherwise,
* Use gpmc registers to modify the values. The defaults configured are:
@@ -43,7 +53,7 @@
void gpmc_generic_init(unsigned int cfg)
{
uint64_t start;
- unsigned int reg = GPMC_REG(CONFIG7_0);
+ void __iomem *reg = GPMC_REG(CONFIG7_0);
char x = 0;
debug("gpmccfg=0x%x\n", cfg);
@@ -89,7 +99,7 @@ EXPORT_SYMBOL(gpmc_generic_init);
*/
void gpmc_cs_config(char cs, struct gpmc_config *config)
{
- unsigned int reg = GPMC_REG(CONFIG1_0) + (cs * GPMC_CONFIG_CS_SIZE);
+ void __iomem *reg = GPMC_REG(CONFIG1_0) + (cs * GPMC_CONFIG_CS_SIZE);
unsigned char x = 0;
debug("gpmccs=0x%x cfg=0x%p\n", cs, config);
diff --git a/arch/arm/mach-omap/include/mach/gpmc.h b/arch/arm/mach-omap/include/mach/gpmc.h
index 957ff55..d4eac79 100644
--- a/arch/arm/mach-omap/include/mach/gpmc.h
+++ b/arch/arm/mach-omap/include/mach/gpmc.h
@@ -32,8 +32,10 @@
#ifndef __ASM_ARCH_OMAP_GPMC_H
#define __ASM_ARCH_OMAP_GPMC_H
+extern void __iomem *omap_gpmc_base;
+
/** GPMC Reg Wrapper */
-#define GPMC_REG(REGNAME) (OMAP_GPMC_BASE + GPMC_##REGNAME)
+#define GPMC_REG(REGNAME) (omap_gpmc_base + GPMC_##REGNAME)
#define GPMC_SYS_CONFIG (0x10)
#define GPMC_SYS_STATUS (0x14)
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 06/14] ARM omap: Make timer base runtime configurable
2012-12-13 16:30 AM33xx support Jan Luebbe
` (4 preceding siblings ...)
2012-12-13 16:30 ` [PATCH 05/14] ARM omap: Make gpmc base runtime configurable Jan Luebbe
@ 2012-12-13 16:30 ` Jan Luebbe
2012-12-13 16:30 ` [PATCH 07/14] ARM omap4: make PRM defines SoC specific Jan Luebbe
` (7 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Jan Luebbe @ 2012-12-13 16:30 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/include/mach/timers.h | 4 ----
arch/arm/mach-omap/omap3_clock.c | 3 +++
arch/arm/mach-omap/omap4_clock.c | 1 +
arch/arm/mach-omap/omap4_generic.c | 2 +-
arch/arm/mach-omap/s32k_clksource.c | 10 +++++++++-
5 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap/include/mach/timers.h b/arch/arm/mach-omap/include/mach/timers.h
index 2df507d..8e4cb92 100644
--- a/arch/arm/mach-omap/include/mach/timers.h
+++ b/arch/arm/mach-omap/include/mach/timers.h
@@ -47,8 +47,4 @@
/* Enable sys_clk NO-prescale /1 */
#define GPT_EN ((0 << 2) | (0x1 << 1) | (0x1 << 0))
-/** Sync 32Khz Timer registers */
-#define S32K_CR (OMAP_32KTIMER_BASE + 0x10)
-#define S32K_FREQUENCY 32768
-
#endif /*__ASM_ARCH_GPT_H */
diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 975bf45..2a5e6f2 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -34,10 +34,13 @@
#include <io.h>
#include <mach/silicon.h>
#include <mach/clocks.h>
+#include <mach/omap3-clock.h>
#include <mach/timers.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
+#define S32K_CR (OMAP_32KTIMER_BASE + 0x10)
+
/* Following functions are exported from omap3_clock_core.S */
/* Helper functions */
static u32 get_osc_clk_speed(void);
diff --git a/arch/arm/mach-omap/omap4_clock.c b/arch/arm/mach-omap/omap4_clock.c
index b489d59..c86e4e5 100644
--- a/arch/arm/mach-omap/omap4_clock.c
+++ b/arch/arm/mach-omap/omap4_clock.c
@@ -3,6 +3,7 @@
#include <mach/syslib.h>
#include <mach/silicon.h>
#include <mach/clocks.h>
+#include <mach/omap4-clock.h>
#define LDELAY 12000000
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index dc1dbae..4653b17 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -1,7 +1,7 @@
#include <common.h>
#include <init.h>
#include <io.h>
-#include <mach/clocks.h>
+#include <mach/omap4-clock.h>
#include <mach/silicon.h>
#include <mach/omap4-mux.h>
#include <mach/syslib.h>
diff --git a/arch/arm/mach-omap/s32k_clksource.c b/arch/arm/mach-omap/s32k_clksource.c
index 2cfcfa9..ca73753 100644
--- a/arch/arm/mach-omap/s32k_clksource.c
+++ b/arch/arm/mach-omap/s32k_clksource.c
@@ -31,6 +31,12 @@
#include <mach/sys_info.h>
#include <mach/syslib.h>
+/** Sync 32Khz Timer registers */
+#define S32K_CR 0x10
+#define S32K_FREQUENCY 32768
+
+static void __iomem *timerbase;
+
/**
* @brief Provide a simple clock read
*
@@ -41,7 +47,7 @@
*/
static uint64_t s32k_clocksource_read(void)
{
- return readl(S32K_CR);
+ return readl(timerbase + S32K_CR);
}
/* A bit obvious isn't it? */
@@ -62,6 +68,8 @@ static struct clocksource s32k_cs = {
*/
static int s32k_clocksource_init(void)
{
+ timerbase = (void *)OMAP_32KTIMER_BASE;
+
s32k_cs.mult = clocksource_hz2mult(S32K_FREQUENCY, s32k_cs.shift);
return init_clock(&s32k_cs);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 07/14] ARM omap4: make PRM defines SoC specific
2012-12-13 16:30 AM33xx support Jan Luebbe
` (5 preceding siblings ...)
2012-12-13 16:30 ` [PATCH 06/14] ARM omap: Make timer " Jan Luebbe
@ 2012-12-13 16:30 ` Jan Luebbe
2012-12-13 16:30 ` [PATCH 08/14] ARM omap3: " Jan Luebbe
` (6 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Jan Luebbe @ 2012-12-13 16:30 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/include/mach/omap4-silicon.h | 8 ++++----
arch/arm/mach-omap/omap4_generic.c | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
index 127257d..0f0d88d 100644
--- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
@@ -147,11 +147,11 @@
*/
/* PRM */
-#define PRM_BASE 0x4A306000
-#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
+#define OMAP44XX_PRM_BASE 0x4A306000
+#define OMAP44XX_PRM_DEVICE_BASE (OMAP44XX_PRM_BASE + 0x1B00)
-#define PRM_RSTCTRL PRM_DEVICE_BASE
-#define PRM_RSTCTRL_RESET 0x01
+#define OMAP44XX_PRM_RSTCTRL OMAP44XX_PRM_DEVICE_BASE
+#define OMAP44XX_PRM_RSTCTRL_RESET 0x01
/*
* Non-secure SRAM Addresses
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index 4653b17..f4841a6 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -36,7 +36,7 @@
void __noreturn reset_cpu(unsigned long addr)
{
- writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
+ writel(OMAP44XX_PRM_RSTCTRL_RESET, OMAP44XX_PRM_RSTCTRL);
while (1);
}
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 08/14] ARM omap3: make PRM defines SoC specific
2012-12-13 16:30 AM33xx support Jan Luebbe
` (6 preceding siblings ...)
2012-12-13 16:30 ` [PATCH 07/14] ARM omap4: make PRM defines SoC specific Jan Luebbe
@ 2012-12-13 16:30 ` Jan Luebbe
2012-12-13 16:30 ` [PATCH 09/14] ARM omap: Use SoC specific defines for gpmc and timer base Jan Luebbe
` (5 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Jan Luebbe @ 2012-12-13 16:30 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/include/mach/omap3-silicon.h | 3 +--
arch/arm/mach-omap/omap3_generic.c | 2 +-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap/include/mach/omap3-silicon.h b/arch/arm/mach-omap/include/mach/omap3-silicon.h
index a655729..1921923 100644
--- a/arch/arm/mach-omap/include/mach/omap3-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap3-silicon.h
@@ -128,7 +128,6 @@
#define OMAP_SDRC_CS1 0xA0000000
/* PRM */
-#define PRM_RSTCTRL_RESET 0x04
+#define OMAP3_PRM_RSTCTRL_RESET 0x04
#endif /* __ASM_ARCH_OMAP3_H */
-
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index cbac06f..9932103 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -52,7 +52,7 @@
*/
void __noreturn reset_cpu(unsigned long addr)
{
- writel(PRM_RSTCTRL_RESET, PRM_REG(RSTCTRL));
+ writel(OMAP3_PRM_RSTCTRL_RESET, PRM_REG(RSTCTRL));
while (1);
}
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 09/14] ARM omap: Use SoC specific defines for gpmc and timer base
2012-12-13 16:30 AM33xx support Jan Luebbe
` (7 preceding siblings ...)
2012-12-13 16:30 ` [PATCH 08/14] ARM omap3: " Jan Luebbe
@ 2012-12-13 16:30 ` Jan Luebbe
2012-12-13 16:30 ` [PATCH 10/14] ARM omap: include individual SoC files Jan Luebbe
` (4 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Jan Luebbe @ 2012-12-13 16:30 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/gpmc.c | 11 +++++++++--
arch/arm/mach-omap/include/mach/omap3-silicon.h | 4 ++--
arch/arm/mach-omap/include/mach/omap4-silicon.h | 4 ++--
arch/arm/mach-omap/omap3_clock.c | 2 +-
arch/arm/mach-omap/s32k_clksource.c | 10 ++++++++--
5 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap/gpmc.c b/arch/arm/mach-omap/gpmc.c
index d2b7024..4f54a10 100644
--- a/arch/arm/mach-omap/gpmc.c
+++ b/arch/arm/mach-omap/gpmc.c
@@ -24,7 +24,8 @@
#include <init.h>
#include <io.h>
#include <errno.h>
-#include <mach/silicon.h>
+#include <mach/omap3-silicon.h>
+#include <mach/omap4-silicon.h>
#include <mach/gpmc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
@@ -33,7 +34,13 @@ void __iomem *omap_gpmc_base;
static int gpmc_init(void)
{
- omap_gpmc_base = (void *)OMAP_GPMC_BASE;
+#if defined(CONFIG_ARCH_OMAP3)
+ omap_gpmc_base = (void *)OMAP3_GPMC_BASE;
+#elif defined(CONFIG_ARCH_OMAP4)
+ omap_gpmc_base = (void *)OMAP44XX_GPMC_BASE;
+#else
+#error "Unknown ARCH"
+#endif
return 0;
}
diff --git a/arch/arm/mach-omap/include/mach/omap3-silicon.h b/arch/arm/mach-omap/include/mach/omap3-silicon.h
index 1921923..5843027 100644
--- a/arch/arm/mach-omap/include/mach/omap3-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap3-silicon.h
@@ -44,7 +44,7 @@
#define OMAP_SMX_APE_BASE 0x68000000
#define OMAP_SMS_BASE 0x6C000000
#define OMAP_SDRC_BASE 0x6D000000
-#define OMAP_GPMC_BASE 0x6E000000
+#define OMAP3_GPMC_BASE 0x6E000000
/** Peripheral Base Addresses */
#define OMAP_CTRL_BASE (OMAP_L4_CORE_BASE + 0x02000)
@@ -74,7 +74,7 @@
#define OMAP_WDTIMER2_BASE (OMAP_L4_WKUP_BASE + 0x14000)
#define OMAP_WDTIMER3_BASE (OMAP_L4_PER_BASE + 0x30000)
-#define OMAP_32KTIMER_BASE (OMAP_L4_WKUP_BASE + 0x20000)
+#define OMAP3_32KTIMER_BASE (OMAP_L4_WKUP_BASE + 0x20000)
#define OMAP_MMC1_BASE (OMAP_L4_CORE_BASE + 0x9C000)
#define OMAP_MMC2_BASE (OMAP_L4_CORE_BASE + 0xB4000)
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
index 0f0d88d..5755856 100644
--- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
@@ -92,7 +92,7 @@
#define OMAP44XX_SCRM_AUXCLK3 (OMAP44XX_SCRM_BASE + 0x31c)
/* 32KTIMER */
-#define OMAP_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
+#define OMAP44XX_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
/* MMC */
#define OMAP44XX_MMC1_BASE (OMAP44XX_L4_PER_BASE + 0x09C100)
@@ -117,7 +117,7 @@
#define OMAP44XX_GPIO6_BASE (OMAP44XX_L4_PER_BASE + 0x5D100)
/* GPMC */
-#define OMAP_GPMC_BASE 0x50000000
+#define OMAP44XX_GPMC_BASE 0x50000000
/* DMM */
#define OMAP44XX_DMM_BASE 0x4E000000
diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 2a5e6f2..11f5117 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -39,7 +39,7 @@
#include <mach/sys_info.h>
#include <mach/syslib.h>
-#define S32K_CR (OMAP_32KTIMER_BASE + 0x10)
+#define S32K_CR (OMAP3_32KTIMER_BASE + 0x10)
/* Following functions are exported from omap3_clock_core.S */
/* Helper functions */
diff --git a/arch/arm/mach-omap/s32k_clksource.c b/arch/arm/mach-omap/s32k_clksource.c
index ca73753..7def8b1 100644
--- a/arch/arm/mach-omap/s32k_clksource.c
+++ b/arch/arm/mach-omap/s32k_clksource.c
@@ -25,7 +25,8 @@
#include <clock.h>
#include <init.h>
#include <io.h>
-#include <mach/silicon.h>
+#include <mach/omap3-silicon.h>
+#include <mach/omap4-silicon.h>
#include <mach/clocks.h>
#include <mach/timers.h>
#include <mach/sys_info.h>
@@ -68,7 +69,12 @@ static struct clocksource s32k_cs = {
*/
static int s32k_clocksource_init(void)
{
- timerbase = (void *)OMAP_32KTIMER_BASE;
+ if (IS_ENABLED(CONFIG_ARCH_OMAP3))
+ timerbase = (void *)OMAP3_32KTIMER_BASE;
+ else if (IS_ENABLED(CONFIG_ARCH_OMAP4))
+ timerbase = (void *)OMAP44XX_32KTIMER_BASE;
+ else
+ BUG();
s32k_cs.mult = clocksource_hz2mult(S32K_FREQUENCY, s32k_cs.shift);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 10/14] ARM omap: include individual SoC files
2012-12-13 16:30 AM33xx support Jan Luebbe
` (8 preceding siblings ...)
2012-12-13 16:30 ` [PATCH 09/14] ARM omap: Use SoC specific defines for gpmc and timer base Jan Luebbe
@ 2012-12-13 16:30 ` Jan Luebbe
2012-12-13 16:30 ` [PATCH 11/14] ARM OMAP AM33XX: create new ARCH for AM33xx Jan Luebbe
` (3 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Jan Luebbe @ 2012-12-13 16:30 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
- remove mach/silicon.h and include omap?-silicon.h directly
- include mach/omap?-clock.h directly where needed
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/archosg9/board.c | 2 +-
arch/arm/boards/beagle/board.c | 2 +-
arch/arm/boards/omap343xdsp/board.c | 2 +-
arch/arm/boards/omap3evm/board.c | 2 +-
arch/arm/boards/panda/board.c | 2 +-
arch/arm/boards/pcm049/board.c | 2 +-
arch/arm/boards/phycard-a-l1/pca-a-l1.c | 2 +-
arch/arm/boards/phycard-a-xl2/pca-a-xl2.c | 2 +-
arch/arm/mach-omap/devices-gpmc-nand.c | 1 -
arch/arm/mach-omap/include/mach/clocks.h | 7 -----
arch/arm/mach-omap/include/mach/omap3-silicon.h | 5 ++++
arch/arm/mach-omap/include/mach/silicon.h | 33 -----------------------
arch/arm/mach-omap/omap3_clock.c | 2 +-
arch/arm/mach-omap/omap3_core.S | 2 +-
arch/arm/mach-omap/omap3_generic.c | 3 ++-
arch/arm/mach-omap/omap4_clock.c | 2 +-
arch/arm/mach-omap/omap4_generic.c | 2 +-
drivers/mtd/nand/nand_omap_gpmc.c | 1 -
18 files changed, 19 insertions(+), 55 deletions(-)
delete mode 100644 arch/arm/mach-omap/include/mach/silicon.h
diff --git a/arch/arm/boards/archosg9/board.c b/arch/arm/boards/archosg9/board.c
index 7076c6f..dab0a36 100644
--- a/arch/arm/boards/archosg9/board.c
+++ b/arch/arm/boards/archosg9/board.c
@@ -15,7 +15,7 @@
#include <ns16550.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
-#include <mach/silicon.h>
+#include <mach/omap4-silicon.h>
#include <sizes.h>
#include <i2c/i2c.h>
#include <gpio.h>
diff --git a/arch/arm/boards/beagle/board.c b/arch/arm/boards/beagle/board.c
index de8206b..f6d9d3f 100644
--- a/arch/arm/boards/beagle/board.c
+++ b/arch/arm/boards/beagle/board.c
@@ -55,7 +55,7 @@
#include <ns16550.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
-#include <mach/silicon.h>
+#include <mach/omap3-silicon.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
diff --git a/arch/arm/boards/omap343xdsp/board.c b/arch/arm/boards/omap343xdsp/board.c
index 8b8e0b2..fc50eb1 100644
--- a/arch/arm/boards/omap343xdsp/board.c
+++ b/arch/arm/boards/omap343xdsp/board.c
@@ -48,7 +48,7 @@
#include <io.h>
#include <ns16550.h>
#include <asm/armlinux.h>
-#include <mach/silicon.h>
+#include <mach/omap3-silicon.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
diff --git a/arch/arm/boards/omap3evm/board.c b/arch/arm/boards/omap3evm/board.c
index d18cf39..a5faf56 100644
--- a/arch/arm/boards/omap3evm/board.c
+++ b/arch/arm/boards/omap3evm/board.c
@@ -46,7 +46,7 @@
#include <sizes.h>
#include <ns16550.h>
#include <asm/armlinux.h>
-#include <mach/silicon.h>
+#include <mach/omap3-silicon.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
diff --git a/arch/arm/boards/panda/board.c b/arch/arm/boards/panda/board.c
index 98c05b2..99222d2 100644
--- a/arch/arm/boards/panda/board.c
+++ b/arch/arm/boards/panda/board.c
@@ -8,7 +8,7 @@
#include <asm/armlinux.h>
#include <linux/stat.h>
#include <generated/mach-types.h>
-#include <mach/silicon.h>
+#include <mach/omap4-silicon.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
diff --git a/arch/arm/boards/pcm049/board.c b/arch/arm/boards/pcm049/board.c
index 3159457..859ce3b 100644
--- a/arch/arm/boards/pcm049/board.c
+++ b/arch/arm/boards/pcm049/board.c
@@ -22,7 +22,7 @@
#include <ns16550.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
-#include <mach/silicon.h>
+#include <mach/omap4-silicon.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
diff --git a/arch/arm/boards/phycard-a-l1/pca-a-l1.c b/arch/arm/boards/phycard-a-l1/pca-a-l1.c
index e35db18..c6a7e60 100644
--- a/arch/arm/boards/phycard-a-l1/pca-a-l1.c
+++ b/arch/arm/boards/phycard-a-l1/pca-a-l1.c
@@ -58,7 +58,7 @@
#include <mach/xload.h>
#include <mach/omap3-mux.h>
#include <mach/sdrc.h>
-#include <mach/silicon.h>
+#include <mach/omap3-silicon.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
diff --git a/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c b/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c
index 64e6d94..26b31dd 100644
--- a/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c
+++ b/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c
@@ -22,7 +22,7 @@
#include <ns16550.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
-#include <mach/silicon.h>
+#include <mach/omap4-silicon.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
diff --git a/arch/arm/mach-omap/devices-gpmc-nand.c b/arch/arm/mach-omap/devices-gpmc-nand.c
index b2a2b0f..c4ddc95 100644
--- a/arch/arm/mach-omap/devices-gpmc-nand.c
+++ b/arch/arm/mach-omap/devices-gpmc-nand.c
@@ -24,7 +24,6 @@
#include <clock.h>
#include <io.h>
-#include <mach/silicon.h>
#include <mach/gpmc.h>
#include <mach/gpmc_nand.h>
diff --git a/arch/arm/mach-omap/include/mach/clocks.h b/arch/arm/mach-omap/include/mach/clocks.h
index cbadec7..e44d98b 100644
--- a/arch/arm/mach-omap/include/mach/clocks.h
+++ b/arch/arm/mach-omap/include/mach/clocks.h
@@ -34,11 +34,4 @@
#define S26M 26000000
#define S38_4M 38400000
-#ifdef CONFIG_ARCH_OMAP3
-#include <mach/omap3-clock.h>
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-#include <mach/omap4-clock.h>
-#endif
-
#endif /* __OMAP_CLOCKS_H_ */
diff --git a/arch/arm/mach-omap/include/mach/omap3-silicon.h b/arch/arm/mach-omap/include/mach/omap3-silicon.h
index 5843027..0cf43bd 100644
--- a/arch/arm/mach-omap/include/mach/omap3-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap3-silicon.h
@@ -130,4 +130,9 @@
/* PRM */
#define OMAP3_PRM_RSTCTRL_RESET 0x04
+/* If Architecture specific init functions are present */
+#ifndef __ASSEMBLY__
+void omap3_core_init(void);
+#endif /* __ASSEMBLY__ */
+
#endif /* __ASM_ARCH_OMAP3_H */
diff --git a/arch/arm/mach-omap/include/mach/silicon.h b/arch/arm/mach-omap/include/mach/silicon.h
deleted file mode 100644
index 5ee1931..0000000
--- a/arch/arm/mach-omap/include/mach/silicon.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Nishanth Menon <x0nishan@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ASM_ARCH_OMAP_SILICON_H
-#define __ASM_ARCH_OMAP_SILICON_H
-
-/* Each platform silicon header comes here */
-#ifdef CONFIG_ARCH_OMAP3
-#include <mach/omap3-silicon.h>
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-#include <mach/omap4-silicon.h>
-#endif
-
-/* If Architecture specific init functions are present */
-#ifndef __ASSEMBLY__
-void omap3_core_init(void);
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASM_ARCH_OMAP_SILICON_H */
diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 11f5117..5cf2747 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -32,7 +32,7 @@
#include <common.h>
#include <io.h>
-#include <mach/silicon.h>
+#include <mach/omap3-silicon.h>
#include <mach/clocks.h>
#include <mach/omap3-clock.h>
#include <mach/timers.h>
diff --git a/arch/arm/mach-omap/omap3_core.S b/arch/arm/mach-omap/omap3_core.S
index 38a8cb4..bc32f55 100644
--- a/arch/arm/mach-omap/omap3_core.S
+++ b/arch/arm/mach-omap/omap3_core.S
@@ -28,7 +28,7 @@
#include <config.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
-#include <mach/silicon.h>
+#include <mach/omap3-silicon.h>
#include <mach/wdt.h>
#include <mach/clocks.h>
#include <asm/barebox-arm-head.h>
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index 9932103..a209129 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -30,12 +30,13 @@
#include <common.h>
#include <init.h>
#include <io.h>
-#include <mach/silicon.h>
+#include <mach/omap3-silicon.h>
#include <mach/gpmc.h>
#include <mach/sdrc.h>
#include <mach/control.h>
#include <mach/omap3-smx.h>
#include <mach/clocks.h>
+#include <mach/omap3-clock.h>
#include <mach/wdt.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
diff --git a/arch/arm/mach-omap/omap4_clock.c b/arch/arm/mach-omap/omap4_clock.c
index c86e4e5..0621fd3 100644
--- a/arch/arm/mach-omap/omap4_clock.c
+++ b/arch/arm/mach-omap/omap4_clock.c
@@ -1,7 +1,7 @@
#include <common.h>
#include <io.h>
#include <mach/syslib.h>
-#include <mach/silicon.h>
+#include <mach/omap4-silicon.h>
#include <mach/clocks.h>
#include <mach/omap4-clock.h>
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index f4841a6..2a09eb6 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -2,7 +2,7 @@
#include <init.h>
#include <io.h>
#include <mach/omap4-clock.h>
-#include <mach/silicon.h>
+#include <mach/omap4-silicon.h>
#include <mach/omap4-mux.h>
#include <mach/syslib.h>
#include <mach/xload.h>
diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c
index 4df5a1e..9050a8d 100644
--- a/drivers/mtd/nand/nand_omap_gpmc.c
+++ b/drivers/mtd/nand/nand_omap_gpmc.c
@@ -68,7 +68,6 @@
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <io.h>
-#include <mach/silicon.h>
#include <mach/gpmc.h>
#include <mach/gpmc_nand.h>
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 11/14] ARM OMAP AM33XX: create new ARCH for AM33xx
2012-12-13 16:30 AM33xx support Jan Luebbe
` (9 preceding siblings ...)
2012-12-13 16:30 ` [PATCH 10/14] ARM omap: include individual SoC files Jan Luebbe
@ 2012-12-13 16:30 ` Jan Luebbe
2012-12-13 16:30 ` [PATCH 12/14] arm: omap: am33xx: add support for low level debug Jan Luebbe
` (2 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Jan Luebbe @ 2012-12-13 16:30 UTC (permalink / raw)
To: barebox
From: Teresa Gámez <t.gamez@phytec.de>
Created ARCH for AM33xx boards as second stage bootloader.
This includes:
- Added dmtimer0
- Created basic header files
- Added MMC support for ARCH_AM33XX
- Added reset function
Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Some header file cleanup by:
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
---
arch/arm/mach-omap/Kconfig | 11 +++
arch/arm/mach-omap/Makefile | 2 +
arch/arm/mach-omap/am33xx_generic.c | 29 +++++++
arch/arm/mach-omap/dmtimer0.c | 89 ++++++++++++++++++++++
arch/arm/mach-omap/include/mach/am33xx-clock.h | 23 ++++++
arch/arm/mach-omap/include/mach/am33xx-silicon.h | 49 ++++++++++++
drivers/mci/Kconfig | 2 +-
7 files changed, 204 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-omap/am33xx_generic.c
create mode 100644 arch/arm/mach-omap/dmtimer0.c
create mode 100644 arch/arm/mach-omap/include/mach/am33xx-clock.h
create mode 100644 arch/arm/mach-omap/include/mach/am33xx-silicon.h
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index 451783e..b94500a 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -42,12 +42,23 @@ config ARCH_OMAP4
help
Say Y here if you are using Texas Instrument's OMAP4 based platform
+config ARCH_AM33XX
+ bool "AM33xx"
+ select CPU_V7
+ select GENERIC_GPIO
+ select OMAP_CLOCK_SOURCE_DMTIMER0
+ help
+ Say Y here if you are using Texas Instrument's AM33xx based platform
+
endchoice
# Blind enable all possible clocks.. think twice before you do this.
config OMAP_CLOCK_SOURCE_S32K
bool
+config OMAP_CLOCK_SOURCE_DMTIMER0
+ bool
+
config OMAP3_CLOCK_CONFIG
prompt "Clock Configuration"
bool
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 2ac7fb2..290034e 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -18,10 +18,12 @@
obj-$(CONFIG_ARCH_OMAP) += syslib.o
pbl-$(CONFIG_ARCH_OMAP) += syslib.o
obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o
+obj-$(CONFIG_OMAP_CLOCK_SOURCE_DMTIMER0) += dmtimer0.o
obj-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o auxcr.o
pbl-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o auxcr.o
obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
+obj-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o
obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c
new file mode 100644
index 0000000..f73f946
--- /dev/null
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <io.h>
+#include <mach/am33xx-silicon.h>
+#include <mach/am33xx-clock.h>
+
+void __noreturn reset_cpu(unsigned long addr)
+{
+ writel(AM33XX_PRM_RSTCTRL_RESET, AM33XX_PRM_RSTCTRL);
+
+ while (1);
+}
diff --git a/arch/arm/mach-omap/dmtimer0.c b/arch/arm/mach-omap/dmtimer0.c
new file mode 100644
index 0000000..b0bd670
--- /dev/null
+++ b/arch/arm/mach-omap/dmtimer0.c
@@ -0,0 +1,89 @@
+/**
+ * @file
+ * @brief Support DMTimer0 counter
+ *
+ * FileName: arch/arm/mach-omap/dmtimer0.c
+ */
+/*
+ * This File is based on arch/arm/mach-omap/s32k_clksource.c
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Nishanth Menon <x0nishan@ti.com>
+ *
+ * (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <clock.h>
+#include <init.h>
+#include <io.h>
+#include <mach/am33xx-silicon.h>
+
+#define CLK_RC32K 32768
+
+#define TIDR 0x0
+#define TIOCP_CFG 0x10
+#define IRQ_EOI 0x20
+#define IRQSTATUS_RAW 0x24
+#define IRQSTATUS 0x28
+#define IRQSTATUS_SET 0x2c
+#define IRQSTATUS_CLR 0x30
+#define IRQWAKEEN 0x34
+#define TCLR 0x38
+#define TCRR 0x3C
+#define TLDR 0x40
+#define TTGR 0x44
+#define TWPS 0x48
+#define TMAR 0x4C
+#define TCAR1 0x50
+#define TSICR 0x54
+#define TCAR2 0x58
+
+/**
+ * @brief Provide a simple counter read
+ *
+ * @return DMTimer0 counter
+ */
+static uint64_t dmtimer0_read(void)
+{
+ return readl(AM33XX_DMTIMER0_BASE + TCRR);
+}
+
+static struct clocksource dmtimer0_cs = {
+ .read = dmtimer0_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .shift = 10,
+};
+
+/**
+ * @brief Initialize the Clock
+ *
+ * Enable dmtimer0.
+ *
+ * @return result of @ref init_clock
+ */
+static int dmtimer0_init(void)
+{
+ dmtimer0_cs.mult = clocksource_hz2mult(CLK_RC32K, dmtimer0_cs.shift);
+ /* Enable counter */
+ writel(0x3, AM33XX_DMTIMER0_BASE + TCLR);
+
+ return init_clock(&dmtimer0_cs);
+}
+
+/* Run me at boot time */
+core_initcall(dmtimer0_init);
diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h
new file mode 100644
index 0000000..6845412
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _AM33XX_CLOCKS_H_
+#define _AM33XX_CLOCKS_H_
+
+
+#endif /* endif _AM33XX_CLOCKS_H_ */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
new file mode 100644
index 0000000..1858756
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
@@ -0,0 +1,49 @@
+/*
+ * This file contains the address info for various AM33XX modules.
+ *
+ * Copyright (C) 2012 Teresa Gámez <t.gamez@phytec.de>,
+ * Phytec Messtechnik GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_AM33XX_H
+#define __ASM_ARCH_AM33XX_H
+
+/** AM335x Internal Bus Base addresses */
+#define AM33XX_L4_WKUP_BASE 0x44C00000
+#define AM33XX_L4_PER_BASE 0x48000000
+#define AM33XX_L4_FAST_BASE 0x4A000000
+
+/* UART */
+#define AM33XX_UART0_BASE (AM33XX_L4_WKUP_BASE + 0x209000)
+#define AM33XX_UART1_BASE (AM33XX_L4_PER_BASE + 0x22000)
+#define AM33XX_UART2_BASE (AM33XX_L4_PER_BASE + 0x24000)
+
+/* EMFI Registers */
+#define AM33XX_EMFI0_BASE 0x4C000000
+
+#define AM33XX_DRAM_ADDR_SPACE_START 0x80000000
+#define AM33XX_DRAM_ADDR_SPACE_END 0xC0000000
+
+/* GPMC */
+#define AM33XX_GPMC_BASE 0x50000000
+
+/* MMC */
+#define AM33XX_MMCHS0_BASE (AM33XX_L4_PER_BASE + 0x60000)
+
+/* DTMTimer0 */
+#define AM33XX_DMTIMER0_BASE (AM33XX_L4_WKUP_BASE + 0x205000)
+
+/* PRM */
+#define OMAP_PRM_BASE (AM33XX_L4_WKUP_BASE + 0x200000)
+
+
+#endif
diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig
index 6876117..9558f28 100644
--- a/drivers/mci/Kconfig
+++ b/drivers/mci/Kconfig
@@ -67,7 +67,7 @@ config MCI_IMX_ESDHC_PIO
config MCI_OMAP_HSMMC
bool "OMAP HSMMC"
- depends on ARCH_OMAP4 || ARCH_OMAP3
+ depends on ARCH_OMAP4 || ARCH_OMAP3 || ARCH_AM33XX
help
Enable this entry to add support to read and write SD cards on
both OMAP3 and OMAP4 based systems.
--
1.7.10.4
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 12/14] arm: omap: am33xx: add support for low level debug
2012-12-13 16:30 AM33xx support Jan Luebbe
` (10 preceding siblings ...)
2012-12-13 16:30 ` [PATCH 11/14] ARM OMAP AM33XX: create new ARCH for AM33xx Jan Luebbe
@ 2012-12-13 16:30 ` Jan Luebbe
2012-12-13 16:30 ` [PATCH 13/14] arm: beaglebone: add first-stage support for AM335x and board Jan Luebbe
2012-12-13 16:30 ` [PATCH 14/14] drivers: net: add driver for TI CPSW Jan Luebbe
13 siblings, 0 replies; 16+ messages in thread
From: Jan Luebbe @ 2012-12-13 16:30 UTC (permalink / raw)
To: barebox
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
---
arch/arm/mach-omap/include/mach/debug_ll.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-omap/include/mach/debug_ll.h b/arch/arm/mach-omap/include/mach/debug_ll.h
index b2714c5..142f01a 100644
--- a/arch/arm/mach-omap/include/mach/debug_ll.h
+++ b/arch/arm/mach-omap/include/mach/debug_ll.h
@@ -35,6 +35,11 @@
#define UART_BASE OMAP44XX_UART3_BASE
#endif
+#ifdef CONFIG_ARCH_AM33XX
+#include <mach/am33xx-silicon.h>
+#define UART_BASE AM33XX_UART0_BASE
+#endif
+
#define LSR_THRE 0x20 /* Xmit holding register empty */
#define LSR (5 << 2)
#define THR (0 << 2)
--
1.7.10.4
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 13/14] arm: beaglebone: add first-stage support for AM335x and board
2012-12-13 16:30 AM33xx support Jan Luebbe
` (11 preceding siblings ...)
2012-12-13 16:30 ` [PATCH 12/14] arm: omap: am33xx: add support for low level debug Jan Luebbe
@ 2012-12-13 16:30 ` Jan Luebbe
2012-12-18 12:52 ` Teresa Gámez
2012-12-13 16:30 ` [PATCH 14/14] drivers: net: add driver for TI CPSW Jan Luebbe
13 siblings, 1 reply; 16+ messages in thread
From: Jan Luebbe @ 2012-12-13 16:30 UTC (permalink / raw)
To: barebox
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
---
arch/arm/Makefile | 1 +
arch/arm/boards/beaglebone/Makefile | 1 +
arch/arm/boards/beaglebone/board.c | 364 ++++++++++++++
arch/arm/boards/beaglebone/config.h | 17 +
arch/arm/boards/beaglebone/env/boot/sd | 11 +
arch/arm/boards/beaglebone/env/config | 21 +
arch/arm/configs/am335x_beaglebone_defconfig | 54 +++
.../configs/am335x_beaglebone_mlo_large_defconfig | 55 +++
.../configs/am335x_beaglebone_mlo_small_defconfig | 31 ++
arch/arm/mach-omap/Kconfig | 11 +-
arch/arm/mach-omap/Makefile | 2 +-
arch/arm/mach-omap/am33xx_clock.c | 289 +++++++++++
arch/arm/mach-omap/am33xx_generic.c | 68 +++
arch/arm/mach-omap/am33xx_mux.c | 506 ++++++++++++++++++++
arch/arm/mach-omap/gpmc.c | 3 +
arch/arm/mach-omap/include/mach/am33xx-clock.h | 171 +++++++
arch/arm/mach-omap/include/mach/am33xx-mux.h | 22 +
arch/arm/mach-omap/include/mach/am33xx-silicon.h | 145 +++++-
arch/arm/mach-omap/include/mach/xload.h | 1 +
arch/arm/mach-omap/xload.c | 2 +
20 files changed, 1772 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/boards/beaglebone/Makefile
create mode 100644 arch/arm/boards/beaglebone/board.c
create mode 100644 arch/arm/boards/beaglebone/config.h
create mode 100644 arch/arm/boards/beaglebone/env/boot/sd
create mode 100644 arch/arm/boards/beaglebone/env/config
create mode 100644 arch/arm/configs/am335x_beaglebone_defconfig
create mode 100644 arch/arm/configs/am335x_beaglebone_mlo_large_defconfig
create mode 100644 arch/arm/configs/am335x_beaglebone_mlo_small_defconfig
create mode 100644 arch/arm/mach-omap/am33xx_clock.c
create mode 100644 arch/arm/mach-omap/am33xx_mux.c
create mode 100644 arch/arm/mach-omap/include/mach/am33xx-mux.h
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 3bd645f..5082a13 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -103,6 +103,7 @@ board-$(CONFIG_MACH_NOMADIK_8815NHK) := nhk8815
board-$(CONFIG_MACH_NXDB500) := netx
board-$(CONFIG_MACH_OMAP343xSDP) := omap343xdsp
board-$(CONFIG_MACH_BEAGLE) := beagle
+board-$(CONFIG_MACH_BEAGLEBONE) := beaglebone
board-$(CONFIG_MACH_OMAP3EVM) := omap3evm
board-$(CONFIG_MACH_PANDA) := panda
board-$(CONFIG_MACH_ARCHOSG9) := archosg9
diff --git a/arch/arm/boards/beaglebone/Makefile b/arch/arm/boards/beaglebone/Makefile
new file mode 100644
index 0000000..dcfc293
--- /dev/null
+++ b/arch/arm/boards/beaglebone/Makefile
@@ -0,0 +1 @@
+obj-y += board.o
diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c
new file mode 100644
index 0000000..fd30dd9
--- /dev/null
+++ b/arch/arm/boards/beaglebone/board.c
@@ -0,0 +1,364 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Raghavendra KH <r-khandenahally@ti.com>
+ *
+ * Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ * @brief BeagleBone Specific Board Initialization routines
+ */
+
+#include <common.h>
+#include <console.h>
+#include <init.h>
+#include <driver.h>
+#include <fs.h>
+#include <linux/stat.h>
+#include <environment.h>
+#include <sizes.h>
+#include <io.h>
+#include <ns16550.h>
+#include <asm/armlinux.h>
+#include <generated/mach-types.h>
+#include <mach/am33xx-silicon.h>
+#include <mach/am33xx-clock.h>
+#include <mach/sdrc.h>
+#include <mach/sys_info.h>
+#include <mach/syslib.h>
+#include <mach/gpmc.h>
+#include <mach/ehci.h>
+#include <i2c/i2c.h>
+#include <linux/err.h>
+#include <usb/ehci.h>
+#include <mach/xload.h>
+#include <mach/am33xx-mux.h>
+
+/* UART Defines */
+#define UART_SYSCFG_OFFSET (0x54)
+#define UART_SYSSTS_OFFSET (0x58)
+
+#define UART_RESET (0x1 << 1)
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_SMART_IDLE_EN (0x1 << 0x3)
+
+/* AM335X EMIF Register values */
+#define EMIF_SDMGT 0x80000000
+#define EMIF_SDRAM 0x00004650
+#define EMIF_PHYCFG 0x2
+#define DDR_PHY_RESET (0x1 << 10)
+#define DDR_FUNCTIONAL_MODE_EN 0x1
+#define DDR_PHY_READY (0x1 << 2)
+#define VTP_CTRL_READY (0x1 << 5)
+#define VTP_CTRL_ENABLE (0x1 << 6)
+#define VTP_CTRL_LOCK_EN (0x1 << 4)
+#define VTP_CTRL_START_EN (0x1)
+#define DDR2_RATIO 0x80 /* for mDDR */
+#define CMD_FORCE 0x00 /* common #def */
+#define CMD_DELAY 0x00
+
+#define EMIF_READ_LATENCY 0x05
+#define EMIF_TIM1 0x0666B3D6
+#define EMIF_TIM2 0x143731DA
+#define EMIF_TIM3 0x00000347
+#define EMIF_SDCFG 0x43805332
+#define EMIF_SDREF 0x0000081a
+#define DDR2_DLL_LOCK_DIFF 0x0
+#define DDR2_RD_DQS 0x12
+#define DDR2_PHY_FIFO_WE 0x80
+
+#define DDR2_INVERT_CLKOUT 0x00
+#define DDR2_WR_DQS 0x00
+#define DDR2_PHY_WRLVL 0x00
+#define DDR2_PHY_GATELVL 0x00
+#define DDR2_PHY_WR_DATA 0x40
+#define PHY_RANK0_DELAY 0x01
+#define PHY_DLL_LOCK_DIFF 0x0
+#define DDR_IOCTRL_VALUE 0x18B
+
+static void beaglebone_data_macro_config(int dataMacroNum)
+{
+ u32 BaseAddrOffset = 0x00;;
+
+ if (dataMacroNum == 1)
+ BaseAddrOffset = 0xA4;
+
+ __raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
+ |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
+ (DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
+ __raw_writel(DDR2_RD_DQS>>2,
+ (DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
+ __raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
+ |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
+ (DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
+ __raw_writel(DDR2_WR_DQS>>2,
+ (DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
+ __raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
+ |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
+ (DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset));
+ __raw_writel(DDR2_PHY_WRLVL>>2,
+ (DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset));
+ __raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
+ |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
+ (DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset));
+ __raw_writel(DDR2_PHY_GATELVL>>2,
+ (DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset));
+ __raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
+ |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
+ (DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset));
+ __raw_writel(DDR2_PHY_FIFO_WE>>2,
+ (DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset));
+ __raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
+ |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
+ (DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset));
+ __raw_writel(DDR2_PHY_WR_DATA>>2,
+ (DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset));
+ __raw_writel(PHY_DLL_LOCK_DIFF,
+ (DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset));
+}
+
+static void beaglebone_cmd_macro_config(void)
+{
+ __raw_writel(DDR2_RATIO, CMD0_CTRL_SLAVE_RATIO_0);
+ __raw_writel(CMD_FORCE, CMD0_CTRL_SLAVE_FORCE_0);
+ __raw_writel(CMD_DELAY, CMD0_CTRL_SLAVE_DELAY_0);
+ __raw_writel(DDR2_DLL_LOCK_DIFF, CMD0_DLL_LOCK_DIFF_0);
+ __raw_writel(DDR2_INVERT_CLKOUT, CMD0_INVERT_CLKOUT_0);
+
+ __raw_writel(DDR2_RATIO, CMD1_CTRL_SLAVE_RATIO_0);
+ __raw_writel(CMD_FORCE, CMD1_CTRL_SLAVE_FORCE_0);
+ __raw_writel(CMD_DELAY, CMD1_CTRL_SLAVE_DELAY_0);
+ __raw_writel(DDR2_DLL_LOCK_DIFF, CMD1_DLL_LOCK_DIFF_0);
+ __raw_writel(DDR2_INVERT_CLKOUT, CMD1_INVERT_CLKOUT_0);
+
+ __raw_writel(DDR2_RATIO, CMD2_CTRL_SLAVE_RATIO_0);
+ __raw_writel(CMD_FORCE, CMD2_CTRL_SLAVE_FORCE_0);
+ __raw_writel(CMD_DELAY, CMD2_CTRL_SLAVE_DELAY_0);
+ __raw_writel(DDR2_DLL_LOCK_DIFF, CMD2_DLL_LOCK_DIFF_0);
+ __raw_writel(DDR2_INVERT_CLKOUT, CMD2_INVERT_CLKOUT_0);
+}
+
+static void beaglebone_config_vtp(void)
+{
+ __raw_writel(__raw_readl(VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
+ VTP0_CTRL_REG);
+ __raw_writel(__raw_readl(VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
+ VTP0_CTRL_REG);
+ __raw_writel(__raw_readl(VTP0_CTRL_REG) | VTP_CTRL_START_EN,
+ VTP0_CTRL_REG);
+
+ /* Poll for READY */
+ while ((__raw_readl(VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY);
+}
+
+static void beaglebone_config_emif_ddr2(void)
+{
+ u32 i;
+
+ /*Program EMIF0 CFG Registers*/
+ __raw_writel(EMIF_READ_LATENCY, EMIF4_0_DDR_PHY_CTRL_1);
+ __raw_writel(EMIF_READ_LATENCY, EMIF4_0_DDR_PHY_CTRL_1_SHADOW);
+ __raw_writel(EMIF_READ_LATENCY, EMIF4_0_DDR_PHY_CTRL_2);
+ __raw_writel(EMIF_TIM1, EMIF4_0_SDRAM_TIM_1);
+ __raw_writel(EMIF_TIM1, EMIF4_0_SDRAM_TIM_1_SHADOW);
+ __raw_writel(EMIF_TIM2, EMIF4_0_SDRAM_TIM_2);
+ __raw_writel(EMIF_TIM2, EMIF4_0_SDRAM_TIM_2_SHADOW);
+ __raw_writel(EMIF_TIM3, EMIF4_0_SDRAM_TIM_3);
+ __raw_writel(EMIF_TIM3, EMIF4_0_SDRAM_TIM_3_SHADOW);
+
+ __raw_writel(EMIF_SDCFG, EMIF4_0_SDRAM_CONFIG);
+ __raw_writel(EMIF_SDCFG, EMIF4_0_SDRAM_CONFIG2);
+
+ /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
+ __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
+ __raw_writel(0x00004650, EMIF4_0_SDRAM_REF_CTRL);
+ __raw_writel(0x00004650, EMIF4_0_SDRAM_REF_CTRL_SHADOW);
+
+ for (i = 0; i < 5000; i++) {
+
+ }
+
+ /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
+ __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
+ __raw_writel(EMIF_SDREF, EMIF4_0_SDRAM_REF_CTRL);
+ __raw_writel(EMIF_SDREF, EMIF4_0_SDRAM_REF_CTRL_SHADOW);
+
+ __raw_writel(EMIF_SDCFG, EMIF4_0_SDRAM_CONFIG);
+ __raw_writel(EMIF_SDCFG, EMIF4_0_SDRAM_CONFIG2);
+}
+
+static void beaglebone_config_ddr(void)
+{
+ enable_ddr_clocks();
+
+ beaglebone_config_vtp();
+
+ beaglebone_cmd_macro_config();
+ beaglebone_data_macro_config(0);
+ beaglebone_data_macro_config(1);
+
+ __raw_writel(PHY_RANK0_DELAY, DATA0_RANK0_DELAYS_0);
+ __raw_writel(PHY_RANK0_DELAY, DATA1_RANK0_DELAYS_0);
+
+ __raw_writel(DDR_IOCTRL_VALUE, DDR_CMD0_IOCTRL);
+ __raw_writel(DDR_IOCTRL_VALUE, DDR_CMD1_IOCTRL);
+ __raw_writel(DDR_IOCTRL_VALUE, DDR_CMD2_IOCTRL);
+ __raw_writel(DDR_IOCTRL_VALUE, DDR_DATA0_IOCTRL);
+ __raw_writel(DDR_IOCTRL_VALUE, DDR_DATA1_IOCTRL);
+
+ __raw_writel(__raw_readl(DDR_IO_CTRL) & 0xefffffff, DDR_IO_CTRL);
+ __raw_writel(__raw_readl(DDR_CKE_CTRL) | 0x00000001, DDR_CKE_CTRL);
+
+ beaglebone_config_emif_ddr2();
+}
+
+/*
+ * early system init of muxing and clocks.
+ */
+void beaglebone_sram_init(void)
+{
+ u32 regVal, uart_base;
+
+ /* Setup the PLLs and the clocks for the peripherals */
+ pll_init();
+
+ beaglebone_config_ddr();
+
+ /* UART softreset */
+ uart_base = AM33XX_UART0_BASE;
+
+ regVal = __raw_readl(uart_base + UART_SYSCFG_OFFSET);
+ regVal |= UART_RESET;
+ __raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET) );
+ while ((__raw_readl(uart_base + UART_SYSSTS_OFFSET) &
+ UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK);
+
+ /* Disable smart idle */
+ regVal = __raw_readl((uart_base + UART_SYSCFG_OFFSET));
+ regVal |= UART_SMART_IDLE_EN;
+ __raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
+}
+
+
+/**
+ * @brief The basic entry point for board initialization.
+ *
+ * This is called as part of machine init (after arch init).
+ * This is again called with stack in SRAM, so not too many
+ * constructs possible here.
+ *
+ * @return void
+ */
+static int beaglebone_board_init(void)
+{
+ int in_sdram = running_in_sdram();
+
+ /* WDT1 is already running when the bootloader gets control
+ * Disable it to avoid "random" resets
+ */
+ __raw_writel(0xAAAA, WDT_WSPR);
+ while(__raw_readl(WDT_WWPS) != 0x0);
+ __raw_writel(0x5555, WDT_WSPR);
+ while(__raw_readl(WDT_WWPS) != 0x0);
+
+ /* Dont reconfigure SDRAM while running in SDRAM! */
+ if (!in_sdram)
+ beaglebone_sram_init();
+
+ /* Enable pin mux */
+ enable_uart0_pin_mux();
+
+ return 0;
+}
+pure_initcall(beaglebone_board_init);
+
+/******************** Board Run Time *******************/
+
+#ifdef CONFIG_DRIVER_SERIAL_NS16550
+
+static struct NS16550_plat serial_plat = {
+ .clock = 48000000, /* 48MHz (APLL96/2) */
+ .shift = 2,
+};
+
+/**
+ * @brief UART serial port initialization - remember to enable COM clocks in
+ * arch
+ *
+ * @return result of device registration
+ */
+static int beaglebone_console_init(void)
+{
+ /* Register the serial port */
+ add_ns16550_device(-1, AM33XX_UART0_BASE, SZ_1K, IORESOURCE_MEM_8BIT,
+ &serial_plat);
+
+ return 0;
+}
+console_initcall(beaglebone_console_init);
+#endif /* CONFIG_DRIVER_SERIAL_NS16550 */
+
+static int beaglebone_mem_init(void)
+{
+ arm_add_mem_device("ram0", 0x80000000, 256 * 1024 * 1024);
+
+ return 0;
+}
+mem_initcall(beaglebone_mem_init);
+
+static int beaglebone_devices_init(void)
+{
+ add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL,
+ AM33XX_MMCHS0_BASE+0x100, SZ_4K,
+ IORESOURCE_MEM, NULL);
+
+ enable_i2c0_pin_mux();
+
+ armlinux_set_bootparams((void *)0x80000100);
+ armlinux_set_architecture(MACH_TYPE_BEAGLEBONE);
+
+ return 0;
+}
+device_initcall(beaglebone_devices_init);
+
+#ifdef CONFIG_DEFAULT_ENVIRONMENT
+static int beaglebone_env_init(void)
+{
+ struct stat s;
+ char *diskdev = "/dev/disk0.0";
+ int ret;
+
+ ret = stat(diskdev, &s);
+ if (ret) {
+ printf("device %s not found. Using default environment\n", diskdev);
+ return 0;
+ }
+
+ mkdir ("/boot", 0666);
+ ret = mount(diskdev, "fat", "/boot");
+ if (ret) {
+ printf("failed to mount %s\n", diskdev);
+ return 0;
+ }
+
+ if (IS_ENABLED(CONFIG_OMAP_BUILD_IFT))
+ default_environment_path = "/dev/defaultenv";
+ else
+ default_environment_path = "/boot/barebox.env";
+
+ return 0;
+}
+late_initcall(beaglebone_env_init);
+#endif
diff --git a/arch/arm/boards/beaglebone/config.h b/arch/arm/boards/beaglebone/config.h
new file mode 100644
index 0000000..252aa79
--- /dev/null
+++ b/arch/arm/boards/beaglebone/config.h
@@ -0,0 +1,17 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _CONFIG_H_
+# define _CONFIG_H_
+
+#endif /* _CONFIG_H_ */
diff --git a/arch/arm/boards/beaglebone/env/boot/sd b/arch/arm/boards/beaglebone/env/boot/sd
new file mode 100644
index 0000000..dce0605
--- /dev/null
+++ b/arch/arm/boards/beaglebone/env/boot/sd
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ boot-menu-add-entry "$0" "kernel & rootfs on SD card"
+ exit
+fi
+
+global.bootm.image=/boot/uImage
+global.bootm.oftree=/boot/oftree
+#global.bootm.initrd=<path to initrd>
+global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
diff --git a/arch/arm/boards/beaglebone/env/config b/arch/arm/boards/beaglebone/env/config
new file mode 100644
index 0000000..4b7a635
--- /dev/null
+++ b/arch/arm/boards/beaglebone/env/config
@@ -0,0 +1,21 @@
+#!/bin/sh
+
+# change network settings in /env/network/eth0
+# change mtd partition settings and automountpoints in /env/init/*
+
+global.hostname=beaglebone
+
+# set to false if you do not want to have colors
+global.allow_color=true
+
+# user (used for network filenames)
+global.user=none
+
+# timeout in seconds before the default boot entry is started
+global.autoboot_timeout=3
+
+# default boot entry (one of /env/boot/*)
+global.boot.default=sd
+
+# base bootargs
+global.linux.bootargs.base="console=ttyO0,115200n8"
diff --git a/arch/arm/configs/am335x_beaglebone_defconfig b/arch/arm/configs/am335x_beaglebone_defconfig
new file mode 100644
index 0000000..2066d9c
--- /dev/null
+++ b/arch/arm/configs/am335x_beaglebone_defconfig
@@ -0,0 +1,54 @@
+CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_AM33XX=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x81000000
+CONFIG_KALLSYMS=y
+CONFIG_PROMPT="barebox> "
+CONFIG_LONGHELP=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+# CONFIG_TIMESTAMP is not set
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/beaglebone/env"
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
+# CONFIG_SPI is not set
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_OMAP_HSMMC=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/configs/am335x_beaglebone_mlo_large_defconfig b/arch/arm/configs/am335x_beaglebone_mlo_large_defconfig
new file mode 100644
index 0000000..d90f581
--- /dev/null
+++ b/arch/arm/configs/am335x_beaglebone_mlo_large_defconfig
@@ -0,0 +1,55 @@
+CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_AM33XX=y
+# CONFIG_OMAP_GPMC is not set
+CONFIG_OMAP_BUILD_IFT=y
+CONFIG_THUMB2_BAREBOX=y
+# CONFIG_CMD_ARM_CPUINFO is not set
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x402F0400
+CONFIG_MEMORY_LAYOUT_FIXED=y
+CONFIG_STACK_BASE=0x4030B800
+CONFIG_STACK_SIZE=0x1600
+CONFIG_MALLOC_BASE=0x8F000000
+CONFIG_MALLOC_SIZE=0x1000000
+CONFIG_PROMPT="barebox> "
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+# CONFIG_TIMESTAMP is not set
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/beaglebone/env"
+CONFIG_BAREBOXENV_TARGET=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+# CONFIG_CMD_UMOUNT is not set
+# CONFIG_CMD_CLEAR is not set
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+# CONFIG_CMD_BOOTU is not set
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIMEOUT=y
+# CONFIG_CMD_VERSION is not set
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
+# CONFIG_SPI is not set
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+# CONFIG_MCI_INFO is not set
+# CONFIG_MCI_WRITE is not set
+CONFIG_MCI_OMAP_HSMMC=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/configs/am335x_beaglebone_mlo_small_defconfig b/arch/arm/configs/am335x_beaglebone_mlo_small_defconfig
new file mode 100644
index 0000000..886dad9
--- /dev/null
+++ b/arch/arm/configs/am335x_beaglebone_mlo_small_defconfig
@@ -0,0 +1,31 @@
+CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_AM33XX=y
+# CONFIG_OMAP_GPMC is not set
+CONFIG_OMAP_BUILD_IFT=y
+CONFIG_THUMB2_BAREBOX=y
+# CONFIG_CMD_ARM_CPUINFO is not set
+# CONFIG_BANNER is not set
+# CONFIG_MEMINFO is not set
+CONFIG_ENVIRONMENT_VARIABLES=y
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x402F0400
+CONFIG_MEMORY_LAYOUT_FIXED=y
+CONFIG_STACK_BASE=0x4030B800
+CONFIG_STACK_SIZE=0x1600
+CONFIG_MALLOC_BASE=0x8F000000
+CONFIG_MALLOC_SIZE=0x1000000
+CONFIG_PROMPT="MLO>"
+CONFIG_SHELL_NONE=y
+# CONFIG_ERRNO_MESSAGES is not set
+# CONFIG_TIMESTAMP is not set
+# CONFIG_DEFAULT_ENVIRONMENT is not set
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
+# CONFIG_SPI is not set
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_OMAP_HSMMC=y
+# CONFIG_FS_RAMFS is not set
+# CONFIG_FS_DEVFS is not set
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index b94500a..ae1e07e 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -105,7 +105,8 @@ config OMAP4_USBBOOT
config BOARDINFO
default "Archos G9" if MACH_ARCHOSG9
default "Texas Instrument's SDP343x" if MACH_OMAP343xSDP
- default "Texas Instrument's Beagle" if MACH_BEAGLE
+ default "Texas Instrument's Beagle Board" if MACH_BEAGLE
+ default "Texas Instrument's Beagle Bone" if MACH_BEAGLEBONE
default "Texas Instrument's OMAP3EVM" if MACH_OMAP3EVM
default "Texas Instrument's Panda" if MACH_PANDA
default "Phytec phyCORE pcm049" if MACH_PCM049
@@ -129,6 +130,14 @@ config MACH_BEAGLE
help
Say Y here if you are using Beagle Board
+config MACH_BEAGLEBONE
+ bool "Texas Instrument's Beagle Bone"
+ select OMAP_CLOCK_ALL
+ select HAVE_NOSHELL
+ depends on ARCH_AM33XX
+ help
+ Say Y here if you are using Beagle Bone
+
config MACH_OMAP3EVM
bool "Texas Instrument's OMAP3 EVM"
select HAVE_NOSHELL
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 290034e..1536744 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -23,7 +23,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o auxcr.o
pbl-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o auxcr.o
obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
-obj-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o
+obj-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o
obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c
new file mode 100644
index 0000000..a28540c
--- /dev/null
+++ b/arch/arm/mach-omap/am33xx_clock.c
@@ -0,0 +1,289 @@
+/*
+ * pll.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <mach/am33xx-clock.h>
+
+#define PRCM_MOD_EN 0x2
+#define PRCM_FORCE_WAKEUP 0x2
+
+#define PRCM_EMIF_CLK_ACTIVITY (0x1 << 2)
+#define PRCM_L3_GCLK_ACTIVITY (0x1 << 4)
+
+#define PLL_BYPASS_MODE 0x4
+#define PLL_LOCK_MODE 0x7
+#define PLL_MULTIPLIER_SHIFT 8
+
+static void interface_clocks_enable(void)
+{
+ /* Enable all the Interconnect Modules */
+ __raw_writel(PRCM_MOD_EN, CM_PER_L3_CLKCTRL);
+ while (__raw_readl(CM_PER_L3_CLKCTRL) != PRCM_MOD_EN);
+
+ __raw_writel(PRCM_MOD_EN, CM_PER_L4LS_CLKCTRL);
+ while (__raw_readl(CM_PER_L4LS_CLKCTRL) != PRCM_MOD_EN);
+
+ __raw_writel(PRCM_MOD_EN, CM_PER_L4FW_CLKCTRL);
+ while (__raw_readl(CM_PER_L4FW_CLKCTRL) != PRCM_MOD_EN);
+
+ __raw_writel(PRCM_MOD_EN, CM_WKUP_L4WKUP_CLKCTRL);
+ while (__raw_readl(CM_WKUP_L4WKUP_CLKCTRL) != PRCM_MOD_EN);
+
+ __raw_writel(PRCM_MOD_EN, CM_PER_L3_INSTR_CLKCTRL);
+ while (__raw_readl(CM_PER_L3_INSTR_CLKCTRL) != PRCM_MOD_EN);
+
+ __raw_writel(PRCM_MOD_EN, CM_PER_L4HS_CLKCTRL);
+ while (__raw_readl(CM_PER_L4HS_CLKCTRL) != PRCM_MOD_EN);
+
+ __raw_writel(PRCM_MOD_EN, CM_PER_SPI1_CLKCTRL);
+ while (__raw_readl(CM_PER_SPI1_CLKCTRL) != PRCM_MOD_EN);
+
+ /* GPIO0 */
+ __raw_writel(PRCM_MOD_EN, CM_WKUP_GPIO0_CLKCTRL);
+ while (__raw_readl(CM_WKUP_GPIO0_CLKCTRL) != PRCM_MOD_EN);
+}
+
+static void power_domain_transition_enable(void)
+{
+ /*
+ * Force power domain wake up transition
+ * Ensure that the corresponding interface clock is active before
+ * using the peripheral
+ */
+ __raw_writel(PRCM_FORCE_WAKEUP, CM_PER_L3_CLKSTCTRL);
+
+ __raw_writel(PRCM_FORCE_WAKEUP, CM_PER_L4LS_CLKSTCTRL);
+
+ __raw_writel(PRCM_FORCE_WAKEUP, CM_WKUP_CLKSTCTRL);
+
+ __raw_writel(PRCM_FORCE_WAKEUP, CM_PER_L4FW_CLKSTCTRL);
+
+ __raw_writel(PRCM_FORCE_WAKEUP, CM_PER_L3S_CLKSTCTRL);
+}
+
+/*
+ * Enable the module clock and the power domain for required peripherals
+ */
+static void per_clocks_enable(void)
+{
+ /* Enable the module clock */
+ __raw_writel(PRCM_MOD_EN, CM_PER_TIMER2_CLKCTRL);
+ while (__raw_readl(CM_PER_TIMER2_CLKCTRL) != PRCM_MOD_EN);
+
+ /* Select the Master osc 24 MHZ as Timer2 clock source */
+ __raw_writel(0x1, CLKSEL_TIMER2_CLK);
+
+ /* UART0 */
+ __raw_writel(PRCM_MOD_EN, CM_WKUP_UART0_CLKCTRL);
+ while (__raw_readl(CM_WKUP_UART0_CLKCTRL) != PRCM_MOD_EN);
+
+ /* UART3 */
+ __raw_writel(PRCM_MOD_EN, CM_PER_UART3_CLKCTRL);
+ while (__raw_readl(CM_PER_UART3_CLKCTRL) != PRCM_MOD_EN);
+
+ /* GPMC */
+ __raw_writel(PRCM_MOD_EN, CM_PER_GPMC_CLKCTRL);
+ while (__raw_readl(CM_PER_GPMC_CLKCTRL) != PRCM_MOD_EN);
+
+ /* ELM */
+ __raw_writel(PRCM_MOD_EN, CM_PER_ELM_CLKCTRL);
+ while (__raw_readl(CM_PER_ELM_CLKCTRL) != PRCM_MOD_EN);
+
+ /* i2c0 */
+ __raw_writel(PRCM_MOD_EN, CM_WKUP_I2C0_CLKCTRL);
+ while (__raw_readl(CM_WKUP_I2C0_CLKCTRL) != PRCM_MOD_EN);
+
+ /* i2c1 */
+ __raw_writel(PRCM_MOD_EN, CM_PER_I2C1_CLKCTRL);
+ while (__raw_readl(CM_PER_I2C1_CLKCTRL) != PRCM_MOD_EN);
+
+ /* i2c2 */
+ __raw_writel(PRCM_MOD_EN, CM_PER_I2C2_CLKCTRL);
+ while (__raw_readl(CM_PER_I2C2_CLKCTRL) != PRCM_MOD_EN);
+
+ /* Ethernet */
+ __raw_writel(PRCM_MOD_EN, CM_PER_CPGMAC0_CLKCTRL);
+ __raw_writel(PRCM_MOD_EN, CM_PER_CPSW_CLKSTCTRL);
+ while ((__raw_readl(CM_PER_CPGMAC0_CLKCTRL) & 0x30000) != 0x0);
+
+ /* MMC 0 & 1 */
+ __raw_writel(PRCM_MOD_EN, CM_PER_MMC0_CLKCTRL);
+ while (__raw_readl(CM_PER_MMC0_CLKCTRL) != PRCM_MOD_EN);
+ __raw_writel(PRCM_MOD_EN, CM_PER_MMC1_CLKCTRL);
+ while (__raw_readl(CM_PER_MMC1_CLKCTRL) != PRCM_MOD_EN);
+
+ /* Enable the control module though RBL would have done it*/
+ __raw_writel(PRCM_MOD_EN, CM_WKUP_CONTROL_CLKCTRL);
+ while (__raw_readl(CM_WKUP_CONTROL_CLKCTRL) != PRCM_MOD_EN);
+
+ /* SPI 0 & 1 */
+ __raw_writel(PRCM_MOD_EN, CM_PER_SPI0_CLKCTRL);
+ while (__raw_readl(CM_PER_SPI0_CLKCTRL) != PRCM_MOD_EN);
+
+ __raw_writel(PRCM_MOD_EN, CM_PER_SPI1_CLKCTRL);
+ while (__raw_readl(CM_PER_SPI1_CLKCTRL) != PRCM_MOD_EN);
+}
+
+static void mpu_pll_config(int mpupll_M)
+{
+ u32 clkmode, clksel, div_m2;
+
+ clkmode = __raw_readl(CM_CLKMODE_DPLL_MPU);
+ clksel = __raw_readl(CM_CLKSEL_DPLL_MPU);
+ div_m2 = __raw_readl(CM_DIV_M2_DPLL_MPU);
+
+ /* Set the PLL to bypass Mode */
+ __raw_writel(PLL_BYPASS_MODE, CM_CLKMODE_DPLL_MPU);
+
+ while(__raw_readl(CM_IDLEST_DPLL_MPU) != 0x00000100);
+
+ clksel = clksel & (~0x7ffff);
+ clksel = clksel | ((mpupll_M << 0x8) | MPUPLL_N);
+ __raw_writel(clksel, CM_CLKSEL_DPLL_MPU);
+
+ div_m2 = div_m2 & ~0x1f;
+ div_m2 = div_m2 | MPUPLL_M2;
+ __raw_writel(div_m2, CM_DIV_M2_DPLL_MPU);
+
+ clkmode = clkmode | 0x7;
+ __raw_writel(clkmode, CM_CLKMODE_DPLL_MPU);
+
+ while(__raw_readl(CM_IDLEST_DPLL_MPU) != 0x1);
+}
+
+static void core_pll_config(void)
+{
+ u32 clkmode, clksel, div_m4, div_m5, div_m6;
+
+ clkmode = __raw_readl(CM_CLKMODE_DPLL_CORE);
+ clksel = __raw_readl(CM_CLKSEL_DPLL_CORE);
+ div_m4 = __raw_readl(CM_DIV_M4_DPLL_CORE);
+ div_m5 = __raw_readl(CM_DIV_M5_DPLL_CORE);
+ div_m6 = __raw_readl(CM_DIV_M6_DPLL_CORE);
+
+ /* Set the PLL to bypass Mode */
+ __raw_writel(PLL_BYPASS_MODE, CM_CLKMODE_DPLL_CORE);
+
+ while(__raw_readl(CM_IDLEST_DPLL_CORE) != 0x00000100);
+
+ clksel = clksel & (~0x7ffff);
+ clksel = clksel | ((COREPLL_M << 0x8) | COREPLL_N);
+ __raw_writel(clksel, CM_CLKSEL_DPLL_CORE);
+
+ div_m4 = div_m4 & ~0x1f;
+ div_m4 = div_m4 | COREPLL_M4;
+ __raw_writel(div_m4, CM_DIV_M4_DPLL_CORE);
+
+ div_m5 = div_m5 & ~0x1f;
+ div_m5 = div_m5 | COREPLL_M5;
+ __raw_writel(div_m5, CM_DIV_M5_DPLL_CORE);
+
+ div_m6 = div_m6 & ~0x1f;
+ div_m6 = div_m6 | COREPLL_M6;
+ __raw_writel(div_m6, CM_DIV_M6_DPLL_CORE);
+
+
+ clkmode = clkmode | 0x7;
+ __raw_writel(clkmode, CM_CLKMODE_DPLL_CORE);
+
+ while(__raw_readl(CM_IDLEST_DPLL_CORE) != 0x1);
+}
+
+static void per_pll_config(void)
+{
+ u32 clkmode, clksel, div_m2;
+
+ clkmode = __raw_readl(CM_CLKMODE_DPLL_PER);
+ clksel = __raw_readl(CM_CLKSEL_DPLL_PER);
+ div_m2 = __raw_readl(CM_DIV_M2_DPLL_PER);
+
+ /* Set the PLL to bypass Mode */
+ __raw_writel(PLL_BYPASS_MODE, CM_CLKMODE_DPLL_PER);
+
+ while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x00000100);
+
+ clksel = clksel & (~0x7ffff);
+ clksel = clksel | ((PERPLL_M << 0x8) | PERPLL_N);
+ __raw_writel(clksel, CM_CLKSEL_DPLL_PER);
+
+ div_m2 = div_m2 & ~0x7f;
+ div_m2 = div_m2 | PERPLL_M2;
+ __raw_writel(div_m2, CM_DIV_M2_DPLL_PER);
+
+ clkmode = clkmode | 0x7;
+ __raw_writel(clkmode, CM_CLKMODE_DPLL_PER);
+
+ while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x1);
+}
+
+static void ddr_pll_config(void)
+{
+ u32 clkmode, clksel, div_m2;
+
+ clkmode = __raw_readl(CM_CLKMODE_DPLL_DDR);
+ clksel = __raw_readl(CM_CLKSEL_DPLL_DDR);
+ div_m2 = __raw_readl(CM_DIV_M2_DPLL_DDR);
+
+ /* Set the PLL to bypass Mode */
+ clkmode = (clkmode & 0xfffffff8) | 0x00000004;
+ __raw_writel(clkmode, CM_CLKMODE_DPLL_DDR);
+
+ while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000100) != 0x00000100);
+
+ clksel = clksel & (~0x7ffff);
+ clksel = clksel | ((DDRPLL_M << 0x8) | DDRPLL_N);
+ __raw_writel(clksel, CM_CLKSEL_DPLL_DDR);
+
+ div_m2 = div_m2 & 0xFFFFFFE0;
+ div_m2 = div_m2 | DDRPLL_M2;
+ __raw_writel(div_m2, CM_DIV_M2_DPLL_DDR);
+
+ clkmode = (clkmode & 0xfffffff8) | 0x7;
+ __raw_writel(clkmode, CM_CLKMODE_DPLL_DDR);
+
+ while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x1);
+}
+
+void enable_ddr_clocks(void)
+{
+ /* Enable the EMIF_FW Functional clock */
+ __raw_writel(PRCM_MOD_EN, CM_PER_EMIF_FW_CLKCTRL);
+ /* Enable EMIF0 Clock */
+ __raw_writel(PRCM_MOD_EN, CM_PER_EMIF_CLKCTRL);
+ /* Poll for emif_gclk & L3_G clock are active */
+ while ((__raw_readl(CM_PER_L3_CLKSTCTRL) & (PRCM_EMIF_CLK_ACTIVITY |
+ PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY |
+ PRCM_L3_GCLK_ACTIVITY));
+ /* Poll if module is functional */
+ while ((__raw_readl(CM_PER_EMIF_CLKCTRL)) != PRCM_MOD_EN);
+
+}
+
+/*
+ * Configure the PLL/PRCM for necessary peripherals
+ */
+void pll_init()
+{
+ mpu_pll_config(MPUPLL_M_500);
+ core_pll_config();
+ per_pll_config();
+ ddr_pll_config();
+ /* Enable the required interconnect clocks */
+ interface_clocks_enable();
+ /* Enable power domain transition */
+ power_domain_transition_enable();
+ /* Enable the required peripherals */
+ per_clocks_enable();
+}
diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c
index f73f946..e8293f7 100644
--- a/arch/arm/mach-omap/am33xx_generic.c
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -1,5 +1,6 @@
/*
* (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH
+ * (C) Copyright 2012 Jan Luebbe <j.luebbe@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -20,6 +21,8 @@
#include <io.h>
#include <mach/am33xx-silicon.h>
#include <mach/am33xx-clock.h>
+#include <mach/sys_info.h>
+#include <mach/xload.h>
void __noreturn reset_cpu(unsigned long addr)
{
@@ -27,3 +30,68 @@ void __noreturn reset_cpu(unsigned long addr)
while (1);
}
+
+/**
+ * @brief Get the upper address of current execution
+ *
+ * we can use this to figure out if we are running in SRAM /
+ * XIP Flash or in SDRAM
+ *
+ * @return base address
+ */
+u32 get_base(void)
+{
+ u32 val;
+ __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
+ val &= 0xF0000000;
+ val >>= 28;
+ return val;
+}
+
+/**
+ * @brief Are we running in Flash XIP?
+ *
+ * If the base is in GPMC address space, we probably are!
+ *
+ * @return 1 if we are running in XIP mode, else return 0
+ */
+u32 running_in_flash(void)
+{
+ if (get_base() < 4)
+ return 1; /* in flash */
+ return 0; /* running in SRAM or SDRAM */
+}
+
+/**
+ * @brief Are we running in OMAP internal SRAM?
+ *
+ * If in SRAM address, then yes!
+ *
+ * @return 1 if we are running in SRAM, else return 0
+ */
+u32 running_in_sram(void)
+{
+ if (get_base() == 4)
+ return 1; /* in SRAM */
+ return 0; /* running in FLASH or SDRAM */
+}
+
+/**
+ * @brief Are we running in SDRAM?
+ *
+ * if we are not in GPMC nor in SRAM address space,
+ * we are in SDRAM execution area
+ *
+ * @return 1 if we are running from SDRAM, else return 0
+ */
+u32 running_in_sdram(void)
+{
+ if (get_base() > 4)
+ return 1; /* in sdram */
+ return 0; /* running in SRAM or FLASH */
+}
+
+enum omap_boot_src am33xx_bootsrc(void)
+{
+ return OMAP_BOOTSRC_MMC1; /* only MMC for now */
+}
diff --git a/arch/arm/mach-omap/am33xx_mux.c b/arch/arm/mach-omap/am33xx_mux.c
new file mode 100644
index 0000000..22bf317
--- /dev/null
+++ b/arch/arm/mach-omap/am33xx_mux.c
@@ -0,0 +1,506 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <mach/am33xx-silicon.h>
+
+#define MUX_CFG(value, offset) \
+ __raw_writel(value, (AM33XX_CTRL_BASE + offset));
+
+/* PAD Control Fields */
+#define SLEWCTRL (0x1 << 6)
+#define RXACTIVE (0x1 << 5)
+#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
+#define PULLUDEN (0x0 << 3) /* Pull up enabled */
+#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
+#define MODE(val) val
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+/* TODO replace with defines */
+struct pad_signals {
+ int gpmc_ad0;
+ int gpmc_ad1;
+ int gpmc_ad2;
+ int gpmc_ad3;
+ int gpmc_ad4;
+ int gpmc_ad5;
+ int gpmc_ad6;
+ int gpmc_ad7;
+ int gpmc_ad8;
+ int gpmc_ad9;
+ int gpmc_ad10;
+ int gpmc_ad11;
+ int gpmc_ad12;
+ int gpmc_ad13;
+ int gpmc_ad14;
+ int gpmc_ad15;
+ int gpmc_a0;
+ int gpmc_a1;
+ int gpmc_a2;
+ int gpmc_a3;
+ int gpmc_a4;
+ int gpmc_a5;
+ int gpmc_a6;
+ int gpmc_a7;
+ int gpmc_a8;
+ int gpmc_a9;
+ int gpmc_a10;
+ int gpmc_a11;
+ int gpmc_wait0;
+ int gpmc_wpn;
+ int gpmc_be1n;
+ int gpmc_csn0;
+ int gpmc_csn1;
+ int gpmc_csn2;
+ int gpmc_csn3;
+ int gpmc_clk;
+ int gpmc_advn_ale;
+ int gpmc_oen_ren;
+ int gpmc_wen;
+ int gpmc_be0n_cle;
+ int lcd_data0;
+ int lcd_data1;
+ int lcd_data2;
+ int lcd_data3;
+ int lcd_data4;
+ int lcd_data5;
+ int lcd_data6;
+ int lcd_data7;
+ int lcd_data8;
+ int lcd_data9;
+ int lcd_data10;
+ int lcd_data11;
+ int lcd_data12;
+ int lcd_data13;
+ int lcd_data14;
+ int lcd_data15;
+ int lcd_vsync;
+ int lcd_hsync;
+ int lcd_pclk;
+ int lcd_ac_bias_en;
+ int mmc0_dat3;
+ int mmc0_dat2;
+ int mmc0_dat1;
+ int mmc0_dat0;
+ int mmc0_clk;
+ int mmc0_cmd;
+ int mii1_col;
+ int mii1_crs;
+ int mii1_rxerr;
+ int mii1_txen;
+ int mii1_rxdv;
+ int mii1_txd3;
+ int mii1_txd2;
+ int mii1_txd1;
+ int mii1_txd0;
+ int mii1_txclk;
+ int mii1_rxclk;
+ int mii1_rxd3;
+ int mii1_rxd2;
+ int mii1_rxd1;
+ int mii1_rxd0;
+ int rmii1_refclk;
+ int mdio_data;
+ int mdio_clk;
+ int spi0_sclk;
+ int spi0_d0;
+ int spi0_d1;
+ int spi0_cs0;
+ int spi0_cs1;
+ int ecap0_in_pwm0_out;
+ int uart0_ctsn;
+ int uart0_rtsn;
+ int uart0_rxd;
+ int uart0_txd;
+ int uart1_ctsn;
+ int uart1_rtsn;
+ int uart1_rxd;
+ int uart1_txd;
+ int i2c0_sda;
+ int i2c0_scl;
+ int mcasp0_aclkx;
+ int mcasp0_fsx;
+ int mcasp0_axr0;
+ int mcasp0_ahclkr;
+ int mcasp0_aclkr;
+ int mcasp0_fsr;
+ int mcasp0_axr1;
+ int mcasp0_ahclkx;
+ int xdma_event_intr0;
+ int xdma_event_intr1;
+ int nresetin_out;
+ int porz;
+ int nnmi;
+ int osc0_in;
+ int osc0_out;
+ int rsvd1;
+ int tms;
+ int tdi;
+ int tdo;
+ int tck;
+ int ntrst;
+ int emu0;
+ int emu1;
+ int osc1_in;
+ int osc1_out;
+ int pmic_power_en;
+ int rtc_porz;
+ int rsvd2;
+ int ext_wakeup;
+ int enz_kaldo_1p8v;
+ int usb0_dm;
+ int usb0_dp;
+ int usb0_ce;
+ int usb0_id;
+ int usb0_vbus;
+ int usb0_drvvbus;
+ int usb1_dm;
+ int usb1_dp;
+ int usb1_ce;
+ int usb1_id;
+ int usb1_vbus;
+ int usb1_drvvbus;
+ int ddr_resetn;
+ int ddr_csn0;
+ int ddr_cke;
+ int ddr_ck;
+ int ddr_nck;
+ int ddr_casn;
+ int ddr_rasn;
+ int ddr_wen;
+ int ddr_ba0;
+ int ddr_ba1;
+ int ddr_ba2;
+ int ddr_a0;
+ int ddr_a1;
+ int ddr_a2;
+ int ddr_a3;
+ int ddr_a4;
+ int ddr_a5;
+ int ddr_a6;
+ int ddr_a7;
+ int ddr_a8;
+ int ddr_a9;
+ int ddr_a10;
+ int ddr_a11;
+ int ddr_a12;
+ int ddr_a13;
+ int ddr_a14;
+ int ddr_a15;
+ int ddr_odt;
+ int ddr_d0;
+ int ddr_d1;
+ int ddr_d2;
+ int ddr_d3;
+ int ddr_d4;
+ int ddr_d5;
+ int ddr_d6;
+ int ddr_d7;
+ int ddr_d8;
+ int ddr_d9;
+ int ddr_d10;
+ int ddr_d11;
+ int ddr_d12;
+ int ddr_d13;
+ int ddr_d14;
+ int ddr_d15;
+ int ddr_dqm0;
+ int ddr_dqm1;
+ int ddr_dqs0;
+ int ddr_dqsn0;
+ int ddr_dqs1;
+ int ddr_dqsn1;
+ int ddr_vref;
+ int ddr_vtp;
+ int ddr_strben0;
+ int ddr_strben1;
+ int ain7;
+ int ain6;
+ int ain5;
+ int ain4;
+ int ain3;
+ int ain2;
+ int ain1;
+ int ain0;
+ int vrefp;
+ int vrefn;
+};
+
+struct module_pin_mux {
+ short reg_offset;
+ unsigned char val;
+};
+
+#define PAD_CTRL_BASE 0x800
+#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
+ (PAD_CTRL_BASE))->x)
+
+static const __maybe_unused struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static const __maybe_unused struct module_pin_mux uart3_pin_mux[] = {
+ {OFFSET(spi0_cs1), (MODE(1) | PULLUDEN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
+ {-1},
+};
+
+
+#ifdef CONFIG_NAND
+static const __maybe_unused struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+#endif
+
+static const __maybe_unused struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static const __maybe_unused struct module_pin_mux i2c1_pin_mux[] = {
+ {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static const __maybe_unused struct module_pin_mux i2c2_pin_mux[] = {
+ {OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static const __maybe_unused struct module_pin_mux rgmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
+ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
+ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
+ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
+ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
+ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
+ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
+ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
+ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static const __maybe_unused struct module_pin_mux rgmii2_pin_mux[] = {
+ {OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */
+ {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */
+ {OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */
+ {OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */
+ {OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */
+ {OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */
+ {OFFSET(gpmc_a6), MODE(2)}, /* RGMII2_TCLK */
+ {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */
+ {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */
+ {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII2_RD2 */
+ {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */
+ {OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII2_RD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static const __maybe_unused struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
+ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
+ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
+ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static const __maybe_unused struct module_pin_mux rmii1_pin_mux[] = {
+ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
+ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
+ {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
+ {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
+ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
+ {-1},
+};
+
+#ifdef CONFIG_NOR
+static const __maybe_unused struct module_pin_mux nor_pin_mux[] = {
+ {OFFSET(lcd_data0), MODE(1) | PULLUDEN}, /* NOR_A0 */
+ {OFFSET(lcd_data1), MODE(1) | PULLUDEN}, /* NOR_A1 */
+ {OFFSET(lcd_data2), MODE(1) | PULLUDEN}, /* NOR_A2 */
+ {OFFSET(lcd_data3), MODE(1) | PULLUDEN}, /* NOR_A3 */
+ {OFFSET(lcd_data4), MODE(1) | PULLUDEN}, /* NOR_A4 */
+ {OFFSET(lcd_data5), MODE(1) | PULLUDEN}, /* NOR_A5 */
+ {OFFSET(lcd_data6), MODE(1) | PULLUDEN}, /* NOR_A6 */
+ {OFFSET(lcd_data7), MODE(1) | PULLUDEN}, /* NOR_A7 */
+ {OFFSET(gpmc_a8), MODE(0)}, /* NOR_A8 */
+ {OFFSET(gpmc_a9), MODE(0)}, /* NOR_A9 */
+ {OFFSET(gpmc_a10), MODE(0)}, /* NOR_A10 */
+ {OFFSET(gpmc_a11), MODE(0)}, /* NOR_A11 */
+ {OFFSET(lcd_data8), MODE(1) | PULLUDEN}, /* NOR_A12 */
+ {OFFSET(lcd_data9), MODE(1) | PULLUDEN}, /* NOR_A13 */
+ {OFFSET(lcd_data10), MODE(1) | PULLUDEN}, /* NOR_A14 */
+ {OFFSET(lcd_data11), MODE(1) | PULLUDEN}, /* NOR_A15 */
+ {OFFSET(lcd_data12), MODE(1) | PULLUDEN}, /* NOR_A16 */
+ {OFFSET(lcd_data13), MODE(1) | PULLUDEN}, /* NOR_A17 */
+ {OFFSET(lcd_data14), MODE(1) | PULLUDEN}, /* NOR_A18 */
+ {OFFSET(lcd_data15), MODE(1) | PULLUDEN}, /* NOR_A19 */
+ {OFFSET(gpmc_a4), MODE(4)}, /* NOR_A20 */
+ {OFFSET(gpmc_a5), MODE(4)}, /* NOR_A21 */
+ {OFFSET(gpmc_a6), MODE(4)}, /* NOR_A22 */
+ {OFFSET(gpmc_ad0), MODE(0) | RXACTIVE}, /* NOR_AD0 */
+ {OFFSET(gpmc_ad1), MODE(0) | RXACTIVE}, /* NOR_AD1 */
+ {OFFSET(gpmc_ad2), MODE(0) | RXACTIVE}, /* NOR_AD2 */
+ {OFFSET(gpmc_ad3), MODE(0) | RXACTIVE}, /* NOR_AD3 */
+ {OFFSET(gpmc_ad4), MODE(0) | RXACTIVE}, /* NOR_AD4 */
+ {OFFSET(gpmc_ad5), MODE(0) | RXACTIVE}, /* NOR_AD5 */
+ {OFFSET(gpmc_ad6), MODE(0) | RXACTIVE}, /* NOR_AD6 */
+ {OFFSET(gpmc_ad7), MODE(0) | RXACTIVE}, /* NOR_AD7 */
+ {OFFSET(gpmc_ad8), MODE(0) | RXACTIVE}, /* NOR_AD8 */
+ {OFFSET(gpmc_ad9), MODE(0) | RXACTIVE}, /* NOR_AD9 */
+ {OFFSET(gpmc_ad10), MODE(0) | RXACTIVE}, /* NOR_AD10 */
+ {OFFSET(gpmc_ad11), MODE(0) | RXACTIVE}, /* NOR_AD11 */
+ {OFFSET(gpmc_ad12), MODE(0) | RXACTIVE}, /* NOR_AD12 */
+ {OFFSET(gpmc_ad13), MODE(0) | RXACTIVE}, /* NOR_AD13 */
+ {OFFSET(gpmc_ad14), MODE(0) | RXACTIVE}, /* NOR_AD14 */
+ {OFFSET(gpmc_ad15), MODE(0) | RXACTIVE}, /* NOR_AD15 */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* NOR_CE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUP_EN)}, /* NOR_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUP_EN)}, /* NOR_WEN */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NOR WAIT */
+ {OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDEN}, /* NOR RESET */
+ {-1},
+};
+#endif
+
+static const __maybe_unused struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+
+static const __maybe_unused struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {OFFSET(uart1_rxd), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
+ {OFFSET(mcasp0_fsx), (MODE(4) | RXACTIVE)}, /* MMC1_CD */
+ {-1},
+};
+
+static const __maybe_unused struct module_pin_mux spi0_pin_mux[] = {
+ {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE}, /*SPI0_SCLK */
+ {OFFSET(spi0_d0), MODE(0) | PULLUDEN | PULLUP_EN |
+ RXACTIVE}, /*SPI0_D0 */
+ {OFFSET(spi0_d1), MODE(0) | PULLUDEN |
+ RXACTIVE}, /*SPI0_D1 */
+ {OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE}, /*SPI0_CS0 */
+ {-1},
+};
+
+static const __maybe_unused struct module_pin_mux spi1_pin_mux[] = {
+ {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE}, /*SPI0_SCLK */
+ {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | PULLUP_EN |
+ RXACTIVE}, /*SPI0_D0 */
+ {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE}, /*SPI0_D1 */
+ {OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN |
+ RXACTIVE}, /*SPI0_CS0 */
+ {-1},
+};
+
+/*
+ * Configure the pin mux for the module
+ */
+static void configure_module_pin_mux(const struct module_pin_mux *mod_pin_mux)
+{
+ int i;
+
+ if (!mod_pin_mux)
+ return;
+
+ for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
+ MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
+}
+
+void enable_mii1_pin_mux(void)
+{
+ configure_module_pin_mux(mii1_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_i2c1_pin_mux(void)
+{
+ configure_module_pin_mux(i2c1_pin_mux);
+}
+
+void enable_i2c2_pin_mux(void)
+{
+ configure_module_pin_mux(i2c2_pin_mux);
+}
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
diff --git a/arch/arm/mach-omap/gpmc.c b/arch/arm/mach-omap/gpmc.c
index 4f54a10..3aaa4f6 100644
--- a/arch/arm/mach-omap/gpmc.c
+++ b/arch/arm/mach-omap/gpmc.c
@@ -26,6 +26,7 @@
#include <errno.h>
#include <mach/omap3-silicon.h>
#include <mach/omap4-silicon.h>
+#include <mach/am33xx-silicon.h>
#include <mach/gpmc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
@@ -38,6 +39,8 @@ static int gpmc_init(void)
omap_gpmc_base = (void *)OMAP3_GPMC_BASE;
#elif defined(CONFIG_ARCH_OMAP4)
omap_gpmc_base = (void *)OMAP44XX_GPMC_BASE;
+#elif defined(CONFIG_ARCH_AM33XX)
+ omap_gpmc_base = (void *)AM33XX_GPMC_BASE;
#else
#error "Unknown ARCH"
#endif
diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h
index 6845412..39c107f 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-clock.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h
@@ -19,5 +19,176 @@
#ifndef _AM33XX_CLOCKS_H_
#define _AM33XX_CLOCKS_H_
+#include "am33xx-silicon.h"
+
+/* Put the pll config values over here */
+
+#define OSC 24
+
+/* MAIN PLL Fdll = 1 GHZ, */
+#define MPUPLL_M_500 500 /* 125 * n */
+#define MPUPLL_M_550 550 /* 125 * n */
+#define MPUPLL_M_600 600 /* 125 * n */
+#define MPUPLL_M_720 720 /* 125 * n */
+
+#define MPUPLL_N 23 /* (n -1 ) */
+#define MPUPLL_M2 1
+
+/* Core PLL Fdll = 1 GHZ, */
+#define COREPLL_M 1000 /* 125 * n */
+#define COREPLL_N 23 /* (n -1 ) */
+
+#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
+#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
+#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
+
+/*
+ * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
+ * frequency needs to be set to 960 MHZ. Hence,
+ * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
+ */
+#define PERPLL_M 960
+#define PERPLL_N 23
+#define PERPLL_M2 5
+
+/* DDR Freq is 166 MHZ for now*/
+/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
+//#if (CONFIG_AM335X_EVM_IS_13x13 == 1)
+#if 0
+#define DDRPLL_M 166 /* M/N + 1 = 25/3 */
+#else
+#define DDRPLL_M 266
+#endif
+
+#define DDRPLL_N 23
+#define DDRPLL_M2 1
+
+/* PRCM */
+/* Module Offsets */
+#define CM_PER (AM33XX_PRM_BASE + 0x0)
+#define CM_WKUP (AM33XX_PRM_BASE + 0x400)
+#define CM_DPLL (AM33XX_PRM_BASE + 0x500)
+#define CM_DEVICE (AM33XX_PRM_BASE + 0x0700)
+#define CM_CEFUSE (AM33XX_PRM_BASE + 0x0A00)
+#define PRM_DEVICE (AM33XX_PRM_BASE + 0x0F00)
+/* Register Offsets */
+/* Core PLL ADPLLS */
+#define CM_CLKSEL_DPLL_CORE (CM_WKUP + 0x68)
+#define CM_CLKMODE_DPLL_CORE (CM_WKUP + 0x90)
+
+/* Core HSDIV */
+#define CM_DIV_M4_DPLL_CORE (CM_WKUP + 0x80)
+#define CM_DIV_M5_DPLL_CORE (CM_WKUP + 0x84)
+#define CM_DIV_M6_DPLL_CORE (CM_WKUP + 0xD8)
+#define CM_IDLEST_DPLL_CORE (CM_WKUP + 0x5c)
+
+/* Peripheral PLL */
+#define CM_CLKSEL_DPLL_PER (CM_WKUP + 0x9c)
+#define CM_CLKMODE_DPLL_PER (CM_WKUP + 0x8c)
+#define CM_DIV_M2_DPLL_PER (CM_WKUP + 0xAC)
+#define CM_IDLEST_DPLL_PER (CM_WKUP + 0x70)
+
+/* Display PLL */
+#define CM_CLKSEL_DPLL_DISP (CM_WKUP + 0x54)
+#define CM_CLKMODE_DPLL_DISP (CM_WKUP + 0x98)
+#define CM_DIV_M2_DPLL_DISP (CM_WKUP + 0xA4)
+
+/* DDR PLL */
+#define CM_CLKSEL_DPLL_DDR (CM_WKUP + 0x40)
+#define CM_CLKMODE_DPLL_DDR (CM_WKUP + 0x94)
+#define CM_DIV_M2_DPLL_DDR (CM_WKUP + 0xA0)
+#define CM_IDLEST_DPLL_DDR (CM_WKUP + 0x34)
+
+/* MPU PLL */
+#define CM_CLKSEL_DPLL_MPU (CM_WKUP + 0x2c)
+#define CM_CLKMODE_DPLL_MPU (CM_WKUP + 0x88)
+#define CM_DIV_M2_DPLL_MPU (CM_WKUP + 0xA8)
+#define CM_IDLEST_DPLL_MPU (CM_WKUP + 0x20)
+
+/* TIMER Clock Source Select */
+#define CLKSEL_TIMER2_CLK (CM_DPLL + 0x8)
+
+/* Interconnect clocks */
+#define CM_PER_L4LS_CLKCTRL (CM_PER + 0x60) /* EMIF */
+#define CM_PER_L4FW_CLKCTRL (CM_PER + 0x64) /* EMIF FW */
+#define CM_PER_L3_CLKCTRL (CM_PER + 0xE0) /* OCMC RAM */
+#define CM_PER_L3_INSTR_CLKCTRL (CM_PER + 0xDC)
+#define CM_PER_L4HS_CLKCTRL (CM_PER + 0x120)
+#define CM_WKUP_L4WKUP_CLKCTRL (CM_WKUP + 0x0c)/* UART0 */
+
+/* Domain Wake UP */
+#define CM_WKUP_CLKSTCTRL (CM_WKUP + 0) /* UART0 */
+#define CM_PER_L4LS_CLKSTCTRL (CM_PER + 0x0) /* TIMER2 */
+#define CM_PER_L3_CLKSTCTRL (CM_PER + 0x0c) /* EMIF */
+#define CM_PER_L4FW_CLKSTCTRL (CM_PER + 0x08) /* EMIF FW */
+#define CM_PER_L3S_CLKSTCTRL (CM_PER + 0x4)
+#define CM_PER_L4HS_CLKSTCTRL (CM_PER + 0x011c)
+#define CM_CEFUSE_CLKSTCTRL (CM_CEFUSE + 0x0)
+
+/* Module Enable Registers */
+#define CM_PER_TIMER2_CLKCTRL (CM_PER + 0x80) /* Timer2 */
+#define CM_WKUP_UART0_CLKCTRL (CM_WKUP + 0xB4)/* UART0 */
+#define CM_WKUP_CONTROL_CLKCTRL (CM_WKUP + 0x4) /* Control Module */
+#define CM_PER_EMIF_CLKCTRL (CM_PER + 0x28) /* EMIF */
+#define CM_PER_EMIF_FW_CLKCTRL (CM_PER + 0xD0) /* EMIF FW */
+#define CM_PER_GPMC_CLKCTRL (CM_PER + 0x30) /* GPMC */
+#define CM_PER_ELM_CLKCTRL (CM_PER + 0x40) /* ELM */
+#define CM_PER_SPI0_CLKCTRL (CM_PER + 0x4c) /* SPI0 */
+#define CM_PER_SPI1_CLKCTRL (CM_PER + 0x50) /* SPI1 */
+#define CM_WKUP_I2C0_CLKCTRL (CM_WKUP + 0xB8) /* I2C0 */
+#define CM_PER_CPGMAC0_CLKCTRL (CM_PER + 0x14) /* Ethernet */
+#define CM_PER_CPSW_CLKSTCTRL (CM_PER + 0x144)/* Ethernet */
+#define CM_PER_OCMCRAM_CLKCTRL (CM_PER + 0x2C) /* OCMC RAM */
+#define CM_PER_GPIO2_CLKCTRL (CM_PER + 0xB0) /* GPIO2 */
+#define CM_PER_UART3_CLKCTRL (CM_PER + 0x74) /* UART3 */
+#define CM_PER_I2C1_CLKCTRL (CM_PER + 0x48) /* I2C1 */
+#define CM_PER_I2C2_CLKCTRL (CM_PER + 0x44) /* I2C2 */
+#define CM_WKUP_GPIO0_CLKCTRL (CM_WKUP + 0x8) /* GPIO0 */
+
+#define CM_PER_MMC0_CLKCTRL (CM_PER + 0x3C)
+#define CM_PER_MMC1_CLKCTRL (CM_PER + 0xF4)
+#define CM_PER_MMC2_CLKCTRL (CM_PER + 0xF8)
+
+/* PRCM */
+#define CM_DPLL_OFFSET (AM33XX_PRM_BASE + 0x0300)
+
+#define CM_ALWON_WDTIMER_CLKCTRL (AM33XX_PRM_BASE + 0x158C)
+#define CM_ALWON_SPI_CLKCTRL (AM33XX_PRM_BASE + 0x1590)
+#define CM_ALWON_CONTROL_CLKCTRL (AM33XX_PRM_BASE + 0x15C4)
+
+#define CM_ALWON_L3_SLOW_CLKSTCTRL (AM33XX_PRM_BASE + 0x1400)
+
+#define CM_ALWON_GPIO_0_CLKCTRL (AM33XX_PRM_BASE + 0x155c)
+#define CM_ALWON_GPIO_0_OPTFCLKEN_DBCLK (AM33XX_PRM_BASE + 0x155c)
+
+/* Ethernet */
+#define CM_ETHERNET_CLKSTCTRL (AM33XX_PRM_BASE + 0x1404)
+#define CM_ALWON_ETHERNET_0_CLKCTRL (AM33XX_PRM_BASE + 0x15D4)
+#define CM_ALWON_ETHERNET_1_CLKCTRL (AM33XX_PRM_BASE + 0x15D8)
+
+/* UARTs */
+#define CM_ALWON_UART_0_CLKCTRL (AM33XX_PRM_BASE + 0x1550)
+#define CM_ALWON_UART_1_CLKCTRL (AM33XX_PRM_BASE + 0x1554)
+#define CM_ALWON_UART_2_CLKCTRL (AM33XX_PRM_BASE + 0x1558)
+
+/* I2C */
+/* Note: In ti814x I2C0 and I2C2 have common clk control */
+#define CM_ALWON_I2C_0_CLKCTRL (AM33XX_PRM_BASE + 0x1564)
+
+/* EMIF4 PRCM Defintion */
+#define CM_DEFAULT_L3_FAST_CLKSTCTRL (AM33XX_PRM_BASE + 0x0508)
+#define CM_DEFAULT_EMIF_0_CLKCTRL (AM33XX_PRM_BASE + 0x0520)
+#define CM_DEFAULT_EMIF_1_CLKCTRL (AM33XX_PRM_BASE + 0x0524)
+#define CM_DEFAULT_DMM_CLKCTRL (AM33XX_PRM_BASE + 0x0528)
+#define CM_DEFAULT_FW_CLKCTRL (AM33XX_PRM_BASE + 0x052C)
+
+/* ALWON PRCM */
+#define CM_ALWON_OCMC_0_CLKSTCTRL CM_PER_L3_CLKSTCTRL
+#define CM_ALWON_OCMC_0_CLKCTRL CM_PER_OCMCRAM_CLKCTRL
+
+#define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL
+
+extern void pll_init(void);
+extern void enable_ddr_clocks(void);
#endif /* endif _AM33XX_CLOCKS_H_ */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-mux.h b/arch/arm/mach-omap/include/mach/am33xx-mux.h
new file mode 100644
index 0000000..ed328f5
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/am33xx-mux.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __AM33XX_MUX_H__
+#define __AM33XX_MUX_H__
+
+extern void enable_mii1_pin_mux(void);
+extern void enable_i2c0_pin_mux(void);
+extern void enable_i2c1_pin_mux(void);
+extern void enable_i2c2_pin_mux(void);
+extern void enable_uart0_pin_mux(void);
+
+#endif /*__AM33XX_MUX_H__ */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
index 1858756..ea44d25 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
@@ -43,7 +43,150 @@
#define AM33XX_DMTIMER0_BASE (AM33XX_L4_WKUP_BASE + 0x205000)
/* PRM */
-#define OMAP_PRM_BASE (AM33XX_L4_WKUP_BASE + 0x200000)
+#define AM33XX_PRM_BASE (AM33XX_L4_WKUP_BASE + 0x200000)
+#define AM33XX_PRM_RSTCTRL (AM33XX_PRM_BASE + 0x0f00)
+#define AM33XX_PRM_RSTCTRL_RESET 0x1
+
+/* CTRL */
+#define AM33XX_CTRL_BASE (AM33XX_L4_WKUP_BASE + 0x210000)
+
+/* Watchdog Timer */
+#define WDT_BASE 0x44E35000
+
+/* EMIF Base address */
+#define EMIF4_0_CFG_BASE 0x4C000000
+#define EMIF4_1_CFG_BASE 0x4D000000
+#define DMM_BASE 0x4E000000
+
+#define AM335X_CPSW_BASE 0x4A100000
+#define AM335X_CPSW_MDIO_BASE 0x4A101000
+
+/*DMM & EMIF4 MMR Declaration*/
+#define DMM_LISA_MAP__0 (DMM_BASE + 0x40)
+#define DMM_LISA_MAP__1 (DMM_BASE + 0x44)
+#define DMM_LISA_MAP__2 (DMM_BASE + 0x48)
+#define DMM_LISA_MAP__3 (DMM_BASE + 0x4C)
+#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x460)
+
+#define EMIF_MOD_ID_REV (EMIF4_0_CFG_BASE + 0x0)
+#define EMIF4_0_SDRAM_STATUS (EMIF4_0_CFG_BASE + 0x04)
+#define EMIF4_0_SDRAM_CONFIG (EMIF4_0_CFG_BASE + 0x08)
+#define EMIF4_0_SDRAM_CONFIG2 (EMIF4_0_CFG_BASE + 0x0C)
+#define EMIF4_0_SDRAM_REF_CTRL (EMIF4_0_CFG_BASE + 0x10)
+#define EMIF4_0_SDRAM_REF_CTRL_SHADOW (EMIF4_0_CFG_BASE + 0x14)
+#define EMIF4_0_SDRAM_TIM_1 (EMIF4_0_CFG_BASE + 0x18)
+#define EMIF4_0_SDRAM_TIM_1_SHADOW (EMIF4_0_CFG_BASE + 0x1C)
+#define EMIF4_0_SDRAM_TIM_2 (EMIF4_0_CFG_BASE + 0x20)
+#define EMIF4_0_SDRAM_TIM_2_SHADOW (EMIF4_0_CFG_BASE + 0x24)
+#define EMIF4_0_SDRAM_TIM_3 (EMIF4_0_CFG_BASE + 0x28)
+#define EMIF4_0_SDRAM_TIM_3_SHADOW (EMIF4_0_CFG_BASE + 0x2C)
+#define EMIF0_0_SDRAM_MGMT_CTRL (EMIF4_0_CFG_BASE + 0x38)
+#define EMIF0_0_SDRAM_MGMT_CTRL_SHD (EMIF4_0_CFG_BASE + 0x3C)
+#define EMIF4_0_DDR_PHY_CTRL_1 (EMIF4_0_CFG_BASE + 0xE4)
+#define EMIF4_0_DDR_PHY_CTRL_1_SHADOW (EMIF4_0_CFG_BASE + 0xE8)
+#define EMIF4_0_DDR_PHY_CTRL_2 (EMIF4_0_CFG_BASE + 0xEC)
+#define EMIF4_0_IODFT_TLGC (EMIF4_0_CFG_BASE + 0x60)
+
+#define EMIF4_1_SDRAM_CONFIG (EMIF4_1_CFG_BASE + 0x08)
+#define EMIF4_1_SDRAM_CONFIG2 (EMIF4_1_CFG_BASE + 0x0C)
+#define EMIF4_1_SDRAM_REF_CTRL (EMIF4_1_CFG_BASE + 0x10)
+#define EMIF4_1_SDRAM_REF_CTRL_SHADOW (EMIF4_1_CFG_BASE + 0x14)
+#define EMIF4_1_SDRAM_TIM_1 (EMIF4_1_CFG_BASE + 0x18)
+#define EMIF4_1_SDRAM_TIM_1_SHADOW (EMIF4_1_CFG_BASE + 0x1C)
+#define EMIF4_1_SDRAM_TIM_2 (EMIF4_1_CFG_BASE + 0x20)
+#define EMIF4_1_SDRAM_TIM_2_SHADOW (EMIF4_1_CFG_BASE + 0x24)
+#define EMIF4_1_SDRAM_TIM_3 (EMIF4_1_CFG_BASE + 0x28)
+#define EMIF4_1_SDRAM_TIM_3_SHADOW (EMIF4_1_CFG_BASE + 0x2C)
+#define EMIF4_1_DDR_PHY_CTRL_1 (EMIF4_1_CFG_BASE + 0xE4)
+#define EMIF4_1_DDR_PHY_CTRL_1_SHADOW (EMIF4_1_CFG_BASE + 0xE8)
+#define EMIF4_1_IODFT_TLGC (EMIF4_1_CFG_BASE + 0x60)
+
+#define VTP0_CTRL_REG 0x44E10E0C
+#define VTP1_CTRL_REG 0x48140E10
+
+/* OCMC */
+#define SRAM0_SIZE (0x1B400) /* 109 KB */
+#define SRAM_GPMC_STACK_SIZE (0x40)
+
+#define LOW_LEVEL_SRAM_STACK (SRAM0_START + SRAM0_SIZE - 4)
+
+/* DDR offsets */
+#define DDR_PHY_BASE_ADDR 0x44E12000
+#define DDR_IO_CTRL 0x44E10E04
+#define DDR_CKE_CTRL 0x44E1131C
+#define CONTROL_BASE_ADDR 0x44E10000
+
+#define DDR_CMD0_IOCTRL (CONTROL_BASE_ADDR + 0x1404)
+#define DDR_CMD1_IOCTRL (CONTROL_BASE_ADDR + 0x1408)
+#define DDR_CMD2_IOCTRL (CONTROL_BASE_ADDR + 0x140C)
+#define DDR_DATA0_IOCTRL (CONTROL_BASE_ADDR + 0x1440)
+#define DDR_DATA1_IOCTRL (CONTROL_BASE_ADDR + 0x1444)
+
+#define CMD0_CTRL_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x01C)
+#define CMD0_CTRL_SLAVE_FORCE_0 (DDR_PHY_BASE_ADDR + 0x020)
+#define CMD0_CTRL_SLAVE_DELAY_0 (DDR_PHY_BASE_ADDR + 0x024)
+#define CMD0_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x028)
+#define CMD0_INVERT_CLKOUT_0 (DDR_PHY_BASE_ADDR + 0x02C)
+
+#define CMD1_CTRL_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x050)
+#define CMD1_CTRL_SLAVE_FORCE_0 (DDR_PHY_BASE_ADDR + 0x054)
+#define CMD1_CTRL_SLAVE_DELAY_0 (DDR_PHY_BASE_ADDR + 0x058)
+#define CMD1_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x05C)
+#define CMD1_INVERT_CLKOUT_0 (DDR_PHY_BASE_ADDR + 0x060)
+
+#define CMD2_CTRL_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x084)
+#define CMD2_CTRL_SLAVE_FORCE_0 (DDR_PHY_BASE_ADDR + 0x088)
+#define CMD2_CTRL_SLAVE_DELAY_0 (DDR_PHY_BASE_ADDR + 0x08C)
+#define CMD2_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x090)
+#define CMD2_INVERT_CLKOUT_0 (DDR_PHY_BASE_ADDR + 0x094)
+
+#define DATA0_RD_DQS_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0C8)
+#define DATA0_RD_DQS_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x0CC)
+#define DATA0_WR_DQS_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0DC)
+
+#define DATA0_WR_DQS_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x0E0)
+#define DATA0_WRLVL_INIT_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0F0)
+
+#define DATA0_WRLVL_INIT_RATIO_1 (DDR_PHY_BASE_ADDR + 0x0F4)
+#define DATA0_GATELVL_INIT_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0FC)
+
+#define DATA0_GATELVL_INIT_RATIO_1 (DDR_PHY_BASE_ADDR + 0x100)
+#define DATA0_FIFO_WE_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x108)
+
+#define DATA0_FIFO_WE_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x10C)
+#define DATA0_WR_DATA_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x120)
+
+#define DATA0_WR_DATA_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x124)
+#define DATA0_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x138)
+
+#define DATA0_RANK0_DELAYS_0 (DDR_PHY_BASE_ADDR + 0x134)
+#define DATA1_RANK0_DELAYS_0 (DDR_PHY_BASE_ADDR + 0x1D8)
+
+/* Ethernet MAC ID from EFuse */
+#define MAC_ID0_LO (AM33XX_CTRL_BASE + 0x630)
+#define MAC_ID0_HI (AM33XX_CTRL_BASE + 0x634)
+#define MAC_ID1_LO (AM33XX_CTRL_BASE + 0x638)
+#define MAC_ID1_HI (AM33XX_CTRL_BASE + 0x63c)
+#define MAC_MII_SEL (AM33XX_CTRL_BASE + 0x650)
+
+/* WDT related */
+#define WDT_WDSC (WDT_BASE + 0x010)
+#define WDT_WDST (WDT_BASE + 0x014)
+#define WDT_WISR (WDT_BASE + 0x018)
+#define WDT_WIER (WDT_BASE + 0x01C)
+#define WDT_WWER (WDT_BASE + 0x020)
+#define WDT_WCLR (WDT_BASE + 0x024)
+#define WDT_WCRR (WDT_BASE + 0x028)
+#define WDT_WLDR (WDT_BASE + 0x02C)
+#define WDT_WTGR (WDT_BASE + 0x030)
+#define WDT_WWPS (WDT_BASE + 0x034)
+#define WDT_WDLY (WDT_BASE + 0x044)
+#define WDT_WSPR (WDT_BASE + 0x048)
+#define WDT_WIRQEOI (WDT_BASE + 0x050)
+#define WDT_WIRQSTATRAW (WDT_BASE + 0x054)
+#define WDT_WIRQSTAT (WDT_BASE + 0x058)
+#define WDT_WIRQENSET (WDT_BASE + 0x05C)
+#define WDT_WIRQENCLR (WDT_BASE + 0x060)
#endif
diff --git a/arch/arm/mach-omap/include/mach/xload.h b/arch/arm/mach-omap/include/mach/xload.h
index 44d3754..d632735 100644
--- a/arch/arm/mach-omap/include/mach/xload.h
+++ b/arch/arm/mach-omap/include/mach/xload.h
@@ -9,6 +9,7 @@ enum omap_boot_src {
OMAP_BOOTSRC_USB1,
};
+enum omap_boot_src am33xx_bootsrc(void);
enum omap_boot_src omap3_bootsrc(void);
enum omap_boot_src omap4_bootsrc(void);
diff --git a/arch/arm/mach-omap/xload.c b/arch/arm/mach-omap/xload.c
index 240d3ff..47c5d98 100644
--- a/arch/arm/mach-omap/xload.c
+++ b/arch/arm/mach-omap/xload.c
@@ -163,6 +163,8 @@ enum omap_boot_src omap_bootsrc(void)
return omap3_bootsrc();
#elif defined(CONFIG_ARCH_OMAP4)
return omap4_bootsrc();
+#elif defined(CONFIG_ARCH_AM33XX)
+ return am33xx_bootsrc();
#endif
}
--
1.7.10.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 13/14] arm: beaglebone: add first-stage support for AM335x and board
2012-12-13 16:30 ` [PATCH 13/14] arm: beaglebone: add first-stage support for AM335x and board Jan Luebbe
@ 2012-12-18 12:52 ` Teresa Gámez
0 siblings, 0 replies; 16+ messages in thread
From: Teresa Gámez @ 2012-12-18 12:52 UTC (permalink / raw)
To: Jan Luebbe; +Cc: barebox
Hello Jan,
thank you on continue to work on am33xx.
Sadly I do not have a beaglebone and my board has ddr3 ram
so I wasn't able to test the first stage support.
I have a small note below.
On Thu, 13. Dec 17:30, Jan Luebbe wrote:
> Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
> ---
> arch/arm/Makefile | 1 +
> arch/arm/boards/beaglebone/Makefile | 1 +
> arch/arm/boards/beaglebone/board.c | 364 ++++++++++++++
> arch/arm/boards/beaglebone/config.h | 17 +
> arch/arm/boards/beaglebone/env/boot/sd | 11 +
> arch/arm/boards/beaglebone/env/config | 21 +
> arch/arm/configs/am335x_beaglebone_defconfig | 54 +++
> .../configs/am335x_beaglebone_mlo_large_defconfig | 55 +++
> .../configs/am335x_beaglebone_mlo_small_defconfig | 31 ++
> arch/arm/mach-omap/Kconfig | 11 +-
> arch/arm/mach-omap/Makefile | 2 +-
> arch/arm/mach-omap/am33xx_clock.c | 289 +++++++++++
> arch/arm/mach-omap/am33xx_generic.c | 68 +++
> arch/arm/mach-omap/am33xx_mux.c | 506 ++++++++++++++++++++
> arch/arm/mach-omap/gpmc.c | 3 +
> arch/arm/mach-omap/include/mach/am33xx-clock.h | 171 +++++++
> arch/arm/mach-omap/include/mach/am33xx-mux.h | 22 +
> arch/arm/mach-omap/include/mach/am33xx-silicon.h | 145 +++++-
> arch/arm/mach-omap/include/mach/xload.h | 1 +
> arch/arm/mach-omap/xload.c | 2 +
> 20 files changed, 1772 insertions(+), 3 deletions(-)
> create mode 100644 arch/arm/boards/beaglebone/Makefile
> create mode 100644 arch/arm/boards/beaglebone/board.c
> create mode 100644 arch/arm/boards/beaglebone/config.h
> create mode 100644 arch/arm/boards/beaglebone/env/boot/sd
> create mode 100644 arch/arm/boards/beaglebone/env/config
> create mode 100644 arch/arm/configs/am335x_beaglebone_defconfig
> create mode 100644 arch/arm/configs/am335x_beaglebone_mlo_large_defconfig
> create mode 100644 arch/arm/configs/am335x_beaglebone_mlo_small_defconfig
> create mode 100644 arch/arm/mach-omap/am33xx_clock.c
> create mode 100644 arch/arm/mach-omap/am33xx_mux.c
> create mode 100644 arch/arm/mach-omap/include/mach/am33xx-mux.h
>
[...]
> diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
> index 1858756..ea44d25 100644
> --- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h
> +++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
> @@ -43,7 +43,150 @@
> #define AM33XX_DMTIMER0_BASE (AM33XX_L4_WKUP_BASE + 0x205000)
>
> /* PRM */
> -#define OMAP_PRM_BASE (AM33XX_L4_WKUP_BASE + 0x200000)
> +#define AM33XX_PRM_BASE (AM33XX_L4_WKUP_BASE + 0x200000)
>
> +#define AM33XX_PRM_RSTCTRL (AM33XX_PRM_BASE + 0x0f00)
> +#define AM33XX_PRM_RSTCTRL_RESET 0x1
> +
> +/* CTRL */
> +#define AM33XX_CTRL_BASE (AM33XX_L4_WKUP_BASE + 0x210000)
> +
> +/* Watchdog Timer */
> +#define WDT_BASE 0x44E35000
> +
> +/* EMIF Base address */
> +#define EMIF4_0_CFG_BASE 0x4C000000
> +#define EMIF4_1_CFG_BASE 0x4D000000
> +#define DMM_BASE 0x4E000000
> +
> +#define AM335X_CPSW_BASE 0x4A100000
> +#define AM335X_CPSW_MDIO_BASE 0x4A101000
> +
> +/*DMM & EMIF4 MMR Declaration*/
> +#define DMM_LISA_MAP__0 (DMM_BASE + 0x40)
> +#define DMM_LISA_MAP__1 (DMM_BASE + 0x44)
> +#define DMM_LISA_MAP__2 (DMM_BASE + 0x48)
> +#define DMM_LISA_MAP__3 (DMM_BASE + 0x4C)
> +#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x460)
> +
> +#define EMIF_MOD_ID_REV (EMIF4_0_CFG_BASE + 0x0)
> +#define EMIF4_0_SDRAM_STATUS (EMIF4_0_CFG_BASE + 0x04)
> +#define EMIF4_0_SDRAM_CONFIG (EMIF4_0_CFG_BASE + 0x08)
> +#define EMIF4_0_SDRAM_CONFIG2 (EMIF4_0_CFG_BASE + 0x0C)
> +#define EMIF4_0_SDRAM_REF_CTRL (EMIF4_0_CFG_BASE + 0x10)
> +#define EMIF4_0_SDRAM_REF_CTRL_SHADOW (EMIF4_0_CFG_BASE + 0x14)
> +#define EMIF4_0_SDRAM_TIM_1 (EMIF4_0_CFG_BASE + 0x18)
> +#define EMIF4_0_SDRAM_TIM_1_SHADOW (EMIF4_0_CFG_BASE + 0x1C)
> +#define EMIF4_0_SDRAM_TIM_2 (EMIF4_0_CFG_BASE + 0x20)
> +#define EMIF4_0_SDRAM_TIM_2_SHADOW (EMIF4_0_CFG_BASE + 0x24)
> +#define EMIF4_0_SDRAM_TIM_3 (EMIF4_0_CFG_BASE + 0x28)
> +#define EMIF4_0_SDRAM_TIM_3_SHADOW (EMIF4_0_CFG_BASE + 0x2C)
> +#define EMIF0_0_SDRAM_MGMT_CTRL (EMIF4_0_CFG_BASE + 0x38)
> +#define EMIF0_0_SDRAM_MGMT_CTRL_SHD (EMIF4_0_CFG_BASE + 0x3C)
> +#define EMIF4_0_DDR_PHY_CTRL_1 (EMIF4_0_CFG_BASE + 0xE4)
> +#define EMIF4_0_DDR_PHY_CTRL_1_SHADOW (EMIF4_0_CFG_BASE + 0xE8)
> +#define EMIF4_0_DDR_PHY_CTRL_2 (EMIF4_0_CFG_BASE + 0xEC)
> +#define EMIF4_0_IODFT_TLGC (EMIF4_0_CFG_BASE + 0x60)
> +
> +#define EMIF4_1_SDRAM_CONFIG (EMIF4_1_CFG_BASE + 0x08)
> +#define EMIF4_1_SDRAM_CONFIG2 (EMIF4_1_CFG_BASE + 0x0C)
> +#define EMIF4_1_SDRAM_REF_CTRL (EMIF4_1_CFG_BASE + 0x10)
> +#define EMIF4_1_SDRAM_REF_CTRL_SHADOW (EMIF4_1_CFG_BASE + 0x14)
> +#define EMIF4_1_SDRAM_TIM_1 (EMIF4_1_CFG_BASE + 0x18)
> +#define EMIF4_1_SDRAM_TIM_1_SHADOW (EMIF4_1_CFG_BASE + 0x1C)
> +#define EMIF4_1_SDRAM_TIM_2 (EMIF4_1_CFG_BASE + 0x20)
> +#define EMIF4_1_SDRAM_TIM_2_SHADOW (EMIF4_1_CFG_BASE + 0x24)
> +#define EMIF4_1_SDRAM_TIM_3 (EMIF4_1_CFG_BASE + 0x28)
> +#define EMIF4_1_SDRAM_TIM_3_SHADOW (EMIF4_1_CFG_BASE + 0x2C)
> +#define EMIF4_1_DDR_PHY_CTRL_1 (EMIF4_1_CFG_BASE + 0xE4)
> +#define EMIF4_1_DDR_PHY_CTRL_1_SHADOW (EMIF4_1_CFG_BASE + 0xE8)
> +#define EMIF4_1_IODFT_TLGC (EMIF4_1_CFG_BASE + 0x60)
> +
> +#define VTP0_CTRL_REG 0x44E10E0C
> +#define VTP1_CTRL_REG 0x48140E10
> +
> +/* OCMC */
> +#define SRAM0_SIZE (0x1B400) /* 109 KB */
> +#define SRAM_GPMC_STACK_SIZE (0x40)
> +
> +#define LOW_LEVEL_SRAM_STACK (SRAM0_START + SRAM0_SIZE - 4)
SRAM0_START is not defined anywhere.
Regards,
Teresa
> +
> +/* DDR offsets */
> +#define DDR_PHY_BASE_ADDR 0x44E12000
> +#define DDR_IO_CTRL 0x44E10E04
> +#define DDR_CKE_CTRL 0x44E1131C
> +#define CONTROL_BASE_ADDR 0x44E10000
> +
> +#define DDR_CMD0_IOCTRL (CONTROL_BASE_ADDR + 0x1404)
> +#define DDR_CMD1_IOCTRL (CONTROL_BASE_ADDR + 0x1408)
> +#define DDR_CMD2_IOCTRL (CONTROL_BASE_ADDR + 0x140C)
> +#define DDR_DATA0_IOCTRL (CONTROL_BASE_ADDR + 0x1440)
> +#define DDR_DATA1_IOCTRL (CONTROL_BASE_ADDR + 0x1444)
> +
> +#define CMD0_CTRL_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x01C)
> +#define CMD0_CTRL_SLAVE_FORCE_0 (DDR_PHY_BASE_ADDR + 0x020)
> +#define CMD0_CTRL_SLAVE_DELAY_0 (DDR_PHY_BASE_ADDR + 0x024)
> +#define CMD0_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x028)
> +#define CMD0_INVERT_CLKOUT_0 (DDR_PHY_BASE_ADDR + 0x02C)
> +
> +#define CMD1_CTRL_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x050)
> +#define CMD1_CTRL_SLAVE_FORCE_0 (DDR_PHY_BASE_ADDR + 0x054)
> +#define CMD1_CTRL_SLAVE_DELAY_0 (DDR_PHY_BASE_ADDR + 0x058)
> +#define CMD1_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x05C)
> +#define CMD1_INVERT_CLKOUT_0 (DDR_PHY_BASE_ADDR + 0x060)
> +
> +#define CMD2_CTRL_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x084)
> +#define CMD2_CTRL_SLAVE_FORCE_0 (DDR_PHY_BASE_ADDR + 0x088)
> +#define CMD2_CTRL_SLAVE_DELAY_0 (DDR_PHY_BASE_ADDR + 0x08C)
> +#define CMD2_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x090)
> +#define CMD2_INVERT_CLKOUT_0 (DDR_PHY_BASE_ADDR + 0x094)
> +
> +#define DATA0_RD_DQS_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0C8)
> +#define DATA0_RD_DQS_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x0CC)
> +#define DATA0_WR_DQS_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0DC)
> +
> +#define DATA0_WR_DQS_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x0E0)
> +#define DATA0_WRLVL_INIT_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0F0)
> +
> +#define DATA0_WRLVL_INIT_RATIO_1 (DDR_PHY_BASE_ADDR + 0x0F4)
> +#define DATA0_GATELVL_INIT_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0FC)
> +
> +#define DATA0_GATELVL_INIT_RATIO_1 (DDR_PHY_BASE_ADDR + 0x100)
> +#define DATA0_FIFO_WE_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x108)
> +
> +#define DATA0_FIFO_WE_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x10C)
> +#define DATA0_WR_DATA_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x120)
> +
> +#define DATA0_WR_DATA_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x124)
> +#define DATA0_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x138)
> +
> +#define DATA0_RANK0_DELAYS_0 (DDR_PHY_BASE_ADDR + 0x134)
> +#define DATA1_RANK0_DELAYS_0 (DDR_PHY_BASE_ADDR + 0x1D8)
> +
> +/* Ethernet MAC ID from EFuse */
> +#define MAC_ID0_LO (AM33XX_CTRL_BASE + 0x630)
> +#define MAC_ID0_HI (AM33XX_CTRL_BASE + 0x634)
> +#define MAC_ID1_LO (AM33XX_CTRL_BASE + 0x638)
> +#define MAC_ID1_HI (AM33XX_CTRL_BASE + 0x63c)
> +#define MAC_MII_SEL (AM33XX_CTRL_BASE + 0x650)
> +
> +/* WDT related */
> +#define WDT_WDSC (WDT_BASE + 0x010)
> +#define WDT_WDST (WDT_BASE + 0x014)
> +#define WDT_WISR (WDT_BASE + 0x018)
> +#define WDT_WIER (WDT_BASE + 0x01C)
> +#define WDT_WWER (WDT_BASE + 0x020)
> +#define WDT_WCLR (WDT_BASE + 0x024)
> +#define WDT_WCRR (WDT_BASE + 0x028)
> +#define WDT_WLDR (WDT_BASE + 0x02C)
> +#define WDT_WTGR (WDT_BASE + 0x030)
> +#define WDT_WWPS (WDT_BASE + 0x034)
> +#define WDT_WDLY (WDT_BASE + 0x044)
> +#define WDT_WSPR (WDT_BASE + 0x048)
> +#define WDT_WIRQEOI (WDT_BASE + 0x050)
> +#define WDT_WIRQSTATRAW (WDT_BASE + 0x054)
> +#define WDT_WIRQSTAT (WDT_BASE + 0x058)
> +#define WDT_WIRQENSET (WDT_BASE + 0x05C)
> +#define WDT_WIRQENCLR (WDT_BASE + 0x060)
>
> #endif
> diff --git a/arch/arm/mach-omap/include/mach/xload.h b/arch/arm/mach-omap/include/mach/xload.h
> index 44d3754..d632735 100644
> --- a/arch/arm/mach-omap/include/mach/xload.h
> +++ b/arch/arm/mach-omap/include/mach/xload.h
> @@ -9,6 +9,7 @@ enum omap_boot_src {
> OMAP_BOOTSRC_USB1,
> };
>
> +enum omap_boot_src am33xx_bootsrc(void);
> enum omap_boot_src omap3_bootsrc(void);
> enum omap_boot_src omap4_bootsrc(void);
>
> diff --git a/arch/arm/mach-omap/xload.c b/arch/arm/mach-omap/xload.c
> index 240d3ff..47c5d98 100644
> --- a/arch/arm/mach-omap/xload.c
> +++ b/arch/arm/mach-omap/xload.c
> @@ -163,6 +163,8 @@ enum omap_boot_src omap_bootsrc(void)
> return omap3_bootsrc();
> #elif defined(CONFIG_ARCH_OMAP4)
> return omap4_bootsrc();
> +#elif defined(CONFIG_ARCH_AM33XX)
> + return am33xx_bootsrc();
> #endif
> }
>
> --
> 1.7.10.4
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 14/14] drivers: net: add driver for TI CPSW
2012-12-13 16:30 AM33xx support Jan Luebbe
` (12 preceding siblings ...)
2012-12-13 16:30 ` [PATCH 13/14] arm: beaglebone: add first-stage support for AM335x and board Jan Luebbe
@ 2012-12-13 16:30 ` Jan Luebbe
13 siblings, 0 replies; 16+ messages in thread
From: Jan Luebbe @ 2012-12-13 16:30 UTC (permalink / raw)
To: barebox
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
---
arch/arm/boards/beaglebone/board.c | 82 +++
arch/arm/mach-omap/include/mach/cpsw.h | 49 ++
drivers/net/Kconfig | 4 +
drivers/net/Makefile | 1 +
drivers/net/cpsw.c | 1021 ++++++++++++++++++++++++++++++++
5 files changed, 1157 insertions(+)
create mode 100644 arch/arm/mach-omap/include/mach/cpsw.h
create mode 100644 drivers/net/cpsw.c
diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c
index fd30dd9..f374598 100644
--- a/arch/arm/boards/beaglebone/board.c
+++ b/arch/arm/boards/beaglebone/board.c
@@ -31,6 +31,7 @@
#include <sizes.h>
#include <io.h>
#include <ns16550.h>
+#include <net.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <mach/am33xx-silicon.h>
@@ -42,9 +43,12 @@
#include <mach/ehci.h>
#include <i2c/i2c.h>
#include <linux/err.h>
+#include <linux/phy.h>
#include <usb/ehci.h>
#include <mach/xload.h>
+#include <mach/am33xx-silicon.h>
#include <mach/am33xx-mux.h>
+#include <mach/cpsw.h>
/* UART Defines */
#define UART_SYSCFG_OFFSET (0x54)
@@ -310,6 +314,84 @@ static int beaglebone_console_init(void)
console_initcall(beaglebone_console_init);
#endif /* CONFIG_DRIVER_SERIAL_NS16550 */
+#ifdef CONFIG_DRIVER_NET_CPSW
+static void cpsw_control(int enabled)
+{
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_id = 0,
+ .phy_if = PHY_INTERFACE_MODE_MII,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_id = 1,
+ .phy_if = PHY_INTERFACE_MODE_MII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = AM335X_CPSW_MDIO_BASE,
+ .cpsw_base = AM335X_CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 2,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .mac_control = (1 << 5) /* MIIEN */,
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+static int beaglebone_eth_init(void)
+{
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ mac_lo = readl(MAC_ID0_LO);
+ mac_hi = readl(MAC_ID0_HI);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+ if (is_valid_ether_addr(mac_addr))
+ eth_register_ethaddr(0, mac_addr);
+
+ mac_lo = readl(MAC_ID1_LO);
+ mac_hi = readl(MAC_ID1_HI);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+ if (is_valid_ether_addr(mac_addr))
+ eth_register_ethaddr(1, mac_addr);
+
+ writel(0, MAC_MII_SEL);
+
+ enable_mii1_pin_mux();
+
+ add_generic_device("cpsw", 0, NULL, AM335X_CPSW_BASE, SZ_4K,
+ IORESOURCE_MEM, &cpsw_data);
+
+ return 0;
+}
+device_initcall(beaglebone_eth_init);
+#endif
+
static int beaglebone_mem_init(void)
{
arm_add_mem_device("ram0", 0x80000000, 256 * 1024 * 1024);
diff --git a/arch/arm/mach-omap/include/mach/cpsw.h b/arch/arm/mach-omap/include/mach/cpsw.h
new file mode 100644
index 0000000..c101c93
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/cpsw.h
@@ -0,0 +1,49 @@
+/*
+ * CPSW Ethernet Switch Driver
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPSW_H_
+#define _CPSW_H_
+
+struct cpsw_slave_data {
+ u32 slave_reg_ofs;
+ u32 sliver_reg_ofs;
+ int phy_id;
+ int phy_if;
+};
+
+enum {
+ CPSW_CTRL_VERSION_1 = 0,
+ CPSW_CTRL_VERSION_2 /* am33xx like devices */
+};
+
+struct cpsw_platform_data {
+ u32 mdio_base;
+ u32 cpsw_base;
+ int mdio_div;
+ int channels; /* number of cpdma channels (symmetric) */
+ u32 cpdma_reg_ofs; /* cpdma register offset */
+ int slaves; /* number of slave cpgmac ports */
+ u32 ale_reg_ofs; /* address lookup engine reg offset */
+ int ale_entries; /* ale table size */
+ u32 host_port_reg_ofs; /* cpdma host port registers */
+ u32 hw_stats_reg_ofs; /* cpsw hw stats counters */
+ u32 mac_control;
+ struct cpsw_slave_data *slave_data;
+ void (*control)(int enabled);
+ u32 host_port_num;
+ u8 version;
+};
+
+#endif /* _CPSW_H_ */
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 43d5984..cf6ceee 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -31,6 +31,10 @@ config DRIVER_NET_CS8900
bool "cs8900 ethernet driver"
depends on HAS_CS8900
+config DRIVER_NET_CPSW
+ bool "CPSW ethernet driver"
+ select PHYLIB
+
config DRIVER_NET_SMC911X
bool "smc911x ethernet driver"
select PHYLIB
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 4e6b49b..6e1aeaa 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_DRIVER_NET_CS8900) += cs8900.o
+obj-$(CONFIG_DRIVER_NET_CPSW) += cpsw.o
obj-$(CONFIG_DRIVER_NET_SMC911X) += smc911x.o
obj-$(CONFIG_DRIVER_NET_SMC91111) += smc91111.o
obj-$(CONFIG_DRIVER_NET_DAVINCI_EMAC) += davinci_emac.o
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
new file mode 100644
index 0000000..69639ff
--- /dev/null
+++ b/drivers/net/cpsw.c
@@ -0,0 +1,1021 @@
+/*
+ * CPSW Ethernet Switch Driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <init.h>
+
+#include <command.h>
+#include <net.h>
+#include <malloc.h>
+#include <net.h>
+#include <linux/phy.h>
+#include <errno.h>
+#include <io.h>
+#include <xfuncs.h>
+#include <asm/mmu.h>
+#include <asm/system.h>
+
+#include <mach/cpsw.h>
+
+#define BITMASK(bits) ((1 << (bits)) - 1)
+#define PHY_REG_MASK 0x1f
+#define PHY_ID_MASK 0x1f
+#define NUM_DESCS (PKTBUFSRX * 2)
+#define PKT_MIN 60
+#define PKT_MAX (1500 + 14 + 4 + 4)
+
+/* DMA Registers */
+#define CPDMA_TXCONTROL 0x004
+#define CPDMA_RXCONTROL 0x014
+#define CPDMA_SOFTRESET 0x01c
+#define CPDMA_RXFREE 0x0e0
+#define CPDMA_TXHDP_VER1 0x100
+#define CPDMA_TXHDP_VER2 0x200
+#define CPDMA_RXHDP_VER1 0x120
+#define CPDMA_RXHDP_VER2 0x220
+#define CPDMA_TXCP_VER1 0x140
+#define CPDMA_TXCP_VER2 0x240
+#define CPDMA_RXCP_VER1 0x160
+#define CPDMA_RXCP_VER2 0x260
+
+#define CPDMA_RAM_ADDR 0x4a102000
+
+/* Descriptor mode bits */
+#define CPDMA_DESC_SOP BIT(31)
+#define CPDMA_DESC_EOP BIT(30)
+#define CPDMA_DESC_OWNER BIT(29)
+#define CPDMA_DESC_EOQ BIT(28)
+
+struct cpsw_mdio_regs {
+ u32 version;
+ u32 control;
+#define CONTROL_IDLE (1 << 31)
+#define CONTROL_ENABLE (1 << 30)
+
+ u32 alive;
+ u32 link;
+ u32 linkintraw;
+ u32 linkintmasked;
+ u32 __reserved_0[2];
+ u32 userintraw;
+ u32 userintmasked;
+ u32 userintmaskset;
+ u32 userintmaskclr;
+ u32 __reserved_1[20];
+
+ struct {
+ u32 access;
+ u32 physel;
+#define USERACCESS_GO (1 << 31)
+#define USERACCESS_WRITE (1 << 30)
+#define USERACCESS_ACK (1 << 29)
+#define USERACCESS_READ (0)
+#define USERACCESS_DATA (0xffff)
+ } user[0];
+};
+
+struct cpsw_regs {
+ u32 id_ver;
+ u32 control;
+ u32 soft_reset;
+ u32 stat_port_en;
+ u32 ptype;
+};
+
+struct cpsw_slave_regs {
+ u32 max_blks;
+ u32 blk_cnt;
+ u32 flow_thresh;
+ u32 port_vlan;
+ u32 tx_pri_map;
+#ifdef CONFIG_TI814X
+ u32 ts_ctl;
+ u32 ts_seq_ltype;
+ u32 ts_vlan;
+#endif
+ u32 sa_lo;
+ u32 sa_hi;
+};
+
+struct cpsw_host_regs {
+ u32 max_blks;
+ u32 blk_cnt;
+ u32 flow_thresh;
+ u32 port_vlan;
+ u32 tx_pri_map;
+ u32 cpdma_tx_pri_map;
+ u32 cpdma_rx_chan_map;
+};
+
+struct cpsw_sliver_regs {
+ u32 id_ver;
+ u32 mac_control;
+ u32 mac_status;
+ u32 soft_reset;
+ u32 rx_maxlen;
+ u32 __reserved_0;
+ u32 rx_pause;
+ u32 tx_pause;
+ u32 __reserved_1;
+ u32 rx_pri_map;
+};
+
+#define ALE_ENTRY_BITS 68
+#define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
+
+/* ALE Registers */
+#define ALE_CONTROL 0x08
+#define ALE_UNKNOWNVLAN 0x18
+#define ALE_TABLE_CONTROL 0x20
+#define ALE_TABLE 0x34
+#define ALE_PORTCTL 0x40
+
+#define ALE_TABLE_WRITE BIT(31)
+
+#define ALE_TYPE_FREE 0
+#define ALE_TYPE_ADDR 1
+#define ALE_TYPE_VLAN 2
+#define ALE_TYPE_VLAN_ADDR 3
+
+#define ALE_UCAST_PERSISTANT 0
+#define ALE_UCAST_UNTOUCHED 1
+#define ALE_UCAST_OUI 2
+#define ALE_UCAST_TOUCHED 3
+
+#define ALE_MCAST_FWD 0
+#define ALE_MCAST_BLOCK_LEARN_FWD 1
+#define ALE_MCAST_FWD_LEARN 2
+#define ALE_MCAST_FWD_2 3
+
+enum cpsw_ale_port_state {
+ ALE_PORT_STATE_DISABLE = 0x00,
+ ALE_PORT_STATE_BLOCK = 0x01,
+ ALE_PORT_STATE_LEARN = 0x02,
+ ALE_PORT_STATE_FORWARD = 0x03,
+};
+
+/* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
+#define ALE_SECURE 1
+#define ALE_BLOCKED 2
+
+struct cpsw_slave {
+ struct cpsw_slave_regs *regs;
+ struct cpsw_sliver_regs *sliver;
+ int slave_num;
+ u32 mac_control;
+ struct cpsw_slave_data *data;
+};
+
+struct cpdma_desc {
+ /* hardware fields */
+ u32 hw_next;
+ u32 hw_buffer;
+ u32 hw_len;
+ u32 hw_mode;
+ /* software fields */
+ u32 sw_buffer;
+ u32 sw_len;
+};
+
+struct cpdma_chan {
+ struct cpdma_desc *head, *tail;
+ void *hdp, *cp, *rxfree;
+};
+
+#define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
+#define desc_read(desc, fld) __raw_readl(&(desc)->fld)
+#define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld))
+
+#define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
+#define chan_read(chan, fld) __raw_readl((chan)->fld)
+#define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
+
+struct cpsw_priv {
+ struct device_d *dev;
+ struct eth_device edev;
+ struct mii_bus miibus;
+
+ struct cpsw_platform_data data;
+ int host_port;
+ uint8_t mac_addr[6];
+
+ struct cpsw_regs *regs;
+ void *dma_regs;
+ struct cpsw_host_regs *host_port_regs;
+ void *ale_regs;
+
+ struct cpdma_desc *descs;
+ struct cpdma_desc *desc_free;
+ struct cpdma_chan rx_chan, tx_chan;
+
+ struct cpsw_slave *slaves;
+#define for_each_slave(priv, func, arg...) \
+ do { \
+ int idx; \
+ for (idx = 0; idx < (priv)->data.slaves; idx++) \
+ (func)((priv)->slaves + idx, ##arg); \
+ } while (0)
+};
+
+static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
+{
+ int idx;
+
+ idx = start / 32;
+ start -= idx * 32;
+ idx = 2 - idx; /* flip */
+ return (ale_entry[idx] >> start) & BITMASK(bits);
+}
+
+static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
+ u32 value)
+{
+ int idx;
+
+ value &= BITMASK(bits);
+ idx = start / 32;
+ start -= idx * 32;
+ idx = 2 - idx; /* flip */
+ ale_entry[idx] &= ~(BITMASK(bits) << start);
+ ale_entry[idx] |= (value << start);
+}
+
+#define DEFINE_ALE_FIELD(name, start, bits) \
+static inline int cpsw_ale_get_##name(u32 *ale_entry) \
+{ \
+ return cpsw_ale_get_field(ale_entry, start, bits); \
+} \
+static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
+{ \
+ cpsw_ale_set_field(ale_entry, start, bits, value); \
+}
+
+DEFINE_ALE_FIELD(entry_type, 60, 2)
+DEFINE_ALE_FIELD(mcast_state, 62, 2)
+DEFINE_ALE_FIELD(port_mask, 66, 3)
+DEFINE_ALE_FIELD(ucast_type, 62, 2)
+DEFINE_ALE_FIELD(port_num, 66, 2)
+DEFINE_ALE_FIELD(blocked, 65, 1)
+DEFINE_ALE_FIELD(secure, 64, 1)
+DEFINE_ALE_FIELD(mcast, 40, 1)
+
+char ethbdaddr [6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+
+/* The MAC address field in the ALE entry cannot be macroized as above */
+static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
+{
+ int i;
+
+ for (i = 0; i < 6; i++)
+ addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
+}
+
+static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr)
+{
+ int i;
+
+ for (i = 0; i < 6; i++)
+ cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
+}
+
+static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
+{
+ int i;
+
+ __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
+
+ for (i = 0; i < ALE_ENTRY_WORDS; i++)
+ ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
+
+ return idx;
+}
+
+static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
+{
+ int i;
+
+ for (i = 0; i < ALE_ENTRY_WORDS; i++)
+ __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
+
+ __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
+
+ return idx;
+}
+
+static int cpsw_ale_match_addr(struct cpsw_priv *priv, u8* addr)
+{
+ u32 ale_entry[ALE_ENTRY_WORDS];
+ int type, idx;
+
+ for (idx = 0; idx < priv->data.ale_entries; idx++) {
+ u8 entry_addr[6];
+
+ cpsw_ale_read(priv, idx, ale_entry);
+ type = cpsw_ale_get_entry_type(ale_entry);
+ if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
+ continue;
+ cpsw_ale_get_addr(ale_entry, entry_addr);
+ if (memcmp(entry_addr, addr, 6) == 0)
+ return idx;
+ }
+ return -ENOENT;
+}
+
+static int cpsw_ale_match_free(struct cpsw_priv *priv)
+{
+ u32 ale_entry[ALE_ENTRY_WORDS];
+ int type, idx;
+
+ for (idx = 0; idx < priv->data.ale_entries; idx++) {
+ cpsw_ale_read(priv, idx, ale_entry);
+ type = cpsw_ale_get_entry_type(ale_entry);
+ if (type == ALE_TYPE_FREE)
+ return idx;
+ }
+ return -ENOENT;
+}
+
+static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
+{
+ u32 ale_entry[ALE_ENTRY_WORDS];
+ int type, idx;
+
+ for (idx = 0; idx < priv->data.ale_entries; idx++) {
+ cpsw_ale_read(priv, idx, ale_entry);
+ type = cpsw_ale_get_entry_type(ale_entry);
+ if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
+ continue;
+ if (cpsw_ale_get_mcast(ale_entry))
+ continue;
+ type = cpsw_ale_get_ucast_type(ale_entry);
+ if (type != ALE_UCAST_PERSISTANT &&
+ type != ALE_UCAST_OUI)
+ return idx;
+ }
+ return -ENOENT;
+}
+
+static int cpsw_ale_add_ucast(struct cpsw_priv *priv, u8 *addr,
+ int port, int flags)
+{
+ u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ int idx;
+
+ cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
+ cpsw_ale_set_addr(ale_entry, addr);
+ cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
+ cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
+ cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
+ cpsw_ale_set_port_num(ale_entry, port);
+
+ idx = cpsw_ale_match_addr(priv, addr);
+ if (idx < 0)
+ idx = cpsw_ale_match_free(priv);
+ if (idx < 0)
+ idx = cpsw_ale_find_ageable(priv);
+ if (idx < 0)
+ return -ENOMEM;
+
+ cpsw_ale_write(priv, idx, ale_entry);
+ return 0;
+}
+
+static int cpsw_ale_add_mcast(struct cpsw_priv *priv, u8 *addr, int port_mask)
+{
+ u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ int idx, mask;
+
+ idx = cpsw_ale_match_addr(priv, addr);
+ if (idx >= 0)
+ cpsw_ale_read(priv, idx, ale_entry);
+
+ cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
+ cpsw_ale_set_addr(ale_entry, addr);
+ cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
+
+ mask = cpsw_ale_get_port_mask(ale_entry);
+ port_mask |= mask;
+ cpsw_ale_set_port_mask(ale_entry, port_mask);
+
+ if (idx < 0)
+ idx = cpsw_ale_match_free(priv);
+ if (idx < 0)
+ idx = cpsw_ale_find_ageable(priv);
+ if (idx < 0)
+ return -ENOMEM;
+
+ cpsw_ale_write(priv, idx, ale_entry);
+ return 0;
+}
+
+static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
+{
+ u32 tmp, mask = BIT(bit);
+
+ tmp = __raw_readl(priv->ale_regs + ALE_CONTROL);
+ tmp &= ~mask;
+ tmp |= val ? mask : 0;
+ __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
+}
+
+#define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
+#define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
+#define cpsw_ale_bypass(priv, val) cpsw_ale_control(priv, 4, val)
+#define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
+
+static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
+ int val)
+{
+ int offset = ALE_PORTCTL + 4 * port;
+ u32 tmp, mask = 0x3;
+
+ tmp = __raw_readl(priv->ale_regs + offset);
+ tmp &= ~mask;
+ tmp |= val & 0x3;
+ __raw_writel(tmp, priv->ale_regs + offset);
+}
+
+static struct cpsw_mdio_regs *mdio_regs;
+
+/* wait until hardware is ready for another user access */
+static inline u32 wait_for_user_access(void)
+{
+ u32 tmp;
+
+ while ((tmp = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO)
+ ;
+
+ return tmp;
+}
+
+/* wait until hardware state machine is idle */
+static inline void wait_for_idle(void)
+{
+ while ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0)
+ ;
+}
+
+static int cpsw_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
+{
+ u32 tmp;
+
+ if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
+ return -EINVAL;
+
+ wait_for_user_access();
+ tmp = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
+ (phy_id << 16));
+ __raw_writel(tmp, &mdio_regs->user[0].access);
+ tmp = wait_for_user_access();
+
+ return (tmp & USERACCESS_ACK) ? (tmp & USERACCESS_DATA) : -1;
+}
+
+static int cpsw_mdio_write(struct mii_bus *bus, int phy_id, int phy_reg, u16 value)
+{
+ u32 tmp;
+
+ if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
+ return -EINVAL;
+
+ wait_for_user_access();
+ tmp = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
+ (phy_id << 16) | (value & USERACCESS_DATA));
+ __raw_writel(tmp, &mdio_regs->user[0].access);
+ wait_for_user_access();
+
+ return 0;
+}
+
+static inline void soft_reset(void *reg)
+{
+ __raw_writel(1, reg);
+ while (__raw_readl(reg) & 1)
+ ;
+}
+
+#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
+ ((mac)[2] << 16) | ((mac)[3] << 24))
+#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
+
+static void cpsw_set_slave_mac(struct cpsw_slave *slave,
+ struct cpsw_priv *priv,
+ unsigned char *mac)
+{
+ dev_dbg(priv->dev, "* %s\n", __func__);
+
+ __raw_writel(mac_hi(mac), &slave->regs->sa_hi);
+ __raw_writel(mac_lo(mac), &slave->regs->sa_lo);
+}
+
+static int cpsw_get_hwaddr(struct eth_device *edev, unsigned char *mac)
+{
+ struct cpsw_priv *priv = edev->priv;
+
+ dev_dbg(priv->dev, "* %s\n", __func__);
+
+ return -1;
+}
+
+static int cpsw_set_hwaddr(struct eth_device *edev, unsigned char *mac)
+{
+ struct cpsw_priv *priv = edev->priv;
+
+ dev_dbg(priv->dev, "* %s\n", __func__);
+
+ memcpy(&priv->mac_addr, mac, sizeof(priv->mac_addr));
+
+ for_each_slave(priv, cpsw_set_slave_mac, priv, mac);
+
+ return 0;
+}
+
+static void cpsw_slave_update_link(struct cpsw_slave *slave,
+ struct cpsw_priv *priv, int *link)
+{
+ struct phy_device *phydev = priv->edev.phydev;
+ u32 mac_control = 0;
+
+ dev_dbg(priv->dev, "* %s\n", __func__);
+
+ if (!phydev)
+ return;
+
+ if (slave->slave_num)
+ return;
+
+ if (phydev->link) {
+ *link = 1;
+ mac_control = priv->data.mac_control;
+ if (phydev->speed == SPEED_10)
+ mac_control |= BIT(18); /* In Band mode */
+ else if (phydev->speed == SPEED_100)
+ mac_control |= BIT(15);
+ else if (phydev->speed == SPEED_1000)
+ mac_control &= ~BIT(7); /* TODO: Do not enable
+ * gig support now */
+ if (phydev->duplex == DUPLEX_FULL)
+ mac_control |= BIT(0); /* FULLDUPLEXEN */
+ }
+
+ if (mac_control == slave->mac_control)
+ return;
+
+ if (mac_control) {
+ dev_dbg(priv->dev, "link up on port %d, speed %d, %s duplex\n",
+ slave->slave_num, phydev->speed,
+ (phydev->duplex == DUPLEX_FULL) ? "full" : "half");
+ } else {
+ dev_dbg(priv->dev, "link down on port %d\n", slave->slave_num);
+ }
+
+ __raw_writel(mac_control, &slave->sliver->mac_control);
+ slave->mac_control = mac_control;
+}
+
+static int cpsw_update_link(struct cpsw_priv *priv)
+{
+ int link = 0;
+
+ dev_dbg(priv->dev, "* %s\n", __func__);
+
+ for_each_slave(priv, cpsw_slave_update_link, priv, &link);
+ return link;
+}
+
+static void cpsw_adjust_link(struct eth_device *edev) {
+ struct cpsw_priv *priv = edev->priv;
+
+ dev_dbg(priv->dev, "* %s\n", __func__);
+
+ cpsw_update_link(priv);
+}
+
+static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
+{
+ if (priv->host_port == 0)
+ return slave_num + 1;
+ else
+ return slave_num;
+}
+
+static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
+{
+ u32 slave_port;
+
+ dev_dbg(priv->dev, "* %s\n", __func__);
+
+ soft_reset(&slave->sliver->soft_reset);
+
+ /* setup priority mapping */
+ __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
+ __raw_writel(0x33221100, &slave->regs->tx_pri_map);
+
+ /* setup max packet size, and mac address */
+ __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
+ //cpsw_set_slave_mac(slave, priv);
+
+ slave->mac_control = 0; /* no link yet */
+
+ /* enable forwarding */
+ slave_port = cpsw_get_slave_port(priv, slave->slave_num);
+ cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
+
+ /* add broadcast address */
+ cpsw_ale_add_mcast(priv, ethbdaddr, 1 << slave_port);
+}
+
+static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
+{
+ struct cpdma_desc *desc = priv->desc_free;
+
+ if (desc)
+ priv->desc_free = desc_read_ptr(desc, hw_next);
+ return desc;
+}
+
+static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
+{
+ if (desc) {
+ desc_write(desc, hw_next, priv->desc_free);
+ priv->desc_free = desc;
+ }
+}
+
+static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
+ volatile void *buffer, int len)
+{
+ struct cpdma_desc *desc, *prev;
+ u32 mode;
+
+ //dev_dbg(priv->dev, "* %s\n", __func__);
+
+ desc = cpdma_desc_alloc(priv);
+ if (!desc)
+ return -ENOMEM;
+
+ if (len < PKT_MIN)
+ len = PKT_MIN;
+
+ mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
+
+ desc_write(desc, hw_next, 0);
+ desc_write(desc, hw_buffer, buffer);
+ desc_write(desc, hw_len, len);
+ desc_write(desc, hw_mode, mode | len);
+ desc_write(desc, sw_buffer, buffer);
+ desc_write(desc, sw_len, len);
+
+ dev_dbg(priv->dev, "%s: submit addr=0x%p len=%i\n", __func__, buffer, len);
+
+ if (!chan->head) {
+ /* simple case - first packet enqueued */
+ chan->head = desc;
+ chan->tail = desc;
+ chan_write(chan, hdp, desc);
+ goto done;
+ }
+
+ /* not the first packet - enqueue at the tail */
+ prev = chan->tail;
+ desc_write(prev, hw_next, desc);
+ chan->tail = desc;
+
+ /* next check if EOQ has been triggered already */
+ if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ) {
+ chan_write(chan, hdp, desc);
+ }
+
+done:
+ if (chan->rxfree)
+ chan_write(chan, rxfree, 1);
+ return 0;
+}
+
+static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
+ void **buffer, int *len)
+{
+ struct cpdma_desc *desc = chan->head;
+ u32 status;
+
+ if (!desc)
+ return -ENOENT;
+
+ status = desc_read(desc, hw_mode);
+
+ if (len)
+ *len = status & 0x7ff;
+
+ if (buffer)
+ *buffer = desc_read_ptr(desc, sw_buffer);
+
+ if (status & CPDMA_DESC_OWNER)
+ return -EBUSY;
+
+ chan->head = desc_read_ptr(desc, hw_next);
+ chan_write(chan, cp, desc);
+
+ cpdma_desc_free(priv, desc);
+ return 0;
+}
+
+static int cpsw_init(struct eth_device *edev)
+{
+ struct cpsw_priv *priv = edev->priv;
+
+ dev_dbg(priv->dev, "* %s\n", __func__);
+
+ return 0;
+}
+
+static int cpsw_open(struct eth_device *edev)
+{
+ struct cpsw_priv *priv = edev->priv;
+ struct cpsw_slave_data *slave_data = priv->data.slave_data;
+ int i, ret;
+
+ dev_dbg(priv->dev, "* %s\n", __func__);
+
+ ret = phy_device_connect(edev, &priv->miibus, slave_data[0].phy_id,
+ cpsw_adjust_link, 0, slave_data[0].phy_if);
+ if (ret)
+ return ret;
+
+ priv->data.control(1);
+
+ /* soft reset the controller and initialize priv */
+ soft_reset(&priv->regs->soft_reset);
+
+ /* initialize and reset the address lookup engine */
+ cpsw_ale_enable(priv, 1);
+ cpsw_ale_clear(priv, 1);
+ cpsw_ale_bypass(priv, 0);
+ cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
+
+ /* setup host port priority mapping */
+ __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
+ __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
+
+ /* disable priority elevation and enable statistics on all ports */
+ __raw_writel(0, &priv->regs->ptype);
+
+ /* enable statistics collection only on the host port */
+ __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
+
+ cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
+
+ cpsw_ale_add_ucast(priv, priv->mac_addr, priv->host_port,
+ ALE_SECURE);
+ cpsw_ale_add_mcast(priv, ethbdaddr, 1 << priv->host_port);
+
+ for_each_slave(priv, cpsw_slave_init, priv);
+
+ cpsw_update_link(priv);
+
+ /* init descriptor pool */
+ for (i = 0; i < NUM_DESCS; i++) {
+ desc_write(&priv->descs[i], hw_next,
+ (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
+ }
+ priv->desc_free = &priv->descs[0];
+
+ /* initialize channels */
+ if (priv->data.version == CPSW_CTRL_VERSION_2) {
+ memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
+ priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
+ priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
+ priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
+
+ memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
+ priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
+ priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
+ } else {
+ memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
+ priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
+ priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
+ priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
+
+ memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
+ priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
+ priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
+ }
+
+ /* clear dma state */
+ soft_reset(priv->dma_regs + CPDMA_SOFTRESET);
+
+ if (priv->data.version == CPSW_CTRL_VERSION_2) {
+ for (i = 0; i < priv->data.channels; i++) {
+ __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
+ * i);
+ }
+ } else {
+ for (i = 0; i < priv->data.channels; i++) {
+ __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
+ * i);
+
+ }
+ }
+
+ __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
+ __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
+
+ /* submit rx descs */
+ for (i = 0; i < PKTBUFSRX; i++) {
+ ret = cpdma_submit(priv, &priv->rx_chan, NetRxPackets[i],
+ PKTSIZE);
+ if (ret < 0) {
+ printf("error %d submitting rx desc\n", ret);
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static void cpsw_halt(struct eth_device *dev)
+{
+ struct cpsw_priv *priv = dev->priv;
+ priv->data.control(0);
+}
+
+static int cpsw_send(struct eth_device *dev, void *packet, int length)
+{
+ // FIXME *packet was volatile before,
+ struct cpsw_priv *priv = dev->priv;
+ void *buffer;
+ int len;
+
+ dev_dbg(priv->dev, "* %s\n", __func__);
+
+ if (!cpsw_update_link(priv))
+ return -EIO;
+
+ /* first reap completed packets */
+ while (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0)
+ ;
+
+ dev_dbg(priv->dev, "%s: %i bytes @ 0x%p\n", __func__, length, packet);
+ dma_flush_range((ulong) packet, (ulong)packet + length);
+ return cpdma_submit(priv, &priv->tx_chan, packet, length);
+}
+
+static int cpsw_recv(struct eth_device *dev)
+{
+ struct cpsw_priv *priv = dev->priv;
+ void *buffer;
+ int len;
+
+ //dev_dbg(priv->dev, "* %s\n", __func__);
+
+ while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) {
+ dev_dbg(priv->dev, "%s: %i bytes @ 0x%p\n", __func__, len, buffer);
+ dma_inv_range((ulong)buffer, (ulong)buffer + len);
+ net_receive(buffer, len);
+ cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE);
+ }
+
+ return 0;
+}
+
+static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
+ struct cpsw_priv *priv)
+{
+ void *regs = priv->regs;
+ struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
+
+ dev_dbg(priv->dev, "* %s\n", __func__);
+
+ slave->slave_num = slave_num;
+ slave->data = data;
+ slave->regs = regs + data->slave_reg_ofs;
+ slave->sliver = regs + data->sliver_reg_ofs;
+}
+
+int cpsw_probe(struct device_d *dev)
+{
+ struct cpsw_platform_data *data = (struct cpsw_platform_data *)dev->platform_data;
+ struct cpsw_priv *priv;
+ void *regs = (void *)data->cpsw_base;
+ struct eth_device *edev;
+ uint64_t start;
+ uint32_t phy_mask;
+
+ dev_dbg(dev, "* %s\n", __func__);
+
+ priv = xzalloc(sizeof(*priv));
+ priv->dev = dev;
+ priv->data = *data;
+ edev = &priv->edev;
+
+ priv->slaves = xzalloc(sizeof(struct cpsw_slave) * data->slaves);
+
+ priv->descs = (void *)CPDMA_RAM_ADDR;
+ priv->host_port = data->host_port_num;
+ priv->regs = regs;
+ priv->host_port_regs = regs + data->host_port_reg_ofs;
+ priv->dma_regs = regs + data->cpdma_reg_ofs;
+ priv->ale_regs = regs + data->ale_reg_ofs;
+
+ for_each_slave(priv, cpsw_slave_setup, idx, priv);
+
+ edev->priv = priv;
+ edev->init = cpsw_init;
+ edev->open = cpsw_open;
+ edev->halt = cpsw_halt;
+ edev->send = cpsw_send;
+ edev->recv = cpsw_recv;
+ edev->get_ethaddr = cpsw_get_hwaddr;
+ edev->set_ethaddr = cpsw_set_hwaddr;
+ edev->parent = dev;
+
+ mdio_regs = (struct cpsw_mdio_regs *)data->mdio_base;
+ priv->miibus.read = cpsw_mdio_read;
+ priv->miibus.write = cpsw_mdio_write;
+ priv->miibus.priv = priv;
+ priv->miibus.parent = dev;
+
+ /* set enable and clock divider */
+ __raw_writel(data->mdio_div | CONTROL_ENABLE, &mdio_regs->control);
+
+ /*
+ * wait for scan logic to settle:
+ * the scan time consists of (a) a large fixed component, and (b) a
+ * small component that varies with the mii bus frequency. These
+ * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
+ * silicon. Since the effect of (b) was found to be largely
+ * negligible, we keep things simple here.
+ */
+ udelay(1000);
+
+ start = get_time_ns();
+ while (1) {
+ phy_mask = readl(&mdio_regs->alive);
+ if (phy_mask) {
+ dev_info(dev, "detected phy mask 0x%x\n", phy_mask);
+ phy_mask = ~phy_mask;
+ break;
+ }
+ if (is_timeout(start, 256 * MSECOND)) {
+ dev_err(dev, "no live phy, scanning all\n");
+ phy_mask = 0;
+ break;
+ }
+ }
+
+ priv->miibus.phy_mask = phy_mask;
+
+ mdiobus_register(&priv->miibus);
+
+ eth_register(edev);
+
+ return 0;
+}
+
+static struct driver_d cpsw_driver = {
+ .name = "cpsw",
+ .probe = cpsw_probe,
+// .remove = cpsw_remove,
+};
+
+static int cpsw_register(void)
+{
+ platform_driver_register(&cpsw_driver);
+ return 0;
+}
+
+device_initcall(cpsw_register);
--
1.7.10.4
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