From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from metis.ext.pengutronix.de ([2001:6f8:1178:4:290:27ff:fe1d:cc33]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TjBgW-0004wZ-P8 for barebox@lists.infradead.org; Thu, 13 Dec 2012 16:31:18 +0000 From: Jan Luebbe Date: Thu, 13 Dec 2012 17:30:49 +0100 Message-Id: <1355416249-22364-15-git-send-email-jlu@pengutronix.de> In-Reply-To: <1355416249-22364-1-git-send-email-jlu@pengutronix.de> References: <1355416249-22364-1-git-send-email-jlu@pengutronix.de> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: barebox-bounces@lists.infradead.org Errors-To: barebox-bounces+u.kleine-koenig=pengutronix.de@lists.infradead.org Subject: [PATCH 14/14] drivers: net: add driver for TI CPSW To: barebox@lists.infradead.org Signed-off-by: Jan Luebbe --- arch/arm/boards/beaglebone/board.c | 82 +++ arch/arm/mach-omap/include/mach/cpsw.h | 49 ++ drivers/net/Kconfig | 4 + drivers/net/Makefile | 1 + drivers/net/cpsw.c | 1021 ++++++++++++++++++++++++++++++++ 5 files changed, 1157 insertions(+) create mode 100644 arch/arm/mach-omap/include/mach/cpsw.h create mode 100644 drivers/net/cpsw.c diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c index fd30dd9..f374598 100644 --- a/arch/arm/boards/beaglebone/board.c +++ b/arch/arm/boards/beaglebone/board.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -42,9 +43,12 @@ #include #include #include +#include #include #include +#include #include +#include /* UART Defines */ #define UART_SYSCFG_OFFSET (0x54) @@ -310,6 +314,84 @@ static int beaglebone_console_init(void) console_initcall(beaglebone_console_init); #endif /* CONFIG_DRIVER_SERIAL_NS16550 */ +#ifdef CONFIG_DRIVER_NET_CPSW +static void cpsw_control(int enabled) +{ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_MII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + .phy_if = PHY_INTERFACE_MODE_MII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = AM335X_CPSW_MDIO_BASE, + .cpsw_base = AM335X_CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 2, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .mac_control = (1 << 5) /* MIIEN */, + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +static int beaglebone_eth_init(void) +{ + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + mac_lo = readl(MAC_ID0_LO); + mac_hi = readl(MAC_ID0_HI); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + if (is_valid_ether_addr(mac_addr)) + eth_register_ethaddr(0, mac_addr); + + mac_lo = readl(MAC_ID1_LO); + mac_hi = readl(MAC_ID1_HI); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + if (is_valid_ether_addr(mac_addr)) + eth_register_ethaddr(1, mac_addr); + + writel(0, MAC_MII_SEL); + + enable_mii1_pin_mux(); + + add_generic_device("cpsw", 0, NULL, AM335X_CPSW_BASE, SZ_4K, + IORESOURCE_MEM, &cpsw_data); + + return 0; +} +device_initcall(beaglebone_eth_init); +#endif + static int beaglebone_mem_init(void) { arm_add_mem_device("ram0", 0x80000000, 256 * 1024 * 1024); diff --git a/arch/arm/mach-omap/include/mach/cpsw.h b/arch/arm/mach-omap/include/mach/cpsw.h new file mode 100644 index 0000000..c101c93 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/cpsw.h @@ -0,0 +1,49 @@ +/* + * CPSW Ethernet Switch Driver + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CPSW_H_ +#define _CPSW_H_ + +struct cpsw_slave_data { + u32 slave_reg_ofs; + u32 sliver_reg_ofs; + int phy_id; + int phy_if; +}; + +enum { + CPSW_CTRL_VERSION_1 = 0, + CPSW_CTRL_VERSION_2 /* am33xx like devices */ +}; + +struct cpsw_platform_data { + u32 mdio_base; + u32 cpsw_base; + int mdio_div; + int channels; /* number of cpdma channels (symmetric) */ + u32 cpdma_reg_ofs; /* cpdma register offset */ + int slaves; /* number of slave cpgmac ports */ + u32 ale_reg_ofs; /* address lookup engine reg offset */ + int ale_entries; /* ale table size */ + u32 host_port_reg_ofs; /* cpdma host port registers */ + u32 hw_stats_reg_ofs; /* cpsw hw stats counters */ + u32 mac_control; + struct cpsw_slave_data *slave_data; + void (*control)(int enabled); + u32 host_port_num; + u8 version; +}; + +#endif /* _CPSW_H_ */ diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 43d5984..cf6ceee 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -31,6 +31,10 @@ config DRIVER_NET_CS8900 bool "cs8900 ethernet driver" depends on HAS_CS8900 +config DRIVER_NET_CPSW + bool "CPSW ethernet driver" + select PHYLIB + config DRIVER_NET_SMC911X bool "smc911x ethernet driver" select PHYLIB diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 4e6b49b..6e1aeaa 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_DRIVER_NET_CS8900) += cs8900.o +obj-$(CONFIG_DRIVER_NET_CPSW) += cpsw.o obj-$(CONFIG_DRIVER_NET_SMC911X) += smc911x.o obj-$(CONFIG_DRIVER_NET_SMC91111) += smc91111.o obj-$(CONFIG_DRIVER_NET_DAVINCI_EMAC) += davinci_emac.o diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c new file mode 100644 index 0000000..69639ff --- /dev/null +++ b/drivers/net/cpsw.c @@ -0,0 +1,1021 @@ +/* + * CPSW Ethernet Switch Driver + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define BITMASK(bits) ((1 << (bits)) - 1) +#define PHY_REG_MASK 0x1f +#define PHY_ID_MASK 0x1f +#define NUM_DESCS (PKTBUFSRX * 2) +#define PKT_MIN 60 +#define PKT_MAX (1500 + 14 + 4 + 4) + +/* DMA Registers */ +#define CPDMA_TXCONTROL 0x004 +#define CPDMA_RXCONTROL 0x014 +#define CPDMA_SOFTRESET 0x01c +#define CPDMA_RXFREE 0x0e0 +#define CPDMA_TXHDP_VER1 0x100 +#define CPDMA_TXHDP_VER2 0x200 +#define CPDMA_RXHDP_VER1 0x120 +#define CPDMA_RXHDP_VER2 0x220 +#define CPDMA_TXCP_VER1 0x140 +#define CPDMA_TXCP_VER2 0x240 +#define CPDMA_RXCP_VER1 0x160 +#define CPDMA_RXCP_VER2 0x260 + +#define CPDMA_RAM_ADDR 0x4a102000 + +/* Descriptor mode bits */ +#define CPDMA_DESC_SOP BIT(31) +#define CPDMA_DESC_EOP BIT(30) +#define CPDMA_DESC_OWNER BIT(29) +#define CPDMA_DESC_EOQ BIT(28) + +struct cpsw_mdio_regs { + u32 version; + u32 control; +#define CONTROL_IDLE (1 << 31) +#define CONTROL_ENABLE (1 << 30) + + u32 alive; + u32 link; + u32 linkintraw; + u32 linkintmasked; + u32 __reserved_0[2]; + u32 userintraw; + u32 userintmasked; + u32 userintmaskset; + u32 userintmaskclr; + u32 __reserved_1[20]; + + struct { + u32 access; + u32 physel; +#define USERACCESS_GO (1 << 31) +#define USERACCESS_WRITE (1 << 30) +#define USERACCESS_ACK (1 << 29) +#define USERACCESS_READ (0) +#define USERACCESS_DATA (0xffff) + } user[0]; +}; + +struct cpsw_regs { + u32 id_ver; + u32 control; + u32 soft_reset; + u32 stat_port_en; + u32 ptype; +}; + +struct cpsw_slave_regs { + u32 max_blks; + u32 blk_cnt; + u32 flow_thresh; + u32 port_vlan; + u32 tx_pri_map; +#ifdef CONFIG_TI814X + u32 ts_ctl; + u32 ts_seq_ltype; + u32 ts_vlan; +#endif + u32 sa_lo; + u32 sa_hi; +}; + +struct cpsw_host_regs { + u32 max_blks; + u32 blk_cnt; + u32 flow_thresh; + u32 port_vlan; + u32 tx_pri_map; + u32 cpdma_tx_pri_map; + u32 cpdma_rx_chan_map; +}; + +struct cpsw_sliver_regs { + u32 id_ver; + u32 mac_control; + u32 mac_status; + u32 soft_reset; + u32 rx_maxlen; + u32 __reserved_0; + u32 rx_pause; + u32 tx_pause; + u32 __reserved_1; + u32 rx_pri_map; +}; + +#define ALE_ENTRY_BITS 68 +#define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32) + +/* ALE Registers */ +#define ALE_CONTROL 0x08 +#define ALE_UNKNOWNVLAN 0x18 +#define ALE_TABLE_CONTROL 0x20 +#define ALE_TABLE 0x34 +#define ALE_PORTCTL 0x40 + +#define ALE_TABLE_WRITE BIT(31) + +#define ALE_TYPE_FREE 0 +#define ALE_TYPE_ADDR 1 +#define ALE_TYPE_VLAN 2 +#define ALE_TYPE_VLAN_ADDR 3 + +#define ALE_UCAST_PERSISTANT 0 +#define ALE_UCAST_UNTOUCHED 1 +#define ALE_UCAST_OUI 2 +#define ALE_UCAST_TOUCHED 3 + +#define ALE_MCAST_FWD 0 +#define ALE_MCAST_BLOCK_LEARN_FWD 1 +#define ALE_MCAST_FWD_LEARN 2 +#define ALE_MCAST_FWD_2 3 + +enum cpsw_ale_port_state { + ALE_PORT_STATE_DISABLE = 0x00, + ALE_PORT_STATE_BLOCK = 0x01, + ALE_PORT_STATE_LEARN = 0x02, + ALE_PORT_STATE_FORWARD = 0x03, +}; + +/* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */ +#define ALE_SECURE 1 +#define ALE_BLOCKED 2 + +struct cpsw_slave { + struct cpsw_slave_regs *regs; + struct cpsw_sliver_regs *sliver; + int slave_num; + u32 mac_control; + struct cpsw_slave_data *data; +}; + +struct cpdma_desc { + /* hardware fields */ + u32 hw_next; + u32 hw_buffer; + u32 hw_len; + u32 hw_mode; + /* software fields */ + u32 sw_buffer; + u32 sw_len; +}; + +struct cpdma_chan { + struct cpdma_desc *head, *tail; + void *hdp, *cp, *rxfree; +}; + +#define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld) +#define desc_read(desc, fld) __raw_readl(&(desc)->fld) +#define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld)) + +#define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld) +#define chan_read(chan, fld) __raw_readl((chan)->fld) +#define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld)) + +struct cpsw_priv { + struct device_d *dev; + struct eth_device edev; + struct mii_bus miibus; + + struct cpsw_platform_data data; + int host_port; + uint8_t mac_addr[6]; + + struct cpsw_regs *regs; + void *dma_regs; + struct cpsw_host_regs *host_port_regs; + void *ale_regs; + + struct cpdma_desc *descs; + struct cpdma_desc *desc_free; + struct cpdma_chan rx_chan, tx_chan; + + struct cpsw_slave *slaves; +#define for_each_slave(priv, func, arg...) \ + do { \ + int idx; \ + for (idx = 0; idx < (priv)->data.slaves; idx++) \ + (func)((priv)->slaves + idx, ##arg); \ + } while (0) +}; + +static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) +{ + int idx; + + idx = start / 32; + start -= idx * 32; + idx = 2 - idx; /* flip */ + return (ale_entry[idx] >> start) & BITMASK(bits); +} + +static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, + u32 value) +{ + int idx; + + value &= BITMASK(bits); + idx = start / 32; + start -= idx * 32; + idx = 2 - idx; /* flip */ + ale_entry[idx] &= ~(BITMASK(bits) << start); + ale_entry[idx] |= (value << start); +} + +#define DEFINE_ALE_FIELD(name, start, bits) \ +static inline int cpsw_ale_get_##name(u32 *ale_entry) \ +{ \ + return cpsw_ale_get_field(ale_entry, start, bits); \ +} \ +static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \ +{ \ + cpsw_ale_set_field(ale_entry, start, bits, value); \ +} + +DEFINE_ALE_FIELD(entry_type, 60, 2) +DEFINE_ALE_FIELD(mcast_state, 62, 2) +DEFINE_ALE_FIELD(port_mask, 66, 3) +DEFINE_ALE_FIELD(ucast_type, 62, 2) +DEFINE_ALE_FIELD(port_num, 66, 2) +DEFINE_ALE_FIELD(blocked, 65, 1) +DEFINE_ALE_FIELD(secure, 64, 1) +DEFINE_ALE_FIELD(mcast, 40, 1) + +char ethbdaddr [6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + +/* The MAC address field in the ALE entry cannot be macroized as above */ +static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr) +{ + int i; + + for (i = 0; i < 6; i++) + addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8); +} + +static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr) +{ + int i; + + for (i = 0; i < 6; i++) + cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]); +} + +static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry) +{ + int i; + + __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL); + + for (i = 0; i < ALE_ENTRY_WORDS; i++) + ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i); + + return idx; +} + +static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry) +{ + int i; + + for (i = 0; i < ALE_ENTRY_WORDS; i++) + __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i); + + __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL); + + return idx; +} + +static int cpsw_ale_match_addr(struct cpsw_priv *priv, u8* addr) +{ + u32 ale_entry[ALE_ENTRY_WORDS]; + int type, idx; + + for (idx = 0; idx < priv->data.ale_entries; idx++) { + u8 entry_addr[6]; + + cpsw_ale_read(priv, idx, ale_entry); + type = cpsw_ale_get_entry_type(ale_entry); + if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) + continue; + cpsw_ale_get_addr(ale_entry, entry_addr); + if (memcmp(entry_addr, addr, 6) == 0) + return idx; + } + return -ENOENT; +} + +static int cpsw_ale_match_free(struct cpsw_priv *priv) +{ + u32 ale_entry[ALE_ENTRY_WORDS]; + int type, idx; + + for (idx = 0; idx < priv->data.ale_entries; idx++) { + cpsw_ale_read(priv, idx, ale_entry); + type = cpsw_ale_get_entry_type(ale_entry); + if (type == ALE_TYPE_FREE) + return idx; + } + return -ENOENT; +} + +static int cpsw_ale_find_ageable(struct cpsw_priv *priv) +{ + u32 ale_entry[ALE_ENTRY_WORDS]; + int type, idx; + + for (idx = 0; idx < priv->data.ale_entries; idx++) { + cpsw_ale_read(priv, idx, ale_entry); + type = cpsw_ale_get_entry_type(ale_entry); + if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) + continue; + if (cpsw_ale_get_mcast(ale_entry)) + continue; + type = cpsw_ale_get_ucast_type(ale_entry); + if (type != ALE_UCAST_PERSISTANT && + type != ALE_UCAST_OUI) + return idx; + } + return -ENOENT; +} + +static int cpsw_ale_add_ucast(struct cpsw_priv *priv, u8 *addr, + int port, int flags) +{ + u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; + int idx; + + cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); + cpsw_ale_set_addr(ale_entry, addr); + cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT); + cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0); + cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0); + cpsw_ale_set_port_num(ale_entry, port); + + idx = cpsw_ale_match_addr(priv, addr); + if (idx < 0) + idx = cpsw_ale_match_free(priv); + if (idx < 0) + idx = cpsw_ale_find_ageable(priv); + if (idx < 0) + return -ENOMEM; + + cpsw_ale_write(priv, idx, ale_entry); + return 0; +} + +static int cpsw_ale_add_mcast(struct cpsw_priv *priv, u8 *addr, int port_mask) +{ + u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; + int idx, mask; + + idx = cpsw_ale_match_addr(priv, addr); + if (idx >= 0) + cpsw_ale_read(priv, idx, ale_entry); + + cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); + cpsw_ale_set_addr(ale_entry, addr); + cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2); + + mask = cpsw_ale_get_port_mask(ale_entry); + port_mask |= mask; + cpsw_ale_set_port_mask(ale_entry, port_mask); + + if (idx < 0) + idx = cpsw_ale_match_free(priv); + if (idx < 0) + idx = cpsw_ale_find_ageable(priv); + if (idx < 0) + return -ENOMEM; + + cpsw_ale_write(priv, idx, ale_entry); + return 0; +} + +static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val) +{ + u32 tmp, mask = BIT(bit); + + tmp = __raw_readl(priv->ale_regs + ALE_CONTROL); + tmp &= ~mask; + tmp |= val ? mask : 0; + __raw_writel(tmp, priv->ale_regs + ALE_CONTROL); +} + +#define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val) +#define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val) +#define cpsw_ale_bypass(priv, val) cpsw_ale_control(priv, 4, val) +#define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val) + +static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port, + int val) +{ + int offset = ALE_PORTCTL + 4 * port; + u32 tmp, mask = 0x3; + + tmp = __raw_readl(priv->ale_regs + offset); + tmp &= ~mask; + tmp |= val & 0x3; + __raw_writel(tmp, priv->ale_regs + offset); +} + +static struct cpsw_mdio_regs *mdio_regs; + +/* wait until hardware is ready for another user access */ +static inline u32 wait_for_user_access(void) +{ + u32 tmp; + + while ((tmp = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO) + ; + + return tmp; +} + +/* wait until hardware state machine is idle */ +static inline void wait_for_idle(void) +{ + while ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0) + ; +} + +static int cpsw_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg) +{ + u32 tmp; + + if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) + return -EINVAL; + + wait_for_user_access(); + tmp = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) | + (phy_id << 16)); + __raw_writel(tmp, &mdio_regs->user[0].access); + tmp = wait_for_user_access(); + + return (tmp & USERACCESS_ACK) ? (tmp & USERACCESS_DATA) : -1; +} + +static int cpsw_mdio_write(struct mii_bus *bus, int phy_id, int phy_reg, u16 value) +{ + u32 tmp; + + if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) + return -EINVAL; + + wait_for_user_access(); + tmp = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) | + (phy_id << 16) | (value & USERACCESS_DATA)); + __raw_writel(tmp, &mdio_regs->user[0].access); + wait_for_user_access(); + + return 0; +} + +static inline void soft_reset(void *reg) +{ + __raw_writel(1, reg); + while (__raw_readl(reg) & 1) + ; +} + +#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ + ((mac)[2] << 16) | ((mac)[3] << 24)) +#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) + +static void cpsw_set_slave_mac(struct cpsw_slave *slave, + struct cpsw_priv *priv, + unsigned char *mac) +{ + dev_dbg(priv->dev, "* %s\n", __func__); + + __raw_writel(mac_hi(mac), &slave->regs->sa_hi); + __raw_writel(mac_lo(mac), &slave->regs->sa_lo); +} + +static int cpsw_get_hwaddr(struct eth_device *edev, unsigned char *mac) +{ + struct cpsw_priv *priv = edev->priv; + + dev_dbg(priv->dev, "* %s\n", __func__); + + return -1; +} + +static int cpsw_set_hwaddr(struct eth_device *edev, unsigned char *mac) +{ + struct cpsw_priv *priv = edev->priv; + + dev_dbg(priv->dev, "* %s\n", __func__); + + memcpy(&priv->mac_addr, mac, sizeof(priv->mac_addr)); + + for_each_slave(priv, cpsw_set_slave_mac, priv, mac); + + return 0; +} + +static void cpsw_slave_update_link(struct cpsw_slave *slave, + struct cpsw_priv *priv, int *link) +{ + struct phy_device *phydev = priv->edev.phydev; + u32 mac_control = 0; + + dev_dbg(priv->dev, "* %s\n", __func__); + + if (!phydev) + return; + + if (slave->slave_num) + return; + + if (phydev->link) { + *link = 1; + mac_control = priv->data.mac_control; + if (phydev->speed == SPEED_10) + mac_control |= BIT(18); /* In Band mode */ + else if (phydev->speed == SPEED_100) + mac_control |= BIT(15); + else if (phydev->speed == SPEED_1000) + mac_control &= ~BIT(7); /* TODO: Do not enable + * gig support now */ + if (phydev->duplex == DUPLEX_FULL) + mac_control |= BIT(0); /* FULLDUPLEXEN */ + } + + if (mac_control == slave->mac_control) + return; + + if (mac_control) { + dev_dbg(priv->dev, "link up on port %d, speed %d, %s duplex\n", + slave->slave_num, phydev->speed, + (phydev->duplex == DUPLEX_FULL) ? "full" : "half"); + } else { + dev_dbg(priv->dev, "link down on port %d\n", slave->slave_num); + } + + __raw_writel(mac_control, &slave->sliver->mac_control); + slave->mac_control = mac_control; +} + +static int cpsw_update_link(struct cpsw_priv *priv) +{ + int link = 0; + + dev_dbg(priv->dev, "* %s\n", __func__); + + for_each_slave(priv, cpsw_slave_update_link, priv, &link); + return link; +} + +static void cpsw_adjust_link(struct eth_device *edev) { + struct cpsw_priv *priv = edev->priv; + + dev_dbg(priv->dev, "* %s\n", __func__); + + cpsw_update_link(priv); +} + +static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) +{ + if (priv->host_port == 0) + return slave_num + 1; + else + return slave_num; +} + +static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) +{ + u32 slave_port; + + dev_dbg(priv->dev, "* %s\n", __func__); + + soft_reset(&slave->sliver->soft_reset); + + /* setup priority mapping */ + __raw_writel(0x76543210, &slave->sliver->rx_pri_map); + __raw_writel(0x33221100, &slave->regs->tx_pri_map); + + /* setup max packet size, and mac address */ + __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen); + //cpsw_set_slave_mac(slave, priv); + + slave->mac_control = 0; /* no link yet */ + + /* enable forwarding */ + slave_port = cpsw_get_slave_port(priv, slave->slave_num); + cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD); + + /* add broadcast address */ + cpsw_ale_add_mcast(priv, ethbdaddr, 1 << slave_port); +} + +static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv) +{ + struct cpdma_desc *desc = priv->desc_free; + + if (desc) + priv->desc_free = desc_read_ptr(desc, hw_next); + return desc; +} + +static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc) +{ + if (desc) { + desc_write(desc, hw_next, priv->desc_free); + priv->desc_free = desc; + } +} + +static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan, + volatile void *buffer, int len) +{ + struct cpdma_desc *desc, *prev; + u32 mode; + + //dev_dbg(priv->dev, "* %s\n", __func__); + + desc = cpdma_desc_alloc(priv); + if (!desc) + return -ENOMEM; + + if (len < PKT_MIN) + len = PKT_MIN; + + mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP; + + desc_write(desc, hw_next, 0); + desc_write(desc, hw_buffer, buffer); + desc_write(desc, hw_len, len); + desc_write(desc, hw_mode, mode | len); + desc_write(desc, sw_buffer, buffer); + desc_write(desc, sw_len, len); + + dev_dbg(priv->dev, "%s: submit addr=0x%p len=%i\n", __func__, buffer, len); + + if (!chan->head) { + /* simple case - first packet enqueued */ + chan->head = desc; + chan->tail = desc; + chan_write(chan, hdp, desc); + goto done; + } + + /* not the first packet - enqueue at the tail */ + prev = chan->tail; + desc_write(prev, hw_next, desc); + chan->tail = desc; + + /* next check if EOQ has been triggered already */ + if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ) { + chan_write(chan, hdp, desc); + } + +done: + if (chan->rxfree) + chan_write(chan, rxfree, 1); + return 0; +} + +static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan, + void **buffer, int *len) +{ + struct cpdma_desc *desc = chan->head; + u32 status; + + if (!desc) + return -ENOENT; + + status = desc_read(desc, hw_mode); + + if (len) + *len = status & 0x7ff; + + if (buffer) + *buffer = desc_read_ptr(desc, sw_buffer); + + if (status & CPDMA_DESC_OWNER) + return -EBUSY; + + chan->head = desc_read_ptr(desc, hw_next); + chan_write(chan, cp, desc); + + cpdma_desc_free(priv, desc); + return 0; +} + +static int cpsw_init(struct eth_device *edev) +{ + struct cpsw_priv *priv = edev->priv; + + dev_dbg(priv->dev, "* %s\n", __func__); + + return 0; +} + +static int cpsw_open(struct eth_device *edev) +{ + struct cpsw_priv *priv = edev->priv; + struct cpsw_slave_data *slave_data = priv->data.slave_data; + int i, ret; + + dev_dbg(priv->dev, "* %s\n", __func__); + + ret = phy_device_connect(edev, &priv->miibus, slave_data[0].phy_id, + cpsw_adjust_link, 0, slave_data[0].phy_if); + if (ret) + return ret; + + priv->data.control(1); + + /* soft reset the controller and initialize priv */ + soft_reset(&priv->regs->soft_reset); + + /* initialize and reset the address lookup engine */ + cpsw_ale_enable(priv, 1); + cpsw_ale_clear(priv, 1); + cpsw_ale_bypass(priv, 0); + cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */ + + /* setup host port priority mapping */ + __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map); + __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); + + /* disable priority elevation and enable statistics on all ports */ + __raw_writel(0, &priv->regs->ptype); + + /* enable statistics collection only on the host port */ + __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); + + cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD); + + cpsw_ale_add_ucast(priv, priv->mac_addr, priv->host_port, + ALE_SECURE); + cpsw_ale_add_mcast(priv, ethbdaddr, 1 << priv->host_port); + + for_each_slave(priv, cpsw_slave_init, priv); + + cpsw_update_link(priv); + + /* init descriptor pool */ + for (i = 0; i < NUM_DESCS; i++) { + desc_write(&priv->descs[i], hw_next, + (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]); + } + priv->desc_free = &priv->descs[0]; + + /* initialize channels */ + if (priv->data.version == CPSW_CTRL_VERSION_2) { + memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); + priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2; + priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2; + priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; + + memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); + priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2; + priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2; + } else { + memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); + priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1; + priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1; + priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; + + memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); + priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1; + priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1; + } + + /* clear dma state */ + soft_reset(priv->dma_regs + CPDMA_SOFTRESET); + + if (priv->data.version == CPSW_CTRL_VERSION_2) { + for (i = 0; i < priv->data.channels; i++) { + __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 + * i); + } + } else { + for (i = 0; i < priv->data.channels; i++) { + __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 + * i); + + } + } + + __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL); + __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL); + + /* submit rx descs */ + for (i = 0; i < PKTBUFSRX; i++) { + ret = cpdma_submit(priv, &priv->rx_chan, NetRxPackets[i], + PKTSIZE); + if (ret < 0) { + printf("error %d submitting rx desc\n", ret); + break; + } + } + + return 0; +} + +static void cpsw_halt(struct eth_device *dev) +{ + struct cpsw_priv *priv = dev->priv; + priv->data.control(0); +} + +static int cpsw_send(struct eth_device *dev, void *packet, int length) +{ + // FIXME *packet was volatile before, + struct cpsw_priv *priv = dev->priv; + void *buffer; + int len; + + dev_dbg(priv->dev, "* %s\n", __func__); + + if (!cpsw_update_link(priv)) + return -EIO; + + /* first reap completed packets */ + while (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0) + ; + + dev_dbg(priv->dev, "%s: %i bytes @ 0x%p\n", __func__, length, packet); + dma_flush_range((ulong) packet, (ulong)packet + length); + return cpdma_submit(priv, &priv->tx_chan, packet, length); +} + +static int cpsw_recv(struct eth_device *dev) +{ + struct cpsw_priv *priv = dev->priv; + void *buffer; + int len; + + //dev_dbg(priv->dev, "* %s\n", __func__); + + while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) { + dev_dbg(priv->dev, "%s: %i bytes @ 0x%p\n", __func__, len, buffer); + dma_inv_range((ulong)buffer, (ulong)buffer + len); + net_receive(buffer, len); + cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE); + } + + return 0; +} + +static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num, + struct cpsw_priv *priv) +{ + void *regs = priv->regs; + struct cpsw_slave_data *data = priv->data.slave_data + slave_num; + + dev_dbg(priv->dev, "* %s\n", __func__); + + slave->slave_num = slave_num; + slave->data = data; + slave->regs = regs + data->slave_reg_ofs; + slave->sliver = regs + data->sliver_reg_ofs; +} + +int cpsw_probe(struct device_d *dev) +{ + struct cpsw_platform_data *data = (struct cpsw_platform_data *)dev->platform_data; + struct cpsw_priv *priv; + void *regs = (void *)data->cpsw_base; + struct eth_device *edev; + uint64_t start; + uint32_t phy_mask; + + dev_dbg(dev, "* %s\n", __func__); + + priv = xzalloc(sizeof(*priv)); + priv->dev = dev; + priv->data = *data; + edev = &priv->edev; + + priv->slaves = xzalloc(sizeof(struct cpsw_slave) * data->slaves); + + priv->descs = (void *)CPDMA_RAM_ADDR; + priv->host_port = data->host_port_num; + priv->regs = regs; + priv->host_port_regs = regs + data->host_port_reg_ofs; + priv->dma_regs = regs + data->cpdma_reg_ofs; + priv->ale_regs = regs + data->ale_reg_ofs; + + for_each_slave(priv, cpsw_slave_setup, idx, priv); + + edev->priv = priv; + edev->init = cpsw_init; + edev->open = cpsw_open; + edev->halt = cpsw_halt; + edev->send = cpsw_send; + edev->recv = cpsw_recv; + edev->get_ethaddr = cpsw_get_hwaddr; + edev->set_ethaddr = cpsw_set_hwaddr; + edev->parent = dev; + + mdio_regs = (struct cpsw_mdio_regs *)data->mdio_base; + priv->miibus.read = cpsw_mdio_read; + priv->miibus.write = cpsw_mdio_write; + priv->miibus.priv = priv; + priv->miibus.parent = dev; + + /* set enable and clock divider */ + __raw_writel(data->mdio_div | CONTROL_ENABLE, &mdio_regs->control); + + /* + * wait for scan logic to settle: + * the scan time consists of (a) a large fixed component, and (b) a + * small component that varies with the mii bus frequency. These + * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x + * silicon. Since the effect of (b) was found to be largely + * negligible, we keep things simple here. + */ + udelay(1000); + + start = get_time_ns(); + while (1) { + phy_mask = readl(&mdio_regs->alive); + if (phy_mask) { + dev_info(dev, "detected phy mask 0x%x\n", phy_mask); + phy_mask = ~phy_mask; + break; + } + if (is_timeout(start, 256 * MSECOND)) { + dev_err(dev, "no live phy, scanning all\n"); + phy_mask = 0; + break; + } + } + + priv->miibus.phy_mask = phy_mask; + + mdiobus_register(&priv->miibus); + + eth_register(edev); + + return 0; +} + +static struct driver_d cpsw_driver = { + .name = "cpsw", + .probe = cpsw_probe, +// .remove = cpsw_remove, +}; + +static int cpsw_register(void) +{ + platform_driver_register(&cpsw_driver); + return 0; +} + +device_initcall(cpsw_register); -- 1.7.10.4 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox