* [PATCH 02/13] at91: enable clock via clock framework
2012-12-28 19:16 ` [PATCH 01/13] at91: factorise dbgu address Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-28 19:16 ` Jean-Christophe PLAGNIOL-VILLARD
2013-01-02 10:58 ` Sascha Hauer
2012-12-28 19:16 ` [PATCH 03/13] at91: factoryse PMC address as it's the same on every soc Jean-Christophe PLAGNIOL-VILLARD
` (10 subsequent siblings)
11 siblings, 1 reply; 19+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-28 19:16 UTC (permalink / raw)
To: barebox
fix at91sam926x timer and dss11
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/boards/dss11/init.c | 6 ++++--
arch/arm/mach-at91/at91sam926x_time.c | 23 ++++++++++++++++-------
2 files changed, 20 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boards/dss11/init.c b/arch/arm/boards/dss11/init.c
index 27c1ec7..12d4263 100644
--- a/arch/arm/boards/dss11/init.c
+++ b/arch/arm/boards/dss11/init.c
@@ -32,8 +32,8 @@
#include <mach/sam9_smc.h>
#include <gpio.h>
#include <mach/io.h>
-#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
+#include <linux/clk.h>
static struct atmel_nand_data nand_pdata = {
.ale = 21,
@@ -82,7 +82,9 @@ static struct at91_ether_platform_data macb_pdata = {
static void dss11_phy_reset(void)
{
unsigned long rstc;
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+ struct clk *clk = clk_get(NULL, "macb_clk");
+
+ clk_enable(clk);
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 7425e0a..1ce8d30 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -30,11 +30,11 @@
#include <clock.h>
#include <asm/hardware.h>
#include <mach/at91_pit.h>
-#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <mach/io.h>
#include <io.h>
#include <linux/clk.h>
+#include <linux/err.h>
uint64_t at91sam9_clocksource_read(void)
{
@@ -49,15 +49,24 @@ static struct clocksource cs = {
static int clocksource_init (void)
{
+ struct clk *clk;
u32 pit_rate;
- /*
- * Enable PITC Clock
- * The clock is already enabled for system controller in boot
- */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+ clk = clk_get(NULL, "mck");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ dev_err(dev, "clock not found: %d\n", ret);
+ return ret;
+ }
- pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
+ ret = clk_enable(clk);
+ if (ret < 0) {
+ dev_err(dev, "clock failed to enable: %d\n", ret);
+ clk_put(clk);
+ return ret;
+ }
+
+ pit_rate = clk_get_rate(clk) / 16;
/* Enable PITC */
at91_sys_write(AT91_PIT_MR, 0xfffff | AT91_PIT_PITEN);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 02/13] at91: enable clock via clock framework
2012-12-28 19:16 ` [PATCH 02/13] at91: enable clock via clock framework Jean-Christophe PLAGNIOL-VILLARD
@ 2013-01-02 10:58 ` Sascha Hauer
0 siblings, 0 replies; 19+ messages in thread
From: Sascha Hauer @ 2013-01-02 10:58 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Fri, Dec 28, 2012 at 08:16:03PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> fix at91sam926x timer and dss11
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
> arch/arm/boards/dss11/init.c | 6 ++++--
> arch/arm/mach-at91/at91sam926x_time.c | 23 ++++++++++++++++-------
> 2 files changed, 20 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/boards/dss11/init.c b/arch/arm/boards/dss11/init.c
> index 27c1ec7..12d4263 100644
> --- a/arch/arm/boards/dss11/init.c
> +++ b/arch/arm/boards/dss11/init.c
> @@ -32,8 +32,8 @@
> #include <mach/sam9_smc.h>
> #include <gpio.h>
> #include <mach/io.h>
> -#include <mach/at91_pmc.h>
> #include <mach/at91_rstc.h>
> +#include <linux/clk.h>
>
> static struct atmel_nand_data nand_pdata = {
> .ale = 21,
> @@ -82,7 +82,9 @@ static struct at91_ether_platform_data macb_pdata = {
> static void dss11_phy_reset(void)
> {
> unsigned long rstc;
> - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
> + struct clk *clk = clk_get(NULL, "macb_clk");
> +
> + clk_enable(clk);
>
> at91_set_gpio_input(AT91_PIN_PA14, 0);
> at91_set_gpio_input(AT91_PIN_PA15, 0);
> diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
> index 7425e0a..1ce8d30 100644
> --- a/arch/arm/mach-at91/at91sam926x_time.c
> +++ b/arch/arm/mach-at91/at91sam926x_time.c
> @@ -30,11 +30,11 @@
> #include <clock.h>
> #include <asm/hardware.h>
> #include <mach/at91_pit.h>
> -#include <mach/at91_pmc.h>
> #include <mach/at91_rstc.h>
> #include <mach/io.h>
> #include <io.h>
> #include <linux/clk.h>
> +#include <linux/err.h>
>
> uint64_t at91sam9_clocksource_read(void)
> {
> @@ -49,15 +49,24 @@ static struct clocksource cs = {
>
> static int clocksource_init (void)
> {
> + struct clk *clk;
> u32 pit_rate;
>
> - /*
> - * Enable PITC Clock
> - * The clock is already enabled for system controller in boot
> - */
> - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
> + clk = clk_get(NULL, "mck");
> + if (IS_ERR(clk)) {
> + ret = PTR_ERR(clk);
> + dev_err(dev, "clock not found: %d\n", ret);
> + return ret;
> + }
This breaks compilation:
arch/arm/mach-at91/at91sam926x_time.c: In function 'clocksource_init':
arch/arm/mach-at91/at91sam926x_time.c:57:3: error: 'ret' undeclared (first use in this function)
arch/arm/mach-at91/at91sam926x_time.c:57:3: note: each undeclared identifier is reported only once for each function it appears in
arch/arm/mach-at91/at91sam926x_time.c:58:3: error: 'dev' undeclared (first use in this function)
I guess the patch order is wrong.
Sascha
--
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 03/13] at91: factoryse PMC address as it's the same on every soc
2012-12-28 19:16 ` [PATCH 01/13] at91: factorise dbgu address Jean-Christophe PLAGNIOL-VILLARD
2012-12-28 19:16 ` [PATCH 02/13] at91: enable clock via clock framework Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-28 19:16 ` Jean-Christophe PLAGNIOL-VILLARD
2013-01-02 11:00 ` Sascha Hauer
2012-12-28 19:16 ` [PATCH 04/13] at91: pmc: drop AT91_BASE_SYS Jean-Christophe PLAGNIOL-VILLARD
` (9 subsequent siblings)
11 siblings, 1 reply; 19+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-28 19:16 UTC (permalink / raw)
To: barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/mach-at91/include/mach/at91rm9200.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9260.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9261.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9263.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9g45.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9n12.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9x5.h | 1 -
arch/arm/mach-at91/include/mach/hardware.h | 2 ++
8 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index 2850f0d..69ebaab 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -84,7 +84,6 @@
*/
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
-#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index be07e57..e1ec7e5 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -87,7 +87,6 @@
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index d51673e..17a3949 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -73,7 +73,6 @@
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index c8374a7..c887b38 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -87,7 +87,6 @@
#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 10f3170..1c98491 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -97,7 +97,6 @@
#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
index dcbdb1b..afe0034 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -93,7 +93,6 @@
#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 2240710..ca778fb 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -100,7 +100,6 @@
#define AT91_DMA1 (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 64efb2a..b4e24af 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -20,6 +20,8 @@
/* 9263, 9g45 */
#define AT91_BASE_DBGU1 0xffffee00
+#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
+
#if defined(CONFIG_ARCH_AT91RM9200)
#include <mach/at91rm9200.h>
#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
--
1.7.10.4
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^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 03/13] at91: factoryse PMC address as it's the same on every soc
2012-12-28 19:16 ` [PATCH 03/13] at91: factoryse PMC address as it's the same on every soc Jean-Christophe PLAGNIOL-VILLARD
@ 2013-01-02 11:00 ` Sascha Hauer
0 siblings, 0 replies; 19+ messages in thread
From: Sascha Hauer @ 2013-01-02 11:00 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
subject: s/factoryse/factorise/
Sascha
On Fri, Dec 28, 2012 at 08:16:04PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
> arch/arm/mach-at91/include/mach/at91rm9200.h | 1 -
> arch/arm/mach-at91/include/mach/at91sam9260.h | 1 -
> arch/arm/mach-at91/include/mach/at91sam9261.h | 1 -
> arch/arm/mach-at91/include/mach/at91sam9263.h | 1 -
> arch/arm/mach-at91/include/mach/at91sam9g45.h | 1 -
> arch/arm/mach-at91/include/mach/at91sam9n12.h | 1 -
> arch/arm/mach-at91/include/mach/at91sam9x5.h | 1 -
> arch/arm/mach-at91/include/mach/hardware.h | 2 ++
> 8 files changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
> index 2850f0d..69ebaab 100644
> --- a/arch/arm/mach-at91/include/mach/at91rm9200.h
> +++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
> @@ -84,7 +84,6 @@
> */
> #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
> #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
> -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
> #define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
> #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
> #define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
> index be07e57..e1ec7e5 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9260.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
> @@ -87,7 +87,6 @@
> #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
> #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
> #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
> -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
> #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
> index d51673e..17a3949 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9261.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
> @@ -73,7 +73,6 @@
> #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
> #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
> #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
> -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
> #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
> index c8374a7..c887b38 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9263.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
> @@ -87,7 +87,6 @@
> #define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
> #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
> #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
> -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
> #define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
> index 10f3170..1c98491 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
> @@ -97,7 +97,6 @@
> #define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
> #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
> #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
> -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
> #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
> index dcbdb1b..afe0034 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
> @@ -93,7 +93,6 @@
> #define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
> #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
> #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
> -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
> #define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> index 2240710..ca778fb 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> @@ -100,7 +100,6 @@
> #define AT91_DMA1 (0xffffee00 - AT91_BASE_SYS)
> #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
> #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
> -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
> #define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
> diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
> index 64efb2a..b4e24af 100644
> --- a/arch/arm/mach-at91/include/mach/hardware.h
> +++ b/arch/arm/mach-at91/include/mach/hardware.h
> @@ -20,6 +20,8 @@
> /* 9263, 9g45 */
> #define AT91_BASE_DBGU1 0xffffee00
>
> +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
> +
> #if defined(CONFIG_ARCH_AT91RM9200)
> #include <mach/at91rm9200.h>
> #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
> --
> 1.7.10.4
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 04/13] at91: pmc: drop AT91_BASE_SYS
2012-12-28 19:16 ` [PATCH 01/13] at91: factorise dbgu address Jean-Christophe PLAGNIOL-VILLARD
2012-12-28 19:16 ` [PATCH 02/13] at91: enable clock via clock framework Jean-Christophe PLAGNIOL-VILLARD
2012-12-28 19:16 ` [PATCH 03/13] at91: factoryse PMC address as it's the same on every soc Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-28 19:16 ` Jean-Christophe PLAGNIOL-VILLARD
2012-12-28 19:16 ` [PATCH 05/13] at91: introduce Kconfig to select the dbgu for lowlevel debug Jean-Christophe PLAGNIOL-VILLARD
` (8 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-28 19:16 UTC (permalink / raw)
To: barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/boards/at91sam9260ek/init.c | 2 +-
arch/arm/mach-at91/at91rm9200_lowlevel_init.c | 18 +++++----
arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 18 +++++----
arch/arm/mach-at91/clock.c | 50 ++++++++++++------------
arch/arm/mach-at91/include/mach/at91_pmc.h | 48 +++++++++++++----------
arch/arm/mach-at91/include/mach/cpu.h | 2 +-
arch/arm/mach-at91/include/mach/hardware.h | 2 +-
7 files changed, 76 insertions(+), 64 deletions(-)
diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c
index 5816a1d..d07eda9 100644
--- a/arch/arm/boards/at91sam9260ek/init.c
+++ b/arch/arm/boards/at91sam9260ek/init.c
@@ -135,7 +135,7 @@ static struct at91_ether_platform_data macb_pdata = {
static void at91sam9260ek_phy_reset(void)
{
unsigned long rstc;
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+ at91_pmc_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
diff --git a/arch/arm/mach-at91/at91rm9200_lowlevel_init.c b/arch/arm/mach-at91/at91rm9200_lowlevel_init.c
index 3ce3e67..4add3d9 100644
--- a/arch/arm/mach-at91/at91rm9200_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91rm9200_lowlevel_init.c
@@ -4,6 +4,8 @@
* Under GPLv2
*/
+#define __LOWLEVEL_INIT__
+
#include <common.h>
#include <asm/system.h>
#include <asm/barebox-arm.h>
@@ -31,17 +33,17 @@ void __naked __bare_init reset(void)
/*
* PMC Check if the PLL is already initialized
*/
- r = at91_sys_read(AT91_PMC_MCKR);
+ r = at91_pmc_read(AT91_PMC_MCKR);
if (r & AT91_PMC_CSS)
goto end;
/*
* Enable the Main Oscillator
*/
- at91_sys_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL);
+ at91_pmc_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL);
do {
- r = at91_sys_read(AT91_PMC_SR);
+ r = at91_pmc_read(AT91_PMC_SR);
} while (!(r & AT91_PMC_MOSCS));
/*
@@ -61,24 +63,24 @@ void __naked __bare_init reset(void)
/*
* PLLAR: x MHz for PCK
*/
- at91_sys_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL);
+ at91_pmc_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL);
do {
- r = at91_sys_read(AT91_PMC_SR);
+ r = at91_pmc_read(AT91_PMC_SR);
} while (!(r & AT91_PMC_LOCKA));
/*
* PCK/x = MCK Master Clock from SLOW
*/
- at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL1);
+ at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL1);
/*
* PCK/x = MCK Master Clock from PLLA
*/
- at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL2);
+ at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL2);
do {
- r = at91_sys_read(AT91_PMC_SR);
+ r = at91_pmc_read(AT91_PMC_SR);
} while (!(r & AT91_PMC_MCKRDY));
/*
diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
index 0ee0345..5edbd8b 100644
--- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
@@ -5,6 +5,8 @@
* Under GPLv2
*/
+#define __LOWLEVEL_INIT__
+
#include <common.h>
#include <asm/system.h>
#include <asm/barebox-arm.h>
@@ -30,7 +32,7 @@ static void inline pmc_check_mckrdy(void)
u32 r;
do {
- r = at91_sys_read(AT91_PMC_SR);
+ r = at91_pmc_read(AT91_PMC_SR);
} while (!(r & AT91_PMC_MCKRDY));
}
@@ -71,39 +73,39 @@ void __naked __bare_init reset(void)
/*
* PMC Check if the PLL is already initialized
*/
- r = at91_sys_read(AT91_PMC_MCKR);
+ r = at91_pmc_read(AT91_PMC_MCKR);
if (r & AT91_PMC_CSS)
goto end;
/*
* Enable the Main Oscillator
*/
- at91_sys_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL);
+ at91_pmc_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL);
do {
- r = at91_sys_read(AT91_PMC_SR);
+ r = at91_pmc_read(AT91_PMC_SR);
} while (!(r & AT91_PMC_MOSCS));
/*
* PLLAR: x MHz for PCK
*/
- at91_sys_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL);
+ at91_pmc_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL);
do {
- r = at91_sys_read(AT91_PMC_SR);
+ r = at91_pmc_read(AT91_PMC_SR);
} while (!(r & AT91_PMC_LOCKA));
/*
* PCK/x = MCK Master Clock from SLOW
*/
- at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR1_VAL);
+ at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR1_VAL);
pmc_check_mckrdy();
/*
* PCK/x = MCK Master Clock from PLLA
*/
- at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL);
+ at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL);
pmc_check_mckrdy();
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index e911270..b231ec0 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -126,11 +126,11 @@ static void pllb_mode(struct clk *clk, int is_on)
value = 0;
// REVISIT: Add work-around for AT91RM9200 Errata #26 ?
- at91_sys_write(AT91_CKGR_PLLBR, value);
+ at91_pmc_write(AT91_CKGR_PLLBR, value);
do {
barrier();
- } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
+ } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
}
static struct clk pllb = {
@@ -145,14 +145,14 @@ static struct clk pllb = {
static void pmc_sys_mode(struct clk *clk, int is_on)
{
if (is_on)
- at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
+ at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
else
- at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
+ at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
}
static void pmc_uckr_mode(struct clk *clk, int is_on)
{
- unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
+ unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
if (cpu_is_at91sam9g45()) {
if (is_on)
@@ -163,13 +163,13 @@ static void pmc_uckr_mode(struct clk *clk, int is_on)
if (is_on) {
is_on = AT91_PMC_LOCKU;
- at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
+ at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
} else
- at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
+ at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
do {
barrier();
- } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
+ } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
}
/* USB function clocks (PLLB must be 48 MHz) */
@@ -205,9 +205,9 @@ struct clk mck = {
static void pmc_periph_mode(struct clk *clk, int is_on)
{
if (is_on)
- at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
+ at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
else
- at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
+ at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
}
static struct clk *at91_css_to_clk(unsigned long css)
@@ -352,10 +352,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
if (actual && actual <= rate) {
u32 pckr;
- pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
+ pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
pckr &= css_mask; /* keep clock selection */
pckr |= prescale << prescale_offset;
- at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
+ at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
clk->rate_hz = actual;
break;
}
@@ -386,7 +386,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
clk->rate_hz = parent->rate_hz;
clk->parent = parent;
- at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
+ at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
return 0;
}
@@ -404,7 +404,7 @@ static void init_programmable_clock(struct clk *clk)
else
css_mask = AT91_PMC_CSS;
- pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
+ pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
parent = at91_css_to_clk(pckr & css_mask);
clk->parent = parent;
clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
@@ -550,14 +550,14 @@ static void at91_pllb_usbfs_clock_init(unsigned long main_clock)
if (cpu_is_at91rm9200()) {
uhpck.pmc_mask = AT91RM9200_PMC_UHP;
udpck.pmc_mask = AT91RM9200_PMC_UDP;
- at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
+ at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
cpu_is_at91sam9g10()) {
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
}
- at91_sys_write(AT91_CKGR_PLLBR, 0);
+ at91_pmc_write(AT91_CKGR_PLLBR, 0);
udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
@@ -574,13 +574,13 @@ static void at91_upll_usbfs_clock_init(unsigned long main_clock)
/* Setup divider by 10 to reach 48 MHz */
usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
- at91_sys_write(AT91_PMC_USB, usbr);
+ at91_pmc_write(AT91_PMC_USB, usbr);
/* Now set uhpck values */
uhpck.parent = &utmi_clk;
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
uhpck.rate_hz = utmi_clk.rate_hz;
- uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
+ uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
}
static int pll_overclock = 0;
@@ -591,6 +591,8 @@ int at91_clock_init(unsigned long main_clock)
unsigned tmp, freq, mckr;
int i;
+
+
/*
* When the bootloader initialized the main oscillator correctly,
* there's no problem using the cycle counter. But if it didn't,
@@ -599,14 +601,14 @@ int at91_clock_init(unsigned long main_clock)
*/
if (!main_clock) {
do {
- tmp = at91_sys_read(AT91_CKGR_MCFR);
+ tmp = at91_pmc_read(AT91_CKGR_MCFR);
} while (!(tmp & AT91_PMC_MAINRDY));
main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
}
main_clk.rate_hz = main_clock;
/* report if PLLA is more than mildly overclocked */
- plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
+ plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
if (cpu_has_300M_plla()) {
if (plla.rate_hz > 300000000)
pll_overclock = 1;
@@ -625,7 +627,7 @@ int at91_clock_init(unsigned long main_clock)
}
if (cpu_has_plladiv2()) {
- mckr = at91_sys_read(AT91_PMC_MCKR);
+ mckr = at91_pmc_read(AT91_PMC_MCKR);
plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
}
@@ -664,7 +666,7 @@ int at91_clock_init(unsigned long main_clock)
* MCK and CPU derive from one of those primary clocks.
* For now, assume this parentage won't change.
*/
- mckr = at91_sys_read(AT91_PMC_MCKR);
+ mckr = at91_pmc_read(AT91_PMC_MCKR);
mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
freq = mck.parent->rate_hz;
freq /= pmc_prescaler_divider(mckr); /* prescale */
@@ -748,8 +750,8 @@ static int at91_clock_reset(void)
pr_debug("Clocks: disable unused %s\n", clk->name);
}
- at91_sys_write(AT91_PMC_PCDR, pcdr);
- at91_sys_write(AT91_PMC_SCDR, scdr);
+ at91_pmc_write(AT91_PMC_PCDR, pcdr);
+ at91_pmc_write(AT91_PMC_SCDR, scdr);
return 0;
}
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 59037cf..6fcbf40 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -16,10 +16,16 @@
#ifndef AT91_PMC_H
#define AT91_PMC_H
-#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
-#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
+#define at91_pmc_read(field) \
+ __raw_readl(AT91_PMC + field)
-#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
+#define at91_pmc_write(field, value) \
+ __raw_writel(value, AT91_PMC + field)
+
+#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
+#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
+
+#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
@@ -35,17 +41,17 @@
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
-#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
-#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
-#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
+#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */
+#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
+#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
-#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */
+#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
-#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
+#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
@@ -54,12 +60,12 @@
#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
-#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
+#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
-#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
-#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
+#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
+#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
#define AT91_PMC_DIV (0xff << 0) /* Divider */
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
@@ -71,7 +77,7 @@
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
-#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
+#define AT91_PMC_MCKR 0x30 /* Master Clock Register */
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
@@ -113,27 +119,27 @@
#define AT91_PMC_PLLADIV2_OFF (0 << 12)
#define AT91_PMC_PLLADIV2_ON (1 << 12)
-#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */
+#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
#define AT91_PMC_USBS_PLLA (0 << 0)
#define AT91_PMC_USBS_UPLL (1 << 0)
#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
-#define AT91_PMC_SMD (AT91_PMC + 0x3c) /* Soft Modem Clock Register [some SAM9 only] */
+#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */
#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV)
-#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
+#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */
#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */
#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
#define AT91_PMC_CSSMCK_CSS (0 << 8)
#define AT91_PMC_CSSMCK_MCK (1 << 8)
-#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
-#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
-#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
+#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */
+#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */
+#define AT91_PMC_SR 0x68 /* Status Register */
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
@@ -146,14 +152,14 @@
#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */
#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
-#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
+#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
-#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
+#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */
-#define AT91_PMC_WPSR (AT91_PMC + 0xe8) /* Write Protect Status Register [some SAM9] */
+#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */
#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */
#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 90b9f8a..636fe03 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -86,7 +86,7 @@ static inline unsigned long at91_arch_identify(void)
static inline unsigned long at91cap9_rev_identify(void)
{
- return (at91_sys_read(AT91_PMC_VER));
+ return (at91_pmc_read(AT91_PMC_VER));
}
#endif
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index b4e24af..e283b9d 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -20,7 +20,7 @@
/* 9263, 9g45 */
#define AT91_BASE_DBGU1 0xffffee00
-#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_PMC 0xfffffc00
#if defined(CONFIG_ARCH_AT91RM9200)
#include <mach/at91rm9200.h>
--
1.7.10.4
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^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH 05/13] at91: introduce Kconfig to select the dbgu for lowlevel debug
2012-12-28 19:16 ` [PATCH 01/13] at91: factorise dbgu address Jean-Christophe PLAGNIOL-VILLARD
` (2 preceding siblings ...)
2012-12-28 19:16 ` [PATCH 04/13] at91: pmc: drop AT91_BASE_SYS Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-28 19:16 ` Jean-Christophe PLAGNIOL-VILLARD
2012-12-28 19:16 ` [PATCH 06/13] at91: sync with the kernel address base Jean-Christophe PLAGNIOL-VILLARD
` (7 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-28 19:16 UTC (permalink / raw)
To: barebox
so we can drop AT91_BASE_SYS too
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/mach-at91/Kconfig | 15 +++++++++++++++
arch/arm/mach-at91/include/mach/debug_ll.h | 6 +++++-
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 4c2e319..0ab7e7e 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,5 +1,11 @@
if ARCH_AT91
+config HAVE_AT91_DBGU0
+ bool
+
+config HAVE_AT91_DBGU1
+ bool
+
config ARCH_TEXT_BASE
hex
default 0x73f00000 if ARCH_AT91SAM9G45
@@ -49,6 +55,7 @@ choice
config ARCH_AT91RM9200
bool "AT91RM9200"
select CPU_ARM920T
+ select HAVE_AT91_DBGU0
select HAS_AT91_ETHER
select MACH_HAS_LOWLEVEL_INIT
select MACH_DO_LOWLEVEL_INIT
@@ -56,46 +63,54 @@ config ARCH_AT91RM9200
config ARCH_AT91SAM9260
bool "AT91SAM9260"
select CPU_ARM926T
+ select HAVE_AT91_DBGU0
select HAS_MACB
select AT91SAM9_RESET
config ARCH_AT91SAM9261
bool "AT91SAM9261"
select CPU_ARM926T
+ select HAVE_AT91_DBGU0
select AT91SAM9_RESET
config ARCH_AT91SAM9263
bool "AT91SAM9263"
select CPU_ARM926T
+ select HAVE_AT91_DBGU1
select HAS_MACB
select AT91SAM9_RESET
config ARCH_AT91SAM9G10
bool "AT91SAM9G10"
select CPU_ARM926T
+ select HAVE_AT91_DBGU0
select AT91SAM9_RESET
config ARCH_AT91SAM9G20
bool "AT91SAM9G20"
select CPU_ARM926T
+ select HAVE_AT91_DBGU0
select HAS_MACB
select AT91SAM9_RESET
config ARCH_AT91SAM9G45
bool "AT91SAM9G45 or AT91SAM9M10"
select CPU_ARM926T
+ select HAVE_AT91_DBGU1
select HAS_MACB
select AT91SAM9G45_RESET
config ARCH_AT91SAM9X5
bool "AT91SAM9X5"
select CPU_ARM926T
+ select HAVE_AT91_DBGU0
select HAS_MACB
select AT91SAM9G45_RESET
config ARCH_AT91SAM9N12
bool "AT91SAM9N12"
select CPU_ARM926T
+ select HAVE_AT91_DBGU0
select AT91SAM9G45_RESET
endchoice
diff --git a/arch/arm/mach-at91/include/mach/debug_ll.h b/arch/arm/mach-at91/include/mach/debug_ll.h
index a85fdee..1a85ae4 100644
--- a/arch/arm/mach-at91/include/mach/debug_ll.h
+++ b/arch/arm/mach-at91/include/mach/debug_ll.h
@@ -11,7 +11,11 @@
#include <asm/io.h>
#include <mach/hardware.h>
-#define UART_BASE (AT91_BASE_SYS + AT91_DBGU)
+#ifdef COFNIG_HAVE_AT91_DBGU0
+#define UART_BASE AT91_BASE_DBGU0
+#else
+#define UART_BASE AT91_BASE_DBGU1
+#endif
#define ATMEL_US_CSR 0x0014
#define ATMEL_US_THR 0x001c
--
1.7.10.4
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH 06/13] at91: sync with the kernel address base
2012-12-28 19:16 ` [PATCH 01/13] at91: factorise dbgu address Jean-Christophe PLAGNIOL-VILLARD
` (3 preceding siblings ...)
2012-12-28 19:16 ` [PATCH 05/13] at91: introduce Kconfig to select the dbgu for lowlevel debug Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-28 19:16 ` Jean-Christophe PLAGNIOL-VILLARD
2012-12-28 19:16 ` [PATCH 07/13] at91: at91sam9: provide its own clkdev for pit Jean-Christophe PLAGNIOL-VILLARD
` (6 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-28 19:16 UTC (permalink / raw)
To: barebox
add non AT91_SYS_BASE offset base address define
This will prepare for multi arch support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/mach-at91/include/mach/at91rm9200.h | 21 +++++++++---
arch/arm/mach-at91/include/mach/at91sam9260.h | 28 +++++++++++----
arch/arm/mach-at91/include/mach/at91sam9261.h | 26 ++++++++++----
arch/arm/mach-at91/include/mach/at91sam9263.h | 45 +++++++++++++++++--------
arch/arm/mach-at91/include/mach/at91sam9g45.h | 38 +++++++++++++++------
arch/arm/mach-at91/include/mach/at91sam9n12.h | 37 +++++++++++++++-----
arch/arm/mach-at91/include/mach/at91sam9x5.h | 37 +++++++++++++++-----
7 files changed, 172 insertions(+), 60 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index 69ebaab..36e940d 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -78,20 +78,31 @@
#define AT91RM9200_BASE_SPI 0xfffe0000
#define AT91_BASE_SYS 0xfffff000
+/*
+ * System Peripherals
+ */
+#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
+#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
+#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
+#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
+#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
+#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
+#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
+#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
+
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
-#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
-#define AT91_BASE_PIOA 0xfffff400 /* PIO Controller A */
-#define AT91_BASE_PIOB 0xfffff600 /* PIO Controller B */
-#define AT91_BASE_PIOC 0xfffff800 /* PIO Controller C */
-#define AT91_BASE_PIOD 0xfffffa00 /* PIO Controller D */
+#define AT91_BASE_PIOA AT91RM9200_BASE_PIOA /* PIO Controller A */
+#define AT91_BASE_PIOB AT91RM9200_BASE_PIOB /* PIO Controller B */
+#define AT91_BASE_PIOC AT91RM9200_BASE_PIOC /* PIO Controller C */
+#define AT91_BASE_PIOD AT91RM9200_BASE_PIOD /* PIO Controller D */
#define AT91_USART0 AT91RM9200_BASE_US0
#define AT91_USART1 AT91RM9200_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index e1ec7e5..3dad806 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -78,25 +78,39 @@
#define AT91_BASE_SYS 0xffffe800
/*
+ * System Peripherals
+ */
+#define AT91SAM9260_BASE_ECC 0xffffe800
+#define AT91SAM9260_BASE_SDRAMC 0xffffea00
+#define AT91SAM9260_BASE_SMC 0xffffec00
+#define AT91SAM9260_BASE_MATRIX 0xffffee00
+#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
+#define AT91SAM9260_BASE_PIOA 0xfffff400
+#define AT91SAM9260_BASE_PIOB 0xfffff600
+#define AT91SAM9260_BASE_PIOC 0xfffff800
+#define AT91SAM9260_BASE_RSTC 0xfffffd00
+#define AT91SAM9260_BASE_SHDWC 0xfffffd10
+#define AT91SAM9260_BASE_RTT 0xfffffd20
+#define AT91SAM9260_BASE_PIT 0xfffffd30
+#define AT91SAM9260_BASE_WDT 0xfffffd40
+#define AT91SAM9260_BASE_GPBR 0xfffffd50
+
+/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
-#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
-#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
-#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
-#define AT91_BASE_PIOA 0xfffff400
-#define AT91_BASE_PIOB 0xfffff600
-#define AT91_BASE_PIOC 0xfffff800
+#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
+#define AT91_BASE_PIOB AT91SAM9260_BASE_PIOB
+#define AT91_BASE_PIOC AT91SAM9260_BASE_PIOC
#define AT91_USART0 AT91SAM9260_BASE_US0
#define AT91_USART1 AT91SAM9260_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 17a3949..591ae29 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -66,23 +66,37 @@
/*
+ * System Peripherals
+ */
+#define AT91SAM9261_BASE_SMC 0xffffec00
+#define AT91SAM9261_BASE_MATRIX 0xffffee00
+#define AT91SAM9261_BASE_SDRAMC 0xffffea00
+#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
+#define AT91SAM9261_BASE_PIOA 0xfffff400
+#define AT91SAM9261_BASE_PIOB 0xfffff600
+#define AT91SAM9261_BASE_PIOC 0xfffff800
+#define AT91SAM9261_BASE_RSTC 0xfffffd00
+#define AT91SAM9261_BASE_SHDWC 0xfffffd10
+#define AT91SAM9261_BASE_RTT 0xfffffd20
+#define AT91SAM9261_BASE_PIT 0xfffffd30
+#define AT91SAM9261_BASE_WDT 0xfffffd40
+#define AT91SAM9261_BASE_GPBR 0xfffffd50
+
+/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
-#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
-#define AT91_BASE_PIOA 0xfffff400
-#define AT91_BASE_PIOB 0xfffff600
-#define AT91_BASE_PIOC 0xfffff800
+#define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA
+#define AT91_BASE_PIOB AT91SAM9261_BASE_PIOB
+#define AT91_BASE_PIOC AT91SAM9261_BASE_PIOC
#define AT91_USART0 AT91SAM9261_BASE_US0
#define AT91_USART1 AT91SAM9261_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index c887b38..a0ed231 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -74,32 +74,49 @@
#define AT91SAM9263_BASE_2DGE 0xfffc8000
#define AT91_BASE_SYS 0xffffe000
+
+/*
+ * System Peripherals
+ */
+#define AT91SAM9263_BASE_ECC0 0xffffe000
+#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
+#define AT91SAM9263_BASE_SMC0 0xffffe400
+#define AT91SAM9263_BASE_ECC1 0xffffe600
+#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
+#define AT91SAM9263_BASE_SMC1 0xffffea00
+#define AT91SAM9263_BASE_MATRIX 0xffffec00
+#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
+#define AT91SAM9263_BASE_PIOA 0xfffff200
+#define AT91SAM9263_BASE_PIOB 0xfffff400
+#define AT91SAM9263_BASE_PIOC 0xfffff600
+#define AT91SAM9263_BASE_PIOD 0xfffff800
+#define AT91SAM9263_BASE_PIOE 0xfffffa00
+#define AT91SAM9263_BASE_RSTC 0xfffffd00
+#define AT91SAM9263_BASE_SHDWC 0xfffffd10
+#define AT91SAM9263_BASE_RTT0 0xfffffd20
+#define AT91SAM9263_BASE_PIT 0xfffffd30
+#define AT91SAM9263_BASE_WDT 0xfffffd40
+#define AT91SAM9263_BASE_RTT1 0xfffffd50
+#define AT91SAM9263_BASE_GPBR 0xfffffd60
+
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
-#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
-#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
-#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
-#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
-
-#define AT91_BASE_PIOA 0xfffff200
-#define AT91_BASE_PIOB 0xfffff400
-#define AT91_BASE_PIOC 0xfffff600
-#define AT91_BASE_PIOD 0xfffff800
-#define AT91_BASE_PIOE 0xfffffa00
+
+#define AT91_BASE_PIOA AT91SAM9263_BASE_PIOA
+#define AT91_BASE_PIOB AT91SAM9263_BASE_PIOB
+#define AT91_BASE_PIOC AT91SAM9263_BASE_PIOC
+#define AT91_BASE_PIOD AT91SAM9263_BASE_PIOD
+#define AT91_BASE_PIOE AT91SAM9263_BASE_PIOE
#define AT91_USART0 AT91SAM9263_BASE_US0
#define AT91_USART1 AT91SAM9263_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 1c98491..961a70f 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -87,6 +87,29 @@
#define AT91_BASE_SYS 0xffffe200
/*
+ * System Peripherals
+ */
+#define AT91SAM9G45_BASE_ECC 0xffffe200
+#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
+#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
+#define AT91SAM9G45_BASE_DMA 0xffffec00
+#define AT91SAM9G45_BASE_SMC 0xffffe800
+#define AT91SAM9G45_BASE_MATRIX 0xffffea00
+#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1
+#define AT91SAM9G45_BASE_PIOA 0xfffff200
+#define AT91SAM9G45_BASE_PIOB 0xfffff400
+#define AT91SAM9G45_BASE_PIOC 0xfffff600
+#define AT91SAM9G45_BASE_PIOD 0xfffff800
+#define AT91SAM9G45_BASE_PIOE 0xfffffa00
+#define AT91SAM9G45_BASE_RSTC 0xfffffd00
+#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
+#define AT91SAM9G45_BASE_RTT 0xfffffd20
+#define AT91SAM9G45_BASE_PIT 0xfffffd30
+#define AT91SAM9G45_BASE_WDT 0xfffffd40
+#define AT91SAM9G45_BASE_RTC 0xfffffdb0
+#define AT91SAM9G45_BASE_GPBR 0xfffffd60
+
+/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
@@ -94,22 +117,17 @@
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
-#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
-#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
-#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)
-#define AT91_BASE_PIOA 0xfffff200
-#define AT91_BASE_PIOB 0xfffff400
-#define AT91_BASE_PIOC 0xfffff600
-#define AT91_BASE_PIOD 0xfffff800
-#define AT91_BASE_PIOE 0xfffffa00
+#define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA
+#define AT91_BASE_PIOB AT91SAM9G45_BASE_PIOB
+#define AT91_BASE_PIOC AT91SAM9G45_BASE_PIOC
+#define AT91_BASE_PIOD AT91SAM9G45_BASE_PIOD
+#define AT91_BASE_PIOE AT91SAM9G45_BASE_PIOE
#define AT91_USART0 AT91SAM9G45_BASE_US0
#define AT91_USART1 AT91SAM9G45_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
index afe0034..706005c 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -82,28 +82,47 @@
#define AT91_BASE_SYS 0xffffc000
/*
+ * System Peripherals
+ */
+#define AT91SAM9N12_BASE_FUSE 0xffffdc00
+#define AT91SAM9N12_BASE_MATRIX 0xffffde00
+#define AT91SAM9N12_BASE_PMECC 0xffffe000
+#define AT91SAM9N12_BASE_PMERRLOC 0xffffe600
+#define AT91SAM9N12_BASE_DDRSDRC0 0xffffe800
+#define AT91SAM9N12_BASE_SMC 0xffffea00
+#define AT91SAM9N12_BASE_DMA 0xffffec00
+#define AT91SAM9N12_BASE_AIC 0xfffff000
+#define AT91SAM9N12_BASE_DBGU 0xfffff200
+#define AT91SAM9N12_BASE_PIOA 0xfffff400
+#define AT91SAM9N12_BASE_PIOB 0xfffff600
+#define AT91SAM9N12_BASE_PIOC 0xfffff800
+#define AT91SAM9N12_BASE_PIOD 0xfffffa00
+#define AT91SAM9N12_BASE_PMC 0xfffffc00
+#define AT91SAM9N12_BASE_RSTC 0xfffffe00
+#define AT91SAM9N12_BASE_SHDWC 0xfffffe10
+#define AT91SAM9N12_BASE_PIT 0xfffffe30
+#define AT91SAM9N12_BASE_WDT 0xfffffe40
+#define AT91SAM9N12_BASE_GPBR 0xfffffe60
+#define AT91SAM9N12_BASE_RTC 0xfffffeb0
+
+/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
-#define AT91_FUSE (0xffffdc00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffde00 - AT91_BASE_SYS)
#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)
#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)
#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
#define AT91_SMC (0xffffea00 - AT91_BASE_SYS)
-#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
-#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
-#define AT91_GPBR (0xfffffe60 - AT91_BASE_SYS)
-#define AT91_RTC (0xfffffeb0 - AT91_BASE_SYS)
-#define AT91_BASE_PIOA 0xfffff400
-#define AT91_BASE_PIOB 0xfffff600
-#define AT91_BASE_PIOC 0xfffff800
-#define AT91_BASE_PIOD 0xfffffa00
+#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA
+#define AT91_BASE_PIOB AT91SAM9N12_BASE_PIOB
+#define AT91_BASE_PIOC AT91SAM9N12_BASE_PIOC
+#define AT91_BASE_PIOD AT91SAM9N12_BASE_PIOD
#define AT91_USART0 AT91SAM9X5_BASE_US0
#define AT91_USART1 AT91SAM9X5_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index ca778fb..b47e3cb 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -89,6 +89,30 @@
#define AT91_BASE_SYS 0xffffc000
/*
+ * System Peripherals
+ */
+#define AT91SAM9X5_BASE_MATRIX 0xffffde00
+#define AT9SAM9X5_BASE1_PMECC 0xffffe000
+#define AT91SAM9X5_BASE_PMERRLOC 0xffffe600
+#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800
+#define AT91SAM9X5_BASE_SMC 0xffffea00
+#define AT91SAM9X5_BASE_DMA0 0xffffec00
+#define AT91SAM9X5_BASE_DMA1 0xffffee00
+#define AT91SAM9X5_BASE_AIC 0xfffff000
+#define AT91SAM9X5_BASE_DBGU 0xfffff200
+#define AT91SAM9X5_BASE_PIOA 0xfffff400
+#define AT91SAM9X5_BASE_PIOB 0xfffff600
+#define AT91SAM9X5_BASE_PIOC 0xfffff800
+#define AT91SAM9X5_BASE_PIOD 0xfffffa00
+#define AT91SAM9X5_BASE_PMC 0xfffffc00
+#define AT91SAM9X5_BASE_RSTC 0xfffffe00
+#define AT91SAM9X5_BASE_SHDWC 0xfffffe10
+#define AT91SAM9X5_BASE_PIT 0xfffffe30
+#define AT91SAM9X5_BASE_WDT 0xfffffe40
+#define AT91SAM9X5_BASE_GPBR 0xfffffe60
+#define AT91SAM9X5_BASE_RTC 0xfffffeb0
+
+/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_MATRIX (0xffffde00 - AT91_BASE_SYS)
@@ -96,21 +120,16 @@
#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)
#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
#define AT91_SMC (0xffffea00 - AT91_BASE_SYS)
-#define AT91_DMA0 (0xffffec00 - AT91_BASE_SYS)
-#define AT91_DMA1 (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
-#define AT91_GPBR (0xfffffe60 - AT91_BASE_SYS)
-#define AT91_RTC (0xfffffeb0 - AT91_BASE_SYS)
-#define AT91_BASE_PIOA 0xfffff400
-#define AT91_BASE_PIOB 0xfffff600
-#define AT91_BASE_PIOC 0xfffff800
-#define AT91_BASE_PIOD 0xfffffa00
+#define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA
+#define AT91_BASE_PIOB AT91SAM9X5_BASE_PIOB
+#define AT91_BASE_PIOC AT91SAM9X5_BASE_PIOC
+#define AT91_BASE_PIOD AT91SAM9X5_BASE_PIOD
#define AT91_USART0 AT91SAM9X5_BASE_US0
#define AT91_USART1 AT91SAM9X5_BASE_US1
--
1.7.10.4
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH 07/13] at91: at91sam9: provide its own clkdev for pit
2012-12-28 19:16 ` [PATCH 01/13] at91: factorise dbgu address Jean-Christophe PLAGNIOL-VILLARD
` (4 preceding siblings ...)
2012-12-28 19:16 ` [PATCH 06/13] at91: sync with the kernel address base Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-28 19:16 ` Jean-Christophe PLAGNIOL-VILLARD
2012-12-28 19:16 ` [PATCH 08/13] at91: PIT: switch to platfrom_driver Jean-Christophe PLAGNIOL-VILLARD
` (5 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-28 19:16 UTC (permalink / raw)
To: barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/mach-at91/at91sam9260.c | 1 +
arch/arm/mach-at91/at91sam9261.c | 1 +
arch/arm/mach-at91/at91sam9263.c | 1 +
arch/arm/mach-at91/at91sam9g45.c | 1 +
arch/arm/mach-at91/at91sam9n12.c | 1 +
arch/arm/mach-at91/at91sam9x5.c | 1 +
6 files changed, 6 insertions(+)
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 6c741f8..fdda9c6 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -175,6 +175,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk),
CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk),
CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
+ CLKDEV_DEV_ID("at91-pit", &mck),
};
static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index b57e119..ac635d7 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -139,6 +139,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk),
CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk),
CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
+ CLKDEV_DEV_ID("at91-pit", &mck),
};
static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index a4387ee..84c986f 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -173,6 +173,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_DEV_ID("at91rm9200-gpio2", &pioCDE_clk),
CLKDEV_DEV_ID("at91rm9200-gpio3", &pioCDE_clk),
CLKDEV_DEV_ID("at91rm9200-gpio4", &pioCDE_clk),
+ CLKDEV_DEV_ID("at91-pit", &mck),
};
static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index c3a3158..0affc67 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -195,6 +195,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
CLKDEV_DEV_ID("at91rm9200-gpio3", &pioDE_clk),
CLKDEV_DEV_ID("at91rm9200-gpio4", &pioDE_clk),
+ CLKDEV_DEV_ID("at91-pit", &mck),
};
static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 3ddaa7d..f4a981e 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -154,6 +154,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_DEV_ID("at91sam9x5-gpio1", &pioAB_clk),
CLKDEV_DEV_ID("at91sam9x5-gpio2", &pioCD_clk),
CLKDEV_DEV_ID("at91sam9x5-gpio3", &pioCD_clk),
+ CLKDEV_DEV_ID("at91-pit", &mck),
};
static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index b4c582f..a6d2b9d 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -213,6 +213,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_DEV_ID("at91sam9x5-gpio1", &pioAB_clk),
CLKDEV_DEV_ID("at91sam9x5-gpio2", &pioCD_clk),
CLKDEV_DEV_ID("at91sam9x5-gpio3", &pioCD_clk),
+ CLKDEV_DEV_ID("at91-pit", &mck),
};
static struct clk_lookup usart_clocks_lookups[] = {
--
1.7.10.4
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH 08/13] at91: PIT: switch to platfrom_driver
2012-12-28 19:16 ` [PATCH 01/13] at91: factorise dbgu address Jean-Christophe PLAGNIOL-VILLARD
` (5 preceding siblings ...)
2012-12-28 19:16 ` [PATCH 07/13] at91: at91sam9: provide its own clkdev for pit Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-28 19:16 ` Jean-Christophe PLAGNIOL-VILLARD
2013-01-02 10:59 ` Sascha Hauer
2012-12-28 19:16 ` [PATCH 09/13] at91: autodetect the soc one time at postcore_initcall Jean-Christophe PLAGNIOL-VILLARD
` (4 subsequent siblings)
11 siblings, 1 reply; 19+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-28 19:16 UTC (permalink / raw)
To: barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/mach-at91/at91sam9260.c | 1 +
arch/arm/mach-at91/at91sam9261.c | 1 +
arch/arm/mach-at91/at91sam9263.c | 1 +
arch/arm/mach-at91/at91sam926x_time.c | 47 +++++++++++++++++++++----
arch/arm/mach-at91/at91sam9g45.c | 1 +
arch/arm/mach-at91/at91sam9n12.c | 1 +
arch/arm/mach-at91/at91sam9x5.c | 1 +
arch/arm/mach-at91/generic.h | 6 ++++
arch/arm/mach-at91/include/mach/at91_pit.h | 8 ++---
arch/arm/mach-at91/include/mach/at91sam9260.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9261.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9263.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9g45.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9n12.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9x5.h | 1 -
15 files changed, 56 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index fdda9c6..b76bfb2 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -239,6 +239,7 @@ static int at91sam9260_gpio_init(void)
at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
+ at91_add_pit(AT91SAM9260_BASE_PIT);
return 0;
}
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index ac635d7..b449236 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -231,6 +231,7 @@ static int at91sam9261_gpio_init(void)
at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
+ at91_add_pit(AT91SAM9261_BASE_PIT);
return 0;
}
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 84c986f..b1522ba 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -250,6 +250,7 @@ static int at91sam9263_gpio_init(void)
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_rm9200_gpio(3, AT91_BASE_PIOD);
at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
+ at91_add_pit(AT91SAM9263_BASE_PIT);
return 0;
}
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 1ce8d30..e18458a 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -30,15 +30,20 @@
#include <clock.h>
#include <asm/hardware.h>
#include <mach/at91_pit.h>
-#include <mach/at91_rstc.h>
#include <mach/io.h>
#include <io.h>
#include <linux/clk.h>
#include <linux/err.h>
+#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
+#define pit_write(reg, val) __raw_writel(val, pit_base + reg)
+#define pit_read(reg) __raw_readl(pit_base + reg)
+
+static __iomem void *pit_base;
+
uint64_t at91sam9_clocksource_read(void)
{
- return at91_sys_read(AT91_PIT_PIIR);
+ return pit_read(AT91_PIT_PIIR);
}
static struct clocksource cs = {
@@ -47,12 +52,30 @@ static struct clocksource cs = {
.shift = 10,
};
-static int clocksource_init (void)
+static void at91_pit_stop(void)
+{
+ /* Disable timer and irqs */
+ pit_write(AT91_PIT_MR, 0);
+
+ /* Clear any pending interrupts, wait for PIT to stop counting */
+ while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0);
+}
+
+static void at91sam926x_pit_reset(void)
+{
+ at91_pit_stop();
+
+ /* Start PIT but don't enable IRQ */
+ pit_write(AT91_PIT_MR, 0xfffff | AT91_PIT_PITEN);
+}
+
+static int at91_pit_probe(struct device_d *dev)
{
struct clk *clk;
u32 pit_rate;
+ int ret;
- clk = clk_get(NULL, "mck");
+ clk = clk_get(dev, NULL);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
dev_err(dev, "clock not found: %d\n", ret);
@@ -66,10 +89,11 @@ static int clocksource_init (void)
return ret;
}
+ pit_base = dev_request_mem_region(dev, 0);
+
pit_rate = clk_get_rate(clk) / 16;
- /* Enable PITC */
- at91_sys_write(AT91_PIT_MR, 0xfffff | AT91_PIT_PITEN);
+ at91sam926x_pit_reset();
cs.mult = clocksource_hz2mult(pit_rate, cs.shift);
@@ -78,4 +102,13 @@ static int clocksource_init (void)
return 0;
}
-core_initcall(clocksource_init);
+static struct driver_d at91_pit_driver = {
+ .name = "at91-pit",
+ .probe = at91_pit_probe,
+};
+
+static int at91_pit_init(void)
+{
+ return platform_driver_register(&at91_pit_driver);
+}
+postcore_initcall(at91_pit_init);
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 0affc67..7dcf93e 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -263,6 +263,7 @@ static int at91sam9g45_gpio_init(void)
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_rm9200_gpio(3, AT91_BASE_PIOD);
at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
+ at91_add_pit(AT91SAM9G45_BASE_PIT);
return 0;
}
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index f4a981e..3777f70 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -222,6 +222,7 @@ static int at91sam9n12_gpio_init(void)
at91_add_sam9x5_gpio(1, AT91_BASE_PIOB);
at91_add_sam9x5_gpio(2, AT91_BASE_PIOC);
at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
+ at91_add_pit(AT91SAM9N12_BASE_PIT);
return 0;
}
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index a6d2b9d..306d3f3 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -307,6 +307,7 @@ static int at91sam9x5_gpio_init(void)
at91_add_sam9x5_gpio(1, AT91_BASE_PIOB);
at91_add_sam9x5_gpio(2, AT91_BASE_PIOC);
at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
+ at91_add_pit(AT91SAM9X5_BASE_PIT);
return 0;
}
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 57f2a84..490cf3c 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -22,3 +22,9 @@ static inline struct device_d *at91_add_sam9x5_gpio(int id, resource_size_t star
return add_generic_device("at91sam9x5-gpio", id, NULL, start, 512,
IORESOURCE_MEM, NULL);
}
+
+static inline struct device_d *at91_add_pit(resource_size_t start)
+{
+ return add_generic_device("at91-pit", DEVICE_ID_SINGLE, NULL, start, 16,
+ IORESOURCE_MEM, NULL);
+}
diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h
index 94dd242..8581efa 100644
--- a/arch/arm/mach-at91/include/mach/at91_pit.h
+++ b/arch/arm/mach-at91/include/mach/at91_pit.h
@@ -16,16 +16,16 @@
#ifndef AT91_PIT_H
#define AT91_PIT_H
-#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
+#define AT91_PIT_MR 0x00 /* Mode Register */
#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
-#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
+#define AT91_PIT_SR 0x04 /* Status Register */
#define AT91_PIT_PITS (1 << 0) /* Timer Status */
-#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
-#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
+#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
+#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 3dad806..5d1b376 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -105,7 +105,6 @@
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 591ae29..1469f7e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -91,7 +91,6 @@
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index a0ed231..a8c067a 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -109,7 +109,6 @@
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_BASE_PIOA AT91SAM9263_BASE_PIOA
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 961a70f..85ed129 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -120,7 +120,6 @@
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
index 706005c..59d7030 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -116,7 +116,6 @@
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
-#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index b47e3cb..63a5138 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -123,7 +123,6 @@
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
-#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
#define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA
--
1.7.10.4
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^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 08/13] at91: PIT: switch to platfrom_driver
2012-12-28 19:16 ` [PATCH 08/13] at91: PIT: switch to platfrom_driver Jean-Christophe PLAGNIOL-VILLARD
@ 2013-01-02 10:59 ` Sascha Hauer
0 siblings, 0 replies; 19+ messages in thread
From: Sascha Hauer @ 2013-01-02 10:59 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
subject: s/platfrom_driver/platform_driver/
Sascha
On Fri, Dec 28, 2012 at 08:16:09PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
> arch/arm/mach-at91/at91sam9260.c | 1 +
> arch/arm/mach-at91/at91sam9261.c | 1 +
> arch/arm/mach-at91/at91sam9263.c | 1 +
> arch/arm/mach-at91/at91sam926x_time.c | 47 +++++++++++++++++++++----
> arch/arm/mach-at91/at91sam9g45.c | 1 +
> arch/arm/mach-at91/at91sam9n12.c | 1 +
> arch/arm/mach-at91/at91sam9x5.c | 1 +
> arch/arm/mach-at91/generic.h | 6 ++++
> arch/arm/mach-at91/include/mach/at91_pit.h | 8 ++---
> arch/arm/mach-at91/include/mach/at91sam9260.h | 1 -
> arch/arm/mach-at91/include/mach/at91sam9261.h | 1 -
> arch/arm/mach-at91/include/mach/at91sam9263.h | 1 -
> arch/arm/mach-at91/include/mach/at91sam9g45.h | 1 -
> arch/arm/mach-at91/include/mach/at91sam9n12.h | 1 -
> arch/arm/mach-at91/include/mach/at91sam9x5.h | 1 -
> 15 files changed, 56 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
> index fdda9c6..b76bfb2 100644
> --- a/arch/arm/mach-at91/at91sam9260.c
> +++ b/arch/arm/mach-at91/at91sam9260.c
> @@ -239,6 +239,7 @@ static int at91sam9260_gpio_init(void)
> at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
> at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
> at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
> + at91_add_pit(AT91SAM9260_BASE_PIT);
>
> return 0;
> }
> diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
> index ac635d7..b449236 100644
> --- a/arch/arm/mach-at91/at91sam9261.c
> +++ b/arch/arm/mach-at91/at91sam9261.c
> @@ -231,6 +231,7 @@ static int at91sam9261_gpio_init(void)
> at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
> at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
> at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
> + at91_add_pit(AT91SAM9261_BASE_PIT);
>
> return 0;
> }
> diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
> index 84c986f..b1522ba 100644
> --- a/arch/arm/mach-at91/at91sam9263.c
> +++ b/arch/arm/mach-at91/at91sam9263.c
> @@ -250,6 +250,7 @@ static int at91sam9263_gpio_init(void)
> at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
> at91_add_rm9200_gpio(3, AT91_BASE_PIOD);
> at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
> + at91_add_pit(AT91SAM9263_BASE_PIT);
>
> return 0;
> }
> diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
> index 1ce8d30..e18458a 100644
> --- a/arch/arm/mach-at91/at91sam926x_time.c
> +++ b/arch/arm/mach-at91/at91sam926x_time.c
> @@ -30,15 +30,20 @@
> #include <clock.h>
> #include <asm/hardware.h>
> #include <mach/at91_pit.h>
> -#include <mach/at91_rstc.h>
> #include <mach/io.h>
> #include <io.h>
> #include <linux/clk.h>
> #include <linux/err.h>
>
> +#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
> +#define pit_write(reg, val) __raw_writel(val, pit_base + reg)
> +#define pit_read(reg) __raw_readl(pit_base + reg)
> +
> +static __iomem void *pit_base;
> +
> uint64_t at91sam9_clocksource_read(void)
> {
> - return at91_sys_read(AT91_PIT_PIIR);
> + return pit_read(AT91_PIT_PIIR);
> }
>
> static struct clocksource cs = {
> @@ -47,12 +52,30 @@ static struct clocksource cs = {
> .shift = 10,
> };
>
> -static int clocksource_init (void)
> +static void at91_pit_stop(void)
> +{
> + /* Disable timer and irqs */
> + pit_write(AT91_PIT_MR, 0);
> +
> + /* Clear any pending interrupts, wait for PIT to stop counting */
> + while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0);
> +}
> +
> +static void at91sam926x_pit_reset(void)
> +{
> + at91_pit_stop();
> +
> + /* Start PIT but don't enable IRQ */
> + pit_write(AT91_PIT_MR, 0xfffff | AT91_PIT_PITEN);
> +}
> +
> +static int at91_pit_probe(struct device_d *dev)
> {
> struct clk *clk;
> u32 pit_rate;
> + int ret;
>
> - clk = clk_get(NULL, "mck");
> + clk = clk_get(dev, NULL);
> if (IS_ERR(clk)) {
> ret = PTR_ERR(clk);
> dev_err(dev, "clock not found: %d\n", ret);
> @@ -66,10 +89,11 @@ static int clocksource_init (void)
> return ret;
> }
>
> + pit_base = dev_request_mem_region(dev, 0);
> +
> pit_rate = clk_get_rate(clk) / 16;
>
> - /* Enable PITC */
> - at91_sys_write(AT91_PIT_MR, 0xfffff | AT91_PIT_PITEN);
> + at91sam926x_pit_reset();
>
> cs.mult = clocksource_hz2mult(pit_rate, cs.shift);
>
> @@ -78,4 +102,13 @@ static int clocksource_init (void)
> return 0;
> }
>
> -core_initcall(clocksource_init);
> +static struct driver_d at91_pit_driver = {
> + .name = "at91-pit",
> + .probe = at91_pit_probe,
> +};
> +
> +static int at91_pit_init(void)
> +{
> + return platform_driver_register(&at91_pit_driver);
> +}
> +postcore_initcall(at91_pit_init);
> diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
> index 0affc67..7dcf93e 100644
> --- a/arch/arm/mach-at91/at91sam9g45.c
> +++ b/arch/arm/mach-at91/at91sam9g45.c
> @@ -263,6 +263,7 @@ static int at91sam9g45_gpio_init(void)
> at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
> at91_add_rm9200_gpio(3, AT91_BASE_PIOD);
> at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
> + at91_add_pit(AT91SAM9G45_BASE_PIT);
>
> return 0;
> }
> diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
> index f4a981e..3777f70 100644
> --- a/arch/arm/mach-at91/at91sam9n12.c
> +++ b/arch/arm/mach-at91/at91sam9n12.c
> @@ -222,6 +222,7 @@ static int at91sam9n12_gpio_init(void)
> at91_add_sam9x5_gpio(1, AT91_BASE_PIOB);
> at91_add_sam9x5_gpio(2, AT91_BASE_PIOC);
> at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
> + at91_add_pit(AT91SAM9N12_BASE_PIT);
>
> return 0;
> }
> diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
> index a6d2b9d..306d3f3 100644
> --- a/arch/arm/mach-at91/at91sam9x5.c
> +++ b/arch/arm/mach-at91/at91sam9x5.c
> @@ -307,6 +307,7 @@ static int at91sam9x5_gpio_init(void)
> at91_add_sam9x5_gpio(1, AT91_BASE_PIOB);
> at91_add_sam9x5_gpio(2, AT91_BASE_PIOC);
> at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
> + at91_add_pit(AT91SAM9X5_BASE_PIT);
>
> return 0;
> }
> diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
> index 57f2a84..490cf3c 100644
> --- a/arch/arm/mach-at91/generic.h
> +++ b/arch/arm/mach-at91/generic.h
> @@ -22,3 +22,9 @@ static inline struct device_d *at91_add_sam9x5_gpio(int id, resource_size_t star
> return add_generic_device("at91sam9x5-gpio", id, NULL, start, 512,
> IORESOURCE_MEM, NULL);
> }
> +
> +static inline struct device_d *at91_add_pit(resource_size_t start)
> +{
> + return add_generic_device("at91-pit", DEVICE_ID_SINGLE, NULL, start, 16,
> + IORESOURCE_MEM, NULL);
> +}
> diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h
> index 94dd242..8581efa 100644
> --- a/arch/arm/mach-at91/include/mach/at91_pit.h
> +++ b/arch/arm/mach-at91/include/mach/at91_pit.h
> @@ -16,16 +16,16 @@
> #ifndef AT91_PIT_H
> #define AT91_PIT_H
>
> -#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
> +#define AT91_PIT_MR 0x00 /* Mode Register */
> #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
> #define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
> #define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
>
> -#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
> +#define AT91_PIT_SR 0x04 /* Status Register */
> #define AT91_PIT_PITS (1 << 0) /* Timer Status */
>
> -#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
> -#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
> +#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
> +#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
> #define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
> #define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
>
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
> index 3dad806..5d1b376 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9260.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
> @@ -105,7 +105,6 @@
> #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
> -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
> #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
>
> #define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
> index 591ae29..1469f7e 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9261.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
> @@ -91,7 +91,6 @@
> #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
> -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
> #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
>
> #define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
> index a0ed231..a8c067a 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9263.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
> @@ -109,7 +109,6 @@
> #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
> -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
> #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
>
> #define AT91_BASE_PIOA AT91SAM9263_BASE_PIOA
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
> index 961a70f..85ed129 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
> @@ -120,7 +120,6 @@
> #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
> -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
> #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
>
> #define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
> index 706005c..59d7030 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
> @@ -116,7 +116,6 @@
> #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
> -#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
> #define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
>
> #define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> index b47e3cb..63a5138 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> @@ -123,7 +123,6 @@
> #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
> -#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
> #define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
>
> #define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA
> --
> 1.7.10.4
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 09/13] at91: autodetect the soc one time at postcore_initcall
2012-12-28 19:16 ` [PATCH 01/13] at91: factorise dbgu address Jean-Christophe PLAGNIOL-VILLARD
` (6 preceding siblings ...)
2012-12-28 19:16 ` [PATCH 08/13] at91: PIT: switch to platfrom_driver Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-28 19:16 ` Jean-Christophe PLAGNIOL-VILLARD
2012-12-28 19:16 ` [PATCH 10/13] at91: SMC: switch to platfrom_driver Jean-Christophe PLAGNIOL-VILLARD
` (3 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-28 19:16 UTC (permalink / raw)
To: barebox
and then register a device
The code is take from linux
drop AT91_BASE_SYS for dbgu
factorise the soc type in the Kconfig but keep the ARCH_ so far
as the device code have the same function accross soc which for now does not
allow us to compile soc together
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/mach-at91/Kconfig | 99 ++++++++----
arch/arm/mach-at91/Makefile | 2 +-
arch/arm/mach-at91/at91rm9200.c | 17 +-
arch/arm/mach-at91/at91sam9260.c | 17 +-
arch/arm/mach-at91/at91sam9261.c | 17 +-
arch/arm/mach-at91/at91sam9263.c | 17 +-
arch/arm/mach-at91/at91sam9g45.c | 18 +--
arch/arm/mach-at91/at91sam9n12.c | 17 +-
arch/arm/mach-at91/at91sam9x5.c | 17 +-
arch/arm/mach-at91/include/mach/at91_dbgu.h | 26 +--
arch/arm/mach-at91/include/mach/cpu.h | 190 +++++++++++-----------
arch/arm/mach-at91/setup.c | 226 +++++++++++++++++++++++++++
arch/arm/mach-at91/soc.h | 66 ++++++++
13 files changed, 515 insertions(+), 214 deletions(-)
create mode 100644 arch/arm/mach-at91/setup.c
create mode 100644 arch/arm/mach-at91/soc.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0ab7e7e..d470e5c 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -49,69 +49,108 @@ config AT91SAM9G45_RESET
comment "Atmel AT91 System-on-Chip"
-choice
- prompt "Atmel AT91 Processor"
-
-config ARCH_AT91RM9200
- bool "AT91RM9200"
+config SOC_AT91RM9200
+ bool
select CPU_ARM920T
select HAVE_AT91_DBGU0
select HAS_AT91_ETHER
select MACH_HAS_LOWLEVEL_INIT
- select MACH_DO_LOWLEVEL_INIT
-config ARCH_AT91SAM9260
- bool "AT91SAM9260"
+config SOC_AT91SAM9260
+ bool
select CPU_ARM926T
select HAVE_AT91_DBGU0
select HAS_MACB
select AT91SAM9_RESET
+ help
+ Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
+ or AT91SAM9G20 SoC.
-config ARCH_AT91SAM9261
- bool "AT91SAM9261"
+config SOC_AT91SAM9261
+ bool
select CPU_ARM926T
select HAVE_AT91_DBGU0
select AT91SAM9_RESET
+ help
+ Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC.
-config ARCH_AT91SAM9263
- bool "AT91SAM9263"
+config SOC_AT91SAM9263
+ bool
select CPU_ARM926T
select HAVE_AT91_DBGU1
select HAS_MACB
select AT91SAM9_RESET
-config ARCH_AT91SAM9G10
- bool "AT91SAM9G10"
+config SOC_AT91SAM9G45
+ bool
select CPU_ARM926T
- select HAVE_AT91_DBGU0
- select AT91SAM9_RESET
+ select HAVE_AT91_DBGU1
+ select HAS_MACB
+ select AT91SAM9G45_RESET
+ help
+ Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
+ This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
-config ARCH_AT91SAM9G20
- bool "AT91SAM9G20"
+config SOC_AT91SAM9X5
+ bool
select CPU_ARM926T
select HAVE_AT91_DBGU0
select HAS_MACB
- select AT91SAM9_RESET
+ select AT91SAM9G45_RESET
+ help
+ Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
+ This means that your SAM9 name finishes with a '5' (except if it is
+ AT91SAM9G45!).
+ This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35
+ and AT91SAM9X35.
-config ARCH_AT91SAM9G45
- bool "AT91SAM9G45 or AT91SAM9M10"
+config SOC_AT91SAM9N12
+ bool
select CPU_ARM926T
- select HAVE_AT91_DBGU1
- select HAS_MACB
+ select HAVE_AT91_DBGU0
select AT91SAM9G45_RESET
+ help
+ Select this if you are using Atmel's AT91SAM9N12 SoC.
+
+choice
+ prompt "Atmel AT91 Processor"
+
+config ARCH_AT91RM9200
+ bool "AT91RM9200"
+ select MACH_DO_LOWLEVEL_INIT
+ select SOC_AT91RM9200
+
+config ARCH_AT91SAM9260
+ bool "AT91SAM9260"
+ select SOC_AT91SAM9260
+
+config ARCH_AT91SAM9261
+ bool "AT91SAM9261"
+ select SOC_AT91SAM9261
+
+config ARCH_AT91SAM9263
+ bool "AT91SAM9263"
+ select SOC_AT91SAM9263
+
+config ARCH_AT91SAM9G10
+ bool "AT91SAM9G10"
+ select SOC_AT91SAM9261
+
+config ARCH_AT91SAM9G20
+ bool "AT91SAM9G20"
+ select SOC_AT91SAM9260
+
+config ARCH_AT91SAM9G45
+ bool "AT91SAM9G45 or AT91SAM9M10"
+ select SOC_AT91SAM9G45
config ARCH_AT91SAM9X5
bool "AT91SAM9X5"
- select CPU_ARM926T
- select HAVE_AT91_DBGU0
- select HAS_MACB
- select AT91SAM9G45_RESET
+ select SOC_AT91SAM9X5
config ARCH_AT91SAM9N12
bool "AT91SAM9N12"
- select CPU_ARM926T
- select HAVE_AT91_DBGU0
- select AT91SAM9G45_RESET
+ select SOC_AT91SAM9N12
endchoice
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 7a1e506..865988e 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,4 +1,4 @@
-obj-y += clock.o gpio.o
+obj-y += setup.o clock.o gpio.o
lowlevel_init-y = at91sam926x_lowlevel_init.o
lowlevel_init-$(CONFIG_ARCH_AT91RM9200) = at91rm9200_lowlevel_init.o
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index e298c97..d3aedea 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -4,6 +4,7 @@
#include <asm/hardware.h>
#include <mach/at91_pmc.h>
+#include "soc.h"
#include "clock.h"
#include "generic.h"
@@ -222,27 +223,21 @@ static void __init at91rm9200_register_clocks(void)
/* --------------------------------------------------------------------
* AT91RM9200 processor initialization
* -------------------------------------------------------------------- */
-static int __init at91rm9200_initialize(void)
+static void __init at91rm9200_initialize(void)
{
-
/* Init clock subsystem */
at91_clock_init(AT91_MAIN_CLOCK);
/* Register the processor-specific clocks */
at91rm9200_register_clocks();
- return 0;
-}
-core_initcall(at91rm9200_initialize);
-
-static int at91rm9200_gpio_init(void)
-{
/* Register GPIO subsystem */
at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_rm9200_gpio(3, AT91_BASE_PIOD);
-
- return 0;
}
-postcore_initcall(at91rm9200_gpio_init);
+
+AT91_SOC_START(rm9200)
+ .init = at91rm9200_initialize,
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index b76bfb2..4c76d94 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -4,6 +4,7 @@
#include <asm/hardware.h>
#include <mach/at91_pmc.h>
+#include "soc.h"
#include "generic.h"
#include "clock.h"
@@ -221,7 +222,7 @@ static void __init at91sam9260_register_clocks(void)
clk_register(&pck1);
}
-static int at91sam9260_initialize(void)
+static void at91sam9260_initialize(void)
{
/* Init clock subsystem */
at91_clock_init(AT91_MAIN_CLOCK);
@@ -229,18 +230,14 @@ static int at91sam9260_initialize(void)
/* Register the processor-specific clocks */
at91sam9260_register_clocks();
- return 0;
-}
-core_initcall(at91sam9260_initialize);
-
-static int at91sam9260_gpio_init(void)
-{
/* Register GPIO subsystem */
at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
- at91_add_pit(AT91SAM9260_BASE_PIT);
- return 0;
+ at91_add_pit(AT91SAM9260_BASE_PIT);
}
-postcore_initcall(at91sam9260_gpio_init);
+
+AT91_SOC_START(sam9260)
+ .init = at91sam9260_initialize,
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index b449236..1efbbee 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -4,6 +4,7 @@
#include <asm/hardware.h>
#include <mach/at91_pmc.h>
+#include "soc.h"
#include "generic.h"
#include "clock.h"
@@ -213,7 +214,7 @@ static void at91sam9261_register_clocks(void)
clk_register(&hck1);
}
-static int at91sam9261_initialize(void)
+static void at91sam9261_initialize(void)
{
/* Init clock subsystem */
at91_clock_init(AT91_MAIN_CLOCK);
@@ -221,18 +222,14 @@ static int at91sam9261_initialize(void)
/* Register the processor-specific clocks */
at91sam9261_register_clocks();
- return 0;
-}
-core_initcall(at91sam9261_initialize);
-
-static int at91sam9261_gpio_init(void)
-{
/* Register GPIO subsystem */
at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
- at91_add_pit(AT91SAM9261_BASE_PIT);
- return 0;
+ at91_add_pit(AT91SAM9261_BASE_PIT);
}
-postcore_initcall(at91sam9261_gpio_init);
+
+AT91_SOC_START(sam9261)
+ .init = at91sam9261_initialize,
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index b1522ba..e1fbe6f 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -4,6 +4,7 @@
#include <asm/hardware.h>
#include <mach/at91_pmc.h>
+#include "soc.h"
#include "clock.h"
#include "generic.h"
@@ -230,7 +231,7 @@ static void __init at91sam9263_register_clocks(void)
clk_register(&pck3);
}
-static int at91sam9263_initialize(void)
+static void at91sam9263_initialize(void)
{
/* Init clock subsystem */
at91_clock_init(AT91_MAIN_CLOCK);
@@ -238,20 +239,16 @@ static int at91sam9263_initialize(void)
/* Register the processor-specific clocks */
at91sam9263_register_clocks();
- return 0;
-}
-core_initcall(at91sam9263_initialize);
-
-static int at91sam9263_gpio_init(void)
-{
/* Register GPIO subsystem */
at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_rm9200_gpio(3, AT91_BASE_PIOD);
at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
- at91_add_pit(AT91SAM9263_BASE_PIT);
- return 0;
+ at91_add_pit(AT91SAM9263_BASE_PIT);
}
-postcore_initcall(at91sam9263_gpio_init);
+
+AT91_SOC_START(sam9263)
+ .init = at91sam9263_initialize,
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 7dcf93e..94fee59 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -6,6 +6,7 @@
#include <mach/at91_pmc.h>
#include <mach/cpu.h>
+#include "soc.h"
#include "generic.h"
#include "clock.h"
@@ -242,7 +243,7 @@ static void __init at91sam9g45_register_clocks(void)
clk_register(&pck1);
}
-static int at91sam9g45_initialize(void)
+static void at91sam9g45_initialize(void)
{
/* Init clock subsystem */
at91_clock_init(AT91_MAIN_CLOCK);
@@ -250,21 +251,16 @@ static int at91sam9g45_initialize(void)
/* Register the processor-specific clocks */
at91sam9g45_register_clocks();
- return 0;
-}
-
-core_initcall(at91sam9g45_initialize);
-
-static int at91sam9g45_gpio_init(void)
-{
/* Register GPIO subsystem */
at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_rm9200_gpio(3, AT91_BASE_PIOD);
at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
- at91_add_pit(AT91SAM9G45_BASE_PIT);
- return 0;
+ at91_add_pit(AT91SAM9G45_BASE_PIT);
}
-postcore_initcall(at91sam9g45_gpio_init);
+
+AT91_SOC_START(sam9g45)
+ .init = at91sam9g45_initialize,
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 3777f70..d1b7ce1 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -6,6 +6,7 @@
#include <mach/io.h>
#include <mach/cpu.h>
+#include "soc.h"
#include "generic.h"
#include "clock.h"
@@ -203,7 +204,7 @@ static void __init at91sam9n12_register_clocks(void)
* AT91SAM9N12 processor initialization
* -------------------------------------------------------------------- */
-static int at91sam9n12_initialize(void)
+static void at91sam9n12_initialize(void)
{
/* Init clock subsystem */
at91_clock_init(AT91_MAIN_CLOCK);
@@ -211,19 +212,15 @@ static int at91sam9n12_initialize(void)
/* Register the processor-specific clocks */
at91sam9n12_register_clocks();
- return 0;
-}
-core_initcall(at91sam9n12_initialize);
-
-static int at91sam9n12_gpio_init(void)
-{
/* Register GPIO subsystem */
at91_add_sam9x5_gpio(0, AT91_BASE_PIOA);
at91_add_sam9x5_gpio(1, AT91_BASE_PIOB);
at91_add_sam9x5_gpio(2, AT91_BASE_PIOC);
at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
- at91_add_pit(AT91SAM9N12_BASE_PIT);
- return 0;
+ at91_add_pit(AT91SAM9N12_BASE_PIT);
}
-postcore_initcall(at91sam9n12_gpio_init);
+
+AT91_SOC_START(sam9n12)
+ .init = at91sam9n12_initialize,
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 306d3f3..7b58e12 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -6,6 +6,7 @@
#include <mach/io.h>
#include <mach/cpu.h>
+#include "soc.h"
#include "generic.h"
#include "clock.h"
@@ -288,7 +289,7 @@ static void __init at91sam9x5_register_clocks(void)
* AT91SAM9x5 processor initialization
* -------------------------------------------------------------------- */
-static int at91sam9x5_initialize(void)
+static void at91sam9x5_initialize(void)
{
/* Init clock subsystem */
at91_clock_init(AT91_MAIN_CLOCK);
@@ -296,19 +297,15 @@ static int at91sam9x5_initialize(void)
/* Register the processor-specific clocks */
at91sam9x5_register_clocks();
- return 0;
-}
-core_initcall(at91sam9x5_initialize);
-
-static int at91sam9x5_gpio_init(void)
-{
/* Register GPIO subsystem */
at91_add_sam9x5_gpio(0, AT91_BASE_PIOA);
at91_add_sam9x5_gpio(1, AT91_BASE_PIOB);
at91_add_sam9x5_gpio(2, AT91_BASE_PIOC);
at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
- at91_add_pit(AT91SAM9X5_BASE_PIT);
- return 0;
+ at91_add_pit(AT91SAM9X5_BASE_PIT);
}
-postcore_initcall(at91sam9x5_gpio_init);
+
+AT91_SOC_START(sam9x5)
+ .init = at91sam9x5_initialize,
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
index 6dcaa77..3b59485 100644
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h
@@ -16,22 +16,22 @@
#ifndef AT91_DBGU_H
#define AT91_DBGU_H
-#ifdef AT91_DBGU
-#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
-#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
-#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
+#if !defined(CONFIG_ARCH_AT91X40)
+#define AT91_DBGU_CR (0x00) /* Control Register */
+#define AT91_DBGU_MR (0x04) /* Mode Register */
+#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
-#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
-#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
-#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
-#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
-#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
-#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
+#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */
+#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */
+#define AT91_DBGU_SR (0x14) /* Status Register */
+#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */
+#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
+#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */
-#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
-#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
-#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */
+#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */
+#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */
+#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */
#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
#endif /* AT91_DBGU */
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 636fe03..b6504c1 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -1,7 +1,8 @@
/*
* arch/arm/mach-at91/include/mach/cpu.h
*
- * Copyright (C) 2006 SAN People
+ * Copyright (C) 2006 SAN People
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -10,12 +11,8 @@
*
*/
-#ifndef __ASM_ARCH_CPU_H
-#define __ASM_ARCH_CPU_H
-
-#include <mach/hardware.h>
-#include <mach/at91_dbgu.h>
-
+#ifndef __MACH_CPU_H__
+#define __MACH_CPU_H__
#define ARCH_ID_AT91RM9200 0x09290780
#define ARCH_ID_AT91SAM9260 0x019803a0
@@ -29,29 +26,16 @@
#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
#define ARCH_ID_AT91SAM9X5 0x819a05a0
#define ARCH_ID_AT91SAM9N12 0x819a07a0
-#define ARCH_ID_AT91CAP9 0x039A03A0
#define ARCH_ID_AT91SAM9XE128 0x329973a0
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
-#define ARCH_ID_AT572D940HF 0x0e0303e0
-
#define ARCH_ID_AT91M40800 0x14080044
#define ARCH_ID_AT91R40807 0x44080746
#define ARCH_ID_AT91M40807 0x14080745
#define ARCH_ID_AT91R40008 0x44000840
-static inline unsigned long at91_cpu_identify(void)
-{
- return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
-}
-
-static inline unsigned long at91_cpu_fully_identify(void)
-{
- return at91_sys_read(AT91_DBGU_CIDR);
-}
-
#define ARCH_EXID_AT91SAM9M11 0x00000001
#define ARCH_EXID_AT91SAM9M10 0x00000002
#define ARCH_EXID_AT91SAM9G46 0x00000003
@@ -63,86 +47,116 @@ static inline unsigned long at91_cpu_fully_identify(void)
#define ARCH_EXID_AT91SAM9G25 0x00000003
#define ARCH_EXID_AT91SAM9X25 0x00000004
-static inline unsigned long at91_exid_identify(void)
-{
- return at91_sys_read(AT91_DBGU_EXID);
-}
-
-
#define ARCH_FAMILY_AT91X92 0x09200000
#define ARCH_FAMILY_AT91SAM9 0x01900000
#define ARCH_FAMILY_AT91SAM9XE 0x02900000
-static inline unsigned long at91_arch_identify(void)
-{
- return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH);
-}
+/* RM9200 type */
+#define ARCH_REVISON_9200_BGA (0 << 0)
+#define ARCH_REVISON_9200_PQFP (1 << 0)
+
+#ifndef __ASSEMBLY__
+enum at91_soc_type {
+ /* 920T */
+ AT91_SOC_RM9200,
+
+ /* SAM92xx */
+ AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
+
+ /* SAM9Gxx */
+ AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45,
+
+ /* SAM9RL */
+ AT91_SOC_SAM9RL,
+
+ /* SAM9X5 */
+ AT91_SOC_SAM9X5,
+
+ /* SAM9N12 */
+ AT91_SOC_SAM9N12,
-#ifdef CONFIG_ARCH_AT91CAP9
-#include <mach/at91_pmc.h>
+ /* Unknown type */
+ AT91_SOC_NONE
+};
-#define ARCH_REVISION_CAP9_B 0x399
-#define ARCH_REVISION_CAP9_C 0x601
+enum at91_soc_subtype {
+ /* RM9200 */
+ AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
-static inline unsigned long at91cap9_rev_identify(void)
+ /* SAM9260 */
+ AT91_SOC_SAM9XE,
+
+ /* SAM9G45 */
+ AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11,
+
+ /* SAM9X5 */
+ AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
+ AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
+
+ /* Unknown subtype */
+ AT91_SOC_SUBTYPE_NONE
+};
+
+struct at91_socinfo {
+ unsigned int type, subtype;
+ unsigned int cidr, exid;
+};
+
+extern struct at91_socinfo at91_soc_initdata;
+const char *at91_get_soc_type(struct at91_socinfo *c);
+const char *at91_get_soc_subtype(struct at91_socinfo *c);
+
+static inline int at91_soc_is_detected(void)
{
- return (at91_pmc_read(AT91_PMC_VER));
+ return at91_soc_initdata.type != AT91_SOC_NONE;
}
-#endif
-#ifdef CONFIG_ARCH_AT91RM9200
-#define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200)
+#ifdef CONFIG_SOC_AT91RM9200
+#define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200)
+#define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA)
+#define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP)
#else
#define cpu_is_at91rm9200() (0)
+#define cpu_is_at91rm9200_bga() (0)
+#define cpu_is_at91rm9200_pqfp() (0)
#endif
-#ifdef CONFIG_ARCH_AT91SAM9260
-#define cpu_is_at91sam9xe() (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE)
-#define cpu_is_at91sam9260() ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) || cpu_is_at91sam9xe())
+#ifdef CONFIG_SOC_AT91SAM9260
+#define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE)
+#define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260)
+#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20)
#else
#define cpu_is_at91sam9xe() (0)
#define cpu_is_at91sam9260() (0)
-#endif
-
-#ifdef CONFIG_ARCH_AT91SAM9G20
-#define cpu_is_at91sam9g20() (at91_cpu_identify() == ARCH_ID_AT91SAM9G20)
-#else
#define cpu_is_at91sam9g20() (0)
#endif
-#ifdef CONFIG_ARCH_AT91SAM9261
-#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
+#ifdef CONFIG_SOC_AT91SAM9261
+#define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261)
+#define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10)
#else
#define cpu_is_at91sam9261() (0)
-#endif
-
-#ifdef CONFIG_ARCH_AT91SAM9G10
-#define cpu_is_at91sam9g10() ((at91_cpu_identify() & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10)
-#else
#define cpu_is_at91sam9g10() (0)
#endif
-#ifdef CONFIG_ARCH_AT91SAM9263
-#define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263)
+#ifdef CONFIG_SOC_AT91SAM9263
+#define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263)
#else
#define cpu_is_at91sam9263() (0)
#endif
-#ifdef CONFIG_ARCH_AT91SAM9RL
-#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64)
+#ifdef CONFIG_SOC_AT91SAM9RL
+#define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL)
#else
#define cpu_is_at91sam9rl() (0)
#endif
-#ifdef CONFIG_ARCH_AT91SAM9G45
-#define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
-#define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES)
-#define cpu_is_at91sam9m10() (cpu_is_at91sam9g45() && \
- (at91_exid_identify() == ARCH_EXID_AT91SAM9M10))
-#define cpu_is_at91sam9m46() (cpu_is_at91sam9g45() && \
- (at91_exid_identify() == ARCH_EXID_AT91SAM9G46))
-#define cpu_is_at91sam9m11() (cpu_is_at91sam9g45() && \
- (at91_exid_identify() == ARCH_EXID_AT91SAM9M11))
+#ifdef CONFIG_SOC_AT91SAM9G45
+#define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45)
+#define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES)
+#define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10)
+#define cpu_is_at91sam9g46() (at91_soc_initdata.subtype == AT91_SOC_SAM9G46)
+#define cpu_is_at91sam9m11() (at91_soc_initdata.subtype == AT91_SOC_SAM9M11)
#else
#define cpu_is_at91sam9g45() (0)
#define cpu_is_at91sam9g45es() (0)
@@ -151,18 +165,13 @@ static inline unsigned long at91cap9_rev_identify(void)
#define cpu_is_at91sam9m11() (0)
#endif
-#ifdef CONFIG_ARCH_AT91SAM9X5
-#define cpu_is_at91sam9x5() (at91_cpu_identify() == ARCH_ID_AT91SAM9X5)
-#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \
- (at91_exid_identify() == ARCH_EXID_AT91SAM9G15))
-#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \
- (at91_exid_identify() == ARCH_EXID_AT91SAM9G35))
-#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \
- (at91_exid_identify() == ARCH_EXID_AT91SAM9X35))
-#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \
- (at91_exid_identify() == ARCH_EXID_AT91SAM9G25))
-#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \
- (at91_exid_identify() == ARCH_EXID_AT91SAM9X25))
+#ifdef CONFIG_SOC_AT91SAM9X5
+#define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5)
+#define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15)
+#define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35)
+#define cpu_is_at91sam9x35() (at91_soc_initdata.subtype == AT91_SOC_SAM9X35)
+#define cpu_is_at91sam9g25() (at91_soc_initdata.subtype == AT91_SOC_SAM9G25)
+#define cpu_is_at91sam9x25() (at91_soc_initdata.subtype == AT91_SOC_SAM9X25)
#else
#define cpu_is_at91sam9x5() (0)
#define cpu_is_at91sam9g15() (0)
@@ -172,32 +181,17 @@ static inline unsigned long at91cap9_rev_identify(void)
#define cpu_is_at91sam9x25() (0)
#endif
-#ifdef CONFIG_ARCH_AT91SAM9N12
-#define cpu_is_at91sam9n12() (at91_cpu_identify() == ARCH_ID_AT91SAM9N12)
+#ifdef CONFIG_SOC_AT91SAM9N12
+#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12)
#else
#define cpu_is_at91sam9n12() (0)
#endif
-#ifdef CONFIG_ARCH_AT91CAP9
-#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
-#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B)
-#define cpu_is_at91cap9_revC() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_C)
-#else
-#define cpu_is_at91cap9() (0)
-#define cpu_is_at91cap9_revB() (0)
-#define cpu_is_at91cap9_revC() (0)
-#endif
-
-#ifdef CONFIG_ARCH_AT572D940HF
-#define cpu_is_at572d940hf() (at91_cpu_identify() == ARCH_ID_AT572D940HF)
-#else
-#define cpu_is_at572d940hf() (0)
-#endif
-
/*
* Since this is ARM, we will never run on any AVR32 CPU. But these
* definitions may reduce clutter in common drivers.
*/
#define cpu_is_at32ap7000() (0)
+#endif /* __ASSEMBLY__ */
-#endif
+#endif /* __MACH_CPU_H__ */
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
new file mode 100644
index 0000000..9b73bcf
--- /dev/null
+++ b/arch/arm/mach-at91/setup.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright (C) 2007 Atmel Corporation.
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <io.h>
+#include <init.h>
+
+#include <mach/hardware.h>
+#include <mach/cpu.h>
+#include <mach/at91_dbgu.h>
+
+#include "soc.h"
+
+struct at91_init_soc __initdata at91_boot_soc;
+
+struct at91_socinfo at91_soc_initdata;
+EXPORT_SYMBOL(at91_soc_initdata);
+
+void __init at91rm9200_set_type(int type)
+{
+ if (type == ARCH_REVISON_9200_PQFP)
+ at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
+ else
+ at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
+
+ pr_info("AT91: filled in soc subtype: %s\n",
+ at91_get_soc_subtype(&at91_soc_initdata));
+}
+
+static void __init soc_detect(u32 dbgu_base)
+{
+ u32 cidr, socid;
+
+ cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
+ socid = cidr & ~AT91_CIDR_VERSION;
+
+ switch (socid) {
+ case ARCH_ID_AT91RM9200:
+ at91_soc_initdata.type = AT91_SOC_RM9200;
+ if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE)
+ at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
+ at91_boot_soc = at91rm9200_soc;
+ break;
+
+ case ARCH_ID_AT91SAM9260:
+ at91_soc_initdata.type = AT91_SOC_SAM9260;
+ at91_boot_soc = at91sam9260_soc;
+ break;
+
+ case ARCH_ID_AT91SAM9261:
+ at91_soc_initdata.type = AT91_SOC_SAM9261;
+ at91_boot_soc = at91sam9261_soc;
+ break;
+
+ case ARCH_ID_AT91SAM9263:
+ at91_soc_initdata.type = AT91_SOC_SAM9263;
+ at91_boot_soc = at91sam9263_soc;
+ break;
+
+ case ARCH_ID_AT91SAM9G20:
+ at91_soc_initdata.type = AT91_SOC_SAM9G20;
+ at91_boot_soc = at91sam9260_soc;
+ break;
+
+ case ARCH_ID_AT91SAM9G45:
+ at91_soc_initdata.type = AT91_SOC_SAM9G45;
+ if (cidr == ARCH_ID_AT91SAM9G45ES)
+ at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
+ at91_boot_soc = at91sam9g45_soc;
+ break;
+
+ case ARCH_ID_AT91SAM9RL64:
+ at91_soc_initdata.type = AT91_SOC_SAM9RL;
+ at91_boot_soc = at91sam9rl_soc;
+ break;
+
+ case ARCH_ID_AT91SAM9X5:
+ at91_soc_initdata.type = AT91_SOC_SAM9X5;
+ at91_boot_soc = at91sam9x5_soc;
+ break;
+
+ case ARCH_ID_AT91SAM9N12:
+ at91_soc_initdata.type = AT91_SOC_SAM9N12;
+ at91_boot_soc = at91sam9n12_soc;
+ break;
+ }
+
+ /* at91sam9g10 */
+ if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
+ at91_soc_initdata.type = AT91_SOC_SAM9G10;
+ at91_boot_soc = at91sam9261_soc;
+ }
+ /* at91sam9xe */
+ else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
+ at91_soc_initdata.type = AT91_SOC_SAM9260;
+ at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
+ at91_boot_soc = at91sam9260_soc;
+ }
+
+ if (!at91_soc_is_detected())
+ return;
+
+ at91_soc_initdata.cidr = cidr;
+
+ /* sub version of soc */
+ at91_soc_initdata.exid = __raw_readl(dbgu_base + AT91_DBGU_EXID);
+
+ if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
+ switch (at91_soc_initdata.exid) {
+ case ARCH_EXID_AT91SAM9M10:
+ at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
+ break;
+ case ARCH_EXID_AT91SAM9G46:
+ at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
+ break;
+ case ARCH_EXID_AT91SAM9M11:
+ at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
+ break;
+ }
+ }
+
+ if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
+ switch (at91_soc_initdata.exid) {
+ case ARCH_EXID_AT91SAM9G15:
+ at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
+ break;
+ case ARCH_EXID_AT91SAM9G35:
+ at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
+ break;
+ case ARCH_EXID_AT91SAM9X35:
+ at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
+ break;
+ case ARCH_EXID_AT91SAM9G25:
+ at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
+ break;
+ case ARCH_EXID_AT91SAM9X25:
+ at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
+ break;
+ }
+ }
+}
+
+static const char *soc_name[] = {
+ [AT91_SOC_RM9200] = "at91rm9200",
+ [AT91_SOC_SAM9260] = "at91sam9260",
+ [AT91_SOC_SAM9261] = "at91sam9261",
+ [AT91_SOC_SAM9263] = "at91sam9263",
+ [AT91_SOC_SAM9G10] = "at91sam9g10",
+ [AT91_SOC_SAM9G20] = "at91sam9g20",
+ [AT91_SOC_SAM9G45] = "at91sam9g45",
+ [AT91_SOC_SAM9RL] = "at91sam9rl",
+ [AT91_SOC_SAM9X5] = "at91sam9x5",
+ [AT91_SOC_SAM9N12] = "at91sam9n12",
+ [AT91_SOC_NONE] = "Unknown"
+};
+
+const char *at91_get_soc_type(struct at91_socinfo *c)
+{
+ return soc_name[c->type];
+}
+EXPORT_SYMBOL(at91_get_soc_type);
+
+static const char *soc_subtype_name[] = {
+ [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
+ [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
+ [AT91_SOC_SAM9XE] = "at91sam9xe",
+ [AT91_SOC_SAM9G45ES] = "at91sam9g45es",
+ [AT91_SOC_SAM9M10] = "at91sam9m10",
+ [AT91_SOC_SAM9G46] = "at91sam9g46",
+ [AT91_SOC_SAM9M11] = "at91sam9m11",
+ [AT91_SOC_SAM9G15] = "at91sam9g15",
+ [AT91_SOC_SAM9G35] = "at91sam9g35",
+ [AT91_SOC_SAM9X35] = "at91sam9x35",
+ [AT91_SOC_SAM9G25] = "at91sam9g25",
+ [AT91_SOC_SAM9X25] = "at91sam9x25",
+ [AT91_SOC_SUBTYPE_NONE] = "Unknown"
+};
+
+const char *at91_get_soc_subtype(struct at91_socinfo *c)
+{
+ return soc_subtype_name[c->subtype];
+}
+EXPORT_SYMBOL(at91_get_soc_subtype);
+
+static int at91_detect(void)
+{
+ at91_soc_initdata.type = AT91_SOC_NONE;
+ at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
+
+ soc_detect(AT91_BASE_DBGU0);
+ if (!at91_soc_is_detected())
+ soc_detect(AT91_BASE_DBGU1);
+
+ if (!at91_soc_is_detected())
+ panic("AT91: Impossible to detect the SOC type");
+
+ pr_info("AT91: Detected soc type: %s\n",
+ at91_get_soc_type(&at91_soc_initdata));
+ pr_info("AT91: Detected soc subtype: %s\n",
+ at91_get_soc_subtype(&at91_soc_initdata));
+
+ if (!at91_soc_is_enabled())
+ panic("AT91: Soc not enabled");
+
+ if (at91_boot_soc.init)
+ at91_boot_soc.init();
+
+ return 0;
+}
+postcore_initcall(at91_detect);
+
+static int at91_soc_device(void)
+{
+ struct device_d *dev;
+
+ dev = add_generic_device_res("soc", DEVICE_ID_SINGLE, NULL, 0, NULL);
+ dev_add_param_fixed(dev, "name", (char*)at91_get_soc_type(&at91_soc_initdata));
+ dev_add_param_fixed(dev, "subname", (char*)at91_get_soc_subtype(&at91_soc_initdata));
+
+ return 0;
+}
+coredevice_initcall(at91_soc_device);
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
new file mode 100644
index 0000000..8019ced
--- /dev/null
+++ b/arch/arm/mach-at91/soc.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+struct at91_init_soc {
+ int builtin;
+ void (*init)(void);
+};
+
+extern struct at91_init_soc at91_boot_soc;
+extern struct at91_init_soc at91rm9200_soc;
+extern struct at91_init_soc at91sam9260_soc;
+extern struct at91_init_soc at91sam9261_soc;
+extern struct at91_init_soc at91sam9263_soc;
+extern struct at91_init_soc at91sam9g45_soc;
+extern struct at91_init_soc at91sam9rl_soc;
+extern struct at91_init_soc at91sam9x5_soc;
+extern struct at91_init_soc at91sam9n12_soc;
+
+#define AT91_SOC_START(_name) \
+struct at91_init_soc __initdata at91##_name##_soc \
+ __used \
+ = { \
+ .builtin = 1, \
+
+#define AT91_SOC_END \
+};
+
+static inline int at91_soc_is_enabled(void)
+{
+ return at91_boot_soc.builtin;
+}
+
+#if !defined(CONFIG_SOC_AT91RM9200)
+#define at91rm9200_soc at91_boot_soc
+#endif
+
+#if !defined(CONFIG_SOC_AT91SAM9260)
+#define at91sam9260_soc at91_boot_soc
+#endif
+
+#if !defined(CONFIG_SOC_AT91SAM9261)
+#define at91sam9261_soc at91_boot_soc
+#endif
+
+#if !defined(CONFIG_SOC_AT91SAM9263)
+#define at91sam9263_soc at91_boot_soc
+#endif
+
+#if !defined(CONFIG_SOC_AT91SAM9G45)
+#define at91sam9g45_soc at91_boot_soc
+#endif
+
+#if !defined(CONFIG_SOC_AT91SAM9RL)
+#define at91sam9rl_soc at91_boot_soc
+#endif
+
+#if !defined(CONFIG_SOC_AT91SAM9X5)
+#define at91sam9x5_soc at91_boot_soc
+#endif
+
+#if !defined(CONFIG_SOC_AT91SAM9N12)
+#define at91sam9n12_soc at91_boot_soc
+#endif
--
1.7.10.4
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^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH 10/13] at91: SMC: switch to platfrom_driver
2012-12-28 19:16 ` [PATCH 01/13] at91: factorise dbgu address Jean-Christophe PLAGNIOL-VILLARD
` (7 preceding siblings ...)
2012-12-28 19:16 ` [PATCH 09/13] at91: autodetect the soc one time at postcore_initcall Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-28 19:16 ` Jean-Christophe PLAGNIOL-VILLARD
2013-01-02 10:59 ` Sascha Hauer
2012-12-28 19:16 ` [PATCH 11/13] at91: wdt: drop AT91_SYS_BASE Jean-Christophe PLAGNIOL-VILLARD
` (2 subsequent siblings)
11 siblings, 1 reply; 19+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-28 19:16 UTC (permalink / raw)
To: barebox
This will allow to support multiple arch
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/boards/at91sam9260ek/init.c | 3 +-
arch/arm/boards/at91sam9261ek/init.c | 5 +-
arch/arm/boards/at91sam9263ek/init.c | 3 +-
arch/arm/boards/at91sam9m10g45ek/init.c | 3 +-
arch/arm/boards/at91sam9n12ek/init.c | 5 +-
arch/arm/boards/at91sam9x5ek/init.c | 3 +-
arch/arm/boards/dss11/init.c | 3 +-
arch/arm/boards/pm9261/init.c | 5 +-
arch/arm/boards/pm9263/init.c | 3 +-
arch/arm/boards/pm9g45/init.c | 3 +-
arch/arm/boards/qil-a9260/init.c | 3 +-
arch/arm/boards/tny-a926x/init.c | 5 +-
arch/arm/boards/usb-a926x/init.c | 5 +-
arch/arm/mach-at91/at91sam9260.c | 1 +
arch/arm/mach-at91/at91sam9261.c | 1 +
arch/arm/mach-at91/at91sam9263.c | 2 +
arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 8 +-
arch/arm/mach-at91/at91sam9g45.c | 1 +
arch/arm/mach-at91/at91sam9n12.c | 1 +
arch/arm/mach-at91/at91sam9x5.c | 1 +
arch/arm/mach-at91/generic.h | 7 ++
arch/arm/mach-at91/include/mach/at91sam9260.h | 3 +-
arch/arm/mach-at91/include/mach/at91sam9261.h | 2 +-
arch/arm/mach-at91/include/mach/at91sam9263.h | 3 +-
arch/arm/mach-at91/include/mach/at91sam9_smc.h | 50 ++++++--
arch/arm/mach-at91/include/mach/at91sam9g45.h | 2 +-
arch/arm/mach-at91/include/mach/at91sam9n12.h | 2 +-
arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 +-
arch/arm/mach-at91/include/mach/sam9_smc.h | 33 ------
arch/arm/mach-at91/sam9_smc.c | 146 ++++++++++++++++++++----
30 files changed, 206 insertions(+), 108 deletions(-)
delete mode 100644 arch/arm/mach-at91/include/mach/sam9_smc.h
diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c
index d07eda9..7bd0279 100644
--- a/arch/arm/boards/at91sam9260ek/init.c
+++ b/arch/arm/boards/at91sam9260ek/init.c
@@ -31,7 +31,6 @@
#include <linux/mtd/nand.h>
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
-#include <mach/sam9_smc.h>
#include <gpio.h>
#include <mach/io.h>
#include <mach/at91_pmc.h>
@@ -122,7 +121,7 @@ static void ek_add_device_nand(void)
smc->mode |= AT91_SMC_DBW_8;
/* configure chip-select 3 (NAND) */
- sam9_smc_configure(3, smc);
+ sam9_smc_configure(0, 3, smc);
at91_add_device_nand(&nand_pdata);
}
diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c
index 0020c92..7c95435 100644
--- a/arch/arm/boards/at91sam9261ek/init.c
+++ b/arch/arm/boards/at91sam9261ek/init.c
@@ -33,7 +33,6 @@
#include <mach/gpio.h>
#include <mach/io.h>
#include <mach/at91sam9_smc.h>
-#include <mach/sam9_smc.h>
#include <dm9000.h>
#include <gpio_keys.h>
#include <readkey.h>
@@ -80,7 +79,7 @@ static void ek_add_device_nand(void)
ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
/* configure chip-select 3 (NAND) */
- sam9_smc_configure(3, &ek_nand_smc_config);
+ sam9_smc_configure(0, 3, &ek_nand_smc_config);
at91_add_device_nand(&nand_pdata);
}
@@ -118,7 +117,7 @@ static struct sam9_smc_config __initdata dm9000_smc_config = {
static void __init ek_add_device_dm9000(void)
{
/* Configure chip-select 2 (DM9000) */
- sam9_smc_configure(2, &dm9000_smc_config);
+ sam9_smc_configure(0, 2, &dm9000_smc_config);
/* Configure Reset signal as output */
at91_set_gpio_output(AT91_PIN_PC10, 0);
diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c
index 7334bae..a86c0fd 100644
--- a/arch/arm/boards/at91sam9263ek/init.c
+++ b/arch/arm/boards/at91sam9263ek/init.c
@@ -35,7 +35,6 @@
#include <mach/gpio.h>
#include <mach/io.h>
#include <mach/at91sam9_smc.h>
-#include <mach/sam9_smc.h>
static struct atmel_nand_data nand_pdata = {
.ale = 21,
@@ -78,7 +77,7 @@ static void ek_add_device_nand(void)
ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
/* configure chip-select 3 (NAND) */
- sam9_smc_configure(3, &ek_nand_smc_config);
+ sam9_smc_configure(0, 3, &ek_nand_smc_config);
at91_add_device_nand(&nand_pdata);
}
diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c
index 7d01d96..d77b2bf 100644
--- a/arch/arm/boards/at91sam9m10g45ek/init.c
+++ b/arch/arm/boards/at91sam9m10g45ek/init.c
@@ -36,7 +36,6 @@
#include <mach/gpio.h>
#include <mach/io.h>
#include <mach/at91sam9_smc.h>
-#include <mach/sam9_smc.h>
#include <gpio_keys.h>
#include <readkey.h>
@@ -101,7 +100,7 @@ static void ek_add_device_nand(void)
ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
/* configure chip-select 3 (NAND) */
- sam9_smc_configure(3, &ek_nand_smc_config);
+ sam9_smc_configure(0, 3, &ek_nand_smc_config);
at91_add_device_nand(&nand_pdata);
}
diff --git a/arch/arm/boards/at91sam9n12ek/init.c b/arch/arm/boards/at91sam9n12ek/init.c
index 51c4fb0..310f418 100644
--- a/arch/arm/boards/at91sam9n12ek/init.c
+++ b/arch/arm/boards/at91sam9n12ek/init.c
@@ -31,7 +31,6 @@
#include <linux/mtd/nand.h>
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
-#include <mach/sam9_smc.h>
#include <gpio.h>
#include <mach/io.h>
#include <mach/at91_pmc.h>
@@ -77,7 +76,7 @@ static void ek_add_device_nand(void)
ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
/* configure chip-select 3 (NAND) */
- sam9_smc_configure(3, &ek_nand_smc_config);
+ sam9_smc_configure(0, 3, &ek_nand_smc_config);
at91_add_device_nand(&nand_pdata);
}
@@ -112,7 +111,7 @@ static struct sam9_smc_config __initdata ks8851_smc_config = {
static void __init ek_add_device_ks8851(void)
{
/* Configure chip-select 2 (KS8851) */
- sam9_smc_configure(2, &ks8851_smc_config);
+ sam9_smc_configure(0, 2, &ks8851_smc_config);
/* Configure NCS signal */
at91_set_B_periph(AT91_PIN_PD19, 0);
/* Configure Interrupt pin as input, no pull-up */
diff --git a/arch/arm/boards/at91sam9x5ek/init.c b/arch/arm/boards/at91sam9x5ek/init.c
index 3f22d02..f230205 100644
--- a/arch/arm/boards/at91sam9x5ek/init.c
+++ b/arch/arm/boards/at91sam9x5ek/init.c
@@ -31,7 +31,6 @@
#include <linux/mtd/nand.h>
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
-#include <mach/sam9_smc.h>
#include <gpio.h>
#include <mach/io.h>
#include <mach/at91_pmc.h>
@@ -93,7 +92,7 @@ static void ek_add_device_nand(void)
cm_nand_smc_config.mode |= AT91_SMC_DBW_8;
/* configure chip-select 3 (NAND) */
- sam9_smc_configure(3, &cm_nand_smc_config);
+ sam9_smc_configure(0, 3, &cm_nand_smc_config);
if (at91sam9x5ek_cm_is_vendor(VENDOR_COGENT)) {
unsigned long csa;
diff --git a/arch/arm/boards/dss11/init.c b/arch/arm/boards/dss11/init.c
index 12d4263..a2e9825 100644
--- a/arch/arm/boards/dss11/init.c
+++ b/arch/arm/boards/dss11/init.c
@@ -29,7 +29,6 @@
#include <linux/mtd/nand.h>
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
-#include <mach/sam9_smc.h>
#include <gpio.h>
#include <mach/io.h>
#include <mach/at91_rstc.h>
@@ -69,7 +68,7 @@ static void dss11_add_device_nand(void)
dss11_nand_smc_config.mode |= AT91_SMC_DBW_16;
/* configure chip-select 3 (NAND) */
- sam9_smc_configure(3, &dss11_nand_smc_config);
+ sam9_smc_configure(0, 3, &dss11_nand_smc_config);
at91_add_device_nand(&nand_pdata);
}
diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c
index a91fa7a..207092c 100644
--- a/arch/arm/boards/pm9261/init.c
+++ b/arch/arm/boards/pm9261/init.c
@@ -34,7 +34,6 @@
#include <mach/gpio.h>
#include <mach/io.h>
#include <mach/at91sam9_smc.h>
-#include <mach/sam9_smc.h>
#include <dm9000.h>
#include <linux/w1-gpio.h>
#include <w1_mac_address.h>
@@ -84,7 +83,7 @@ static void pm_add_device_nand(void)
pm_nand_smc_config.mode |= AT91_SMC_DBW_8;
/* configure chip-select 3 (NAND) */
- sam9_smc_configure(3, &pm_nand_smc_config);
+ sam9_smc_configure(0, 3, &pm_nand_smc_config);
at91_add_device_nand(&nand_pdata);
}
@@ -123,7 +122,7 @@ static void __init pm_add_device_dm9000(void)
{
w1_local_mac_address_register(0, "ron", "w1-1-0");
/* Configure chip-select 2 (DM9000) */
- sam9_smc_configure(2, &dm9000_smc_config);
+ sam9_smc_configure(0, 2, &dm9000_smc_config);
add_dm9000_device(0, AT91_CHIPSELECT_2, AT91_CHIPSELECT_2 + 4,
IORESOURCE_MEM_16BIT, &dm9000_data);
diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c
index f719c65..f7ef148 100644
--- a/arch/arm/boards/pm9263/init.c
+++ b/arch/arm/boards/pm9263/init.c
@@ -35,7 +35,6 @@
#include <mach/gpio.h>
#include <mach/io.h>
#include <mach/at91sam9_smc.h>
-#include <mach/sam9_smc.h>
#include <linux/w1-gpio.h>
#include <w1_mac_address.h>
@@ -84,7 +83,7 @@ static void pm_add_device_nand(void)
pm_nand_smc_config.mode |= AT91_SMC_DBW_8;
/* configure chip-select 3 (NAND) */
- sam9_smc_configure(3, &pm_nand_smc_config);
+ sam9_smc_configure(0, 3, &pm_nand_smc_config);
at91_add_device_nand(&nand_pdata);
}
diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c
index fabe97b..8e29f62 100644
--- a/arch/arm/boards/pm9g45/init.c
+++ b/arch/arm/boards/pm9g45/init.c
@@ -34,7 +34,6 @@
#include <mach/gpio.h>
#include <mach/io.h>
#include <mach/at91sam9_smc.h>
-#include <mach/sam9_smc.h>
#include <linux/w1-gpio.h>
#include <w1_mac_address.h>
@@ -76,7 +75,7 @@ static void pm_add_device_nand(void)
pm_nand_smc_config.mode |= AT91_SMC_DBW_8;
/* configure chip-select 3 (NAND) */
- sam9_smc_configure(3, &pm_nand_smc_config);
+ sam9_smc_configure(0, 3, &pm_nand_smc_config);
at91_add_device_nand(&nand_pdata);
}
diff --git a/arch/arm/boards/qil-a9260/init.c b/arch/arm/boards/qil-a9260/init.c
index a06566c..4977d3b 100644
--- a/arch/arm/boards/qil-a9260/init.c
+++ b/arch/arm/boards/qil-a9260/init.c
@@ -22,7 +22,6 @@
#include <linux/clk.h>
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
-#include <mach/sam9_smc.h>
#include <gpio.h>
#include <led.h>
#include <mach/io.h>
@@ -59,7 +58,7 @@ static struct sam9_smc_config nand_smc_config = {
static void qil_a9260_add_device_nand(void)
{
/* configure chip-select 3 (NAND) */
- sam9_smc_configure(3, &nand_smc_config);
+ sam9_smc_configure(0, 3, &nand_smc_config);
at91_add_device_nand(&nand_pdata);
}
diff --git a/arch/arm/boards/tny-a926x/init.c b/arch/arm/boards/tny-a926x/init.c
index e30cccf..5fe6531 100644
--- a/arch/arm/boards/tny-a926x/init.c
+++ b/arch/arm/boards/tny-a926x/init.c
@@ -32,7 +32,6 @@
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <mach/at91sam9_sdramc.h>
-#include <mach/sam9_smc.h>
#include <gpio.h>
#include <mach/io.h>
#include <mach/at91_pmc.h>
@@ -100,9 +99,9 @@ static void tny_a9260_add_device_nand(void)
{
/* configure chip-select 3 (NAND) */
if (machine_is_tny_a9g20())
- sam9_smc_configure(3, &tny_a9g20_nand_smc_config);
+ sam9_smc_configure(0, 3, &tny_a9g20_nand_smc_config);
else
- sam9_smc_configure(3, &tny_a9260_nand_smc_config);
+ sam9_smc_configure(0, 3, &tny_a9260_nand_smc_config);
if (machine_is_tny_a9263()) {
nand_pdata.rdy_pin = AT91_PIN_PA22;
diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c
index dd136da..95ac6a8 100644
--- a/arch/arm/boards/usb-a926x/init.c
+++ b/arch/arm/boards/usb-a926x/init.c
@@ -32,7 +32,6 @@
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <mach/at91sam9_sdramc.h>
-#include <mach/sam9_smc.h>
#include <gpio.h>
#include <led.h>
#include <mach/io.h>
@@ -101,9 +100,9 @@ static void usb_a9260_add_device_nand(void)
{
/* configure chip-select 3 (NAND) */
if (machine_is_usb_a9g20())
- sam9_smc_configure(3, &usb_a9g20_nand_smc_config);
+ sam9_smc_configure(0, 3, &usb_a9g20_nand_smc_config);
else
- sam9_smc_configure(3, &usb_a9260_nand_smc_config);
+ sam9_smc_configure(0, 3, &usb_a9260_nand_smc_config);
if (machine_is_usb_a9263()) {
nand_pdata.rdy_pin = AT91_PIN_PA22;
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 4c76d94..2a06f0d 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -236,6 +236,7 @@ static void at91sam9260_initialize(void)
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_pit(AT91SAM9260_BASE_PIT);
+ at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9260_BASE_SMC, 0x200);
}
AT91_SOC_START(sam9260)
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 1efbbee..c801d9d 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -228,6 +228,7 @@ static void at91sam9261_initialize(void)
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_pit(AT91SAM9261_BASE_PIT);
+ at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9261_BASE_SMC, 0x200);
}
AT91_SOC_START(sam9261)
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index e1fbe6f..42777d0 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -247,6 +247,8 @@ static void at91sam9263_initialize(void)
at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
at91_add_pit(AT91SAM9263_BASE_PIT);
+ at91_add_sam9_smc(0, AT91SAM9263_BASE_SMC0, 0x200);
+ at91_add_sam9_smc(1, AT91SAM9263_BASE_SMC1, 0x200);
}
AT91_SOC_START(sam9263)
diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
index 5edbd8b..6e4101d 100644
--- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
@@ -62,13 +62,13 @@ void __naked __bare_init reset(void)
#endif
/* flash */
- at91_sys_write(AT91_SMC_MODE(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_MODE_VAL);
+ at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_MODE, CONFIG_SYS_SMC_MODE_VAL);
- at91_sys_write(AT91_SMC_CYCLE(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_CYCLE_VAL);
+ at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_CYCLE, CONFIG_SYS_SMC_CYCLE_VAL);
- at91_sys_write(AT91_SMC_PULSE(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_PULSE_VAL);
+ at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_PULSE, CONFIG_SYS_SMC_PULSE_VAL);
- at91_sys_write(AT91_SMC_SETUP(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_SETUP_VAL);
+ at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_SETUP, CONFIG_SYS_SMC_SETUP_VAL);
/*
* PMC Check if the PLL is already initialized
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 94fee59..7ca1f3b 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -259,6 +259,7 @@ static void at91sam9g45_initialize(void)
at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
at91_add_pit(AT91SAM9G45_BASE_PIT);
+ at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9G45_BASE_SMC, 0x200);
}
AT91_SOC_START(sam9g45)
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index d1b7ce1..967885a 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -219,6 +219,7 @@ static void at91sam9n12_initialize(void)
at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
at91_add_pit(AT91SAM9N12_BASE_PIT);
+ at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9N12_BASE_SMC, 0x200);
}
AT91_SOC_START(sam9n12)
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 7b58e12..090d9dd 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -304,6 +304,7 @@ static void at91sam9x5_initialize(void)
at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
at91_add_pit(AT91SAM9X5_BASE_PIT);
+ at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9X5_BASE_SMC, 0x200);
}
AT91_SOC_START(sam9x5)
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 490cf3c..a19c1c5 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -28,3 +28,10 @@ static inline struct device_d *at91_add_pit(resource_size_t start)
return add_generic_device("at91-pit", DEVICE_ID_SINGLE, NULL, start, 16,
IORESOURCE_MEM, NULL);
}
+
+static inline struct device_d *at91_add_sam9_smc(int id, resource_size_t start,
+ resource_size_t size)
+{
+ return add_generic_device("at91sam9-smc", id, NULL, start, size,
+ IORESOURCE_MEM, NULL);
+}
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 5d1b376..0804dc3 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -100,13 +100,14 @@
*/
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_BASE_SMC AT91SAM9260_BASE_SMC
+#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9260_BASE_PIOB
#define AT91_BASE_PIOC AT91SAM9260_BASE_PIOC
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 1469f7e..0565e1b 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -86,13 +86,13 @@
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_BASE_SMC AT91SAM9261_BASE_SMC
#define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9261_BASE_PIOB
#define AT91_BASE_PIOC AT91SAM9261_BASE_PIOC
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index a8c067a..9eff27a 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -104,13 +104,13 @@
*/
#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
-#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_BASE_SMC AT91SAM9263_BASE_SMC0
#define AT91_BASE_PIOA AT91SAM9263_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9263_BASE_PIOB
#define AT91_BASE_PIOC AT91SAM9263_BASE_PIOC
@@ -122,7 +122,6 @@
#define AT91_USART2 AT91SAM9263_BASE_US2
#define AT91_NB_USART 4
-#define AT91_SMC AT91_SMC0
#define AT91_SDRAMC AT91_SDRAMC0
#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index d64511b..d5cf5f7 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -16,7 +16,42 @@
#ifndef AT91SAM9_SMC_H
#define AT91SAM9_SMC_H
-#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
+#define at91_smc_read(id, field) \
+ __raw_readl(AT91_BASE_SMC + ((id) * 0x10) + field)
+
+#define at91_smc_write(id, field, value) \
+ __raw_writel(value, AT91_BASE_SMC + ((id) * 0x10) + field)
+
+#ifndef __ASSEMBLY__
+struct sam9_smc_config {
+ /* Setup register */
+ u8 ncs_read_setup;
+ u8 nrd_setup;
+ u8 ncs_write_setup;
+ u8 nwe_setup;
+
+ /* Pulse register */
+ u8 ncs_read_pulse;
+ u8 nrd_pulse;
+ u8 ncs_write_pulse;
+ u8 nwe_pulse;
+
+ /* Cycle register */
+ u16 read_cycle;
+ u16 write_cycle;
+
+ /* Mode register */
+ u32 mode;
+ u8 tdf_cycles:4;
+};
+
+extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
+extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
+extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
+extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
+#endif
+
+#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
#define AT91_SMC_NWESETUP_(x) ((x) << 0)
#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
@@ -26,7 +61,7 @@
#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
-#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
+#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */
#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
@@ -36,13 +71,13 @@
#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
-#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
+#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */
#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
-#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
+#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */
#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
@@ -66,11 +101,4 @@
#define AT91_SMC_PS_16 (2 << 28)
#define AT91_SMC_PS_32 (3 << 28)
-#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
-#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
-#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
-#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
-#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
-#endif
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 85ed129..9c5234a 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -115,13 +115,13 @@
#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
-#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_BASE_SMC AT91SAM9G45_BASE_SMC
#define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9G45_BASE_PIOB
#define AT91_BASE_PIOC AT91SAM9G45_BASE_PIOC
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
index 59d7030..b55e5f0 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -112,12 +112,12 @@
#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)
#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)
#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
+#define AT91_BASE_SMC AT91SAM9N12_BASE_SMC
#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9N12_BASE_PIOB
#define AT91_BASE_PIOC AT91SAM9N12_BASE_PIOC
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 63a5138..8a48eed 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -119,12 +119,12 @@
#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)
#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)
#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
+#define AT91_BASE_SMC AT91SAM9X5_BASE_SMC
#define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9X5_BASE_PIOB
#define AT91_BASE_PIOC AT91SAM9X5_BASE_PIOC
diff --git a/arch/arm/mach-at91/include/mach/sam9_smc.h b/arch/arm/mach-at91/include/mach/sam9_smc.h
deleted file mode 100644
index bf72cfb..0000000
--- a/arch/arm/mach-at91/include/mach/sam9_smc.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/sam9_smc.
- *
- * Copyright (C) 2008 Andrew Victor
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-struct sam9_smc_config {
- /* Setup register */
- u8 ncs_read_setup;
- u8 nrd_setup;
- u8 ncs_write_setup;
- u8 nwe_setup;
-
- /* Pulse register */
- u8 ncs_read_pulse;
- u8 nrd_pulse;
- u8 ncs_write_pulse;
- u8 nwe_pulse;
-
- /* Cycle register */
- u16 read_cycle;
- u16 write_cycle;
-
- /* Mode register */
- u32 mode;
- u8 tdf_cycles:4;
-};
-
-extern void __init sam9_smc_configure(int cs, struct sam9_smc_config* config);
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index c397fe4..b48275e 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -9,40 +9,142 @@
*/
#include <common.h>
+#include <init.h>
#include <io.h>
#include <mach/hardware.h>
#include <mach/io.h>
#include <mach/at91sam9_smc.h>
-#include <mach/sam9_smc.h>
-void sam9_smc_configure(int cs, struct sam9_smc_config* config)
+#define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x10))
+
+static void __iomem *smc_base_addr[2];
+
+static void sam9_smc_cs_write_mode(void __iomem *base,
+ struct sam9_smc_config *config)
+{
+ __raw_writel(config->mode
+ | AT91_SMC_TDF_(config->tdf_cycles),
+ base + AT91_SMC_MODE);
+}
+
+void sam9_smc_write_mode(int id, int cs,
+ struct sam9_smc_config *config)
+{
+ sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
+}
+
+static void sam9_smc_cs_configure(void __iomem *base,
+ struct sam9_smc_config *config)
+{
+
+ /* Setup register */
+ __raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup)
+ | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
+ | AT91_SMC_NRDSETUP_(config->nrd_setup)
+ | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),
+ base + AT91_SMC_SETUP);
+
+ /* Pulse register */
+ __raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)
+ | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
+ | AT91_SMC_NRDPULSE_(config->nrd_pulse)
+ | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),
+ base + AT91_SMC_PULSE);
+
+ /* Cycle register */
+ __raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle)
+ | AT91_SMC_NRDCYCLE_(config->read_cycle),
+ base + AT91_SMC_CYCLE);
+
+ /* Mode register */
+ sam9_smc_cs_write_mode(base, config);
+}
+
+void sam9_smc_configure(int id, int cs,
+ struct sam9_smc_config *config)
+{
+ sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
+}
+
+static void sam9_smc_cs_read_mode(void __iomem *base,
+ struct sam9_smc_config *config)
+{
+ u32 val = __raw_readl(base + AT91_SMC_MODE);
+
+ config->mode = (val & ~AT91_SMC_NWECYCLE);
+ config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ;
+}
+
+void sam9_smc_read_mode(int id, int cs,
+ struct sam9_smc_config *config)
+{
+ sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
+}
+
+static void sam9_smc_cs_read(void __iomem *base,
+ struct sam9_smc_config *config)
{
+ u32 val;
+
/* Setup register */
- at91_sys_write(AT91_SMC_SETUP(cs),
- AT91_SMC_NWESETUP_(config->nwe_setup)
- | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
- | AT91_SMC_NRDSETUP_(config->nrd_setup)
- | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup)
- );
+ val = __raw_readl(base + AT91_SMC_SETUP);
+
+ config->nwe_setup = val & AT91_SMC_NWESETUP;
+ config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8;
+ config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16;
+ config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24;
/* Pulse register */
- at91_sys_write(AT91_SMC_PULSE(cs),
- AT91_SMC_NWEPULSE_(config->nwe_pulse)
- | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
- | AT91_SMC_NRDPULSE_(config->nrd_pulse)
- | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse)
- );
+ val = __raw_readl(base + AT91_SMC_PULSE);
+
+ config->nwe_setup = val & AT91_SMC_NWEPULSE;
+ config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
+ config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
+ config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
/* Cycle register */
- at91_sys_write(AT91_SMC_CYCLE(cs),
- AT91_SMC_NWECYCLE_(config->write_cycle)
- | AT91_SMC_NRDCYCLE_(config->read_cycle)
- );
+ val = __raw_readl(base + AT91_SMC_CYCLE);
+
+ config->write_cycle = val & AT91_SMC_NWECYCLE;
+ config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16;
/* Mode register */
- at91_sys_write(AT91_SMC_MODE(cs),
- config->mode
- | AT91_SMC_TDF_(config->tdf_cycles)
- );
+ sam9_smc_cs_read_mode(base, config);
+}
+
+void sam9_smc_read(int id, int cs, struct sam9_smc_config *config)
+{
+ sam9_smc_cs_read(AT91_SMC_CS(id, cs), config);
+}
+
+static int at91sam9_smc_probe(struct device_d *dev)
+{
+ int id;
+
+ if (dev->id < 0) {
+ id = 0;
+ } else if (dev->id > 1) {
+ dev_warn(dev, ": id > 2\n");
+ return -EIO;
+ }
+
+ smc_base_addr[id] = dev_request_mem_region(dev, 0);
+ if (!smc_base_addr[id]) {
+ dev_err(dev, "Impossible to request smc.%d\n", id);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static struct driver_d at91sam9_smc_driver = {
+ .name = "at91sam9-smc",
+ .probe = at91sam9_smc_probe,
+};
+
+static int at91sam9_smc_init(void)
+{
+ return platform_driver_register(&at91sam9_smc_driver);
}
+coredevice_initcall(at91sam9_smc_init);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 10/13] at91: SMC: switch to platfrom_driver
2012-12-28 19:16 ` [PATCH 10/13] at91: SMC: switch to platfrom_driver Jean-Christophe PLAGNIOL-VILLARD
@ 2013-01-02 10:59 ` Sascha Hauer
0 siblings, 0 replies; 19+ messages in thread
From: Sascha Hauer @ 2013-01-02 10:59 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
subject: s/platfrom_driver/platform_driver
Sascha
On Fri, Dec 28, 2012 at 08:16:11PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> This will allow to support multiple arch
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
> arch/arm/boards/at91sam9260ek/init.c | 3 +-
> arch/arm/boards/at91sam9261ek/init.c | 5 +-
> arch/arm/boards/at91sam9263ek/init.c | 3 +-
> arch/arm/boards/at91sam9m10g45ek/init.c | 3 +-
> arch/arm/boards/at91sam9n12ek/init.c | 5 +-
> arch/arm/boards/at91sam9x5ek/init.c | 3 +-
> arch/arm/boards/dss11/init.c | 3 +-
> arch/arm/boards/pm9261/init.c | 5 +-
> arch/arm/boards/pm9263/init.c | 3 +-
> arch/arm/boards/pm9g45/init.c | 3 +-
> arch/arm/boards/qil-a9260/init.c | 3 +-
> arch/arm/boards/tny-a926x/init.c | 5 +-
> arch/arm/boards/usb-a926x/init.c | 5 +-
> arch/arm/mach-at91/at91sam9260.c | 1 +
> arch/arm/mach-at91/at91sam9261.c | 1 +
> arch/arm/mach-at91/at91sam9263.c | 2 +
> arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 8 +-
> arch/arm/mach-at91/at91sam9g45.c | 1 +
> arch/arm/mach-at91/at91sam9n12.c | 1 +
> arch/arm/mach-at91/at91sam9x5.c | 1 +
> arch/arm/mach-at91/generic.h | 7 ++
> arch/arm/mach-at91/include/mach/at91sam9260.h | 3 +-
> arch/arm/mach-at91/include/mach/at91sam9261.h | 2 +-
> arch/arm/mach-at91/include/mach/at91sam9263.h | 3 +-
> arch/arm/mach-at91/include/mach/at91sam9_smc.h | 50 ++++++--
> arch/arm/mach-at91/include/mach/at91sam9g45.h | 2 +-
> arch/arm/mach-at91/include/mach/at91sam9n12.h | 2 +-
> arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 +-
> arch/arm/mach-at91/include/mach/sam9_smc.h | 33 ------
> arch/arm/mach-at91/sam9_smc.c | 146 ++++++++++++++++++++----
> 30 files changed, 206 insertions(+), 108 deletions(-)
> delete mode 100644 arch/arm/mach-at91/include/mach/sam9_smc.h
>
> diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c
> index d07eda9..7bd0279 100644
> --- a/arch/arm/boards/at91sam9260ek/init.c
> +++ b/arch/arm/boards/at91sam9260ek/init.c
> @@ -31,7 +31,6 @@
> #include <linux/mtd/nand.h>
> #include <mach/board.h>
> #include <mach/at91sam9_smc.h>
> -#include <mach/sam9_smc.h>
> #include <gpio.h>
> #include <mach/io.h>
> #include <mach/at91_pmc.h>
> @@ -122,7 +121,7 @@ static void ek_add_device_nand(void)
> smc->mode |= AT91_SMC_DBW_8;
>
> /* configure chip-select 3 (NAND) */
> - sam9_smc_configure(3, smc);
> + sam9_smc_configure(0, 3, smc);
>
> at91_add_device_nand(&nand_pdata);
> }
> diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c
> index 0020c92..7c95435 100644
> --- a/arch/arm/boards/at91sam9261ek/init.c
> +++ b/arch/arm/boards/at91sam9261ek/init.c
> @@ -33,7 +33,6 @@
> #include <mach/gpio.h>
> #include <mach/io.h>
> #include <mach/at91sam9_smc.h>
> -#include <mach/sam9_smc.h>
> #include <dm9000.h>
> #include <gpio_keys.h>
> #include <readkey.h>
> @@ -80,7 +79,7 @@ static void ek_add_device_nand(void)
> ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
>
> /* configure chip-select 3 (NAND) */
> - sam9_smc_configure(3, &ek_nand_smc_config);
> + sam9_smc_configure(0, 3, &ek_nand_smc_config);
>
> at91_add_device_nand(&nand_pdata);
> }
> @@ -118,7 +117,7 @@ static struct sam9_smc_config __initdata dm9000_smc_config = {
> static void __init ek_add_device_dm9000(void)
> {
> /* Configure chip-select 2 (DM9000) */
> - sam9_smc_configure(2, &dm9000_smc_config);
> + sam9_smc_configure(0, 2, &dm9000_smc_config);
>
> /* Configure Reset signal as output */
> at91_set_gpio_output(AT91_PIN_PC10, 0);
> diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c
> index 7334bae..a86c0fd 100644
> --- a/arch/arm/boards/at91sam9263ek/init.c
> +++ b/arch/arm/boards/at91sam9263ek/init.c
> @@ -35,7 +35,6 @@
> #include <mach/gpio.h>
> #include <mach/io.h>
> #include <mach/at91sam9_smc.h>
> -#include <mach/sam9_smc.h>
>
> static struct atmel_nand_data nand_pdata = {
> .ale = 21,
> @@ -78,7 +77,7 @@ static void ek_add_device_nand(void)
> ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
>
> /* configure chip-select 3 (NAND) */
> - sam9_smc_configure(3, &ek_nand_smc_config);
> + sam9_smc_configure(0, 3, &ek_nand_smc_config);
>
> at91_add_device_nand(&nand_pdata);
> }
> diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c
> index 7d01d96..d77b2bf 100644
> --- a/arch/arm/boards/at91sam9m10g45ek/init.c
> +++ b/arch/arm/boards/at91sam9m10g45ek/init.c
> @@ -36,7 +36,6 @@
> #include <mach/gpio.h>
> #include <mach/io.h>
> #include <mach/at91sam9_smc.h>
> -#include <mach/sam9_smc.h>
> #include <gpio_keys.h>
> #include <readkey.h>
>
> @@ -101,7 +100,7 @@ static void ek_add_device_nand(void)
> ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
>
> /* configure chip-select 3 (NAND) */
> - sam9_smc_configure(3, &ek_nand_smc_config);
> + sam9_smc_configure(0, 3, &ek_nand_smc_config);
>
> at91_add_device_nand(&nand_pdata);
> }
> diff --git a/arch/arm/boards/at91sam9n12ek/init.c b/arch/arm/boards/at91sam9n12ek/init.c
> index 51c4fb0..310f418 100644
> --- a/arch/arm/boards/at91sam9n12ek/init.c
> +++ b/arch/arm/boards/at91sam9n12ek/init.c
> @@ -31,7 +31,6 @@
> #include <linux/mtd/nand.h>
> #include <mach/board.h>
> #include <mach/at91sam9_smc.h>
> -#include <mach/sam9_smc.h>
> #include <gpio.h>
> #include <mach/io.h>
> #include <mach/at91_pmc.h>
> @@ -77,7 +76,7 @@ static void ek_add_device_nand(void)
> ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
>
> /* configure chip-select 3 (NAND) */
> - sam9_smc_configure(3, &ek_nand_smc_config);
> + sam9_smc_configure(0, 3, &ek_nand_smc_config);
>
> at91_add_device_nand(&nand_pdata);
> }
> @@ -112,7 +111,7 @@ static struct sam9_smc_config __initdata ks8851_smc_config = {
> static void __init ek_add_device_ks8851(void)
> {
> /* Configure chip-select 2 (KS8851) */
> - sam9_smc_configure(2, &ks8851_smc_config);
> + sam9_smc_configure(0, 2, &ks8851_smc_config);
> /* Configure NCS signal */
> at91_set_B_periph(AT91_PIN_PD19, 0);
> /* Configure Interrupt pin as input, no pull-up */
> diff --git a/arch/arm/boards/at91sam9x5ek/init.c b/arch/arm/boards/at91sam9x5ek/init.c
> index 3f22d02..f230205 100644
> --- a/arch/arm/boards/at91sam9x5ek/init.c
> +++ b/arch/arm/boards/at91sam9x5ek/init.c
> @@ -31,7 +31,6 @@
> #include <linux/mtd/nand.h>
> #include <mach/board.h>
> #include <mach/at91sam9_smc.h>
> -#include <mach/sam9_smc.h>
> #include <gpio.h>
> #include <mach/io.h>
> #include <mach/at91_pmc.h>
> @@ -93,7 +92,7 @@ static void ek_add_device_nand(void)
> cm_nand_smc_config.mode |= AT91_SMC_DBW_8;
>
> /* configure chip-select 3 (NAND) */
> - sam9_smc_configure(3, &cm_nand_smc_config);
> + sam9_smc_configure(0, 3, &cm_nand_smc_config);
>
> if (at91sam9x5ek_cm_is_vendor(VENDOR_COGENT)) {
> unsigned long csa;
> diff --git a/arch/arm/boards/dss11/init.c b/arch/arm/boards/dss11/init.c
> index 12d4263..a2e9825 100644
> --- a/arch/arm/boards/dss11/init.c
> +++ b/arch/arm/boards/dss11/init.c
> @@ -29,7 +29,6 @@
> #include <linux/mtd/nand.h>
> #include <mach/board.h>
> #include <mach/at91sam9_smc.h>
> -#include <mach/sam9_smc.h>
> #include <gpio.h>
> #include <mach/io.h>
> #include <mach/at91_rstc.h>
> @@ -69,7 +68,7 @@ static void dss11_add_device_nand(void)
> dss11_nand_smc_config.mode |= AT91_SMC_DBW_16;
>
> /* configure chip-select 3 (NAND) */
> - sam9_smc_configure(3, &dss11_nand_smc_config);
> + sam9_smc_configure(0, 3, &dss11_nand_smc_config);
>
> at91_add_device_nand(&nand_pdata);
> }
> diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c
> index a91fa7a..207092c 100644
> --- a/arch/arm/boards/pm9261/init.c
> +++ b/arch/arm/boards/pm9261/init.c
> @@ -34,7 +34,6 @@
> #include <mach/gpio.h>
> #include <mach/io.h>
> #include <mach/at91sam9_smc.h>
> -#include <mach/sam9_smc.h>
> #include <dm9000.h>
> #include <linux/w1-gpio.h>
> #include <w1_mac_address.h>
> @@ -84,7 +83,7 @@ static void pm_add_device_nand(void)
> pm_nand_smc_config.mode |= AT91_SMC_DBW_8;
>
> /* configure chip-select 3 (NAND) */
> - sam9_smc_configure(3, &pm_nand_smc_config);
> + sam9_smc_configure(0, 3, &pm_nand_smc_config);
>
> at91_add_device_nand(&nand_pdata);
> }
> @@ -123,7 +122,7 @@ static void __init pm_add_device_dm9000(void)
> {
> w1_local_mac_address_register(0, "ron", "w1-1-0");
> /* Configure chip-select 2 (DM9000) */
> - sam9_smc_configure(2, &dm9000_smc_config);
> + sam9_smc_configure(0, 2, &dm9000_smc_config);
>
> add_dm9000_device(0, AT91_CHIPSELECT_2, AT91_CHIPSELECT_2 + 4,
> IORESOURCE_MEM_16BIT, &dm9000_data);
> diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c
> index f719c65..f7ef148 100644
> --- a/arch/arm/boards/pm9263/init.c
> +++ b/arch/arm/boards/pm9263/init.c
> @@ -35,7 +35,6 @@
> #include <mach/gpio.h>
> #include <mach/io.h>
> #include <mach/at91sam9_smc.h>
> -#include <mach/sam9_smc.h>
> #include <linux/w1-gpio.h>
> #include <w1_mac_address.h>
>
> @@ -84,7 +83,7 @@ static void pm_add_device_nand(void)
> pm_nand_smc_config.mode |= AT91_SMC_DBW_8;
>
> /* configure chip-select 3 (NAND) */
> - sam9_smc_configure(3, &pm_nand_smc_config);
> + sam9_smc_configure(0, 3, &pm_nand_smc_config);
>
> at91_add_device_nand(&nand_pdata);
> }
> diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c
> index fabe97b..8e29f62 100644
> --- a/arch/arm/boards/pm9g45/init.c
> +++ b/arch/arm/boards/pm9g45/init.c
> @@ -34,7 +34,6 @@
> #include <mach/gpio.h>
> #include <mach/io.h>
> #include <mach/at91sam9_smc.h>
> -#include <mach/sam9_smc.h>
> #include <linux/w1-gpio.h>
> #include <w1_mac_address.h>
>
> @@ -76,7 +75,7 @@ static void pm_add_device_nand(void)
> pm_nand_smc_config.mode |= AT91_SMC_DBW_8;
>
> /* configure chip-select 3 (NAND) */
> - sam9_smc_configure(3, &pm_nand_smc_config);
> + sam9_smc_configure(0, 3, &pm_nand_smc_config);
>
> at91_add_device_nand(&nand_pdata);
> }
> diff --git a/arch/arm/boards/qil-a9260/init.c b/arch/arm/boards/qil-a9260/init.c
> index a06566c..4977d3b 100644
> --- a/arch/arm/boards/qil-a9260/init.c
> +++ b/arch/arm/boards/qil-a9260/init.c
> @@ -22,7 +22,6 @@
> #include <linux/clk.h>
> #include <mach/board.h>
> #include <mach/at91sam9_smc.h>
> -#include <mach/sam9_smc.h>
> #include <gpio.h>
> #include <led.h>
> #include <mach/io.h>
> @@ -59,7 +58,7 @@ static struct sam9_smc_config nand_smc_config = {
> static void qil_a9260_add_device_nand(void)
> {
> /* configure chip-select 3 (NAND) */
> - sam9_smc_configure(3, &nand_smc_config);
> + sam9_smc_configure(0, 3, &nand_smc_config);
>
> at91_add_device_nand(&nand_pdata);
> }
> diff --git a/arch/arm/boards/tny-a926x/init.c b/arch/arm/boards/tny-a926x/init.c
> index e30cccf..5fe6531 100644
> --- a/arch/arm/boards/tny-a926x/init.c
> +++ b/arch/arm/boards/tny-a926x/init.c
> @@ -32,7 +32,6 @@
> #include <mach/board.h>
> #include <mach/at91sam9_smc.h>
> #include <mach/at91sam9_sdramc.h>
> -#include <mach/sam9_smc.h>
> #include <gpio.h>
> #include <mach/io.h>
> #include <mach/at91_pmc.h>
> @@ -100,9 +99,9 @@ static void tny_a9260_add_device_nand(void)
> {
> /* configure chip-select 3 (NAND) */
> if (machine_is_tny_a9g20())
> - sam9_smc_configure(3, &tny_a9g20_nand_smc_config);
> + sam9_smc_configure(0, 3, &tny_a9g20_nand_smc_config);
> else
> - sam9_smc_configure(3, &tny_a9260_nand_smc_config);
> + sam9_smc_configure(0, 3, &tny_a9260_nand_smc_config);
>
> if (machine_is_tny_a9263()) {
> nand_pdata.rdy_pin = AT91_PIN_PA22;
> diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c
> index dd136da..95ac6a8 100644
> --- a/arch/arm/boards/usb-a926x/init.c
> +++ b/arch/arm/boards/usb-a926x/init.c
> @@ -32,7 +32,6 @@
> #include <mach/board.h>
> #include <mach/at91sam9_smc.h>
> #include <mach/at91sam9_sdramc.h>
> -#include <mach/sam9_smc.h>
> #include <gpio.h>
> #include <led.h>
> #include <mach/io.h>
> @@ -101,9 +100,9 @@ static void usb_a9260_add_device_nand(void)
> {
> /* configure chip-select 3 (NAND) */
> if (machine_is_usb_a9g20())
> - sam9_smc_configure(3, &usb_a9g20_nand_smc_config);
> + sam9_smc_configure(0, 3, &usb_a9g20_nand_smc_config);
> else
> - sam9_smc_configure(3, &usb_a9260_nand_smc_config);
> + sam9_smc_configure(0, 3, &usb_a9260_nand_smc_config);
>
> if (machine_is_usb_a9263()) {
> nand_pdata.rdy_pin = AT91_PIN_PA22;
> diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
> index 4c76d94..2a06f0d 100644
> --- a/arch/arm/mach-at91/at91sam9260.c
> +++ b/arch/arm/mach-at91/at91sam9260.c
> @@ -236,6 +236,7 @@ static void at91sam9260_initialize(void)
> at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
>
> at91_add_pit(AT91SAM9260_BASE_PIT);
> + at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9260_BASE_SMC, 0x200);
> }
>
> AT91_SOC_START(sam9260)
> diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
> index 1efbbee..c801d9d 100644
> --- a/arch/arm/mach-at91/at91sam9261.c
> +++ b/arch/arm/mach-at91/at91sam9261.c
> @@ -228,6 +228,7 @@ static void at91sam9261_initialize(void)
> at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
>
> at91_add_pit(AT91SAM9261_BASE_PIT);
> + at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9261_BASE_SMC, 0x200);
> }
>
> AT91_SOC_START(sam9261)
> diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
> index e1fbe6f..42777d0 100644
> --- a/arch/arm/mach-at91/at91sam9263.c
> +++ b/arch/arm/mach-at91/at91sam9263.c
> @@ -247,6 +247,8 @@ static void at91sam9263_initialize(void)
> at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
>
> at91_add_pit(AT91SAM9263_BASE_PIT);
> + at91_add_sam9_smc(0, AT91SAM9263_BASE_SMC0, 0x200);
> + at91_add_sam9_smc(1, AT91SAM9263_BASE_SMC1, 0x200);
> }
>
> AT91_SOC_START(sam9263)
> diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
> index 5edbd8b..6e4101d 100644
> --- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
> +++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
> @@ -62,13 +62,13 @@ void __naked __bare_init reset(void)
> #endif
>
> /* flash */
> - at91_sys_write(AT91_SMC_MODE(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_MODE_VAL);
> + at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_MODE, CONFIG_SYS_SMC_MODE_VAL);
>
> - at91_sys_write(AT91_SMC_CYCLE(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_CYCLE_VAL);
> + at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_CYCLE, CONFIG_SYS_SMC_CYCLE_VAL);
>
> - at91_sys_write(AT91_SMC_PULSE(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_PULSE_VAL);
> + at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_PULSE, CONFIG_SYS_SMC_PULSE_VAL);
>
> - at91_sys_write(AT91_SMC_SETUP(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_SETUP_VAL);
> + at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_SETUP, CONFIG_SYS_SMC_SETUP_VAL);
>
> /*
> * PMC Check if the PLL is already initialized
> diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
> index 94fee59..7ca1f3b 100644
> --- a/arch/arm/mach-at91/at91sam9g45.c
> +++ b/arch/arm/mach-at91/at91sam9g45.c
> @@ -259,6 +259,7 @@ static void at91sam9g45_initialize(void)
> at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
>
> at91_add_pit(AT91SAM9G45_BASE_PIT);
> + at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9G45_BASE_SMC, 0x200);
> }
>
> AT91_SOC_START(sam9g45)
> diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
> index d1b7ce1..967885a 100644
> --- a/arch/arm/mach-at91/at91sam9n12.c
> +++ b/arch/arm/mach-at91/at91sam9n12.c
> @@ -219,6 +219,7 @@ static void at91sam9n12_initialize(void)
> at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
>
> at91_add_pit(AT91SAM9N12_BASE_PIT);
> + at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9N12_BASE_SMC, 0x200);
> }
>
> AT91_SOC_START(sam9n12)
> diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
> index 7b58e12..090d9dd 100644
> --- a/arch/arm/mach-at91/at91sam9x5.c
> +++ b/arch/arm/mach-at91/at91sam9x5.c
> @@ -304,6 +304,7 @@ static void at91sam9x5_initialize(void)
> at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
>
> at91_add_pit(AT91SAM9X5_BASE_PIT);
> + at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9X5_BASE_SMC, 0x200);
> }
>
> AT91_SOC_START(sam9x5)
> diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
> index 490cf3c..a19c1c5 100644
> --- a/arch/arm/mach-at91/generic.h
> +++ b/arch/arm/mach-at91/generic.h
> @@ -28,3 +28,10 @@ static inline struct device_d *at91_add_pit(resource_size_t start)
> return add_generic_device("at91-pit", DEVICE_ID_SINGLE, NULL, start, 16,
> IORESOURCE_MEM, NULL);
> }
> +
> +static inline struct device_d *at91_add_sam9_smc(int id, resource_size_t start,
> + resource_size_t size)
> +{
> + return add_generic_device("at91sam9-smc", id, NULL, start, size,
> + IORESOURCE_MEM, NULL);
> +}
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
> index 5d1b376..0804dc3 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9260.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
> @@ -100,13 +100,14 @@
> */
> #define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
> #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
> -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
> #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
> #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
> #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
>
> +#define AT91_BASE_SMC AT91SAM9260_BASE_SMC
> +#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
> #define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
> #define AT91_BASE_PIOB AT91SAM9260_BASE_PIOB
> #define AT91_BASE_PIOC AT91SAM9260_BASE_PIOC
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
> index 1469f7e..0565e1b 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9261.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
> @@ -86,13 +86,13 @@
> * System Peripherals (offset from AT91_BASE_SYS)
> */
> #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
> -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
> #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
> #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
> #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
>
> +#define AT91_BASE_SMC AT91SAM9261_BASE_SMC
> #define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA
> #define AT91_BASE_PIOB AT91SAM9261_BASE_PIOB
> #define AT91_BASE_PIOC AT91SAM9261_BASE_PIOC
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
> index a8c067a..9eff27a 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9263.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
> @@ -104,13 +104,13 @@
> */
> #define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
> #define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
> -#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
> #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
> #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
> #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
>
> +#define AT91_BASE_SMC AT91SAM9263_BASE_SMC0
> #define AT91_BASE_PIOA AT91SAM9263_BASE_PIOA
> #define AT91_BASE_PIOB AT91SAM9263_BASE_PIOB
> #define AT91_BASE_PIOC AT91SAM9263_BASE_PIOC
> @@ -122,7 +122,6 @@
> #define AT91_USART2 AT91SAM9263_BASE_US2
> #define AT91_NB_USART 4
>
> -#define AT91_SMC AT91_SMC0
> #define AT91_SDRAMC AT91_SDRAMC0
>
> #define AT91_BASE_SPI AT91SAM9263_BASE_SPI0
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
> index d64511b..d5cf5f7 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
> @@ -16,7 +16,42 @@
> #ifndef AT91SAM9_SMC_H
> #define AT91SAM9_SMC_H
>
> -#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
> +#define at91_smc_read(id, field) \
> + __raw_readl(AT91_BASE_SMC + ((id) * 0x10) + field)
> +
> +#define at91_smc_write(id, field, value) \
> + __raw_writel(value, AT91_BASE_SMC + ((id) * 0x10) + field)
> +
> +#ifndef __ASSEMBLY__
> +struct sam9_smc_config {
> + /* Setup register */
> + u8 ncs_read_setup;
> + u8 nrd_setup;
> + u8 ncs_write_setup;
> + u8 nwe_setup;
> +
> + /* Pulse register */
> + u8 ncs_read_pulse;
> + u8 nrd_pulse;
> + u8 ncs_write_pulse;
> + u8 nwe_pulse;
> +
> + /* Cycle register */
> + u16 read_cycle;
> + u16 write_cycle;
> +
> + /* Mode register */
> + u32 mode;
> + u8 tdf_cycles:4;
> +};
> +
> +extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
> +extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
> +extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
> +extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
> +#endif
> +
> +#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
> #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
> #define AT91_SMC_NWESETUP_(x) ((x) << 0)
> #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
> @@ -26,7 +61,7 @@
> #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
> #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
>
> -#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
> +#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */
> #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
> #define AT91_SMC_NWEPULSE_(x) ((x) << 0)
> #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
> @@ -36,13 +71,13 @@
> #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
> #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
>
> -#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
> +#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */
> #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
> #define AT91_SMC_NWECYCLE_(x) ((x) << 0)
> #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
> #define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
>
> -#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
> +#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */
> #define AT91_SMC_READMODE (1 << 0) /* Read Mode */
> #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
> #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
> @@ -66,11 +101,4 @@
> #define AT91_SMC_PS_16 (2 << 28)
> #define AT91_SMC_PS_32 (3 << 28)
>
> -#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
> -#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
> -#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
> -#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
> -#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
> -#endif
> -
> #endif
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
> index 85ed129..9c5234a 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
> @@ -115,13 +115,13 @@
> #define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
> #define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
> #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
> -#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
> #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
> #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
> #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
>
> +#define AT91_BASE_SMC AT91SAM9G45_BASE_SMC
> #define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA
> #define AT91_BASE_PIOB AT91SAM9G45_BASE_PIOB
> #define AT91_BASE_PIOC AT91SAM9G45_BASE_PIOC
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
> index 59d7030..b55e5f0 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
> @@ -112,12 +112,12 @@
> #define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)
> #define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)
> #define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
> -#define AT91_SMC (0xffffea00 - AT91_BASE_SYS)
> #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
> #define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
>
> +#define AT91_BASE_SMC AT91SAM9N12_BASE_SMC
> #define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA
> #define AT91_BASE_PIOB AT91SAM9N12_BASE_PIOB
> #define AT91_BASE_PIOC AT91SAM9N12_BASE_PIOC
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> index 63a5138..8a48eed 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> @@ -119,12 +119,12 @@
> #define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)
> #define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)
> #define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
> -#define AT91_SMC (0xffffea00 - AT91_BASE_SYS)
> #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
> #define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
> #define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
> #define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
>
> +#define AT91_BASE_SMC AT91SAM9X5_BASE_SMC
> #define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA
> #define AT91_BASE_PIOB AT91SAM9X5_BASE_PIOB
> #define AT91_BASE_PIOC AT91SAM9X5_BASE_PIOC
> diff --git a/arch/arm/mach-at91/include/mach/sam9_smc.h b/arch/arm/mach-at91/include/mach/sam9_smc.h
> deleted file mode 100644
> index bf72cfb..0000000
> --- a/arch/arm/mach-at91/include/mach/sam9_smc.h
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -/*
> - * linux/arch/arm/mach-at91/sam9_smc.
> - *
> - * Copyright (C) 2008 Andrew Victor
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -struct sam9_smc_config {
> - /* Setup register */
> - u8 ncs_read_setup;
> - u8 nrd_setup;
> - u8 ncs_write_setup;
> - u8 nwe_setup;
> -
> - /* Pulse register */
> - u8 ncs_read_pulse;
> - u8 nrd_pulse;
> - u8 ncs_write_pulse;
> - u8 nwe_pulse;
> -
> - /* Cycle register */
> - u16 read_cycle;
> - u16 write_cycle;
> -
> - /* Mode register */
> - u32 mode;
> - u8 tdf_cycles:4;
> -};
> -
> -extern void __init sam9_smc_configure(int cs, struct sam9_smc_config* config);
> diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
> index c397fe4..b48275e 100644
> --- a/arch/arm/mach-at91/sam9_smc.c
> +++ b/arch/arm/mach-at91/sam9_smc.c
> @@ -9,40 +9,142 @@
> */
>
> #include <common.h>
> +#include <init.h>
> #include <io.h>
> #include <mach/hardware.h>
> #include <mach/io.h>
>
> #include <mach/at91sam9_smc.h>
> -#include <mach/sam9_smc.h>
>
> -void sam9_smc_configure(int cs, struct sam9_smc_config* config)
> +#define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x10))
> +
> +static void __iomem *smc_base_addr[2];
> +
> +static void sam9_smc_cs_write_mode(void __iomem *base,
> + struct sam9_smc_config *config)
> +{
> + __raw_writel(config->mode
> + | AT91_SMC_TDF_(config->tdf_cycles),
> + base + AT91_SMC_MODE);
> +}
> +
> +void sam9_smc_write_mode(int id, int cs,
> + struct sam9_smc_config *config)
> +{
> + sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
> +}
> +
> +static void sam9_smc_cs_configure(void __iomem *base,
> + struct sam9_smc_config *config)
> +{
> +
> + /* Setup register */
> + __raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup)
> + | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
> + | AT91_SMC_NRDSETUP_(config->nrd_setup)
> + | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),
> + base + AT91_SMC_SETUP);
> +
> + /* Pulse register */
> + __raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)
> + | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
> + | AT91_SMC_NRDPULSE_(config->nrd_pulse)
> + | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),
> + base + AT91_SMC_PULSE);
> +
> + /* Cycle register */
> + __raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle)
> + | AT91_SMC_NRDCYCLE_(config->read_cycle),
> + base + AT91_SMC_CYCLE);
> +
> + /* Mode register */
> + sam9_smc_cs_write_mode(base, config);
> +}
> +
> +void sam9_smc_configure(int id, int cs,
> + struct sam9_smc_config *config)
> +{
> + sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
> +}
> +
> +static void sam9_smc_cs_read_mode(void __iomem *base,
> + struct sam9_smc_config *config)
> +{
> + u32 val = __raw_readl(base + AT91_SMC_MODE);
> +
> + config->mode = (val & ~AT91_SMC_NWECYCLE);
> + config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ;
> +}
> +
> +void sam9_smc_read_mode(int id, int cs,
> + struct sam9_smc_config *config)
> +{
> + sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
> +}
> +
> +static void sam9_smc_cs_read(void __iomem *base,
> + struct sam9_smc_config *config)
> {
> + u32 val;
> +
> /* Setup register */
> - at91_sys_write(AT91_SMC_SETUP(cs),
> - AT91_SMC_NWESETUP_(config->nwe_setup)
> - | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
> - | AT91_SMC_NRDSETUP_(config->nrd_setup)
> - | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup)
> - );
> + val = __raw_readl(base + AT91_SMC_SETUP);
> +
> + config->nwe_setup = val & AT91_SMC_NWESETUP;
> + config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8;
> + config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16;
> + config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24;
>
> /* Pulse register */
> - at91_sys_write(AT91_SMC_PULSE(cs),
> - AT91_SMC_NWEPULSE_(config->nwe_pulse)
> - | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
> - | AT91_SMC_NRDPULSE_(config->nrd_pulse)
> - | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse)
> - );
> + val = __raw_readl(base + AT91_SMC_PULSE);
> +
> + config->nwe_setup = val & AT91_SMC_NWEPULSE;
> + config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
> + config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
> + config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
>
> /* Cycle register */
> - at91_sys_write(AT91_SMC_CYCLE(cs),
> - AT91_SMC_NWECYCLE_(config->write_cycle)
> - | AT91_SMC_NRDCYCLE_(config->read_cycle)
> - );
> + val = __raw_readl(base + AT91_SMC_CYCLE);
> +
> + config->write_cycle = val & AT91_SMC_NWECYCLE;
> + config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16;
>
> /* Mode register */
> - at91_sys_write(AT91_SMC_MODE(cs),
> - config->mode
> - | AT91_SMC_TDF_(config->tdf_cycles)
> - );
> + sam9_smc_cs_read_mode(base, config);
> +}
> +
> +void sam9_smc_read(int id, int cs, struct sam9_smc_config *config)
> +{
> + sam9_smc_cs_read(AT91_SMC_CS(id, cs), config);
> +}
> +
> +static int at91sam9_smc_probe(struct device_d *dev)
> +{
> + int id;
> +
> + if (dev->id < 0) {
> + id = 0;
> + } else if (dev->id > 1) {
> + dev_warn(dev, ": id > 2\n");
> + return -EIO;
> + }
> +
> + smc_base_addr[id] = dev_request_mem_region(dev, 0);
> + if (!smc_base_addr[id]) {
> + dev_err(dev, "Impossible to request smc.%d\n", id);
> + return -ENOMEM;
> + }
> +
> + return 0;
> +}
> +
> +static struct driver_d at91sam9_smc_driver = {
> + .name = "at91sam9-smc",
> + .probe = at91sam9_smc_probe,
> +};
> +
> +static int at91sam9_smc_init(void)
> +{
> + return platform_driver_register(&at91sam9_smc_driver);
> }
> +coredevice_initcall(at91sam9_smc_init);
> --
> 1.7.10.4
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 11/13] at91: wdt: drop AT91_SYS_BASE
2012-12-28 19:16 ` [PATCH 01/13] at91: factorise dbgu address Jean-Christophe PLAGNIOL-VILLARD
` (8 preceding siblings ...)
2012-12-28 19:16 ` [PATCH 10/13] at91: SMC: switch to platfrom_driver Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-28 19:16 ` Jean-Christophe PLAGNIOL-VILLARD
2012-12-28 19:16 ` [PATCH 12/13] at91: introduce AT91SAM9_SMC and AT91SAM9_TIMER Jean-Christophe PLAGNIOL-VILLARD
2012-12-28 19:16 ` [PATCH 13/13] at91: drop AT91_BASE_PIOx for soc specific one for none boot code Jean-Christophe PLAGNIOL-VILLARD
11 siblings, 0 replies; 19+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-28 19:16 UTC (permalink / raw)
To: barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 2 +-
arch/arm/mach-at91/include/mach/at91_wdt.h | 6 +++---
arch/arm/mach-at91/include/mach/at91sam9260.h | 2 +-
arch/arm/mach-at91/include/mach/at91sam9261.h | 2 +-
arch/arm/mach-at91/include/mach/at91sam9263.h | 2 +-
arch/arm/mach-at91/include/mach/at91sam9g45.h | 2 +-
arch/arm/mach-at91/include/mach/at91sam9n12.h | 2 +-
arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 +-
8 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
index 6e4101d..cfae982 100644
--- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
@@ -43,7 +43,7 @@ void __naked __bare_init reset(void)
common_reset();
- at91_sys_write(AT91_WDT_MR, CONFIG_SYS_WDTC_WDMR_VAL);
+ __raw_writel(CONFIG_SYS_WDTC_WDMR_VAL, AT91_BASE_WDT + AT91_WDT_MR);
/* configure PIOx as EBI0 D[16-31] */
#ifdef CONFIG_ARCH_AT91SAM9263
diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h
index 7e18537..36d37b9 100644
--- a/arch/arm/mach-at91/include/mach/at91_wdt.h
+++ b/arch/arm/mach-at91/include/mach/at91_wdt.h
@@ -17,11 +17,11 @@
#ifndef AT91_WDT_H
#define AT91_WDT_H
-#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */
+#define AT91_WDT_CR 0x00 /* Watchdog Control Register */
#define AT91_WDT_WDRSTT (1 << 0) /* Restart */
#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */
-#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */
+#define AT91_WDT_MR 0x04 /* Watchdog Mode Register */
#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
@@ -31,7 +31,7 @@
#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
-#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */
+#define AT91_WDT_SR 0x08 /* Watchdog Status Register */
#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 0804dc3..3f3a0e1 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -104,8 +104,8 @@
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_BASE_WDT AT91SAM9260_BASE_WDT
#define AT91_BASE_SMC AT91SAM9260_BASE_SMC
#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 0565e1b..1b48e23 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -90,8 +90,8 @@
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_BASE_WDT AT91SAM9261_BASE_WDT
#define AT91_BASE_SMC AT91SAM9261_BASE_SMC
#define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9261_BASE_PIOB
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 9eff27a..b42d191 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -108,8 +108,8 @@
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_BASE_WDT AT91SAM9263_BASE_WDT
#define AT91_BASE_SMC AT91SAM9263_BASE_SMC0
#define AT91_BASE_PIOA AT91SAM9263_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9263_BASE_PIOB
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 9c5234a..c81bb80 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -119,8 +119,8 @@
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_BASE_WDT AT91SAM9G45_BASE_WDT
#define AT91_BASE_SMC AT91SAM9G45_BASE_SMC
#define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9G45_BASE_PIOB
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
index b55e5f0..26bdd13 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -115,8 +115,8 @@
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
-#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
+#define AT91_BASE_WDT AT91SAM9N12_BASE_WDT
#define AT91_BASE_SMC AT91SAM9N12_BASE_SMC
#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9N12_BASE_PIOB
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 8a48eed..13b4f44 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -122,8 +122,8 @@
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
-#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
+#define AT91_BASE_WDT AT91SAM9X5_BASE_WDT
#define AT91_BASE_SMC AT91SAM9X5_BASE_SMC
#define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9X5_BASE_PIOB
--
1.7.10.4
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^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH 12/13] at91: introduce AT91SAM9_SMC and AT91SAM9_TIMER
2012-12-28 19:16 ` [PATCH 01/13] at91: factorise dbgu address Jean-Christophe PLAGNIOL-VILLARD
` (9 preceding siblings ...)
2012-12-28 19:16 ` [PATCH 11/13] at91: wdt: drop AT91_SYS_BASE Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-28 19:16 ` Jean-Christophe PLAGNIOL-VILLARD
2012-12-28 19:16 ` [PATCH 13/13] at91: drop AT91_BASE_PIOx for soc specific one for none boot code Jean-Christophe PLAGNIOL-VILLARD
11 siblings, 0 replies; 19+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-28 19:16 UTC (permalink / raw)
To: barebox
to select the smc and timer for at91sam9 soc
This will allow to simplify the Makefile
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/mach-at91/Kconfig | 24 ++++++++++++++++++------
arch/arm/mach-at91/Makefile | 19 +++++++++++--------
2 files changed, 29 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index d470e5c..fcba7fb 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -6,6 +6,18 @@ config HAVE_AT91_DBGU0
config HAVE_AT91_DBGU1
bool
+config AT91SAM9_SMC
+ bool
+
+config AT91SAM9_TIMER
+ bool
+
+config SOC_AT91SAM9
+ bool
+ select CPU_ARM926T
+ select AT91SAM9_SMC
+ select AT91SAM9_TIMER
+
config ARCH_TEXT_BASE
hex
default 0x73f00000 if ARCH_AT91SAM9G45
@@ -58,7 +70,7 @@ config SOC_AT91RM9200
config SOC_AT91SAM9260
bool
- select CPU_ARM926T
+ select SOC_AT91SAM9
select HAVE_AT91_DBGU0
select HAS_MACB
select AT91SAM9_RESET
@@ -68,7 +80,7 @@ config SOC_AT91SAM9260
config SOC_AT91SAM9261
bool
- select CPU_ARM926T
+ select SOC_AT91SAM9
select HAVE_AT91_DBGU0
select AT91SAM9_RESET
help
@@ -76,14 +88,14 @@ config SOC_AT91SAM9261
config SOC_AT91SAM9263
bool
- select CPU_ARM926T
+ select SOC_AT91SAM9
select HAVE_AT91_DBGU1
select HAS_MACB
select AT91SAM9_RESET
config SOC_AT91SAM9G45
bool
- select CPU_ARM926T
+ select SOC_AT91SAM9
select HAVE_AT91_DBGU1
select HAS_MACB
select AT91SAM9G45_RESET
@@ -93,7 +105,7 @@ config SOC_AT91SAM9G45
config SOC_AT91SAM9X5
bool
- select CPU_ARM926T
+ select SOC_AT91SAM9
select HAVE_AT91_DBGU0
select HAS_MACB
select AT91SAM9G45_RESET
@@ -106,7 +118,7 @@ config SOC_AT91SAM9X5
config SOC_AT91SAM9N12
bool
- select CPU_ARM926T
+ select SOC_AT91SAM9
select HAVE_AT91_DBGU0
select AT91SAM9G45_RESET
help
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 865988e..53b4dd8 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -9,13 +9,16 @@ pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
obj-$(CONFIG_AT91SAM9_RESET) += at91sam9_reset.o
obj-$(CONFIG_AT91SAM9G45_RESET) += at91sam9g45_reset.o
+obj-$(CONFIG_AT91SAM9_SMC) += sam9_smc.o
+obj-$(CONFIG_AT91SAM9_TIMER) += at91sam926x_time.o
+
# CPU-specific support
obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o at91sam9x5_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9N12) += at91sam9n12.o at91sam926x_time.o at91sam9n12_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam9261_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam9261_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam9x5_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9N12) += at91sam9n12.o at91sam9n12_devices.o
--
1.7.10.4
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^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH 13/13] at91: drop AT91_BASE_PIOx for soc specific one for none boot code
2012-12-28 19:16 ` [PATCH 01/13] at91: factorise dbgu address Jean-Christophe PLAGNIOL-VILLARD
` (10 preceding siblings ...)
2012-12-28 19:16 ` [PATCH 12/13] at91: introduce AT91SAM9_SMC and AT91SAM9_TIMER Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-28 19:16 ` Jean-Christophe PLAGNIOL-VILLARD
11 siblings, 0 replies; 19+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-28 19:16 UTC (permalink / raw)
To: barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/mach-at91/at91rm9200.c | 8 ++++----
arch/arm/mach-at91/at91sam9260.c | 6 +++---
arch/arm/mach-at91/at91sam9261.c | 6 +++---
arch/arm/mach-at91/at91sam9263.c | 10 +++++-----
arch/arm/mach-at91/at91sam9g45.c | 10 +++++-----
arch/arm/mach-at91/at91sam9n12.c | 8 ++++----
arch/arm/mach-at91/at91sam9x5.c | 8 ++++----
7 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index d3aedea..8eeaa55 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -232,10 +232,10 @@ static void __init at91rm9200_initialize(void)
at91rm9200_register_clocks();
/* Register GPIO subsystem */
- at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
- at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
- at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
- at91_add_rm9200_gpio(3, AT91_BASE_PIOD);
+ at91_add_rm9200_gpio(0, AT91RM9200_BASE_PIOA);
+ at91_add_rm9200_gpio(1, AT91RM9200_BASE_PIOB);
+ at91_add_rm9200_gpio(2, AT91RM9200_BASE_PIOC);
+ at91_add_rm9200_gpio(3, AT91RM9200_BASE_PIOD);
}
AT91_SOC_START(rm9200)
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 2a06f0d..fa65fe7 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -231,9 +231,9 @@ static void at91sam9260_initialize(void)
at91sam9260_register_clocks();
/* Register GPIO subsystem */
- at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
- at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
- at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
+ at91_add_rm9200_gpio(0, AT91SAM9260_BASE_PIOA);
+ at91_add_rm9200_gpio(1, AT91SAM9260_BASE_PIOB);
+ at91_add_rm9200_gpio(2, AT91SAM9260_BASE_PIOC);
at91_add_pit(AT91SAM9260_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9260_BASE_SMC, 0x200);
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index c801d9d..edac177 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -223,9 +223,9 @@ static void at91sam9261_initialize(void)
at91sam9261_register_clocks();
/* Register GPIO subsystem */
- at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
- at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
- at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
+ at91_add_rm9200_gpio(0, AT91SAM9261_BASE_PIOA);
+ at91_add_rm9200_gpio(1, AT91SAM9261_BASE_PIOB);
+ at91_add_rm9200_gpio(2, AT91SAM9261_BASE_PIOC);
at91_add_pit(AT91SAM9261_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9261_BASE_SMC, 0x200);
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 42777d0..eeea1ce 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -240,11 +240,11 @@ static void at91sam9263_initialize(void)
at91sam9263_register_clocks();
/* Register GPIO subsystem */
- at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
- at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
- at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
- at91_add_rm9200_gpio(3, AT91_BASE_PIOD);
- at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
+ at91_add_rm9200_gpio(0, AT91SAM9263_BASE_PIOA);
+ at91_add_rm9200_gpio(1, AT91SAM9263_BASE_PIOB);
+ at91_add_rm9200_gpio(2, AT91SAM9263_BASE_PIOC);
+ at91_add_rm9200_gpio(3, AT91SAM9263_BASE_PIOD);
+ at91_add_rm9200_gpio(4, AT91SAM9263_BASE_PIOE);
at91_add_pit(AT91SAM9263_BASE_PIT);
at91_add_sam9_smc(0, AT91SAM9263_BASE_SMC0, 0x200);
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 7ca1f3b..7118efe 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -252,11 +252,11 @@ static void at91sam9g45_initialize(void)
at91sam9g45_register_clocks();
/* Register GPIO subsystem */
- at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
- at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
- at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
- at91_add_rm9200_gpio(3, AT91_BASE_PIOD);
- at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
+ at91_add_rm9200_gpio(0, AT91SAM9G45_BASE_PIOA);
+ at91_add_rm9200_gpio(1, AT91SAM9G45_BASE_PIOB);
+ at91_add_rm9200_gpio(2, AT91SAM9G45_BASE_PIOC);
+ at91_add_rm9200_gpio(3, AT91SAM9G45_BASE_PIOD);
+ at91_add_rm9200_gpio(4, AT91SAM9G45_BASE_PIOE);
at91_add_pit(AT91SAM9G45_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9G45_BASE_SMC, 0x200);
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 967885a..c177975 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -213,10 +213,10 @@ static void at91sam9n12_initialize(void)
at91sam9n12_register_clocks();
/* Register GPIO subsystem */
- at91_add_sam9x5_gpio(0, AT91_BASE_PIOA);
- at91_add_sam9x5_gpio(1, AT91_BASE_PIOB);
- at91_add_sam9x5_gpio(2, AT91_BASE_PIOC);
- at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
+ at91_add_sam9x5_gpio(0, AT91SAM9N12_BASE_PIOA);
+ at91_add_sam9x5_gpio(1, AT91SAM9N12_BASE_PIOB);
+ at91_add_sam9x5_gpio(2, AT91SAM9N12_BASE_PIOC);
+ at91_add_sam9x5_gpio(3, AT91SAM9N12_BASE_PIOD);
at91_add_pit(AT91SAM9N12_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9N12_BASE_SMC, 0x200);
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 090d9dd..5d43423 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -298,10 +298,10 @@ static void at91sam9x5_initialize(void)
at91sam9x5_register_clocks();
/* Register GPIO subsystem */
- at91_add_sam9x5_gpio(0, AT91_BASE_PIOA);
- at91_add_sam9x5_gpio(1, AT91_BASE_PIOB);
- at91_add_sam9x5_gpio(2, AT91_BASE_PIOC);
- at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
+ at91_add_sam9x5_gpio(0, AT91SAM9X5_BASE_PIOA);
+ at91_add_sam9x5_gpio(1, AT91SAM9X5_BASE_PIOB);
+ at91_add_sam9x5_gpio(2, AT91SAM9X5_BASE_PIOC);
+ at91_add_sam9x5_gpio(3, AT91SAM9X5_BASE_PIOD);
at91_add_pit(AT91SAM9X5_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9X5_BASE_SMC, 0x200);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 19+ messages in thread