[PATCH 01/11] ARM: clps711x: Move lowlevel initialization in common CLPS711X location

[PATCH 01/11] ARM: clps711x: Move lowlevel initialization in common CLPS711X location

[Alexander Shiyan]

One lowlevel initialization will be used on any CLPS711X-target,
so move it in the common location.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/boards/clep7212/Makefile   |    3 +-
 arch/arm/boards/clep7212/lowlevel.c |   57 -----------------------------------
 arch/arm/mach-clps711x/Makefile     |    3 +-
 arch/arm/mach-clps711x/lowlevel.c   |   57 +++++++++++++++++++++++++++++++++++
 4 files changed, 60 insertions(+), 60 deletions(-)
 delete mode 100644 arch/arm/boards/clep7212/lowlevel.c
 create mode 100644 arch/arm/mach-clps711x/lowlevel.c

diff --git a/arch/arm/boards/clep7212/Makefile b/arch/arm/boards/clep7212/Makefile
index a63aeae..676e867 100644
--- a/arch/arm/boards/clep7212/Makefile
+++ b/arch/arm/boards/clep7212/Makefile
@@ -1,2 +1 @@
-obj-y += lowlevel.o clep7212.o
-pbl-y += lowlevel.o
+obj-y += clep7212.o
diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
deleted file mode 100644
index b4d1bf1..0000000
--- a/arch/arm/boards/clep7212/lowlevel.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- */
-
-#include <common.h>
-#include <init.h>
-#include <sizes.h>
-
-#include <asm/io.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-
-#include <mach/clps711x.h>
-
-#define MAIN_CLOCK		3686400
-#define CPU_SPEED		92160000
-#define BUS_SPEED		(CPU_SPEED / 2)
-
-#define PLL_VALUE		(((CPU_SPEED * 2) / MAIN_CLOCK) << 24)
-#define SDRAM_REFRESH_RATE	(64 * (BUS_SPEED / (8192 * 1000)))
-
-void __naked __bare_init barebox_arm_reset_vector(void)
-{
-	u32 tmp;
-
-	arm_cpu_lowlevel_init();
-
-	/* Setup base clock */
-	writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3);
-	asm("nop");
-
-	/* Setup PLL */
-	writel(PLL_VALUE, PLLW);
-	asm("nop");
-
-	/* CLKEN select, SDRAM width=32 */
-	writel(SYSCON2_CLKENSL, SYSCON2);
-
-	/* Enable SDQM pins */
-	tmp = readl(SYSCON3);
-	tmp &= ~SYSCON3_ENPD67;
-	writel(tmp, SYSCON3);
-
-	/* Setup Refresh Rate (64ms 8K Blocks) */
-	writel(SDRAM_REFRESH_RATE, SDRFPR);
-
-	/* Setup SDRAM (32MB, 16Bit*2, CAS=3) */
-	writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 |
-	       SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF);
-
-	barebox_arm_entry(SDRAM0_BASE, SZ_32M, 0);
-}
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index 41012bc..69a4a3c 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -1 +1,2 @@
-obj-y += clock.o devices.o reset.o
+obj-y += clock.o devices.o lowlevel.o reset.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c
new file mode 100644
index 0000000..b4d1bf1
--- /dev/null
+++ b/arch/arm/mach-clps711x/lowlevel.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <sizes.h>
+
+#include <asm/io.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+
+#include <mach/clps711x.h>
+
+#define MAIN_CLOCK		3686400
+#define CPU_SPEED		92160000
+#define BUS_SPEED		(CPU_SPEED / 2)
+
+#define PLL_VALUE		(((CPU_SPEED * 2) / MAIN_CLOCK) << 24)
+#define SDRAM_REFRESH_RATE	(64 * (BUS_SPEED / (8192 * 1000)))
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	u32 tmp;
+
+	arm_cpu_lowlevel_init();
+
+	/* Setup base clock */
+	writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3);
+	asm("nop");
+
+	/* Setup PLL */
+	writel(PLL_VALUE, PLLW);
+	asm("nop");
+
+	/* CLKEN select, SDRAM width=32 */
+	writel(SYSCON2_CLKENSL, SYSCON2);
+
+	/* Enable SDQM pins */
+	tmp = readl(SYSCON3);
+	tmp &= ~SYSCON3_ENPD67;
+	writel(tmp, SYSCON3);
+
+	/* Setup Refresh Rate (64ms 8K Blocks) */
+	writel(SDRAM_REFRESH_RATE, SDRFPR);
+
+	/* Setup SDRAM (32MB, 16Bit*2, CAS=3) */
+	writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 |
+	       SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF);
+
+	barebox_arm_entry(SDRAM0_BASE, SZ_32M, 0);
+}
-- 
1.7.3.4


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[PATCH 02/11] ARM: clps711x: Fix SDRAM setup comment

[Alexander Shiyan]

We are set up maximum SDRAM size 64MB, so fix comment text.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/mach-clps711x/lowlevel.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c
index b4d1bf1..0249c60 100644
--- a/arch/arm/mach-clps711x/lowlevel.c
+++ b/arch/arm/mach-clps711x/lowlevel.c
@@ -49,7 +49,7 @@ void __naked __bare_init barebox_arm_reset_vector(void)
 	/* Setup Refresh Rate (64ms 8K Blocks) */
 	writel(SDRAM_REFRESH_RATE, SDRFPR);
 
-	/* Setup SDRAM (32MB, 16Bit*2, CAS=3) */
+	/* Setup SDRAM params (64MB, 16Bit*2, CAS=3) */
 	writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 |
 	       SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF);
 
-- 
1.7.3.4


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[PATCH 03/11] ARM: clps711x: Adds config option for CPU PLL multiplier

[Alexander Shiyan]

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/mach-clps711x/Kconfig    |   13 +++++++++++++
 arch/arm/mach-clps711x/lowlevel.c |    4 ++--
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index f0adeda..d2873b4 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -10,6 +10,19 @@ config MACH_CLEP7212
 
 endchoice
 
+menu "CLPS711X specific settings"
+
+config CLPS711X_CPU_PLL_MULT
+	int "CPU PLL multiplier (20-50)"
+	range 20 50
+	default "40"
+	help
+	  Define CPU PLL multiplier. PLL is calculated by formula:
+	    PLL Frequency = (PLL Multiplier / 2) * 3686400 Hz
+	  Default value is 40, for achieve 73 MHz.
+
+endmenu
+
 config BOARDINFO
 	default "Cirrus Logic CLEP7212" if MACH_CLEP7212
 
diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c
index 0249c60..245ac93 100644
--- a/arch/arm/mach-clps711x/lowlevel.c
+++ b/arch/arm/mach-clps711x/lowlevel.c
@@ -18,10 +18,10 @@
 #include <mach/clps711x.h>
 
 #define MAIN_CLOCK		3686400
-#define CPU_SPEED		92160000
+#define CPU_SPEED		((CONFIG_CLPS711X_CPU_PLL_MULT * MAIN_CLOCK) / 2)
 #define BUS_SPEED		(CPU_SPEED / 2)
 
-#define PLL_VALUE		(((CPU_SPEED * 2) / MAIN_CLOCK) << 24)
+#define PLL_VALUE		(CONFIG_CLPS711X_CPU_PLL_MULT << 24)
 #define SDRAM_REFRESH_RATE	(64 * (BUS_SPEED / (8192 * 1000)))
 
 void __naked __bare_init barebox_arm_reset_vector(void)
-- 
1.7.3.4


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Re: [PATCH 03/11] ARM: clps711x: Adds config option for CPU PLL multiplier

[Jean-Christophe PLAGNIOL-VILLARD]

On 14:02 Fri 08 Feb     , Alexander Shiyan wrote:
> 
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> ---
>  arch/arm/mach-clps711x/Kconfig    |   13 +++++++++++++
>  arch/arm/mach-clps711x/lowlevel.c |    4 ++--
>  2 files changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
> index f0adeda..d2873b4 100644
> --- a/arch/arm/mach-clps711x/Kconfig
> +++ b/arch/arm/mach-clps711x/Kconfig
> @@ -10,6 +10,19 @@ config MACH_CLEP7212
>  
>  endchoice
>  
> +menu "CLPS711X specific settings"
> +
> +config CLPS711X_CPU_PLL_MULT
> +	int "CPU PLL multiplier (20-50)"
> +	range 20 50
> +	default "40"
> +	help
> +	  Define CPU PLL multiplier. PLL is calculated by formula:
> +	    PLL Frequency = (PLL Multiplier / 2) * 3686400 Hz
> +	  Default value is 40, for achieve 73 MHz.
> +
this board specific put this in c code
kconfig is too easy to break

check how we do on at91

Best Regards,
J.
> +endmenu
> +
>  config BOARDINFO
>  	default "Cirrus Logic CLEP7212" if MACH_CLEP7212
>  
> diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c
> index 0249c60..245ac93 100644
> --- a/arch/arm/mach-clps711x/lowlevel.c
> +++ b/arch/arm/mach-clps711x/lowlevel.c
> @@ -18,10 +18,10 @@
>  #include <mach/clps711x.h>
>  
>  #define MAIN_CLOCK		3686400
> -#define CPU_SPEED		92160000
> +#define CPU_SPEED		((CONFIG_CLPS711X_CPU_PLL_MULT * MAIN_CLOCK) / 2)
>  #define BUS_SPEED		(CPU_SPEED / 2)
>  
> -#define PLL_VALUE		(((CPU_SPEED * 2) / MAIN_CLOCK) << 24)
> +#define PLL_VALUE		(CONFIG_CLPS711X_CPU_PLL_MULT << 24)
>  #define SDRAM_REFRESH_RATE	(64 * (BUS_SPEED / (8192 * 1000)))
>  
>  void __naked __bare_init barebox_arm_reset_vector(void)
> -- 
> 1.7.3.4
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox

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Re[2]: [PATCH 03/11] ARM: clps711x: Adds config option for CPU PLL multiplier

[Alexander Shiyan]

Hello.

...
> > +menu "CLPS711X specific settings"
> > +
> > +config CLPS711X_CPU_PLL_MULT
> > +	int "CPU PLL multiplier (20-50)"
> > +	range 20 50
> > +	default "40"
> > +	help
> > +	  Define CPU PLL multiplier. PLL is calculated by formula:
> > +	    PLL Frequency = (PLL Multiplier / 2) * 3686400 Hz
> > +	  Default value is 40, for achieve 73 MHz.
> > +
> this board specific put this in c code
> kconfig is too easy to break
> 
> check how we do on at91

This is not board-specific, this is CPU-specific. PLL multiplier is set up
at the start and we not touch it anymore since all system frequencies is
depends on it, including SDRAM refresh.
How to place this configurable parameter in C code i am not understand.
For Kconfig, we can add additional compile-time checker into lowlevel unit
which uses this symbol:

#if (CLPS711X_CPU_PLL_MULT < 20) || (CLPS711X_CPU_PLL_MULT > 50)
#error "CPU PLL multiplier out of range"
#endif

Thanks!

---
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Re: [SPAM] Re[2]: [PATCH 03/11] ARM: clps711x: Adds config option for CPU PLL multiplier

[Jean-Christophe PLAGNIOL-VILLARD]

On 15:58 Fri 08 Feb     , Alexander Shiyan wrote:
> Hello.
> 
> ...
> > > +menu "CLPS711X specific settings"
> > > +
> > > +config CLPS711X_CPU_PLL_MULT
> > > +	int "CPU PLL multiplier (20-50)"
> > > +	range 20 50
> > > +	default "40"
> > > +	help
> > > +	  Define CPU PLL multiplier. PLL is calculated by formula:
> > > +	    PLL Frequency = (PLL Multiplier / 2) * 3686400 Hz
> > > +	  Default value is 40, for achieve 73 MHz.
> > > +
> > this board specific put this in c code
> > kconfig is too easy to break
> > 
> > check how we do on at91
> 
> This is not board-specific, this is CPU-specific. PLL multiplier is set up
> at the start and we not touch it anymore since all system frequencies is
> depends on it, including SDRAM refresh.
> How to place this configurable parameter in C code i am not understand.
> For Kconfig, we can add additional compile-time checker into lowlevel unit
> which uses this symbol:
> 
> #if (CLPS711X_CPU_PLL_MULT < 20) || (CLPS711X_CPU_PLL_MULT > 50)
> #error "CPU PLL multiplier out of range"
> #endif
so it's even worse

detect the cpu in c and dorp the Kconfig

Best Regards,
J.
> 
> Thanks!
> 
> ---

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[PATCH 04/11] ARM: clps711x: Decrease initial memory size to 8MB

[Alexander Shiyan]

Minimal known SDRAM size for CLPS711X-target is 8MB, so decrease
initial memory size to this value.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/mach-clps711x/lowlevel.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c
index 245ac93..7eed556 100644
--- a/arch/arm/mach-clps711x/lowlevel.c
+++ b/arch/arm/mach-clps711x/lowlevel.c
@@ -53,5 +53,5 @@ void __naked __bare_init barebox_arm_reset_vector(void)
 	writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 |
 	       SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF);
 
-	barebox_arm_entry(SDRAM0_BASE, SZ_32M, 0);
+	barebox_arm_entry(SDRAM0_BASE, SZ_8M, 0);
 }
-- 
1.7.3.4


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[PATCH 05/11] ARM: clps711x: Remove unused "start" declaration from reset.c

[Alexander Shiyan]

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/mach-clps711x/reset.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-clps711x/reset.c b/arch/arm/mach-clps711x/reset.c
index 4a42ef4..67c9c8b 100644
--- a/arch/arm/mach-clps711x/reset.c
+++ b/arch/arm/mach-clps711x/reset.c
@@ -9,8 +9,6 @@
 
 #include <common.h>
 
-extern void start(void);
-
 void __noreturn reset_cpu(unsigned long addr)
 {
 	arch_shutdown();
-- 
1.7.3.4


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[PATCH 06/11] ARM: clps711x: Mark private functions that not will be used outside as static

[Alexander Shiyan]

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/mach-clps711x/clock.c   |    8 +++-----
 arch/arm/mach-clps711x/devices.c |    2 +-
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-clps711x/clock.c b/arch/arm/mach-clps711x/clock.c
index 5cafba9..09cbaf9 100644
--- a/arch/arm/mach-clps711x/clock.c
+++ b/arch/arm/mach-clps711x/clock.c
@@ -15,13 +15,11 @@
 
 #include <mach/clps711x.h>
 
-struct clk {
+static struct clk {
 	unsigned long	rate;
-};
-
-static struct clk uart_clk, bus_clk;
+} uart_clk, bus_clk;
 
-uint64_t clocksource_read(void)
+static uint64_t clocksource_read(void)
 {
 	return ~readw(TC2D);
 }
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
index 08f27d2..de5813a 100644
--- a/arch/arm/mach-clps711x/devices.c
+++ b/arch/arm/mach-clps711x/devices.c
@@ -14,7 +14,7 @@
 
 #include <mach/clps711x.h>
 
-inline void _clps711x_setup_memcfg(int bank, u32 addr, u32 val)
+inline static void _clps711x_setup_memcfg(int bank, u32 addr, u32 val)
 {
 	u32 tmp = readl(addr);
 
-- 
1.7.3.4


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[PATCH 07/11] ARM: clep7212: Fix NULL pointer exception if MMU is enabled

[Alexander Shiyan]

NOR-flash is placed at address 0x0, so if MMU is turned on, initialization
will fails. This patch fix this problem.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/boards/clep7212/clep7212.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boards/clep7212/clep7212.c b/arch/arm/boards/clep7212/clep7212.c
index a32337f..b96e480 100644
--- a/arch/arm/boards/clep7212/clep7212.c
+++ b/arch/arm/boards/clep7212/clep7212.c
@@ -14,6 +14,7 @@
 #include <io.h>
 #include <sizes.h>
 #include <asm/armlinux.h>
+#include <asm/mmu.h>
 #include <generated/mach-types.h>
 
 #include <mach/clps711x.h>
@@ -32,6 +33,7 @@ mem_initcall(clps711x_mem_init);
 static int clps711x_devices_init(void)
 {
 	u32 serial_h = 0, serial_l = readl(UNIQID);
+	void *cfi_io;
 
 	/* Setup Chipselects */
 	clps711x_setup_memcfg(0, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_16);
@@ -40,7 +42,9 @@ static int clps711x_devices_init(void)
 			      MEMCFG_CLKENB);
 	clps711x_setup_memcfg(3, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_32);
 
-	add_cfi_flash_device(0, CS0_BASE, SZ_32M, 0);
+	cfi_io = map_io_sections(CS0_BASE, (void *)0x90000000, SZ_32M);
+	add_cfi_flash_device(DEVICE_ID_DYNAMIC, (unsigned long)cfi_io, SZ_32M,
+			     IORESOURCE_MEM);
 
 	devfs_add_partition("nor0", 0x00000, SZ_256K, DEVFS_PARTITION_FIXED,
 			    "self0");
-- 
1.7.3.4


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[PATCH 08/11] ARM: mmu: Clear unpredictable bits for translation table

[Alexander Shiyan]

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/cpu/mmu.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 73dd0d3..99f12b5 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -279,6 +279,9 @@ static int mmu_init(void)
 	if (get_cr() & CR_M) {
 		asm volatile ("mrc  p15,0,%0,c2,c0,0" : "=r"(ttb));
 
+		/* Clear unpredictable bits [13:0] */
+		ttb = (unsigned long *)((unsigned long)ttb & ~0x3fff);
+
 		if (!request_sdram_region("ttb", (unsigned long)ttb, SZ_16K))
 			pr_err("Error: Can't request SDRAM region for ttb\n");
 	} else {
-- 
1.7.3.4


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Re: [PATCH 08/11] ARM: mmu: Clear unpredictable bits for translation table

[Sascha Hauer]

On Fri, Feb 08, 2013 at 02:02:20PM +0400, Alexander Shiyan wrote:
> 
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>

Applied this one for master.

Sascha

> ---
>  arch/arm/cpu/mmu.c |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
> index 73dd0d3..99f12b5 100644
> --- a/arch/arm/cpu/mmu.c
> +++ b/arch/arm/cpu/mmu.c
> @@ -279,6 +279,9 @@ static int mmu_init(void)
>  	if (get_cr() & CR_M) {
>  		asm volatile ("mrc  p15,0,%0,c2,c0,0" : "=r"(ttb));
>  
> +		/* Clear unpredictable bits [13:0] */
> +		ttb = (unsigned long *)((unsigned long)ttb & ~0x3fff);
> +
>  		if (!request_sdram_region("ttb", (unsigned long)ttb, SZ_16K))
>  			pr_err("Error: Can't request SDRAM region for ttb\n");
>  	} else {
> -- 
> 1.7.3.4
> 
> 
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Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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[PATCH 09/11] ARM: clps711x: Move memory initialization in common CLPS711X location

[Alexander Shiyan]

One memory initialization will be used on any CLPS711X-target,
so move it in the common location.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/boards/clep7212/clep7212.c |   10 ----------
 arch/arm/mach-clps711x/devices.c    |   12 ++++++++++++
 2 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boards/clep7212/clep7212.c b/arch/arm/boards/clep7212/clep7212.c
index b96e480..ec9a9cb 100644
--- a/arch/arm/boards/clep7212/clep7212.c
+++ b/arch/arm/boards/clep7212/clep7212.c
@@ -20,16 +20,6 @@
 #include <mach/clps711x.h>
 #include <mach/devices.h>
 
-static int clps711x_mem_init(void)
-{
-	ulong memsize = get_ram_size((ulong *)SDRAM0_BASE, SZ_32M);
-
-	arm_add_mem_device("ram0", SDRAM0_BASE, memsize);
-
-	return 0;
-}
-mem_initcall(clps711x_mem_init);
-
 static int clps711x_devices_init(void)
 {
 	u32 serial_h = 0, serial_l = readl(UNIQID);
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
index de5813a..6c760db 100644
--- a/arch/arm/mach-clps711x/devices.c
+++ b/arch/arm/mach-clps711x/devices.c
@@ -9,11 +9,23 @@
 
 #include <common.h>
 #include <init.h>
+#include <sizes.h>
 
 #include <asm/io.h>
+#include <asm/memory.h>
 
 #include <mach/clps711x.h>
 
+static int clps711x_mem_init(void)
+{
+	ulong memsize = get_ram_size((ulong *)SDRAM0_BASE, SZ_64M);
+
+	arm_add_mem_device("ram0", SDRAM0_BASE, memsize);
+
+	return 0;
+}
+mem_initcall(clps711x_mem_init);
+
 inline static void _clps711x_setup_memcfg(int bank, u32 addr, u32 val)
 {
 	u32 tmp = readl(addr);
-- 
1.7.3.4


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[PATCH 10/11] ARM: clps711x: Turn off all peripherals on startup

[Alexander Shiyan]

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/mach-clps711x/lowlevel.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c
index 7eed556..752619b 100644
--- a/arch/arm/mach-clps711x/lowlevel.c
+++ b/arch/arm/mach-clps711x/lowlevel.c
@@ -53,5 +53,12 @@ void __naked __bare_init barebox_arm_reset_vector(void)
 	writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 |
 	       SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF);
 
+	/* Disable UART1, IrDa, LCD */
+	writel(0, SYSCON1);
+	/* Disable PWM */
+	writew(0, PMPCON);
+	/* Disable LED flasher */
+	writew(0, LEDFLSH);
+
 	barebox_arm_entry(SDRAM0_BASE, SZ_8M, 0);
 }
-- 
1.7.3.4


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[PATCH 11/11] ARM: clps711x: Update defconfig

[Alexander Shiyan]

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/configs/clps711x_defconfig |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
index cf2b3b6..3cc939e 100644
--- a/arch/arm/configs/clps711x_defconfig
+++ b/arch/arm/configs/clps711x_defconfig
@@ -1,13 +1,14 @@
 CONFIG_ARCH_CLPS711X=y
+CONFIG_CLPS711X_CPU_PLL_MULT=50
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 # CONFIG_MEMINFO is not set
-CONFIG_TEXT_BASE=0xc0780000
+CONFIG_PBL_IMAGE=y
+CONFIG_MMU=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_BAUDRATE=57600
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
-CONFIG_DEFAULT_ENVIRONMENT_COMPRESSED_LZO=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
 CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/clep7212/env"
 CONFIG_CMD_EDIT=y
@@ -32,6 +33,7 @@ CONFIG_CMD_MAGICVAR_HELP=y
 CONFIG_DRIVER_CFI=y
 # CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set
 # CONFIG_DRIVER_CFI_BANK_WIDTH_4 is not set
+CONFIG_CFI_BUFFER_WRITE=y
 CONFIG_MTD=y
 CONFIG_DISK=y
 CONFIG_DISK_WRITE=y
-- 
1.7.3.4


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Re: [PATCH 01/11] ARM: clps711x: Move lowlevel initialization in common CLPS711X location

[Sascha Hauer]

On Fri, Feb 08, 2013 at 02:02:13PM +0400, Alexander Shiyan wrote:
> One lowlevel initialization will be used on any CLPS711X-target,
> so move it in the common location.
> 
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> ---
>  arch/arm/boards/clep7212/Makefile   |    3 +-
>  arch/arm/boards/clep7212/lowlevel.c |   57 -----------------------------------
>  arch/arm/mach-clps711x/Makefile     |    3 +-
>  arch/arm/mach-clps711x/lowlevel.c   |   57 +++++++++++++++++++++++++++++++++++
>  4 files changed, 60 insertions(+), 60 deletions(-)
>  delete mode 100644 arch/arm/boards/clep7212/lowlevel.c
>  create mode 100644 arch/arm/mach-clps711x/lowlevel.c
> 
> diff --git a/arch/arm/boards/clep7212/Makefile b/arch/arm/boards/clep7212/Makefile
> index a63aeae..676e867 100644
> --- a/arch/arm/boards/clep7212/Makefile
> +++ b/arch/arm/boards/clep7212/Makefile
> @@ -1,2 +1 @@
> -obj-y += lowlevel.o clep7212.o
> -pbl-y += lowlevel.o
> +obj-y += clep7212.o
> diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c

I think it's better to keep the reset vector in board specific code.
Then you can have a board specific reset vector, which simply calls
a SoC specific one. This also solves the Kconfig problem with the
PLL setup. So you would have this in your board:

void __naked __bare_init barebox_arm_reset_vector(void)
{
	arm_cpu_lowlevel_init();

	clps711x_barebox_entry();
}

You could add different more specific clps711x_* functions which will
result in different CPU speeds, or you could pass a PLL value to the
entry function, if that better fits your needs.

The rest of this series looks fine.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re[2]: [PATCH 01/11] ARM: clps711x: Move lowlevel initialization in common CLPS711X location

[Alexander Shiyan]

Hello.

...
> > diff --git a/arch/arm/boards/clep7212/Makefile b/arch/arm/boards/clep7212/Makefile
> > index a63aeae..676e867 100644
> > --- a/arch/arm/boards/clep7212/Makefile
> > +++ b/arch/arm/boards/clep7212/Makefile
> > @@ -1,2 +1 @@
> > -obj-y += lowlevel.o clep7212.o
> > -pbl-y += lowlevel.o
> > +obj-y += clep7212.o
> > diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
> 
> I think it's better to keep the reset vector in board specific code.
> Then you can have a board specific reset vector, which simply calls
> a SoC specific one. This also solves the Kconfig problem with the
> PLL setup. So you would have this in your board:
> 
> void __naked __bare_init barebox_arm_reset_vector(void)
> {
> 	arm_cpu_lowlevel_init();
> 
> 	clps711x_barebox_entry();
> }
> 
> You could add different more specific clps711x_* functions which will
> result in different CPU speeds, or you could pass a PLL value to the
> entry function, if that better fits your needs.
> 
> The rest of this series looks fine.

Can we leave this basic clps711x_barebox_entry in mach-clps711x/lowlevel.c
and just additionally mark it as "__weak" for ability to override?

---
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Re: [PATCH 01/11] ARM: clps711x: Move lowlevel initialization in common CLPS711X location

[Sascha Hauer]

On Mon, Feb 11, 2013 at 01:30:53PM +0400, Alexander Shiyan wrote:
> Hello.
> 
> ...
> > > diff --git a/arch/arm/boards/clep7212/Makefile b/arch/arm/boards/clep7212/Makefile
> > > index a63aeae..676e867 100644
> > > --- a/arch/arm/boards/clep7212/Makefile
> > > +++ b/arch/arm/boards/clep7212/Makefile
> > > @@ -1,2 +1 @@
> > > -obj-y += lowlevel.o clep7212.o
> > > -pbl-y += lowlevel.o
> > > +obj-y += clep7212.o
> > > diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
> > 
> > I think it's better to keep the reset vector in board specific code.
> > Then you can have a board specific reset vector, which simply calls
> > a SoC specific one. This also solves the Kconfig problem with the
> > PLL setup. So you would have this in your board:
> > 
> > void __naked __bare_init barebox_arm_reset_vector(void)
> > {
> > 	arm_cpu_lowlevel_init();
> > 
> > 	clps711x_barebox_entry();
> > }
> > 
> > You could add different more specific clps711x_* functions which will
> > result in different CPU speeds, or you could pass a PLL value to the
> > entry function, if that better fits your needs.
> > 
> > The rest of this series looks fine.
> 
> Can we leave this basic clps711x_barebox_entry in mach-clps711x/lowlevel.c
> and just additionally mark it as "__weak" for ability to override?

I'm not a big fan of __weak functions. Also, if you mark it as weak this
would mean that you would have to duplicate the other setup the original
weak function does.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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