[PATCH v2 1/9] ARM: clps711x: Rework lowlevel initialization code

[PATCH v2 1/9] ARM: clps711x: Rework lowlevel initialization code

[Alexander Shiyan]

This is a rework of CLPS711X low level initialization code which includes:
- Prepare for changing CPU PLL multiplier from board lowlevel code.
- Decrease initial memory size to 8MB. It is minimal known size.
- Fix SDRAM initialization comment about size.
- Turn off all peripherals on startup.
- Skip PLL initialization if CPU is running from external 13 MHz clock.
- Use correct CPU speed for older CPUs without PLL.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/boards/clep7212/lowlevel.c |   53 +++++++++++++++++++++--------------
 1 files changed, 32 insertions(+), 21 deletions(-)

diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
index b4d1bf1..fcee5bf 100644
--- a/arch/arm/boards/clep7212/lowlevel.c
+++ b/arch/arm/boards/clep7212/lowlevel.c
@@ -17,41 +17,52 @@
 
 #include <mach/clps711x.h>
 
-#define MAIN_CLOCK		3686400
-#define CPU_SPEED		92160000
-#define BUS_SPEED		(CPU_SPEED / 2)
-
-#define PLL_VALUE		(((CPU_SPEED * 2) / MAIN_CLOCK) << 24)
-#define SDRAM_REFRESH_RATE	(64 * (BUS_SPEED / (8192 * 1000)))
-
 void __naked __bare_init barebox_arm_reset_vector(void)
 {
-	u32 tmp;
+	const u32 pllmult = 50;
+	u32 cpu, bus;
 
 	arm_cpu_lowlevel_init();
 
-	/* Setup base clock */
+	/* Setup base clocking, Enable SDQM pins  */
 	writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3);
 	asm("nop");
 
-	/* Setup PLL */
-	writel(PLL_VALUE, PLLW);
-	asm("nop");
+	/* Check if we running from external 13 MHz clock */
+	if (!(readl(SYSFLG2) & SYSFLG2_CKMODE)) {
+		/* Setup PLL */
+		writel(pllmult << 24, PLLW);
+		asm("nop");
+
+		/* Check for old CPUs without PLL */
+		if ((readl(PLLR) >> 24) != pllmult)
+			cpu = 73728000;
+		else
+			cpu = pllmult * 3686400;
+
+		if (cpu >= 36864000)
+			bus = cpu /2;
+		else
+			bus = 36864000 / 2;
+	} else
+		bus = 13000000;
 
 	/* CLKEN select, SDRAM width=32 */
 	writel(SYSCON2_CLKENSL, SYSCON2);
 
-	/* Enable SDQM pins */
-	tmp = readl(SYSCON3);
-	tmp &= ~SYSCON3_ENPD67;
-	writel(tmp, SYSCON3);
+	/* Setup SDRAM params (64MB, 16Bit*2, CAS=3) */
+	writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 |
+	       SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF);
 
 	/* Setup Refresh Rate (64ms 8K Blocks) */
-	writel(SDRAM_REFRESH_RATE, SDRFPR);
+	writel((64 * bus) / (8192 * 1000), SDRFPR);
 
-	/* Setup SDRAM (32MB, 16Bit*2, CAS=3) */
-	writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 |
-	       SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF);
+	/* Disable UART, IrDa, LCD */
+	writel(0, SYSCON1);
+	/* Disable PWM */
+	writew(0, PMPCON);
+	/* Disable LED flasher */
+	writew(0, LEDFLSH);
 
-	barebox_arm_entry(SDRAM0_BASE, SZ_32M, 0);
+	barebox_arm_entry(SDRAM0_BASE, SZ_8M, 0);
 }
-- 
1.7.3.4


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[PATCH v2 2/9] ARM: clps711x: Move basic lowlevel initialization in common CLPS711X location

[Alexander Shiyan]

One lowlevel initialization will be used on any CLPS711X-target,
so move it in the common location.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/boards/clep7212/lowlevel.c            |   48 +-----------------
 arch/arm/mach-clps711x/Makefile                |    3 +-
 arch/arm/mach-clps711x/include/mach/clps711x.h |    2 +
 arch/arm/mach-clps711x/lowlevel.c              |   66 ++++++++++++++++++++++++
 4 files changed, 71 insertions(+), 48 deletions(-)
 create mode 100644 arch/arm/mach-clps711x/lowlevel.c

diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
index fcee5bf..b7d6d1d 100644
--- a/arch/arm/boards/clep7212/lowlevel.c
+++ b/arch/arm/boards/clep7212/lowlevel.c
@@ -9,60 +9,14 @@
 
 #include <common.h>
 #include <init.h>
-#include <sizes.h>
 
-#include <asm/io.h>
-#include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
 
 #include <mach/clps711x.h>
 
 void __naked __bare_init barebox_arm_reset_vector(void)
 {
-	const u32 pllmult = 50;
-	u32 cpu, bus;
-
 	arm_cpu_lowlevel_init();
 
-	/* Setup base clocking, Enable SDQM pins  */
-	writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3);
-	asm("nop");
-
-	/* Check if we running from external 13 MHz clock */
-	if (!(readl(SYSFLG2) & SYSFLG2_CKMODE)) {
-		/* Setup PLL */
-		writel(pllmult << 24, PLLW);
-		asm("nop");
-
-		/* Check for old CPUs without PLL */
-		if ((readl(PLLR) >> 24) != pllmult)
-			cpu = 73728000;
-		else
-			cpu = pllmult * 3686400;
-
-		if (cpu >= 36864000)
-			bus = cpu /2;
-		else
-			bus = 36864000 / 2;
-	} else
-		bus = 13000000;
-
-	/* CLKEN select, SDRAM width=32 */
-	writel(SYSCON2_CLKENSL, SYSCON2);
-
-	/* Setup SDRAM params (64MB, 16Bit*2, CAS=3) */
-	writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 |
-	       SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF);
-
-	/* Setup Refresh Rate (64ms 8K Blocks) */
-	writel((64 * bus) / (8192 * 1000), SDRFPR);
-
-	/* Disable UART, IrDa, LCD */
-	writel(0, SYSCON1);
-	/* Disable PWM */
-	writew(0, PMPCON);
-	/* Disable LED flasher */
-	writew(0, LEDFLSH);
-
-	barebox_arm_entry(SDRAM0_BASE, SZ_8M, 0);
+	clps711x_barebox_entry();
 }
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index 41012bc..69a4a3c 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -1 +1,2 @@
-obj-y += clock.o devices.o reset.o
+obj-y += clock.o devices.o lowlevel.o reset.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 048992a..5b8fe82 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -281,4 +281,6 @@
 #define MEMCFG_WAITSTATE_2_0	(14 << 2)
 #define MEMCFG_WAITSTATE_1_0	(15 << 2)
 
+void clps711x_barebox_entry(void);
+
 #endif
diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c
new file mode 100644
index 0000000..cd3216a
--- /dev/null
+++ b/arch/arm/mach-clps711x/lowlevel.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <sizes.h>
+
+#include <asm/io.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+
+#include <mach/clps711x.h>
+
+void __naked __bare_init clps711x_barebox_entry(void)
+{
+	const u32 pllmult = 50;
+	u32 cpu, bus;
+
+	/* Setup base clocking, Enable SDQM pins  */
+	writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3);
+	asm("nop");
+
+	/* Check if we running from external 13 MHz clock */
+	if (!(readl(SYSFLG2) & SYSFLG2_CKMODE)) {
+		/* Setup PLL */
+		writel(pllmult << 24, PLLW);
+		asm("nop");
+
+		/* Check for old CPUs without PLL */
+		if ((readl(PLLR) >> 24) != pllmult)
+			cpu = 73728000;
+		else
+			cpu = pllmult * 3686400;
+
+		if (cpu >= 36864000)
+			bus = cpu /2;
+		else
+			bus = 36864000 / 2;
+	} else
+		bus = 13000000;
+
+	/* CLKEN select, SDRAM width=32 */
+	writel(SYSCON2_CLKENSL, SYSCON2);
+
+	/* Setup SDRAM params (64MB, 16Bit*2, CAS=3) */
+	writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 |
+	       SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF);
+
+	/* Setup Refresh Rate (64ms 8K Blocks) */
+	writel((64 * bus) / (8192 * 1000), SDRFPR);
+
+	/* Disable UART, IrDa, LCD */
+	writel(0, SYSCON1);
+	/* Disable PWM */
+	writew(0, PMPCON);
+	/* Disable LED flasher */
+	writew(0, LEDFLSH);
+
+	barebox_arm_entry(SDRAM0_BASE, SZ_8M, 0);
+}
-- 
1.7.3.4


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[PATCH v2 3/9] ARM: clps711x: Adds config option for CPU PLL multiplier

[Alexander Shiyan]

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/boards/clep7212/lowlevel.c            |    6 +++++-
 arch/arm/mach-clps711x/Kconfig                 |   13 +++++++++++++
 arch/arm/mach-clps711x/include/mach/clps711x.h |    2 +-
 arch/arm/mach-clps711x/lowlevel.c              |    7 +++++--
 4 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
index b7d6d1d..fcf8285 100644
--- a/arch/arm/boards/clep7212/lowlevel.c
+++ b/arch/arm/boards/clep7212/lowlevel.c
@@ -14,9 +14,13 @@
 
 #include <mach/clps711x.h>
 
+#if (CONFIG_CLPS711X_CPU_PLL_MULT < 20) || (CONFIG_CLPS711X_CPU_PLL_MULT > 50)
+# error "CPU PLL multiplier out of range"
+#endif
+
 void __naked __bare_init barebox_arm_reset_vector(void)
 {
 	arm_cpu_lowlevel_init();
 
-	clps711x_barebox_entry();
+	clps711x_barebox_entry(CONFIG_CLPS711X_CPU_PLL_MULT);
 }
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index f0adeda..d2873b4 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -10,6 +10,19 @@ config MACH_CLEP7212
 
 endchoice
 
+menu "CLPS711X specific settings"
+
+config CLPS711X_CPU_PLL_MULT
+	int "CPU PLL multiplier (20-50)"
+	range 20 50
+	default "40"
+	help
+	  Define CPU PLL multiplier. PLL is calculated by formula:
+	    PLL Frequency = (PLL Multiplier / 2) * 3686400 Hz
+	  Default value is 40, for achieve 73 MHz.
+
+endmenu
+
 config BOARDINFO
 	default "Cirrus Logic CLEP7212" if MACH_CLEP7212
 
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 5b8fe82..cc65cc8 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -281,6 +281,6 @@
 #define MEMCFG_WAITSTATE_2_0	(14 << 2)
 #define MEMCFG_WAITSTATE_1_0	(15 << 2)
 
-void clps711x_barebox_entry(void);
+void clps711x_barebox_entry(u32);
 
 #endif
diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c
index cd3216a..193f61a 100644
--- a/arch/arm/mach-clps711x/lowlevel.c
+++ b/arch/arm/mach-clps711x/lowlevel.c
@@ -17,9 +17,8 @@
 
 #include <mach/clps711x.h>
 
-void __naked __bare_init clps711x_barebox_entry(void)
+void __naked __bare_init clps711x_barebox_entry(u32 pllmult)
 {
-	const u32 pllmult = 50;
 	u32 cpu, bus;
 
 	/* Setup base clocking, Enable SDQM pins  */
@@ -28,6 +27,10 @@ void __naked __bare_init clps711x_barebox_entry(void)
 
 	/* Check if we running from external 13 MHz clock */
 	if (!(readl(SYSFLG2) & SYSFLG2_CKMODE)) {
+		/* Check valid multiplier, default to 74 MHz */
+		if ((pllmult < 20) || (pllmult > 50))
+			pllmult = 40;
+
 		/* Setup PLL */
 		writel(pllmult << 24, PLLW);
 		asm("nop");
-- 
1.7.3.4


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[PATCH v2 4/9] ARM: clps711x: Remove unused "start" declaration from reset.c

[Alexander Shiyan]

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/mach-clps711x/reset.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-clps711x/reset.c b/arch/arm/mach-clps711x/reset.c
index 4a42ef4..67c9c8b 100644
--- a/arch/arm/mach-clps711x/reset.c
+++ b/arch/arm/mach-clps711x/reset.c
@@ -9,8 +9,6 @@
 
 #include <common.h>
 
-extern void start(void);
-
 void __noreturn reset_cpu(unsigned long addr)
 {
 	arch_shutdown();
-- 
1.7.3.4


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[PATCH v2 5/9] ARM: clps711x: Mark private functions that not will be used outside as static

[Alexander Shiyan]

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/mach-clps711x/clock.c   |    8 +++-----
 arch/arm/mach-clps711x/devices.c |    2 +-
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-clps711x/clock.c b/arch/arm/mach-clps711x/clock.c
index 5cafba9..09cbaf9 100644
--- a/arch/arm/mach-clps711x/clock.c
+++ b/arch/arm/mach-clps711x/clock.c
@@ -15,13 +15,11 @@
 
 #include <mach/clps711x.h>
 
-struct clk {
+static struct clk {
 	unsigned long	rate;
-};
-
-static struct clk uart_clk, bus_clk;
+} uart_clk, bus_clk;
 
-uint64_t clocksource_read(void)
+static uint64_t clocksource_read(void)
 {
 	return ~readw(TC2D);
 }
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
index 08f27d2..de5813a 100644
--- a/arch/arm/mach-clps711x/devices.c
+++ b/arch/arm/mach-clps711x/devices.c
@@ -14,7 +14,7 @@
 
 #include <mach/clps711x.h>
 
-inline void _clps711x_setup_memcfg(int bank, u32 addr, u32 val)
+inline static void _clps711x_setup_memcfg(int bank, u32 addr, u32 val)
 {
 	u32 tmp = readl(addr);
 
-- 
1.7.3.4


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[PATCH v2 6/9] ARM: clep7212: Fix NULL pointer exception if MMU is enabled

[Alexander Shiyan]

NOR-flash is placed at address 0x0, so if MMU is turned on, initialization
will fails. This patch fix this problem.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/boards/clep7212/clep7212.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boards/clep7212/clep7212.c b/arch/arm/boards/clep7212/clep7212.c
index a32337f..b96e480 100644
--- a/arch/arm/boards/clep7212/clep7212.c
+++ b/arch/arm/boards/clep7212/clep7212.c
@@ -14,6 +14,7 @@
 #include <io.h>
 #include <sizes.h>
 #include <asm/armlinux.h>
+#include <asm/mmu.h>
 #include <generated/mach-types.h>
 
 #include <mach/clps711x.h>
@@ -32,6 +33,7 @@ mem_initcall(clps711x_mem_init);
 static int clps711x_devices_init(void)
 {
 	u32 serial_h = 0, serial_l = readl(UNIQID);
+	void *cfi_io;
 
 	/* Setup Chipselects */
 	clps711x_setup_memcfg(0, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_16);
@@ -40,7 +42,9 @@ static int clps711x_devices_init(void)
 			      MEMCFG_CLKENB);
 	clps711x_setup_memcfg(3, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_32);
 
-	add_cfi_flash_device(0, CS0_BASE, SZ_32M, 0);
+	cfi_io = map_io_sections(CS0_BASE, (void *)0x90000000, SZ_32M);
+	add_cfi_flash_device(DEVICE_ID_DYNAMIC, (unsigned long)cfi_io, SZ_32M,
+			     IORESOURCE_MEM);
 
 	devfs_add_partition("nor0", 0x00000, SZ_256K, DEVFS_PARTITION_FIXED,
 			    "self0");
-- 
1.7.3.4


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[PATCH v2 7/9] ARM: clps711x: Move memory initialization in common CLPS711X location

[Alexander Shiyan]

One memory initialization will be used on any CLPS711X-target,
so move it in the common location.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/boards/clep7212/clep7212.c |   10 ----------
 arch/arm/mach-clps711x/devices.c    |   12 ++++++++++++
 2 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boards/clep7212/clep7212.c b/arch/arm/boards/clep7212/clep7212.c
index b96e480..ec9a9cb 100644
--- a/arch/arm/boards/clep7212/clep7212.c
+++ b/arch/arm/boards/clep7212/clep7212.c
@@ -20,16 +20,6 @@
 #include <mach/clps711x.h>
 #include <mach/devices.h>
 
-static int clps711x_mem_init(void)
-{
-	ulong memsize = get_ram_size((ulong *)SDRAM0_BASE, SZ_32M);
-
-	arm_add_mem_device("ram0", SDRAM0_BASE, memsize);
-
-	return 0;
-}
-mem_initcall(clps711x_mem_init);
-
 static int clps711x_devices_init(void)
 {
 	u32 serial_h = 0, serial_l = readl(UNIQID);
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
index de5813a..6c760db 100644
--- a/arch/arm/mach-clps711x/devices.c
+++ b/arch/arm/mach-clps711x/devices.c
@@ -9,11 +9,23 @@
 
 #include <common.h>
 #include <init.h>
+#include <sizes.h>
 
 #include <asm/io.h>
+#include <asm/memory.h>
 
 #include <mach/clps711x.h>
 
+static int clps711x_mem_init(void)
+{
+	ulong memsize = get_ram_size((ulong *)SDRAM0_BASE, SZ_64M);
+
+	arm_add_mem_device("ram0", SDRAM0_BASE, memsize);
+
+	return 0;
+}
+mem_initcall(clps711x_mem_init);
+
 inline static void _clps711x_setup_memcfg(int bank, u32 addr, u32 val)
 {
 	u32 tmp = readl(addr);
-- 
1.7.3.4


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[PATCH v2 8/9] ARM: clep7212: Update default environment

[Alexander Shiyan]

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/boards/clep7212/env/bin/mtdparts-add   |   21 ---------------------
 arch/arm/boards/clep7212/env/boot/nor           |    2 +-
 arch/arm/boards/clep7212/env/config             |   20 ++++++++++++++++++++
 arch/arm/boards/clep7212/env/init/automount     |    6 ------
 arch/arm/boards/clep7212/env/init/bootargs-base |    8 --------
 arch/arm/boards/clep7212/env/init/general       |   12 ------------
 arch/arm/boards/clep7212/env/init/hostname      |    8 --------
 arch/arm/boards/clep7212/env/init/mtdparts-nor  |   11 +++++++++++
 8 files changed, 32 insertions(+), 56 deletions(-)
 delete mode 100644 arch/arm/boards/clep7212/env/bin/mtdparts-add
 create mode 100644 arch/arm/boards/clep7212/env/config
 delete mode 100644 arch/arm/boards/clep7212/env/init/automount
 delete mode 100644 arch/arm/boards/clep7212/env/init/bootargs-base
 delete mode 100644 arch/arm/boards/clep7212/env/init/general
 delete mode 100644 arch/arm/boards/clep7212/env/init/hostname
 create mode 100644 arch/arm/boards/clep7212/env/init/mtdparts-nor

diff --git a/arch/arm/boards/clep7212/env/bin/mtdparts-add b/arch/arm/boards/clep7212/env/bin/mtdparts-add
deleted file mode 100644
index ef1bc02..0000000
--- a/arch/arm/boards/clep7212/env/bin/mtdparts-add
+++ /dev/null
@@ -1,21 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = menu ]; then
-	init-menu-add-entry "$0" "Partitions"
-	exit
-fi
-
-norparts="256k(barebox),256k(bareboxenv),3584k(kernel),-(root)"
-ramparts="-(ramdisk)"
-
-if [ -e /dev/nor0 ]; then
-	addpart -n /dev/nor0 "${norparts}"
-
-	global linux.mtdparts.nor
-	global.linux.mtdparts.nor="physmap-flash.0:${norparts}"
-else
-	echo "NOR Flash not found."
-fi
-
-global linux.mtdparts.ram
-global.linux.mtdparts.ram="mtd-ram.0:${ramparts}"
diff --git a/arch/arm/boards/clep7212/env/boot/nor b/arch/arm/boards/clep7212/env/boot/nor
index 5cf1e15..df8c983 100644
--- a/arch/arm/boards/clep7212/env/boot/nor
+++ b/arch/arm/boards/clep7212/env/boot/nor
@@ -6,4 +6,4 @@ if [ "$1" = menu ]; then
 fi
 
 global.bootm.image="/dev/kernel"
-global.linux.bootargs.dyn.root="root=/dev/mtdblock4 ro"
+global.linux.bootargs.dyn.root="root=/dev/mtdblock3 ro"
diff --git a/arch/arm/boards/clep7212/env/config b/arch/arm/boards/clep7212/env/config
new file mode 100644
index 0000000..e8f2c3a
--- /dev/null
+++ b/arch/arm/boards/clep7212/env/config
@@ -0,0 +1,20 @@
+#!/bin/sh
+
+global.hostname=clps711x
+
+# set to false if you do not want to have colors
+global.allow_color=true
+
+# user (used for network filenames)
+global.user=anonymous
+
+# timeout in seconds before the default boot entry is started
+global.autoboot_timeout=2
+
+# default boot entry (one of /env/boot/*)
+if [ -e /dev/nor0 ]; then
+	global.boot.default=nor
+fi
+
+# default bootargs
+global.linux.bootargs.base="earlyprintk console=ttyCL0,57600n8"
diff --git a/arch/arm/boards/clep7212/env/init/automount b/arch/arm/boards/clep7212/env/init/automount
deleted file mode 100644
index 978b964..0000000
--- a/arch/arm/boards/clep7212/env/init/automount
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = menu ]; then
-	init-menu-add-entry "$0" "Automountpoints"
-	exit
-fi
diff --git a/arch/arm/boards/clep7212/env/init/bootargs-base b/arch/arm/boards/clep7212/env/init/bootargs-base
deleted file mode 100644
index ec08e39..0000000
--- a/arch/arm/boards/clep7212/env/init/bootargs-base
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = menu ]; then
-	init-menu-add-entry "$0" "Base bootargs"
-	exit
-fi
-
-global.linux.bootargs.base="earlyprintk console=ttyCL0,57600n8"
diff --git a/arch/arm/boards/clep7212/env/init/general b/arch/arm/boards/clep7212/env/init/general
deleted file mode 100644
index 77e6a59..0000000
--- a/arch/arm/boards/clep7212/env/init/general
+++ /dev/null
@@ -1,12 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = menu ]; then
-	init-menu-add-entry "$0" "general config settings"
-	exit
-fi
-
-global.user=barebox
-global.autoboot_timeout=2
-global.boot.default=nor
-
-/env/bin/mtdparts-add
diff --git a/arch/arm/boards/clep7212/env/init/hostname b/arch/arm/boards/clep7212/env/init/hostname
deleted file mode 100644
index 684ee63..0000000
--- a/arch/arm/boards/clep7212/env/init/hostname
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = menu ]; then
-	init-menu-add-entry "$0" "hostname"
-	exit
-fi
-
-global.hostname=clep7212
diff --git a/arch/arm/boards/clep7212/env/init/mtdparts-nor b/arch/arm/boards/clep7212/env/init/mtdparts-nor
new file mode 100644
index 0000000..7910299
--- /dev/null
+++ b/arch/arm/boards/clep7212/env/init/mtdparts-nor
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+	init-menu-add-entry "$0" "NOR partitions"
+	exit
+fi
+
+mtdparts="256k(barebox),256k(bareboxenv),3584k(kernel),-(root)"
+kernelname="physmap-flash.0"
+
+mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts}
-- 
1.7.3.4


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[PATCH v2 9/9] ARM: clps711x: Update defconfig

[Alexander Shiyan]

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/configs/clps711x_defconfig |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
index cf2b3b6..3c81776 100644
--- a/arch/arm/configs/clps711x_defconfig
+++ b/arch/arm/configs/clps711x_defconfig
@@ -1,13 +1,14 @@
 CONFIG_ARCH_CLPS711X=y
+CONFIG_CLPS711X_CPU_PLL_MULT=50
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 # CONFIG_MEMINFO is not set
-CONFIG_TEXT_BASE=0xc0780000
+CONFIG_PBL_IMAGE=y
+CONFIG_MMU=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_BAUDRATE=57600
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
-CONFIG_DEFAULT_ENVIRONMENT_COMPRESSED_LZO=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
 CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/clep7212/env"
 CONFIG_CMD_EDIT=y
-- 
1.7.3.4


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Re: [PATCH v2 3/9] ARM: clps711x: Adds config option for CPU PLL multiplier

[Jean-Christophe PLAGNIOL-VILLARD]

On 15:41 Wed 13 Feb     , Alexander Shiyan wrote:
> 
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> ---
>  arch/arm/boards/clep7212/lowlevel.c            |    6 +++++-
>  arch/arm/mach-clps711x/Kconfig                 |   13 +++++++++++++
>  arch/arm/mach-clps711x/include/mach/clps711x.h |    2 +-
>  arch/arm/mach-clps711x/lowlevel.c              |    7 +++++--
>  4 files changed, 24 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
> index b7d6d1d..fcf8285 100644
> --- a/arch/arm/boards/clep7212/lowlevel.c
> +++ b/arch/arm/boards/clep7212/lowlevel.c
> @@ -14,9 +14,13 @@
>  
>  #include <mach/clps711x.h>
>  
> +#if (CONFIG_CLPS711X_CPU_PLL_MULT < 20) || (CONFIG_CLPS711X_CPU_PLL_MULT > 50)
> +# error "CPU PLL multiplier out of range"
> +#endif
> +
>  void __naked __bare_init barebox_arm_reset_vector(void)
>  {
>  	arm_cpu_lowlevel_init();
>  
> -	clps711x_barebox_entry();
> +	clps711x_barebox_entry(CONFIG_CLPS711X_CPU_PLL_MULT);
>  }
> diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
> index f0adeda..d2873b4 100644
> --- a/arch/arm/mach-clps711x/Kconfig
> +++ b/arch/arm/mach-clps711x/Kconfig
> @@ -10,6 +10,19 @@ config MACH_CLEP7212
>  
>  endchoice
>  
> +menu "CLPS711X specific settings"
> +
> +config CLPS711X_CPU_PLL_MULT
> +	int "CPU PLL multiplier (20-50)"
> +	range 20 50
> +	default "40"
> +	help
> +	  Define CPU PLL multiplier. PLL is calculated by formula:
> +	    PLL Frequency = (PLL Multiplier / 2) * 3686400 Hz
> +	  Default value is 40, for achieve 73 MHz.
> +
Nack NO KConfig for such sensitve value

if it's soc detect it I do not have the datasheet but I'm sure you can

Best Regards,
J.
> +endmenu
> +
>  config BOARDINFO
>  	default "Cirrus Logic CLEP7212" if MACH_CLEP7212
>  
> diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
> index 5b8fe82..cc65cc8 100644
> --- a/arch/arm/mach-clps711x/include/mach/clps711x.h
> +++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
> @@ -281,6 +281,6 @@
>  #define MEMCFG_WAITSTATE_2_0	(14 << 2)
>  #define MEMCFG_WAITSTATE_1_0	(15 << 2)
>  
> -void clps711x_barebox_entry(void);
> +void clps711x_barebox_entry(u32);
>  
>  #endif
> diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c
> index cd3216a..193f61a 100644
> --- a/arch/arm/mach-clps711x/lowlevel.c
> +++ b/arch/arm/mach-clps711x/lowlevel.c
> @@ -17,9 +17,8 @@
>  
>  #include <mach/clps711x.h>
>  
> -void __naked __bare_init clps711x_barebox_entry(void)
> +void __naked __bare_init clps711x_barebox_entry(u32 pllmult)
>  {
> -	const u32 pllmult = 50;
>  	u32 cpu, bus;
>  
>  	/* Setup base clocking, Enable SDQM pins  */
> @@ -28,6 +27,10 @@ void __naked __bare_init clps711x_barebox_entry(void)
>  
>  	/* Check if we running from external 13 MHz clock */
>  	if (!(readl(SYSFLG2) & SYSFLG2_CKMODE)) {
> +		/* Check valid multiplier, default to 74 MHz */
> +		if ((pllmult < 20) || (pllmult > 50))
> +			pllmult = 40;
> +
>  		/* Setup PLL */
>  		writel(pllmult << 24, PLLW);
>  		asm("nop");
> -- 
> 1.7.3.4
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox

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Re[2]: [PATCH v2 3/9] ARM: clps711x: Adds config option for CPU PLL multiplier

[Alexander Shiyan]

...
> > diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
> > index b7d6d1d..fcf8285 100644
> > --- a/arch/arm/boards/clep7212/lowlevel.c
> > +++ b/arch/arm/boards/clep7212/lowlevel.c
> > @@ -14,9 +14,13 @@
> >  
> >  #include <mach/clps711x.h>
> >  
> > +#if (CONFIG_CLPS711X_CPU_PLL_MULT < 20) || (CONFIG_CLPS711X_CPU_PLL_MULT > 50)
> > +# error "CPU PLL multiplier out of range"
> > +#endif
> > +
> >  void __naked __bare_init barebox_arm_reset_vector(void)
> >  {
> >  	arm_cpu_lowlevel_init();
> >  
> > -	clps711x_barebox_entry();
> > +	clps711x_barebox_entry(CONFIG_CLPS711X_CPU_PLL_MULT);
> >  }
> > diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
> > index f0adeda..d2873b4 100644
> > --- a/arch/arm/mach-clps711x/Kconfig
> > +++ b/arch/arm/mach-clps711x/Kconfig
> > @@ -10,6 +10,19 @@ config MACH_CLEP7212
> >  
> >  endchoice
> >  
> > +menu "CLPS711X specific settings"
> > +
> > +config CLPS711X_CPU_PLL_MULT
> > +	int "CPU PLL multiplier (20-50)"
> > +	range 20 50
> > +	default "40"
> > +	help
> > +	  Define CPU PLL multiplier. PLL is calculated by formula:
> > +	    PLL Frequency = (PLL Multiplier / 2) * 3686400 Hz
> > +	  Default value is 40, for achieve 73 MHz.
> > +
> Nack NO KConfig for such sensitve value
> 
> if it's soc detect it I do not have the datasheet but I'm sure you can

There are two possible clock sources: 3.6864 MHz crystal or 13 MHz
clock. Only source can be detected. When crystal is chosen, CPU starts at
low speed, so we should setup PLL register to increase speed.
Detect more is impossible.

Datasheet, if you interest, here www.cirrus.com/en/pubs/manual/ep73xx_um-f.pdf
But I am doubt if you find more.

Thanks!

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Re: [SPAM] Re[2]: [PATCH v2 3/9] ARM: clps711x: Adds config option for CPU PLL multiplier

[Jean-Christophe PLAGNIOL-VILLARD]

On 16:23 Wed 13 Feb     , Alexander Shiyan wrote:
> ...
> > > diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
> > > index b7d6d1d..fcf8285 100644
> > > --- a/arch/arm/boards/clep7212/lowlevel.c
> > > +++ b/arch/arm/boards/clep7212/lowlevel.c
> > > @@ -14,9 +14,13 @@
> > >  
> > >  #include <mach/clps711x.h>
> > >  
> > > +#if (CONFIG_CLPS711X_CPU_PLL_MULT < 20) || (CONFIG_CLPS711X_CPU_PLL_MULT > 50)
> > > +# error "CPU PLL multiplier out of range"
> > > +#endif
> > > +
> > >  void __naked __bare_init barebox_arm_reset_vector(void)
> > >  {
> > >  	arm_cpu_lowlevel_init();
> > >  
> > > -	clps711x_barebox_entry();
> > > +	clps711x_barebox_entry(CONFIG_CLPS711X_CPU_PLL_MULT);
> > >  }
> > > diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
> > > index f0adeda..d2873b4 100644
> > > --- a/arch/arm/mach-clps711x/Kconfig
> > > +++ b/arch/arm/mach-clps711x/Kconfig
> > > @@ -10,6 +10,19 @@ config MACH_CLEP7212
> > >  
> > >  endchoice
> > >  
> > > +menu "CLPS711X specific settings"
> > > +
> > > +config CLPS711X_CPU_PLL_MULT
> > > +	int "CPU PLL multiplier (20-50)"
> > > +	range 20 50
> > > +	default "40"
> > > +	help
> > > +	  Define CPU PLL multiplier. PLL is calculated by formula:
> > > +	    PLL Frequency = (PLL Multiplier / 2) * 3686400 Hz
> > > +	  Default value is 40, for achieve 73 MHz.
> > > +
> > Nack NO KConfig for such sensitve value
> > 
> > if it's soc detect it I do not have the datasheet but I'm sure you can
> 
> There are two possible clock sources: 3.6864 MHz crystal or 13 MHz
> clock. Only source can be detected. When crystal is chosen, CPU starts at
> low speed, so we should setup PLL register to increase speed.
> Detect more is impossible.
> 
> Datasheet, if you interest, here www.cirrus.com/en/pubs/manual/ep73xx_um-f.pdf
> But I am doubt if you find more.
so do it in C anyway if someone want diferent tehy modify the C it's too much
dangerous otherwise

Best Regards,
J.
> 
> Thanks!
> 
> ---

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Re: [PATCH v2 3/9] ARM: clps711x: Adds config option for CPU PLL multiplier

[Sascha Hauer]

On Wed, Feb 13, 2013 at 03:41:38PM +0400, Alexander Shiyan wrote:
> 
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> ---
>  arch/arm/boards/clep7212/lowlevel.c            |    6 +++++-
>  arch/arm/mach-clps711x/Kconfig                 |   13 +++++++++++++
>  arch/arm/mach-clps711x/include/mach/clps711x.h |    2 +-
>  arch/arm/mach-clps711x/lowlevel.c              |    7 +++++--
>  4 files changed, 24 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
> index b7d6d1d..fcf8285 100644
> --- a/arch/arm/boards/clep7212/lowlevel.c
> +++ b/arch/arm/boards/clep7212/lowlevel.c
> @@ -14,9 +14,13 @@
>  
>  #include <mach/clps711x.h>
>  
> +#if (CONFIG_CLPS711X_CPU_PLL_MULT < 20) || (CONFIG_CLPS711X_CPU_PLL_MULT > 50)
> +# error "CPU PLL multiplier out of range"
> +#endif
> +
>  void __naked __bare_init barebox_arm_reset_vector(void)
>  {
>  	arm_cpu_lowlevel_init();
>  
> -	clps711x_barebox_entry();
> +	clps711x_barebox_entry(CONFIG_CLPS711X_CPU_PLL_MULT);

I don't quite understand why you want to have this configurable. I mean
this is a single board only, why not simply run it with the maximum
allowed frequency? Or does this board come with multiple SoCs for which
different maximum values exist?

Sascha


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Re[2]: [PATCH v2 3/9] ARM: clps711x: Adds config option for CPU PLL multiplier

[Alexander Shiyan]

> > Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> > ---
> >  arch/arm/boards/clep7212/lowlevel.c            |    6 +++++-
> >  arch/arm/mach-clps711x/Kconfig                 |   13 +++++++++++++
> >  arch/arm/mach-clps711x/include/mach/clps711x.h |    2 +-
> >  arch/arm/mach-clps711x/lowlevel.c              |    7 +++++--
> >  4 files changed, 24 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
> > index b7d6d1d..fcf8285 100644
> > --- a/arch/arm/boards/clep7212/lowlevel.c
> > +++ b/arch/arm/boards/clep7212/lowlevel.c
> > @@ -14,9 +14,13 @@
> >  
> >  #include <mach/clps711x.h>
> >  
> > +#if (CONFIG_CLPS711X_CPU_PLL_MULT < 20) || (CONFIG_CLPS711X_CPU_PLL_MULT > 50)
> > +# error "CPU PLL multiplier out of range"
> > +#endif
> > +
> >  void __naked __bare_init barebox_arm_reset_vector(void)
> >  {
> >  	arm_cpu_lowlevel_init();
> >  
> > -	clps711x_barebox_entry();
> > +	clps711x_barebox_entry(CONFIG_CLPS711X_CPU_PLL_MULT);
> 
> I don't quite understand why you want to have this configurable. I mean
> this is a single board only, why not simply run it with the maximum
> allowed frequency? Or does this board come with multiple SoCs for which
> different maximum values exist?

Yes. There are 2 versions of the chip. One with a maximum operating
frequency of 74 MHz, second with 90 MHz. The only difference is on the CPU label.
Which version is used, it is impossible to know in runtime.
You can simply reject this patch [3/9], all other should not depend on this one.
Later I'll try to make another different version.

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Re: [PATCH v2 3/9] ARM: clps711x: Adds config option for CPU PLL multiplier

[Sascha Hauer]

On Wed, Feb 13, 2013 at 09:20:09PM +0400, Alexander Shiyan wrote:
> > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> > > ---
> > >  arch/arm/boards/clep7212/lowlevel.c            |    6 +++++-
> > >  arch/arm/mach-clps711x/Kconfig                 |   13 +++++++++++++
> > >  arch/arm/mach-clps711x/include/mach/clps711x.h |    2 +-
> > >  arch/arm/mach-clps711x/lowlevel.c              |    7 +++++--
> > >  4 files changed, 24 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
> > > index b7d6d1d..fcf8285 100644
> > > --- a/arch/arm/boards/clep7212/lowlevel.c
> > > +++ b/arch/arm/boards/clep7212/lowlevel.c
> > > @@ -14,9 +14,13 @@
> > >  
> > >  #include <mach/clps711x.h>
> > >  
> > > +#if (CONFIG_CLPS711X_CPU_PLL_MULT < 20) || (CONFIG_CLPS711X_CPU_PLL_MULT > 50)
> > > +# error "CPU PLL multiplier out of range"
> > > +#endif
> > > +
> > >  void __naked __bare_init barebox_arm_reset_vector(void)
> > >  {
> > >  	arm_cpu_lowlevel_init();
> > >  
> > > -	clps711x_barebox_entry();
> > > +	clps711x_barebox_entry(CONFIG_CLPS711X_CPU_PLL_MULT);
> > 
> > I don't quite understand why you want to have this configurable. I mean
> > this is a single board only, why not simply run it with the maximum
> > allowed frequency? Or does this board come with multiple SoCs for which
> > different maximum values exist?
> 
> Yes. There are 2 versions of the chip. One with a maximum operating
> frequency of 74 MHz, second with 90 MHz. The only difference is on the CPU label.
> Which version is used, it is impossible to know in runtime.
> You can simply reject this patch [3/9], all other should not depend on this one.
> Later I'll try to make another different version.

Ok, thanks for explaining. It's really discouraged to put such things in
Kconfig, but in this case it seems acceptable: There's no way to detect
it during runtime *and* it varies across the same board type. So I
applied this series.

One option out of this might be that you could always startup with 74MHz
and add a command to switch to 90MHz. You could put this into the
environment on boards that you know work with 90MHz. Aynway, I don't
want to force you to do this on an Architecture you're probably
currently the only user of.

Sascha

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Re: [PATCH v2 3/9] ARM: clps711x: Adds config option for CPU PLL multiplier

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:40 Wed 13 Feb     , Sascha Hauer wrote:
> On Wed, Feb 13, 2013 at 09:20:09PM +0400, Alexander Shiyan wrote:
> > > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> > > > ---
> > > >  arch/arm/boards/clep7212/lowlevel.c            |    6 +++++-
> > > >  arch/arm/mach-clps711x/Kconfig                 |   13 +++++++++++++
> > > >  arch/arm/mach-clps711x/include/mach/clps711x.h |    2 +-
> > > >  arch/arm/mach-clps711x/lowlevel.c              |    7 +++++--
> > > >  4 files changed, 24 insertions(+), 4 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
> > > > index b7d6d1d..fcf8285 100644
> > > > --- a/arch/arm/boards/clep7212/lowlevel.c
> > > > +++ b/arch/arm/boards/clep7212/lowlevel.c
> > > > @@ -14,9 +14,13 @@
> > > >  
> > > >  #include <mach/clps711x.h>
> > > >  
> > > > +#if (CONFIG_CLPS711X_CPU_PLL_MULT < 20) || (CONFIG_CLPS711X_CPU_PLL_MULT > 50)
> > > > +# error "CPU PLL multiplier out of range"
> > > > +#endif
> > > > +
> > > >  void __naked __bare_init barebox_arm_reset_vector(void)
> > > >  {
> > > >  	arm_cpu_lowlevel_init();
> > > >  
> > > > -	clps711x_barebox_entry();
> > > > +	clps711x_barebox_entry(CONFIG_CLPS711X_CPU_PLL_MULT);
> > > 
> > > I don't quite understand why you want to have this configurable. I mean
> > > this is a single board only, why not simply run it with the maximum
> > > allowed frequency? Or does this board come with multiple SoCs for which
> > > different maximum values exist?
> > 
> > Yes. There are 2 versions of the chip. One with a maximum operating
> > frequency of 74 MHz, second with 90 MHz. The only difference is on the CPU label.
> > Which version is used, it is impossible to know in runtime.
> > You can simply reject this patch [3/9], all other should not depend on this one.
> > Later I'll try to make another different version.
> 
> Ok, thanks for explaining. It's really discouraged to put such things in
> Kconfig, but in this case it seems acceptable: There's no way to detect
> it during runtime *and* it varies across the same board type. So I
> applied this series.
> 
> One option out of this might be that you could always startup with 74MHz
> and add a command to switch to 90MHz. You could put this into the
> environment on boards that you know work with 90MHz. Aynway, I don't
> want to force you to do this on an Architecture you're probably
> currently the only user of.
agress if not possible so use specific KConfig not a value

Best Regards,
J.
> 
> Sascha
> 
> -- 
> Pengutronix e.K.                           |                             |
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Re[2]: [PATCH v2 3/9] ARM: clps711x: Adds config option for CPU PLL multiplier

[Alexander Shiyan]

...
> > > I don't quite understand why you want to have this configurable. I mean
> > > this is a single board only, why not simply run it with the maximum
> > > allowed frequency? Or does this board come with multiple SoCs for which
> > > different maximum values exist?
> > 
> > Yes. There are 2 versions of the chip. One with a maximum operating
> > frequency of 74 MHz, second with 90 MHz. The only difference is on the CPU label.
> > Which version is used, it is impossible to know in runtime.
> > You can simply reject this patch [3/9], all other should not depend on this one.
> > Later I'll try to make another different version.
> 
> Ok, thanks for explaining. It's really discouraged to put such things in
> Kconfig, but in this case it seems acceptable: There's no way to detect
> it during runtime *and* it varies across the same board type. So I
> applied this series.
> 
> One option out of this might be that you could always startup with 74MHz
> and add a command to switch to 90MHz. You could put this into the
> environment on boards that you know work with 90MHz. Aynway, I don't
> want to force you to do this on an Architecture you're probably
> currently the only user of.

OK. Thanks.

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