From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from ns.lynxeye.de ([87.118.118.114] helo=lynxeye.de) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UdQ0O-0004LW-K2 for barebox@lists.infradead.org; Fri, 17 May 2013 19:07:53 +0000 Message-ID: <1368817605.2463.1.camel@antimon> From: Lucas Stach Date: Fri, 17 May 2013 21:06:45 +0200 In-Reply-To: <1368779715-3143-1-git-send-email-s.hauer@pengutronix.de> References: <1368779715-3143-1-git-send-email-s.hauer@pengutronix.de> Mime-Version: 1.0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============9067412433413715852==" Sender: "barebox" Errors-To: barebox-bounces+u.kleine-koenig=pengutronix.de@lists.infradead.org Subject: Re: [PATCH] ARM: invalidate data caches during early init To: Sascha Hauer Cc: barebox@lists.infradead.org, Enrico Scholz --===============9067412433413715852== Content-Type: multipart/signed; micalg="sha1"; protocol="application/x-pkcs7-signature"; boundary="=-0WMEjNv5vq+WWhnYV0o8" --=-0WMEjNv5vq+WWhnYV0o8 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Am Freitag, den 17.05.2013, 10:35 +0200 schrieb Sascha Hauer: > Some SoCs come up with invalid entries in the data cache. This can > lead to memory corruption when we enable them later, so invalidate > the caches early. >=20 > Signed-off-by: Sascha Hauer > CC: Enrico Scholz Reviewed-by: Lucas Stach Tested-by: Lucas Stach > --- >=20 > This is based on the patches Enrico recently sent. Enrico, I hope > this fixes your data cache issues in a way that you do not have > to add this to your board code. >=20 > arch/arm/cpu/cache.c | 21 +++++++++++++++++++++ > arch/arm/cpu/start-pbl.c | 2 ++ > arch/arm/cpu/start.c | 2 ++ > arch/arm/include/asm/cache.h | 5 +++++ > 4 files changed, 30 insertions(+) >=20 > diff --git a/arch/arm/cpu/cache.c b/arch/arm/cpu/cache.c > index 95c8338..7aab55b 100644 > --- a/arch/arm/cpu/cache.c > +++ b/arch/arm/cpu/cache.c > @@ -134,3 +134,24 @@ void arm_early_mmu_cache_flush(void) > #endif > } > } > + > +void v7_mmu_cache_invalidate(void); > + > +void arm_early_mmu_cache_invalidate(void) > +{ > + switch (arm_early_get_cpu_architecture()) { > + case CPU_ARCH_ARMv4T: > + case CPU_ARCH_ARMv5: > + case CPU_ARCH_ARMv5T: > + case CPU_ARCH_ARMv5TE: > + case CPU_ARCH_ARMv5TEJ: > + case CPU_ARCH_ARMv6: > + asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0)); > + return; > +#ifdef CONFIG_CPU_32v7 > + case CPU_ARCH_ARMv7: > + v7_mmu_cache_invalidate(); > + return; > +#endif > + } > +} > diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c > index 6f03c4a..3ef0118 100644 > --- a/arch/arm/cpu/start-pbl.c > +++ b/arch/arm/cpu/start-pbl.c > @@ -59,6 +59,8 @@ static noinline __noreturn void __barebox_arm_entry(uin= t32_t membase, > =20 > endmem -=3D STACK_SIZE; /* stack */ > =20 > + arm_early_mmu_cache_invalidate(); > + > if (IS_ENABLED(CONFIG_PBL_RELOCATABLE)) > relocate_to_current_adr(); > =20 > diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c > index 580c1fe..5a3c629 100644 > --- a/arch/arm/cpu/start.c > +++ b/arch/arm/cpu/start.c > @@ -124,6 +124,8 @@ void __naked __noreturn barebox_arm_entry(uint32_t me= mbase, uint32_t memsize, > { > arm_setup_stack(membase + memsize - 16); > =20 > + arm_early_mmu_cache_invalidate(); > + > __start(membase, memsize, boarddata); > } > #else > diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h > index e5621eb..f5f8bf3 100644 > --- a/arch/arm/include/asm/cache.h > +++ b/arch/arm/include/asm/cache.h > @@ -10,10 +10,15 @@ int arm_set_cache_functions(void); > =20 > #ifdef CONFIG_MMU > void arm_early_mmu_cache_flush(void); > +void arm_early_mmu_cache_invalidate(void); > #else > static inline void arm_early_mmu_cache_flush(void) > { > } > + > +static inline void arm_early_mmu_cache_invalidate(void) > +{ > +} > #endif > =20 > #endif --=-0WMEjNv5vq+WWhnYV0o8 Content-Type: application/x-pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExCzAJBgUrDgMCGgUAMIAGCSqGSIb3DQEHAQAAoIISpjCCBjMw ggUboAMCAQICAwZk4jANBgkqhkiG9w0BAQUFADCBjDELMAkGA1UEBhMCSUwxFjAUBgNVBAoTDVN0 YXJ0Q29tIEx0ZC4xKzApBgNVBAsTIlNlY3VyZSBEaWdpdGFsIENlcnRpZmljYXRlIFNpZ25pbmcx ODA2BgNVBAMTL1N0YXJ0Q29tIENsYXNzIDEgUHJpbWFyeSBJbnRlcm1lZGlhdGUgQ2xpZW50IENB MB4XDTEzMDQxNDA4MTkxMFoXDTE0MDQxNTE1MjIzNlowUzEZMBcGA1UEDRMQVzBZM3MzM2ZHVmRM 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