From: Sascha Hauer <s.hauer@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Juergen Beisert <jbe@pengutronix.de>
Subject: [PATCH 05/17] ARM: MXS: add clk drivers
Date: Thu, 20 Jun 2013 08:54:09 +0200 [thread overview]
Message-ID: <1371711261-10039-6-git-send-email-s.hauer@pengutronix.de> (raw)
In-Reply-To: <1371711261-10039-1-git-send-email-s.hauer@pengutronix.de>
This adds support for the i.MX23 and i.MX28 clock modules. This mostly is
a copy from the kernel.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-mxs/soc-imx23.c | 9 ++
arch/arm/mach-mxs/soc-imx28.c | 9 ++
drivers/clk/mxs/Makefile | 3 +
drivers/clk/mxs/clk-imx23.c | 156 +++++++++++++++++++++++++++++++++
drivers/clk/mxs/clk-imx28.c | 195 ++++++++++++++++++++++++++++++++++++++++++
5 files changed, 372 insertions(+)
create mode 100644 drivers/clk/mxs/clk-imx23.c
create mode 100644 drivers/clk/mxs/clk-imx28.c
diff --git a/arch/arm/mach-mxs/soc-imx23.c b/arch/arm/mach-mxs/soc-imx23.c
index 6819b3c..4e45064 100644
--- a/arch/arm/mach-mxs/soc-imx23.c
+++ b/arch/arm/mach-mxs/soc-imx23.c
@@ -35,3 +35,12 @@ void __noreturn reset_cpu(unsigned long addr)
/*NOTREACHED*/
}
EXPORT_SYMBOL(reset_cpu);
+
+static int imx23_devices_init(void)
+{
+
+ add_generic_device("imx23-clkctrl", 0, NULL, IMX_CCM_BASE, 0x100, IORESOURCE_MEM, NULL);
+
+ return 0;
+}
+postcore_initcall(imx23_devices_init);
diff --git a/arch/arm/mach-mxs/soc-imx28.c b/arch/arm/mach-mxs/soc-imx28.c
index ed931af..426f8ac 100644
--- a/arch/arm/mach-mxs/soc-imx28.c
+++ b/arch/arm/mach-mxs/soc-imx28.c
@@ -53,3 +53,12 @@ static int imx28_init(void)
return 0;
}
postcore_initcall(imx28_init);
+
+static int imx28_devices_init(void)
+{
+
+ add_generic_device("imx28-clkctrl", 0, NULL, IMX_CCM_BASE, 0x100, IORESOURCE_MEM, NULL);
+
+ return 0;
+}
+postcore_initcall(imx28_devices_init);
diff --git a/drivers/clk/mxs/Makefile b/drivers/clk/mxs/Makefile
index 8b1173d..fb4e5db 100644
--- a/drivers/clk/mxs/Makefile
+++ b/drivers/clk/mxs/Makefile
@@ -1,2 +1,5 @@
obj-$(CONFIG_ARCH_MXS) += clk-ref.o clk-pll.o clk-frac.o clk-div.o
obj-$(CONFIG_DRIVER_VIDEO_STM) += clk-lcdif.o
+
+obj-$(CONFIG_ARCH_IMX23) += clk-imx23.o
+obj-$(CONFIG_ARCH_IMX28) += clk-imx28.o
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
new file mode 100644
index 0000000..4b15350
--- /dev/null
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <mach/imx-regs.h>
+
+#include "clk.h"
+
+#define PLLCTRL0 (regs + 0x0000)
+#define CPU (regs + 0x0020)
+#define HBUS (regs + 0x0030)
+#define XBUS (regs + 0x0040)
+#define XTAL (regs + 0x0050)
+#define PIX (regs + 0x0060)
+#define SSP (regs + 0x0070)
+#define GPMI (regs + 0x0080)
+#define SPDIF (regs + 0x0090)
+#define EMI (regs + 0x00a0)
+#define SAIF (regs + 0x00c0)
+#define TV (regs + 0x00d0)
+#define ETM (regs + 0x00e0)
+#define FRAC (regs + 0x00f0)
+#define CLKSEQ (regs + 0x0110)
+
+static const char *sel_pll[] = { "pll", "ref_xtal", };
+static const char *sel_cpu[] = { "ref_cpu", "ref_xtal", };
+static const char *sel_pix[] = { "ref_pix", "ref_xtal", };
+static const char *sel_io[] = { "ref_io", "ref_xtal", };
+static const char *cpu_sels[] = { "cpu_pll", "cpu_xtal", };
+static const char *emi_sels[] = { "emi_pll", "emi_xtal", };
+
+enum imx23_clk {
+ ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel,
+ lcdif_sel, gpmi_sel, ssp_sel, emi_sel, cpu, etm_sel, cpu_pll,
+ cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll,
+ emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div,
+ clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif,
+ lcdif, etm, usb, usb_phy, lcdif_comp,
+ clk_max
+};
+
+static struct clk *clks[clk_max];
+
+int __init mx23_clocks_init(void __iomem *regs)
+{
+ clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
+ clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000);
+ clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0);
+ clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1);
+ clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2);
+ clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3);
+ clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll));
+ clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix));
+ clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io));
+ clks[ssp_sel] = mxs_clk_mux("ssp_sel", CLKSEQ, 5, 1, sel_io, ARRAY_SIZE(sel_io));
+ clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 6, 1, emi_sels, ARRAY_SIZE(emi_sels));
+ clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 7, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
+ clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
+ clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
+ clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
+ clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29);
+ clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
+ clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29);
+ clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29);
+ clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
+ clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
+ clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
+ clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29);
+ clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29);
+ clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
+ clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
+ clks[adc] = mxs_clk_fixed_factor("adc", "clk32k", 1, 16);
+ clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4);
+ clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
+ clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28);
+ clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
+ clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30);
+ clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
+ clks[ssp] = mxs_clk_gate("ssp", "ssp_div", SSP, 31);
+ clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
+ clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
+ clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
+ clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31);
+ clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31);
+ clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
+ clks[lcdif_comp] = mxs_clk_lcdif("lcdif_comp", clks[ref_pix],
+ clks[lcdif_div], clks[lcdif]);
+
+ clk_set_rate(clks[ref_io], 480000000);
+ clk_set_parent(clks[ssp_sel], clks[ref_io]);
+ clk_set_rate(clks[ssp_div], 96000000);
+ clk_set_parent(clks[lcdif_sel], clks[ref_pix]);
+
+ clkdev_add_physbase(clks[ssp], IMX_SSP1_BASE, NULL);
+ clkdev_add_physbase(clks[ssp], IMX_SSP2_BASE, NULL);
+ clkdev_add_physbase(clks[xbus], IMX_DBGUART_BASE, NULL);
+ clkdev_add_physbase(clks[hbus], IMX_OCOTP_BASE, NULL);
+ clkdev_add_physbase(clks[uart], IMX_UART1_BASE, NULL);
+ clkdev_add_physbase(clks[uart], IMX_UART2_BASE, NULL);
+ clkdev_add_physbase(clks[gpmi], MXS_GPMI_BASE, NULL);
+ if (IS_ENABLED(CONFIG_DRIVER_VIDEO_STM))
+ clkdev_add_physbase(clks[lcdif_comp], IMX_FB_BASE, NULL);
+
+ return 0;
+}
+
+static int imx23_ccm_probe(struct device_d *dev)
+{
+ void __iomem *regs;
+
+ regs = dev_request_mem_region(dev, 0);
+
+ mx23_clocks_init(regs);
+
+ return 0;
+}
+
+static __maybe_unused struct of_device_id imx23_ccm_dt_ids[] = {
+ {
+ .compatible = "fsl,imx23-clkctrl",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d imx23_ccm_driver = {
+ .probe = imx23_ccm_probe,
+ .name = "imx23-clkctrl",
+ .of_compatible = DRV_OF_COMPAT(imx23_ccm_dt_ids),
+};
+
+static int imx23_ccm_init(void)
+{
+ return platform_driver_register(&imx23_ccm_driver);
+}
+postcore_initcall(imx23_ccm_init);
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
new file mode 100644
index 0000000..0350aff
--- /dev/null
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <mach/imx-regs.h>
+
+#include "clk.h"
+
+#define PLL0CTRL0 (regs + 0x0000)
+#define PLL1CTRL0 (regs + 0x0020)
+#define PLL2CTRL0 (regs + 0x0040)
+#define CPU (regs + 0x0050)
+#define HBUS (regs + 0x0060)
+#define XBUS (regs + 0x0070)
+#define XTAL (regs + 0x0080)
+#define SSP0 (regs + 0x0090)
+#define SSP1 (regs + 0x00a0)
+#define SSP2 (regs + 0x00b0)
+#define SSP3 (regs + 0x00c0)
+#define GPMI (regs + 0x00d0)
+#define SPDIF (regs + 0x00e0)
+#define EMI (regs + 0x00f0)
+#define SAIF0 (regs + 0x0100)
+#define SAIF1 (regs + 0x0110)
+#define LCDIF (regs + 0x0120)
+#define ETM (regs + 0x0130)
+#define ENET (regs + 0x0140)
+#define FLEXCAN (regs + 0x0160)
+#define FRAC0 (regs + 0x01b0)
+#define FRAC1 (regs + 0x01c0)
+#define CLKSEQ (regs + 0x01d0)
+
+static const char *sel_cpu[] = { "ref_cpu", "ref_xtal", };
+static const char *sel_io0[] = { "ref_io0", "ref_xtal", };
+static const char *sel_io1[] = { "ref_io1", "ref_xtal", };
+static const char *sel_pix[] = { "ref_pix", "ref_xtal", };
+static const char *sel_gpmi[] = { "ref_gpmi", "ref_xtal", };
+static const char *cpu_sels[] = { "cpu_pll", "cpu_xtal", };
+static const char *emi_sels[] = { "emi_pll", "emi_xtal", };
+static const char *ptp_sels[] = { "ref_xtal", "pll0", };
+
+enum imx28_clk {
+ ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1,
+ ref_pix, ref_hsadc, ref_gpmi, saif0_sel, saif1_sel, gpmi_sel,
+ ssp0_sel, ssp1_sel, ssp2_sel, ssp3_sel, emi_sel, etm_sel,
+ lcdif_sel, cpu, ptp_sel, cpu_pll, cpu_xtal, hbus, xbus,
+ ssp0_div, ssp1_div, ssp2_div, ssp3_div, gpmi_div, emi_pll,
+ emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div,
+ clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0,
+ ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,
+ fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out,
+ lcdif_comp, clk_max
+};
+
+static struct clk *clks[clk_max];
+
+int __init mx28_clocks_init(void __iomem *regs)
+{
+ clks[ref_xtal] = clk_fixed("ref_xtal", 24000000);
+ clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000);
+ clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000);
+ clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000);
+ clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0);
+ clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1);
+ clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2);
+ clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3);
+ clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0);
+ clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1);
+ clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2);
+ clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi));
+ clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0));
+ clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0));
+ clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1));
+ clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1));
+ clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels));
+ clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
+ clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix));
+ clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
+ clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels));
+ clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
+ clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
+ clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31);
+ clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
+ clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29);
+ clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29);
+ clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29);
+ clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29);
+ clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
+ clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
+ clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
+ clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29);
+ clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29);
+ clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
+ clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
+ clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16);
+ clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
+ clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
+ clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
+ clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31);
+ clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31);
+ clks[ssp2] = mxs_clk_gate("ssp2", "ssp2_div", SSP2, 31);
+ clks[ssp3] = mxs_clk_gate("ssp3", "ssp3_div", SSP3, 31);
+ clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
+ clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
+ clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31);
+ clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
+ clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30);
+ clks[usb0_phy] = mxs_clk_gate("usb0_phy", "pll0", PLL0CTRL0, 18);
+ clks[usb1_phy] = mxs_clk_gate("usb1_phy", "pll1", PLL1CTRL0, 18);
+ clks[enet_out] = clk_gate("enet_out", "pll2", ENET, 18);
+ clks[lcdif_comp] = mxs_clk_lcdif("lcdif_comp", clks[ref_pix],
+ clks[lcdif_div], clks[lcdif]);
+
+ clk_set_rate(clks[ref_io0], 480000000);
+ clk_set_rate(clks[ref_io1], 480000000);
+ clk_set_parent(clks[ssp0_sel], clks[ref_io0]);
+ clk_set_parent(clks[ssp1_sel], clks[ref_io0]);
+ clk_set_parent(clks[ssp2_sel], clks[ref_io1]);
+ clk_set_parent(clks[ssp3_sel], clks[ref_io1]);
+ clk_set_rate(clks[ssp0_div], 96000000);
+ clk_set_rate(clks[ssp1_div], 96000000);
+ clk_set_rate(clks[ssp2_div], 96000000);
+ clk_set_rate(clks[ssp3_div], 96000000);
+ clk_set_parent(clks[lcdif_sel], clks[ref_pix]);
+ clk_enable(clks[enet_out]);
+
+ clkdev_add_physbase(clks[ssp0], IMX_SSP0_BASE, NULL);
+ clkdev_add_physbase(clks[ssp1], IMX_SSP1_BASE, NULL);
+ clkdev_add_physbase(clks[ssp2], IMX_SSP2_BASE, NULL);
+ clkdev_add_physbase(clks[ssp3], IMX_SSP3_BASE, NULL);
+ clkdev_add_physbase(clks[fec], IMX_FEC0_BASE, NULL);
+ clkdev_add_physbase(clks[xbus], IMX_DBGUART_BASE, NULL);
+ clkdev_add_physbase(clks[hbus], IMX_OCOTP_BASE, NULL);
+ clkdev_add_physbase(clks[uart], IMX_UART0_BASE, NULL);
+ clkdev_add_physbase(clks[uart], IMX_UART1_BASE, NULL);
+ clkdev_add_physbase(clks[uart], IMX_UART2_BASE, NULL);
+ clkdev_add_physbase(clks[uart], IMX_UART3_BASE, NULL);
+ clkdev_add_physbase(clks[uart], IMX_UART4_BASE, NULL);
+ clkdev_add_physbase(clks[gpmi], MXS_GPMI_BASE, NULL);
+ if (IS_ENABLED(CONFIG_DRIVER_VIDEO_STM))
+ clkdev_add_physbase(clks[lcdif_comp], IMX_FB_BASE, NULL);
+
+ return 0;
+}
+
+static int imx28_ccm_probe(struct device_d *dev)
+{
+ void __iomem *regs;
+
+ regs = dev_request_mem_region(dev, 0);
+
+ mx28_clocks_init(regs);
+
+ return 0;
+}
+
+static __maybe_unused struct of_device_id imx28_ccm_dt_ids[] = {
+ {
+ .compatible = "fsl,imx28-clkctrl",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d imx28_ccm_driver = {
+ .probe = imx28_ccm_probe,
+ .name = "imx28-clkctrl",
+ .of_compatible = DRV_OF_COMPAT(imx28_ccm_dt_ids),
+};
+
+static int imx28_ccm_init(void)
+{
+ return platform_driver_register(&imx28_ccm_driver);
+}
+postcore_initcall(imx28_ccm_init);
--
1.8.3.1
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next prev parent reply other threads:[~2013-06-20 6:55 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-20 6:54 [PATCH] convert MXS to common clk Sascha Hauer
2013-06-20 6:54 ` [PATCH 01/17] clk: divider: Add onebased divider support Sascha Hauer
2013-06-20 6:54 ` [PATCH 02/17] clk: gate: Add inverted gate support Sascha Hauer
2013-06-20 6:54 ` [PATCH 03/17] clk: add prototype for clk_is_enabled Sascha Hauer
2013-06-20 6:54 ` [PATCH 04/17] ARM: MXS: Add MXS specific clk types Sascha Hauer
2013-06-21 12:14 ` Jürgen Beisert
2013-06-20 6:54 ` Sascha Hauer [this message]
2013-06-20 6:54 ` [PATCH 06/17] ARM: MXS: remove board specific clock setups Sascha Hauer
2013-06-20 6:54 ` [PATCH 07/17] mci: mxs: Use dev_* Sascha Hauer
2013-06-20 6:54 ` [PATCH 08/17] net: fec: Use clk API unconditionally Sascha Hauer
2013-06-20 6:54 ` [PATCH 09/17] mci: mxs: use common clk API Sascha Hauer
2013-06-20 6:54 ` [PATCH 10/17] mtd: gpmi-nand: switch to clk support Sascha Hauer
2013-06-20 6:54 ` [PATCH 11/17] serial: auart: Use " Sascha Hauer
2013-06-20 6:54 ` [PATCH 12/17] serial: stm: " Sascha Hauer
2013-06-20 6:54 ` [PATCH 13/17] spi: mxs: " Sascha Hauer
2013-06-20 6:54 ` [PATCH 14/17] ARM: MXS: octotp: switch to " Sascha Hauer
2013-06-20 6:54 ` [PATCH 15/17] ARM: MXS: remove imx_enable_enetclk Sascha Hauer
2013-06-20 6:54 ` [PATCH 16/17] video: stm: switch to clk support Sascha Hauer
2013-06-20 6:54 ` [PATCH 17/17] ARM: MXS: remove old clock support Sascha Hauer
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