[PATCH] prepare i.MX6 NAND support

[PATCH] prepare i.MX6 NAND support

[Sascha Hauer]

The i.MX6 uses the same GPMI Nand controller as the i.MX23/28.
We already have this driver in the tree. This series prepares
using it on i.MX6 aswell.
This series is only preparation, i.MX6 Nand support itself has
to wait a few more days.

Sascha

----------------------------------------------------------------
Sascha Hauer (11):
      ARM: MXS: introduce stmp device support
      dma: apbh: introduce private struct
      dma: apbh-dma: move header file to common location
      dma: apbh: remove CONFIG_ARCH_DMA_PIO_WORDS
      dma: apbh: Turn into a driver
      dma: apbh: add devicetree probe support
      dma: apbh: cleanup includes
      mtd: nand: gpmi: use io_base instead of MXS_GPMI_BASE
      mtd: nand: gpmi: cleanup includes
      ARM: mxs: Add convenience wrapper to register mxs_nand device
      mtd: nand: gpmi: replace MXS_BCH_BASE with driver resources

 arch/arm/boards/freescale-mx28-evk/mx28-evk.c      |   4 +-
 arch/arm/boards/karo-tx28/tx28.c                   |   4 +-
 arch/arm/mach-mxs/Kconfig                          |   2 +
 arch/arm/mach-mxs/Makefile                         |   2 +-
 arch/arm/mach-mxs/imx.c                            |   3 +-
 arch/arm/mach-mxs/include/mach/devices.h           |  47 ++++++
 arch/arm/mach-mxs/include/mach/imx-regs.h          |   5 -
 arch/arm/mach-mxs/include/mach/mxs.h               |   6 -
 arch/arm/mach-mxs/iomux-imx.c                      |  27 ++--
 arch/arm/mach-mxs/ocotp.c                          |   9 +-
 arch/arm/mach-mxs/power.c                          |   5 +-
 arch/arm/mach-mxs/soc-imx23.c                      |   2 +-
 arch/arm/mach-mxs/soc-imx28.c                      |   2 +-
 drivers/dma/Kconfig                                |   1 +
 drivers/dma/apbh_dma.c                             | 176 ++++++++++++++-------
 drivers/mci/mxs.c                                  |   4 +-
 drivers/mtd/nand/nand_mxs.c                        |  40 +++--
 drivers/serial/serial_auart.c                      |   2 +-
 drivers/spi/mxs_spi.c                              |  27 ++--
 drivers/video/stm.c                                |  11 +-
 .../include/mach/dma.h => include/dma/apbh-dma.h   |   9 +-
 include/driver.h                                   |   2 +
 include/stmp-device.h                              |  22 +++
 lib/Kconfig                                        |   3 +
 lib/Makefile                                       |   1 +
 arch/arm/mach-mxs/common.c => lib/stmp-device.c    |  29 ++--
 26 files changed, 290 insertions(+), 155 deletions(-)
 create mode 100644 arch/arm/mach-mxs/include/mach/devices.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/mxs.h
 rename arch/arm/mach-mxs/include/mach/dma.h => include/dma/apbh-dma.h (95%)
 create mode 100644 include/stmp-device.h
 rename arch/arm/mach-mxs/common.c => lib/stmp-device.c (51%)

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[PATCH 01/11] ARM: MXS: introduce stmp device support

[Sascha Hauer]

MXS specific devices have some common infrastructure in the kernel
known as STMP devices. We have the same in barebox, but with a
mxs_ prefix instead of a stmp_ prefix. As some STMP devices are
also found on i.MX6 move the common infrastructure out of MXS
specific files and use the stmp_ prefix.

This is done in preparation for i.MX6 NAND support.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-mxs/Kconfig                 |  2 +
 arch/arm/mach-mxs/Makefile                |  2 +-
 arch/arm/mach-mxs/common.c                | 64 -------------------------------
 arch/arm/mach-mxs/imx.c                   |  3 +-
 arch/arm/mach-mxs/include/mach/imx-regs.h |  5 ---
 arch/arm/mach-mxs/include/mach/mxs.h      |  6 ---
 arch/arm/mach-mxs/iomux-imx.c             | 27 +++++++------
 arch/arm/mach-mxs/ocotp.c                 |  9 +++--
 arch/arm/mach-mxs/power.c                 |  5 ++-
 drivers/dma/Kconfig                       |  1 +
 drivers/dma/apbh_dma.c                    | 24 ++++++------
 drivers/mci/mxs.c                         |  4 +-
 drivers/mtd/nand/nand_mxs.c               | 12 +++---
 drivers/serial/serial_auart.c             |  2 +-
 drivers/spi/mxs_spi.c                     | 27 ++++++-------
 drivers/video/stm.c                       | 11 +++---
 include/stmp-device.h                     | 22 +++++++++++
 lib/Kconfig                               |  3 ++
 lib/Makefile                              |  1 +
 lib/stmp-device.c                         | 63 ++++++++++++++++++++++++++++++
 20 files changed, 160 insertions(+), 133 deletions(-)
 delete mode 100644 arch/arm/mach-mxs/common.c
 delete mode 100644 arch/arm/mach-mxs/include/mach/mxs.h
 create mode 100644 include/stmp-device.h
 create mode 100644 lib/stmp-device.c

diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index d1bf8fc..128bf84 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -24,11 +24,13 @@ choice
 
 config ARCH_IMX23
 	bool "i.MX23"
+	select STMP_DEVICE
 	select CPU_ARM926T
 
 config ARCH_IMX28
 	bool "i.MX28"
 	select CPU_ARM926T
+	select STMP_DEVICE
 	select ARCH_HAS_FEC_IMX
 
 endchoice
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index a183987..bd6892e 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,4 +1,4 @@
-obj-y += imx.o iomux-imx.o power.o common.o
+obj-y += imx.o iomux-imx.o power.o
 obj-$(CONFIG_ARCH_IMX23) += clocksource-imx23.o usb-imx23.o soc-imx23.o
 obj-$(CONFIG_ARCH_IMX28) += clocksource-imx28.o usb-imx28.o soc-imx28.o
 obj-$(CONFIG_MXS_OCOTP) += ocotp.o
diff --git a/arch/arm/mach-mxs/common.c b/arch/arm/mach-mxs/common.c
deleted file mode 100644
index 122d883..0000000
--- a/arch/arm/mach-mxs/common.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Freescale i.MXS common code
- *
- * Copyright (C) 2012 Wolfram Sang <w.sang@pengutronix.de>
- *
- * Based on code from LTIB:
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- */
-
-#include <common.h>
-#include <io.h>
-#include <errno.h>
-#include <clock.h>
-#include <mach/mxs.h>
-#include <mach/imx-regs.h>
-
-#define	MXS_IP_RESET_TIMEOUT	(10 * MSECOND)
-
-#define	MXS_BLOCK_SFTRST				(1 << 31)
-#define	MXS_BLOCK_CLKGATE				(1 << 30)
-
-int mxs_reset_block(void __iomem *reg, int just_enable)
-{
-	/* Clear SFTRST */
-	writel(MXS_BLOCK_SFTRST, reg + BIT_CLR);
-
-	if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, !(readl(reg) & MXS_BLOCK_SFTRST)))
-		goto timeout;
-
-	/* Clear CLKGATE */
-	writel(MXS_BLOCK_CLKGATE, reg + BIT_CLR);
-
-	if (!just_enable) {
-		/* Set SFTRST */
-		writel(MXS_BLOCK_SFTRST, reg + BIT_SET);
-
-		/* Wait for CLKGATE being set */
-		if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, readl(reg) & MXS_BLOCK_CLKGATE))
-			goto timeout;
-	}
-
-	/* Clear SFTRST */
-	writel(MXS_BLOCK_SFTRST, reg + BIT_CLR);
-
-	if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, !(readl(reg) & MXS_BLOCK_SFTRST)))
-		goto timeout;
-
-	/* Clear CLKGATE */
-	writel(MXS_BLOCK_CLKGATE, reg + BIT_CLR);
-
-	if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, !(readl(reg) & MXS_BLOCK_CLKGATE)))
-		goto timeout;
-
-	return 0;
-
-timeout:
-	printf("MXS: Timeout resetting block via register 0x%p\n", reg);
-	return -ETIMEDOUT;
-}
diff --git a/arch/arm/mach-mxs/imx.c b/arch/arm/mach-mxs/imx.c
index 9f195e4..b7247b9 100644
--- a/arch/arm/mach-mxs/imx.c
+++ b/arch/arm/mach-mxs/imx.c
@@ -19,6 +19,7 @@
 #include <complete.h>
 #include <init.h>
 #include <io.h>
+#include <stmp-device.h>
 
 #include <mach/generic.h>
 #include <mach/imx-regs.h>
@@ -39,7 +40,7 @@ static int imx_reset_usb_bootstrap(void)
 	 * To prevent this (and boot from the configured bootsource instead)
 	 * clear this bit here.
 	 */
-	writel(0x2, IMX_WDT_BASE + HW_RTC_PERSISTENT1 + BIT_CLR);
+	writel(0x2, IMX_WDT_BASE + HW_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
 
 	return 0;
 }
diff --git a/arch/arm/mach-mxs/include/mach/imx-regs.h b/arch/arm/mach-mxs/include/mach/imx-regs.h
index 39c97b7..f5abd8b 100644
--- a/arch/arm/mach-mxs/include/mach/imx-regs.h
+++ b/arch/arm/mach-mxs/include/mach/imx-regs.h
@@ -16,11 +16,6 @@
 #ifndef _IMX_REGS_H
 # define _IMX_REGS_H
 
-/* Note: Some registers do not support this bit change feature! */
-#define BIT_SET 0x04
-#define BIT_CLR 0x08
-#define BIT_TGL 0x0C
-
 #if defined CONFIG_ARCH_IMX23
 # include <mach/imx23-regs.h>
 #endif
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
deleted file mode 100644
index 182ed8a..0000000
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __MACH_MXS_H
-#define __MACH_MXS_H
-
-int mxs_reset_block(void __iomem *reg, int just_enable);
-
-#endif /* __MACH_MXS_H */
diff --git a/arch/arm/mach-mxs/iomux-imx.c b/arch/arm/mach-mxs/iomux-imx.c
index 66ba743..3d26302 100644
--- a/arch/arm/mach-mxs/iomux-imx.c
+++ b/arch/arm/mach-mxs/iomux-imx.c
@@ -18,6 +18,7 @@
 #include <gpio.h>
 #include <errno.h>
 #include <io.h>
+#include <stmp-device.h>
 #include <mach/imx-regs.h>
 
 #define HW_PINCTRL_CTRL 0x000
@@ -112,22 +113,24 @@ void imx_gpio_mode(uint32_t m)
 		reg_offset = calc_strength_reg(gpio_pin);
 		if (GET_VOLTAGE(m) == 1)
 			writel(0x1 << (((gpio_pin % 8) << 2) + 2),
-				IMX_IOMUXC_BASE + reg_offset + BIT_SET);
+				IMX_IOMUXC_BASE + reg_offset + STMP_OFFSET_REG_SET);
 		else
 			writel(0x1 << (((gpio_pin % 8) << 2) + 2),
-				IMX_IOMUXC_BASE + reg_offset + BIT_CLR);
+				IMX_IOMUXC_BASE + reg_offset + STMP_OFFSET_REG_CLR);
 	}
 
 	if (PE_PRESENT(m)) {
 		reg_offset = calc_pullup_reg(gpio_pin);
 		writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset +
-				(GET_PULLUP(m) == 1 ? BIT_SET : BIT_CLR));
+				(GET_PULLUP(m) == 1 ?
+				 STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR));
 	}
 
 	if (BK_PRESENT(m)) {
 		reg_offset = calc_pullup_reg(gpio_pin);
 		writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset +
-				(GET_BITKEEPER(m) == 1 ? BIT_CLR : BIT_SET));
+				(GET_BITKEEPER(m) == 1 ?
+				 STMP_OFFSET_REG_CLR : STMP_OFFSET_REG_SET));
 	}
 
 	if (GET_FUNC(m) == IS_GPIO) {
@@ -135,16 +138,17 @@ void imx_gpio_mode(uint32_t m)
 			/* first set the output value */
 			reg_offset = calc_output_reg(gpio_pin);
 			writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE +
-				reg_offset + (GET_GPIOVAL(m) == 1 ? BIT_SET : BIT_CLR));
+				reg_offset + (GET_GPIOVAL(m) == 1 ?
+					STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR));
 			/* then the direction */
 			reg_offset = calc_output_enable_reg(gpio_pin);
 			writel(0x1 << (gpio_pin % 32),
-				IMX_IOMUXC_BASE + reg_offset + BIT_SET);
+				IMX_IOMUXC_BASE + reg_offset + STMP_OFFSET_REG_SET);
 		} else {
 			/* then the direction */
 			reg_offset = calc_output_enable_reg(gpio_pin);
 			writel(0x1 << (gpio_pin % 32),
-				IMX_IOMUXC_BASE + reg_offset + BIT_CLR);
+				IMX_IOMUXC_BASE + reg_offset + STMP_OFFSET_REG_CLR);
 		}
 	}
 }
@@ -157,7 +161,7 @@ int gpio_direction_input(unsigned gpio)
 		return -EINVAL;
 
 	reg_offset = calc_output_enable_reg(gpio);
-	writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + reg_offset + BIT_CLR);
+	writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + reg_offset + STMP_OFFSET_REG_CLR);
 
 	return 0;
 }
@@ -172,10 +176,10 @@ int gpio_direction_output(unsigned gpio, int val)
 	/* first set the output value... */
 	reg_offset = calc_output_reg(gpio);
 	writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE +
-		reg_offset + (val != 0 ? BIT_SET : BIT_CLR));
+		reg_offset + (val != 0 ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR));
 	/* ...then the direction */
 	reg_offset = calc_output_enable_reg(gpio);
-	writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + reg_offset + BIT_SET);
+	writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + reg_offset + STMP_OFFSET_REG_SET);
 
 	return 0;
 }
@@ -186,7 +190,8 @@ void gpio_set_value(unsigned gpio, int val)
 
 	reg_offset = calc_output_reg(gpio);
 	writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE +
-				reg_offset + (val != 0 ? BIT_SET : BIT_CLR));
+				reg_offset + (val != 0 ?
+					STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR));
 }
 
 int gpio_get_value(unsigned gpio)
diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c
index 6bfa3e2..59c3b8a 100644
--- a/arch/arm/mach-mxs/ocotp.c
+++ b/arch/arm/mach-mxs/ocotp.c
@@ -20,6 +20,7 @@
 #include <fcntl.h>
 #include <malloc.h>
 #include <io.h>
+#include <stmp-device.h>
 #include <clock.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -75,13 +76,13 @@ static ssize_t mxs_ocotp_cdev_read(struct cdev *cdev, void *buf, size_t count,
 	 */
 
 	/* try to clear ERROR bit */
-	writel(OCOTP_CTRL_ERROR, base + OCOTP_CTRL + BIT_CLR);
+	writel(OCOTP_CTRL_ERROR, base + OCOTP_CTRL + STMP_OFFSET_REG_CLR);
 
 	if (mxs_ocotp_wait_busy(priv))
 		return -ETIMEDOUT;
 
 	/* open OCOTP banks for read */
-	writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + BIT_SET);
+	writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + STMP_OFFSET_REG_SET);
 
 	/* approximately wait 32 hclk cycles */
 	udelay(1);
@@ -96,7 +97,7 @@ static ssize_t mxs_ocotp_cdev_read(struct cdev *cdev, void *buf, size_t count,
 				(((i + offset) & 0xfc) << 2) + ((i + offset) & 3));
 
 	/* close banks for power saving */
-	writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + BIT_CLR);
+	writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + STMP_OFFSET_REG_CLR);
 
 	return size;
 }
@@ -139,7 +140,7 @@ static ssize_t mxs_ocotp_cdev_write(struct cdev *cdev, const void *buf, size_t c
 	clk_set_rate(priv->clk, 24000000);
 	imx_set_vddio(2800000);
 
-	writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + BIT_CLR);
+	writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + STMP_OFFSET_REG_CLR);
 
 	if (mxs_ocotp_wait_busy(priv)) {
 		ret = -ETIMEDOUT;
diff --git a/arch/arm/mach-mxs/power.c b/arch/arm/mach-mxs/power.c
index f4d0b9e..74c5479 100644
--- a/arch/arm/mach-mxs/power.c
+++ b/arch/arm/mach-mxs/power.c
@@ -11,6 +11,7 @@
  */
 #include <common.h>
 #include <io.h>
+#include <stmp-device.h>
 #include <errno.h>
 #include <mach/imx-regs.h>
 
@@ -72,11 +73,11 @@ void imx_power_prepare_usbphy(void)
 	 * Set these bits so that we can force the OTG bits high
 	 * so the ARC core operates properly
 	 */
-	writel(POWER_CTRL_CLKGATE, POWER_CTRL + BIT_CLR);
+	writel(POWER_CTRL_CLKGATE, POWER_CTRL + STMP_OFFSET_REG_CLR);
 
 	writel(POWER_DEBUG_VBUSVALIDPIOLOCK |
 			   POWER_DEBUG_AVALIDPIOLOCK |
-			   POWER_DEBUG_BVALIDPIOLOCK, POWER_DEBUG + BIT_SET);
+			   POWER_DEBUG_BVALIDPIOLOCK, POWER_DEBUG + STMP_OFFSET_REG_SET);
 
 	reg = readl(POWER_STS);
 	reg |= POWER_STS_BVALID | POWER_STS_AVALID | POWER_STS_VBUSVALID;
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index a30fa37..c43c93e 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -3,6 +3,7 @@ menu "DMA support"
 config MXS_APBH_DMA
 	tristate "MXS APBH DMA ENGINE"
 	depends on ARCH_IMX23 || ARCH_IMX28
+	select STMP_DEVICE
 	help
 	  Experimental!
 endmenu
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index d30b8fb..c8b20fb 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -20,12 +20,12 @@
 #include <common.h>
 #include <malloc.h>
 #include <errno.h>
+#include <stmp-device.h>
 #include <asm/mmu.h>
 #include <asm/io.h>
 #include <mach/clock.h>
 #include <mach/imx-regs.h>
 #include <mach/dma.h>
-#include <mach/mxs.h>
 
 #define HW_APBHX_CTRL0				0x000
 #define BM_APBH_CTRL0_APB_BURST8_EN		(1 << 29)
@@ -165,7 +165,7 @@ static int mxs_dma_enable(int channel)
 		writel(pchan->active_num,
 			apbh_regs + HW_APBHX_CHn_SEMA(channel));
 		channel_bit = channel + (apbh_is_old ? BP_APBH_CTRL0_CLKGATE_CHANNEL : 0);
-		writel(1 << channel_bit, apbh_regs + HW_APBHX_CTRL0 + BIT_CLR);
+		writel(1 << channel_bit, apbh_regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
 	}
 
 	pchan->flags |= MXS_DMA_FLAGS_BUSY;
@@ -202,7 +202,7 @@ static int mxs_dma_disable(int channel)
 		return -EINVAL;
 
 	channel_bit = channel + (apbh_is_old ? BP_APBH_CTRL0_CLKGATE_CHANNEL : 0);
-	writel(1 << channel_bit, apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
+	writel(1 << channel_bit, apbh_regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
 
 	pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
 	pchan->active_num = 0;
@@ -226,10 +226,10 @@ static int mxs_dma_reset(int channel)
 
 	if (apbh_is_old)
 		writel(1 << (channel + BP_APBH_CTRL0_RESET_CHANNEL),
-			apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
+			apbh_regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
 	else
 		writel(1 << (channel + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
-			apbh_regs + HW_APBHX_CHANNEL_CTRL + BIT_SET);
+			apbh_regs + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
 
 	return 0;
 }
@@ -250,10 +250,10 @@ static int mxs_dma_enable_irq(int channel, int enable)
 
 	if (enable)
 		writel(1 << (channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN),
-			apbh_regs + HW_APBHX_CTRL1 + BIT_SET);
+			apbh_regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
 	else
 		writel(1 << (channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN),
-			apbh_regs + HW_APBHX_CTRL1 + BIT_CLR);
+			apbh_regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
 
 	return 0;
 }
@@ -273,8 +273,8 @@ static int mxs_dma_ack_irq(int channel)
 	if (ret)
 		return ret;
 
-	writel(1 << channel, apbh_regs + HW_APBHX_CTRL1 + BIT_CLR);
-	writel(1 << channel, apbh_regs + HW_APBHX_CTRL2 + BIT_CLR);
+	writel(1 << channel, apbh_regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
+	writel(1 << channel, apbh_regs + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
 
 	return 0;
 }
@@ -555,7 +555,7 @@ int mxs_dma_init(void)
 	int ret, channel;
 	u32 val, reg;
 
-	ret = mxs_reset_block(apbh_regs, 0);
+	ret = stmp_reset_block(apbh_regs, 0);
 	if (ret)
 		return ret;
 
@@ -569,10 +569,10 @@ int mxs_dma_init(void)
 	apbh_is_old = (readl((void *)reg) >> 24) < 3;
 
 	writel(BM_APBH_CTRL0_APB_BURST8_EN,
-		apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
+		apbh_regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
 
 	writel(BM_APBH_CTRL0_APB_BURST_EN,
-		apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
+		apbh_regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
 
 	for (channel = 0; channel < MXS_MAX_DMA_CHANNELS; channel++) {
 		pchan = mxs_dma_channels + channel;
diff --git a/drivers/mci/mxs.c b/drivers/mci/mxs.c
index 023f922..1b935f7 100644
--- a/drivers/mci/mxs.c
+++ b/drivers/mci/mxs.c
@@ -36,10 +36,10 @@
 #include <errno.h>
 #include <clock.h>
 #include <io.h>
+#include <stmp-device.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <asm/bitops.h>
-#include <mach/mxs.h>
 #include <mach/imx-regs.h>
 #include <mach/mci.h>
 #include <mach/clock.h>
@@ -457,7 +457,7 @@ static int mxs_mci_initialize(struct mci_host *host, struct device_d *mci_dev)
 	writel(SSP_CTRL0_CLKGATE, mxs_mci->regs + HW_SSP_CTRL0 + 8);
 
 	/* reset the unit */
-	mxs_reset_block(mxs_mci->regs + HW_SSP_CTRL0, 0);
+	stmp_reset_block(mxs_mci->regs + HW_SSP_CTRL0, 0);
 
 	/* restore the last settings */
 	mxs_mci_setup_timeout(mxs_mci, 0xffff);
diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index 56d5ecf..55a0e3e 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -28,12 +28,12 @@
 #include <errno.h>
 #include <driver.h>
 #include <init.h>
+#include <stmp-device.h>
 #include <asm/mmu.h>
 #include <asm/io.h>
 #include <mach/clock.h>
 #include <mach/imx-regs.h>
 #include <mach/dma.h>
-#include <mach/mxs.h>
 
 #define	MX28_BLOCK_SFTRST				(1 << 31)
 #define	MX28_BLOCK_CLKGATE				(1 << 30)
@@ -313,7 +313,7 @@ static int mxs_nand_wait_for_bch_complete(void)
 
 	ret = (timeout == 0) ? -ETIMEDOUT : 0;
 
-	writel(BCH_CTRL_COMPLETE_IRQ, bch_regs + BCH_CTRL + BIT_CLR);
+	writel(BCH_CTRL_COMPLETE_IRQ, bch_regs + BCH_CTRL + STMP_OFFSET_REG_CLR);
 
 	return ret;
 }
@@ -1045,7 +1045,7 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd)
 	int ret;
 
 	/* Reset BCH. Don't use SFTRST on MX23 due to Errata #2847 */
-	ret = mxs_reset_block(bch_regs + BCH_CTRL,
+	ret = stmp_reset_block(bch_regs + BCH_CTRL,
 				nand_info->version == GPMI_VERSION_TYPE_MX23);
 	if (ret)
 		return ret;
@@ -1070,7 +1070,7 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd)
 	writel(0, bch_regs + BCH_LAYOUTSELECT);
 
 	/* Enable BCH complete interrupt */
-	writel(BCH_CTRL_COMPLETE_IRQ_EN, bch_regs + BCH_CTRL + BIT_SET);
+	writel(BCH_CTRL_COMPLETE_IRQ_EN, bch_regs + BCH_CTRL + STMP_OFFSET_REG_SET);
 
 	/* Hook some operations at the MTD level. */
 	if (mtd->read_oob != mxs_nand_hook_read_oob) {
@@ -1151,7 +1151,7 @@ int mxs_nand_hw_init(struct mxs_nand_info *info)
 	mxs_dma_init();
 
 	/* Reset the GPMI block. */
-	ret = mxs_reset_block(gpmi_regs + GPMI_CTRL0, 0);
+	ret = stmp_reset_block(gpmi_regs + GPMI_CTRL0, 0);
 	if (ret)
 		return ret;
 
@@ -1159,7 +1159,7 @@ int mxs_nand_hw_init(struct mxs_nand_info *info)
 	info->version = val >> GPMI_VERSION_MINOR_OFFSET;
 
 	/* Reset BCH. Don't use SFTRST on MX23 due to Errata #2847 */
-	ret = mxs_reset_block(bch_regs + BCH_CTRL,
+	ret = stmp_reset_block(bch_regs + BCH_CTRL,
 				info->version == GPMI_VERSION_TYPE_MX23);
 	if (ret)
 		return ret;
diff --git a/drivers/serial/serial_auart.c b/drivers/serial/serial_auart.c
index 98f7c75..6518dbb 100644
--- a/drivers/serial/serial_auart.c
+++ b/drivers/serial/serial_auart.c
@@ -171,7 +171,7 @@ static int auart_clocksource_clock_change(struct notifier_block *nb, unsigned lo
 
 static void auart_serial_init_port(struct auart_priv *priv)
 {
-	mxs_reset_block(priv->base + HW_UARTAPP_CTRL0, 0);
+	stmp_reset_block(priv->base + HW_UARTAPP_CTRL0, 0);
 
 	/* Disable UART */
 	writel(0x0, priv->base + HW_UARTAPP_CTRL2);
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 8dfd6d5..4e539bf 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -20,6 +20,7 @@
 #include <clock.h>
 #include <errno.h>
 #include <io.h>
+#include <stmp-device.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <asm/mmu.h>
@@ -99,11 +100,11 @@ static int mxs_spi_setup(struct spi_device *spi)
 		return -EINVAL;
 	}
 
-	mxs_reset_block(mxs->regs + HW_SSP_CTRL0, 0);
+	stmp_reset_block(mxs->regs + HW_SSP_CTRL0);
 
 	val |= SSP_CTRL0_SSP_ASSERT_OUT(spi->chip_select);
 	val |= SSP_CTRL0_BUS_WIDTH(0);
-	writel(val, mxs->regs + HW_SSP_CTRL0 + BIT_SET);
+	writel(val, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 
 	val = SSP_CTRL1_SSP_MODE(0) | SSP_CTRL1_WORD_LENGTH(7);
 	val |= (mxs->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
@@ -120,14 +121,14 @@ static int mxs_spi_setup(struct spi_device *spi)
 
 static void mxs_spi_start_xfer(struct mxs_spi *mxs)
 {
-	writel(SSP_CTRL0_LOCK_CS, mxs->regs + HW_SSP_CTRL0 + BIT_SET);
-	writel(SSP_CTRL0_IGNORE_CRC, mxs->regs + HW_SSP_CTRL0 + BIT_CLR);
+	writel(SSP_CTRL0_LOCK_CS, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
+	writel(SSP_CTRL0_IGNORE_CRC, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 }
 
 static void mxs_spi_end_xfer(struct mxs_spi *mxs)
 {
-	writel(SSP_CTRL0_LOCK_CS, mxs->regs + HW_SSP_CTRL0 + BIT_CLR);
-	writel(SSP_CTRL0_IGNORE_CRC, mxs->regs + HW_SSP_CTRL0 + BIT_SET);
+	writel(SSP_CTRL0_LOCK_CS, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
+	writel(SSP_CTRL0_IGNORE_CRC, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 }
 
 static void mxs_spi_set_cs(struct spi_device *spi)
@@ -136,8 +137,8 @@ static void mxs_spi_set_cs(struct spi_device *spi)
 	const uint32_t mask = SSP_CTRL0_WAIT_FOR_CMD | SSP_CTRL0_WAIT_FOR_IRQ;
 	uint32_t select = SSP_CTRL0_SSP_ASSERT_OUT(spi->chip_select);
 
-	writel(mask, mxs->regs + HW_SSP_CTRL0 + BIT_CLR);
-	writel(select, mxs->regs + HW_SSP_CTRL0 + BIT_SET);
+	writel(mask, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
+	writel(select, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 }
 
 static int mxs_spi_xfer_pio(struct spi_device *spi,
@@ -159,11 +160,11 @@ static int mxs_spi_xfer_pio(struct spi_device *spi,
 		writel(1, mxs->regs + HW_SSP_XFER_COUNT);
 
 		if (write)
-			writel(SSP_CTRL0_READ, mxs->regs + HW_SSP_CTRL0 + BIT_CLR);
+			writel(SSP_CTRL0_READ, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 		else
-			writel(SSP_CTRL0_READ, mxs->regs + HW_SSP_CTRL0 + BIT_SET);
+			writel(SSP_CTRL0_READ, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 
-		writel(SSP_CTRL0_RUN, mxs->regs + HW_SSP_CTRL0 + BIT_SET);
+		writel(SSP_CTRL0_RUN, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 
 		if (wait_on_timeout(MXS_SPI_MAX_TIMEOUT,
 				(readl(mxs->regs + HW_SSP_CTRL0) & SSP_CTRL0_RUN) == SSP_CTRL0_RUN)) {
@@ -174,7 +175,7 @@ static int mxs_spi_xfer_pio(struct spi_device *spi,
 		if (write)
 			writel(*data++, mxs->regs + HW_SSP_DATA);
 
-		writel(SSP_CTRL0_DATA_XFER, mxs->regs + HW_SSP_CTRL0 + BIT_SET);
+		writel(SSP_CTRL0_DATA_XFER, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 
 		if (!write) {
 			if (wait_on_timeout(MXS_SPI_MAX_TIMEOUT,
@@ -240,7 +241,7 @@ static int mxs_spi_transfer(struct spi_device *spi, struct spi_message *mesg)
 			}
 		}
 
-		writel(SSP_CTRL1_DMA_ENABLE, mxs->regs + HW_SSP_CTRL1 + BIT_CLR);
+		writel(SSP_CTRL1_DMA_ENABLE, mxs->regs + HW_SSP_CTRL1 + STMP_OFFSET_REG_CLR);
 		ret = mxs_spi_xfer_pio(spi, data, t->len, write, flags);
 		if (ret < 0)
 			return ret;
diff --git a/drivers/video/stm.c b/drivers/video/stm.c
index d5212f8..0875c9b 100644
--- a/drivers/video/stm.c
+++ b/drivers/video/stm.c
@@ -24,6 +24,7 @@
 #include <errno.h>
 #include <xfuncs.h>
 #include <io.h>
+#include <stmp-device.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <mach/imx-regs.h>
@@ -222,7 +223,7 @@ static void stmfb_enable_controller(struct fb_info *fb_info)
 	 * Sometimes some data is still present in the FIFO. This leads into
 	 * a correct but shifted picture. Clearing the FIFO helps
 	 */
-	writel(CTRL1_FIFO_CLEAR, fbi->base + HW_LCDIF_CTRL1 + BIT_SET);
+	writel(CTRL1_FIFO_CLEAR, fbi->base + HW_LCDIF_CTRL1 + STMP_OFFSET_REG_SET);
 
 	/* if it was disabled, re-enable the mode again */
 	reg = readl(fbi->base + HW_LCDIF_CTRL);
@@ -255,14 +256,14 @@ static void stmfb_enable_controller(struct fb_info *fb_info)
 	}
 
 	/* stop FIFO reset */
-	writel(CTRL1_FIFO_CLEAR, fbi->base + HW_LCDIF_CTRL1 + BIT_CLR);
+	writel(CTRL1_FIFO_CLEAR, fbi->base + HW_LCDIF_CTRL1 + STMP_OFFSET_REG_CLR);
 
 	/* enable LCD using LCD_RESET signal*/
 	if (fbi->pdata->flags & USE_LCD_RESET)
-		writel(CTRL1_RESET,  fbi->base + HW_LCDIF_CTRL1 + BIT_SET);
+		writel(CTRL1_RESET,  fbi->base + HW_LCDIF_CTRL1 + STMP_OFFSET_REG_SET);
 
 	/* start the engine right now */
-	writel(CTRL_RUN, fbi->base + HW_LCDIF_CTRL + BIT_SET);
+	writel(CTRL_RUN, fbi->base + HW_LCDIF_CTRL + STMP_OFFSET_REG_SET);
 
 	if (fbi->pdata->enable)
 		fbi->pdata->enable(1);
@@ -277,7 +278,7 @@ static void stmfb_disable_controller(struct fb_info *fb_info)
 
 	/* disable LCD using LCD_RESET signal*/
 	if (fbi->pdata->flags & USE_LCD_RESET)
-		writel(CTRL1_RESET,  fbi->base + HW_LCDIF_CTRL1 + BIT_CLR);
+		writel(CTRL1_RESET,  fbi->base + HW_LCDIF_CTRL1 + STMP_OFFSET_REG_CLR);
 
 	if (fbi->pdata->enable)
 		fbi->pdata->enable(0);
diff --git a/include/stmp-device.h b/include/stmp-device.h
new file mode 100644
index 0000000..9b5bee4
--- /dev/null
+++ b/include/stmp-device.h
@@ -0,0 +1,22 @@
+/*
+ * basic functions for devices following the "stmp" style register layout
+ *
+ * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __STMP_DEVICE_H__
+#define __STMP_DEVICE_H__
+
+#include <linux/compiler.h>
+
+#define STMP_OFFSET_REG_SET	0x4
+#define STMP_OFFSET_REG_CLR	0x8
+#define STMP_OFFSET_REG_TOG	0xc
+
+extern int stmp_reset_block(void __iomem *, int just_enable);
+#endif /* __STMP_DEVICE_H__ */
diff --git a/lib/Kconfig b/lib/Kconfig
index 646fdb7..4fa3009 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -43,6 +43,9 @@ config LIBUBIGEN
 config LIBMTD
 	bool
 
+config STMP_DEVICE
+	bool
+
 source lib/gui/Kconfig
 
 source lib/bootstrap/Kconfig
diff --git a/lib/Makefile b/lib/Makefile
index 7c42537..8436d27 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -41,3 +41,4 @@ obj-$(CONFIG_LIBMTD)	+= libmtd.o
 obj-y			+= gui/
 obj-$(CONFIG_XYMODEM)	+= xymodem.o
 obj-y			+= unlink-recursive.o
+obj-$(CONFIG_STMP_DEVICE) += stmp-device.o
diff --git a/lib/stmp-device.c b/lib/stmp-device.c
new file mode 100644
index 0000000..74d4763
--- /dev/null
+++ b/lib/stmp-device.c
@@ -0,0 +1,63 @@
+/*
+ * Freescale i.MXS common code
+ *
+ * Copyright (C) 2012 Wolfram Sang <w.sang@pengutronix.de>
+ *
+ * Based on code from LTIB:
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <io.h>
+#include <stmp-device.h>
+#include <errno.h>
+#include <clock.h>
+
+#define	STMP_IP_RESET_TIMEOUT	(10 * MSECOND)
+
+#define	STMP_BLOCK_SFTRST				(1 << 31)
+#define	STMP_BLOCK_CLKGATE				(1 << 30)
+
+int stmp_reset_block(void __iomem *reg, int just_enable)
+{
+	/* Clear SFTRST */
+	writel(STMP_BLOCK_SFTRST, reg + STMP_OFFSET_REG_CLR);
+
+	if (wait_on_timeout(STMP_IP_RESET_TIMEOUT, !(readl(reg) & STMP_BLOCK_SFTRST)))
+		goto timeout;
+
+	/* Clear CLKGATE */
+	writel(STMP_BLOCK_CLKGATE, reg + STMP_OFFSET_REG_CLR);
+
+	if (!just_enable) {
+		/* Set SFTRST */
+		writel(STMP_BLOCK_SFTRST, reg + STMP_OFFSET_REG_SET);
+
+		/* Wait for CLKGATE being set */
+		if (wait_on_timeout(STMP_IP_RESET_TIMEOUT, readl(reg) & STMP_BLOCK_CLKGATE))
+			goto timeout;
+	}
+
+	/* Clear SFTRST */
+	writel(STMP_BLOCK_SFTRST, reg + STMP_OFFSET_REG_CLR);
+
+	if (wait_on_timeout(STMP_IP_RESET_TIMEOUT, !(readl(reg) & STMP_BLOCK_SFTRST)))
+		goto timeout;
+
+	/* Clear CLKGATE */
+	writel(STMP_BLOCK_CLKGATE, reg + STMP_OFFSET_REG_CLR);
+
+	if (wait_on_timeout(STMP_IP_RESET_TIMEOUT, !(readl(reg) & STMP_BLOCK_CLKGATE)))
+		goto timeout;
+
+	return 0;
+
+timeout:
+	printf("MXS: Timeout resetting block via register 0x%p\n", reg);
+	return -ETIMEDOUT;
+}
-- 
1.8.3.2


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[PATCH 02/11] dma: apbh: introduce private struct

[Sascha Hauer]

Currently the apbh driver uses a hardcoded base (MXS_APBH_BASE).
As a first step to clean this up add a private data struct
which is initialized during startup.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/dma/apbh_dma.c | 66 +++++++++++++++++++++++++++++---------------------
 1 file changed, 38 insertions(+), 28 deletions(-)

diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index c8b20fb..2354364 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -50,6 +50,12 @@
 static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
 static bool apbh_is_old;
 
+struct apbh_dma {
+	void __iomem *regs;
+};
+
+static struct apbh_dma *apbh_dma;
+
 /*
  * Test is the DMA channel is valid channel
  */
@@ -91,7 +97,7 @@ static unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
  */
 static int mxs_dma_read_semaphore(int channel)
 {
-	void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+	struct apbh_dma *apbh = apbh_dma;
 	uint32_t tmp;
 	int ret;
 
@@ -99,7 +105,7 @@ static int mxs_dma_read_semaphore(int channel)
 	if (ret)
 		return ret;
 
-	tmp = readl(apbh_regs + HW_APBHX_CHn_SEMA(channel));
+	tmp = readl(apbh->regs + HW_APBHX_CHn_SEMA(channel));
 
 	tmp &= BM_APBHX_CHn_SEMA_PHORE;
 	tmp >>= BP_APBHX_CHn_SEMA_PHORE;
@@ -118,7 +124,7 @@ static int mxs_dma_read_semaphore(int channel)
  */
 static int mxs_dma_enable(int channel)
 {
-	void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+	struct apbh_dma *apbh = apbh_dma;
 	unsigned int sem;
 	struct mxs_dma_chan *pchan;
 	struct mxs_dma_desc *pdesc;
@@ -151,21 +157,21 @@ static int mxs_dma_enable(int channel)
 			pdesc = list_entry(pdesc->node.next,
 					   struct mxs_dma_desc, node);
 			writel(mxs_dma_cmd_address(pdesc),
-				apbh_regs + HW_APBHX_CHn_NXTCMDAR(channel));
+				apbh->regs + HW_APBHX_CHn_NXTCMDAR(channel));
 		}
 		writel(pchan->pending_num,
-			apbh_regs + HW_APBHX_CHn_SEMA(channel));
+			apbh->regs + HW_APBHX_CHn_SEMA(channel));
 		pchan->active_num += pchan->pending_num;
 		pchan->pending_num = 0;
 	} else {
 		pchan->active_num += pchan->pending_num;
 		pchan->pending_num = 0;
 		writel(mxs_dma_cmd_address(pdesc),
-			apbh_regs + HW_APBHX_CHn_NXTCMDAR(channel));
+			apbh->regs + HW_APBHX_CHn_NXTCMDAR(channel));
 		writel(pchan->active_num,
-			apbh_regs + HW_APBHX_CHn_SEMA(channel));
+			apbh->regs + HW_APBHX_CHn_SEMA(channel));
 		channel_bit = channel + (apbh_is_old ? BP_APBH_CTRL0_CLKGATE_CHANNEL : 0);
-		writel(1 << channel_bit, apbh_regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
+		writel(1 << channel_bit, apbh->regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
 	}
 
 	pchan->flags |= MXS_DMA_FLAGS_BUSY;
@@ -189,7 +195,7 @@ static int mxs_dma_enable(int channel)
 static int mxs_dma_disable(int channel)
 {
 	struct mxs_dma_chan *pchan;
-	void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+	struct apbh_dma *apbh = apbh_dma;
 	int channel_bit, ret;
 
 	ret = mxs_dma_validate_chan(channel);
@@ -202,7 +208,7 @@ static int mxs_dma_disable(int channel)
 		return -EINVAL;
 
 	channel_bit = channel + (apbh_is_old ? BP_APBH_CTRL0_CLKGATE_CHANNEL : 0);
-	writel(1 << channel_bit, apbh_regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
+	writel(1 << channel_bit, apbh->regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
 
 	pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
 	pchan->active_num = 0;
@@ -217,7 +223,7 @@ static int mxs_dma_disable(int channel)
  */
 static int mxs_dma_reset(int channel)
 {
-	void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+	struct apbh_dma *apbh = apbh_dma;
 	int ret;
 
 	ret = mxs_dma_validate_chan(channel);
@@ -226,10 +232,10 @@ static int mxs_dma_reset(int channel)
 
 	if (apbh_is_old)
 		writel(1 << (channel + BP_APBH_CTRL0_RESET_CHANNEL),
-			apbh_regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
+			apbh->regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
 	else
 		writel(1 << (channel + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
-			apbh_regs + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
+			apbh->regs + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
 
 	return 0;
 }
@@ -241,7 +247,7 @@ static int mxs_dma_reset(int channel)
  */
 static int mxs_dma_enable_irq(int channel, int enable)
 {
-	void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+	struct apbh_dma *apbh = apbh_dma;
 	int ret;
 
 	ret = mxs_dma_validate_chan(channel);
@@ -250,10 +256,10 @@ static int mxs_dma_enable_irq(int channel, int enable)
 
 	if (enable)
 		writel(1 << (channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN),
-			apbh_regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
+			apbh->regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
 	else
 		writel(1 << (channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN),
-			apbh_regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
+			apbh->regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
 
 	return 0;
 }
@@ -266,15 +272,15 @@ static int mxs_dma_enable_irq(int channel, int enable)
  */
 static int mxs_dma_ack_irq(int channel)
 {
-	void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+	struct apbh_dma *apbh = apbh_dma;
 	int ret;
 
 	ret = mxs_dma_validate_chan(channel);
 	if (ret)
 		return ret;
 
-	writel(1 << channel, apbh_regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
-	writel(1 << channel, apbh_regs + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
+	writel(1 << channel, apbh->regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
+	writel(1 << channel, apbh->regs + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
 
 	return 0;
 }
@@ -496,7 +502,7 @@ static int mxs_dma_finish(int channel, struct list_head *head)
  */
 static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
 {
-	void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+	struct apbh_dma *apbh = apbh_dma;
 	int ret;
 
 	ret = mxs_dma_validate_chan(chan);
@@ -504,7 +510,7 @@ static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
 		return ret;
 
 	while (--timeout) {
-		if (readl(apbh_regs + HW_APBHX_CTRL1) & (1 << chan))
+		if (readl(apbh->regs + HW_APBHX_CTRL1) & (1 << chan))
 			break;
 		udelay(1);
 	}
@@ -550,29 +556,33 @@ int mxs_dma_go(int chan)
  */
 int mxs_dma_init(void)
 {
-	void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
+	struct apbh_dma *apbh;
 	struct mxs_dma_chan *pchan;
 	int ret, channel;
-	u32 val, reg;
+	u32 val;
+	void __iomem *reg;
+
+	apbh = xzalloc(sizeof(*apbh));
+	apbh->regs = (void __iomem *)MXS_APBH_BASE;
 
-	ret = stmp_reset_block(apbh_regs, 0);
+	ret = stmp_reset_block(apbh->regs, 0);
 	if (ret)
 		return ret;
 
 	/* HACK: Get CPUID and determine APBH version */
 	val = readl(0x8001c310) >> 16;
 	if (val == 0x2800)
-		reg = MXS_APBH_BASE + 0x0800;
+		reg = apbh->regs + 0x0800;
 	else
-		reg = MXS_APBH_BASE + 0x03f0;
+		reg = apbh->regs + 0x03f0;
 
 	apbh_is_old = (readl((void *)reg) >> 24) < 3;
 
 	writel(BM_APBH_CTRL0_APB_BURST8_EN,
-		apbh_regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
+		apbh->regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
 
 	writel(BM_APBH_CTRL0_APB_BURST_EN,
-		apbh_regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
+		apbh->regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
 
 	for (channel = 0; channel < MXS_MAX_DMA_CHANNELS; channel++) {
 		pchan = mxs_dma_channels + channel;
-- 
1.8.3.2


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[PATCH 03/11] dma: apbh-dma: move header file to common location

[Sascha Hauer]

As the apbh dma engine is also found on i.MX6 move the header file
out of MXS specific directories.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-mxs/include/mach/dma.h | 145 -----------------------------------
 drivers/dma/apbh_dma.c               |   2 +-
 drivers/mtd/nand/nand_mxs.c          |   2 +-
 include/dma/apbh-dma.h               | 145 +++++++++++++++++++++++++++++++++++
 4 files changed, 147 insertions(+), 147 deletions(-)
 delete mode 100644 arch/arm/mach-mxs/include/mach/dma.h
 create mode 100644 include/dma/apbh-dma.h

diff --git a/arch/arm/mach-mxs/include/mach/dma.h b/arch/arm/mach-mxs/include/mach/dma.h
deleted file mode 100644
index 52747e2..0000000
--- a/arch/arm/mach-mxs/include/mach/dma.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Freescale i.MX28 APBH DMA
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * Based on code from LTIB:
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- *
- */
-
-#ifndef __DMA_H__
-#define __DMA_H__
-
-#include <linux/list.h>
-
-#ifndef	CONFIG_ARCH_DMA_PIO_WORDS
-#define	DMA_PIO_WORDS		15
-#else
-#define	DMA_PIO_WORDS		CONFIG_ARCH_DMA_PIO_WORDS
-#endif
-
-#define MXS_DMA_ALIGNMENT	32
-
-/*
- * MXS DMA channels
- */
-enum {
-	MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
-	MXS_DMA_CHANNEL_AHB_APBH_SSP1,
-	MXS_DMA_CHANNEL_AHB_APBH_SSP2,
-	MXS_DMA_CHANNEL_AHB_APBH_SSP3,
-	MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
-	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
-	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
-	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
-	MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
-	MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
-	MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
-	MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
-	MXS_DMA_CHANNEL_AHB_APBH_SSP,
-	MXS_MAX_DMA_CHANNELS,
-};
-
-/*
- * MXS DMA hardware command.
- *
- * This structure describes the in-memory layout of an entire DMA command,
- * including space for the maximum number of PIO accesses. See the appropriate
- * reference manual for a detailed description of what these fields mean to the
- * DMA hardware.
- */
-#define	MXS_DMA_DESC_COMMAND_MASK	0x3
-#define	MXS_DMA_DESC_COMMAND_OFFSET	0
-#define	MXS_DMA_DESC_COMMAND_NO_DMAXFER	0x0
-#define	MXS_DMA_DESC_COMMAND_DMA_WRITE	0x1
-#define	MXS_DMA_DESC_COMMAND_DMA_READ	0x2
-#define	MXS_DMA_DESC_COMMAND_DMA_SENSE	0x3
-#define	MXS_DMA_DESC_CHAIN		(1 << 2)
-#define	MXS_DMA_DESC_IRQ		(1 << 3)
-#define	MXS_DMA_DESC_NAND_LOCK		(1 << 4)
-#define	MXS_DMA_DESC_NAND_WAIT_4_READY	(1 << 5)
-#define	MXS_DMA_DESC_DEC_SEM		(1 << 6)
-#define	MXS_DMA_DESC_WAIT4END		(1 << 7)
-#define	MXS_DMA_DESC_HALT_ON_TERMINATE	(1 << 8)
-#define	MXS_DMA_DESC_TERMINATE_FLUSH	(1 << 9)
-#define	MXS_DMA_DESC_PIO_WORDS_MASK	(0xf << 12)
-#define	MXS_DMA_DESC_PIO_WORDS_OFFSET	12
-#define	MXS_DMA_DESC_BYTES_MASK		(0xffff << 16)
-#define	MXS_DMA_DESC_BYTES_OFFSET	16
-
-struct mxs_dma_cmd {
-	unsigned long		next;
-	unsigned long		data;
-	union {
-		dma_addr_t	address;
-		unsigned long	alternate;
-	};
-	unsigned long		pio_words[DMA_PIO_WORDS];
-};
-
-/*
- * MXS DMA command descriptor.
- *
- * This structure incorporates an MXS DMA hardware command structure, along
- * with metadata.
- */
-#define	MXS_DMA_DESC_FIRST	(1 << 0)
-#define	MXS_DMA_DESC_LAST	(1 << 1)
-#define	MXS_DMA_DESC_READY	(1 << 31)
-
-struct mxs_dma_desc {
-	struct mxs_dma_cmd	cmd;
-	unsigned int		flags;
-	dma_addr_t		address;
-	void			*buffer;
-	struct list_head	node;
-};
-
-/**
- * MXS DMA channel
- *
- * This structure represents a single DMA channel. The MXS platform code
- * maintains an array of these structures to represent every DMA channel in the
- * system (see mxs_dma_channels).
- */
-#define	MXS_DMA_FLAGS_IDLE	0
-#define	MXS_DMA_FLAGS_BUSY	(1 << 0)
-#define	MXS_DMA_FLAGS_FREE	0
-#define	MXS_DMA_FLAGS_ALLOCATED	(1 << 16)
-#define	MXS_DMA_FLAGS_VALID	(1 << 31)
-
-struct mxs_dma_chan {
-	const char *name;
-	unsigned long dev;
-	struct mxs_dma_device *dma;
-	unsigned int flags;
-	unsigned int active_num;
-	unsigned int pending_num;
-	struct list_head active;
-	struct list_head done;
-};
-
-struct mxs_dma_desc *mxs_dma_desc_alloc(void);
-void mxs_dma_desc_free(struct mxs_dma_desc *);
-int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
-
-int mxs_dma_go(int chan);
-int mxs_dma_init(void);
-
-#endif	/* __DMA_H__ */
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 2354364..b0a20b8 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -20,12 +20,12 @@
 #include <common.h>
 #include <malloc.h>
 #include <errno.h>
+#include <dma/apbh-dma.h>
 #include <stmp-device.h>
 #include <asm/mmu.h>
 #include <asm/io.h>
 #include <mach/clock.h>
 #include <mach/imx-regs.h>
-#include <mach/dma.h>
 
 #define HW_APBHX_CTRL0				0x000
 #define BM_APBH_CTRL0_APB_BURST8_EN		(1 << 29)
diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index 55a0e3e..adb0500 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -28,12 +28,12 @@
 #include <errno.h>
 #include <driver.h>
 #include <init.h>
+#include <dma/apbh-dma.h>
 #include <stmp-device.h>
 #include <asm/mmu.h>
 #include <asm/io.h>
 #include <mach/clock.h>
 #include <mach/imx-regs.h>
-#include <mach/dma.h>
 
 #define	MX28_BLOCK_SFTRST				(1 << 31)
 #define	MX28_BLOCK_CLKGATE				(1 << 30)
diff --git a/include/dma/apbh-dma.h b/include/dma/apbh-dma.h
new file mode 100644
index 0000000..52747e2
--- /dev/null
+++ b/include/dma/apbh-dma.h
@@ -0,0 +1,145 @@
+/*
+ * Freescale i.MX28 APBH DMA
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __DMA_H__
+#define __DMA_H__
+
+#include <linux/list.h>
+
+#ifndef	CONFIG_ARCH_DMA_PIO_WORDS
+#define	DMA_PIO_WORDS		15
+#else
+#define	DMA_PIO_WORDS		CONFIG_ARCH_DMA_PIO_WORDS
+#endif
+
+#define MXS_DMA_ALIGNMENT	32
+
+/*
+ * MXS DMA channels
+ */
+enum {
+	MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP2,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP3,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP,
+	MXS_MAX_DMA_CHANNELS,
+};
+
+/*
+ * MXS DMA hardware command.
+ *
+ * This structure describes the in-memory layout of an entire DMA command,
+ * including space for the maximum number of PIO accesses. See the appropriate
+ * reference manual for a detailed description of what these fields mean to the
+ * DMA hardware.
+ */
+#define	MXS_DMA_DESC_COMMAND_MASK	0x3
+#define	MXS_DMA_DESC_COMMAND_OFFSET	0
+#define	MXS_DMA_DESC_COMMAND_NO_DMAXFER	0x0
+#define	MXS_DMA_DESC_COMMAND_DMA_WRITE	0x1
+#define	MXS_DMA_DESC_COMMAND_DMA_READ	0x2
+#define	MXS_DMA_DESC_COMMAND_DMA_SENSE	0x3
+#define	MXS_DMA_DESC_CHAIN		(1 << 2)
+#define	MXS_DMA_DESC_IRQ		(1 << 3)
+#define	MXS_DMA_DESC_NAND_LOCK		(1 << 4)
+#define	MXS_DMA_DESC_NAND_WAIT_4_READY	(1 << 5)
+#define	MXS_DMA_DESC_DEC_SEM		(1 << 6)
+#define	MXS_DMA_DESC_WAIT4END		(1 << 7)
+#define	MXS_DMA_DESC_HALT_ON_TERMINATE	(1 << 8)
+#define	MXS_DMA_DESC_TERMINATE_FLUSH	(1 << 9)
+#define	MXS_DMA_DESC_PIO_WORDS_MASK	(0xf << 12)
+#define	MXS_DMA_DESC_PIO_WORDS_OFFSET	12
+#define	MXS_DMA_DESC_BYTES_MASK		(0xffff << 16)
+#define	MXS_DMA_DESC_BYTES_OFFSET	16
+
+struct mxs_dma_cmd {
+	unsigned long		next;
+	unsigned long		data;
+	union {
+		dma_addr_t	address;
+		unsigned long	alternate;
+	};
+	unsigned long		pio_words[DMA_PIO_WORDS];
+};
+
+/*
+ * MXS DMA command descriptor.
+ *
+ * This structure incorporates an MXS DMA hardware command structure, along
+ * with metadata.
+ */
+#define	MXS_DMA_DESC_FIRST	(1 << 0)
+#define	MXS_DMA_DESC_LAST	(1 << 1)
+#define	MXS_DMA_DESC_READY	(1 << 31)
+
+struct mxs_dma_desc {
+	struct mxs_dma_cmd	cmd;
+	unsigned int		flags;
+	dma_addr_t		address;
+	void			*buffer;
+	struct list_head	node;
+};
+
+/**
+ * MXS DMA channel
+ *
+ * This structure represents a single DMA channel. The MXS platform code
+ * maintains an array of these structures to represent every DMA channel in the
+ * system (see mxs_dma_channels).
+ */
+#define	MXS_DMA_FLAGS_IDLE	0
+#define	MXS_DMA_FLAGS_BUSY	(1 << 0)
+#define	MXS_DMA_FLAGS_FREE	0
+#define	MXS_DMA_FLAGS_ALLOCATED	(1 << 16)
+#define	MXS_DMA_FLAGS_VALID	(1 << 31)
+
+struct mxs_dma_chan {
+	const char *name;
+	unsigned long dev;
+	struct mxs_dma_device *dma;
+	unsigned int flags;
+	unsigned int active_num;
+	unsigned int pending_num;
+	struct list_head active;
+	struct list_head done;
+};
+
+struct mxs_dma_desc *mxs_dma_desc_alloc(void);
+void mxs_dma_desc_free(struct mxs_dma_desc *);
+int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
+
+int mxs_dma_go(int chan);
+int mxs_dma_init(void);
+
+#endif	/* __DMA_H__ */
-- 
1.8.3.2


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[PATCH 04/11] dma: apbh: remove CONFIG_ARCH_DMA_PIO_WORDS

[Sascha Hauer]

This define allows to overwrite DMA_PIO_WORDS with an architecture
specific value. Since this is unused and not clean anyway remove
it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 include/dma/apbh-dma.h | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/include/dma/apbh-dma.h b/include/dma/apbh-dma.h
index 52747e2..f10bb6f 100644
--- a/include/dma/apbh-dma.h
+++ b/include/dma/apbh-dma.h
@@ -28,12 +28,6 @@
 
 #include <linux/list.h>
 
-#ifndef	CONFIG_ARCH_DMA_PIO_WORDS
-#define	DMA_PIO_WORDS		15
-#else
-#define	DMA_PIO_WORDS		CONFIG_ARCH_DMA_PIO_WORDS
-#endif
-
 #define MXS_DMA_ALIGNMENT	32
 
 /*
@@ -90,7 +84,8 @@ struct mxs_dma_cmd {
 		dma_addr_t	address;
 		unsigned long	alternate;
 	};
-	unsigned long		pio_words[DMA_PIO_WORDS];
+#define	APBH_DMA_PIO_WORDS		15
+	unsigned long		pio_words[APBH_DMA_PIO_WORDS];
 };
 
 /*
-- 
1.8.3.2


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[PATCH 05/11] dma: apbh: Turn into a driver

[Sascha Hauer]

This converts the apbh driver into a real driver.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-mxs/soc-imx23.c |   2 +-
 arch/arm/mach-mxs/soc-imx28.c |   2 +-
 drivers/dma/apbh_dma.c        | 113 ++++++++++++++++++++++++++++++------------
 drivers/mtd/nand/nand_mxs.c   |   3 --
 include/driver.h              |   2 +
 5 files changed, 84 insertions(+), 38 deletions(-)

diff --git a/arch/arm/mach-mxs/soc-imx23.c b/arch/arm/mach-mxs/soc-imx23.c
index 4e45064..825ea20 100644
--- a/arch/arm/mach-mxs/soc-imx23.c
+++ b/arch/arm/mach-mxs/soc-imx23.c
@@ -38,7 +38,7 @@ EXPORT_SYMBOL(reset_cpu);
 
 static int imx23_devices_init(void)
 {
-
+	add_generic_device("imx23-dma-apbh", 0, NULL, MXS_APBH_BASE, 0x2000, IORESOURCE_MEM, NULL);
 	add_generic_device("imx23-clkctrl", 0, NULL, IMX_CCM_BASE, 0x100, IORESOURCE_MEM, NULL);
 
 	return 0;
diff --git a/arch/arm/mach-mxs/soc-imx28.c b/arch/arm/mach-mxs/soc-imx28.c
index 426f8ac..01bc20a 100644
--- a/arch/arm/mach-mxs/soc-imx28.c
+++ b/arch/arm/mach-mxs/soc-imx28.c
@@ -56,7 +56,7 @@ postcore_initcall(imx28_init);
 
 static int imx28_devices_init(void)
 {
-
+	add_generic_device("imx28-dma-apbh", 0, NULL, MXS_APBH_BASE, 0x2000, IORESOURCE_MEM, NULL);
 	add_generic_device("imx28-clkctrl", 0, NULL, IMX_CCM_BASE, 0x100, IORESOURCE_MEM, NULL);
 
 	return 0;
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index b0a20b8..fa4dd34 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -18,6 +18,8 @@
 #include <linux/list.h>
 
 #include <common.h>
+#include <driver.h>
+#include <init.h>
 #include <malloc.h>
 #include <errno.h>
 #include <dma/apbh-dma.h>
@@ -37,23 +39,28 @@
 #define HW_APBHX_CTRL2				0x020
 #define HW_APBHX_CHANNEL_CTRL			0x030
 #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL	16
-#define HW_APBH_VERSION				(cpu_is_mx23() ? 0x3f0 : 0x800)
-#define HW_APBX_VERSION				0x800
 #define BP_APBHX_VERSION_MAJOR			24
-#define HW_APBHX_CHn_NXTCMDAR(n) \
-	((apbh_is_old ? 0x050 : 0x110) + (n) * 0x70)
-#define HW_APBHX_CHn_SEMA(n) \
-	((apbh_is_old ? 0x080 : 0x140) + (n) * 0x70)
+#define HW_APBHX_CHn_NXTCMDAR_MX23(n)		(0x050 + (n) * 0x70)
+#define HW_APBHX_CHn_NXTCMDAR_MX28(n)		(0x110 + (n) * 0x70)
+#define HW_APBHX_CHn_SEMA_MX23(n)		(0x080 + (n) * 0x70)
+#define HW_APBHX_CHn_SEMA_MX28(n)		(0x140 + (n) * 0x70)
 #define	BM_APBHX_CHn_SEMA_PHORE			(0xff << 16)
 #define	BP_APBHX_CHn_SEMA_PHORE			16
 
 static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
-static bool apbh_is_old;
+
+enum mxs_dma_id {
+	IMX23_DMA,
+	IMX28_DMA,
+};
 
 struct apbh_dma {
 	void __iomem *regs;
+	enum mxs_dma_id id;
 };
 
+#define apbh_dma_is_imx23(aphb) ((apbh)->id == IMX23_DMA)
+
 static struct apbh_dma *apbh_dma;
 
 /*
@@ -105,7 +112,10 @@ static int mxs_dma_read_semaphore(int channel)
 	if (ret)
 		return ret;
 
-	tmp = readl(apbh->regs + HW_APBHX_CHn_SEMA(channel));
+	if (apbh_dma_is_imx23(apbh))
+		tmp = readl(apbh->regs + HW_APBHX_CHn_SEMA_MX23(channel));
+	else
+		tmp = readl(apbh->regs + HW_APBHX_CHn_SEMA_MX28(channel));
 
 	tmp &= BM_APBHX_CHn_SEMA_PHORE;
 	tmp >>= BP_APBHX_CHn_SEMA_PHORE;
@@ -156,21 +166,39 @@ static int mxs_dma_enable(int channel)
 		if (sem == 1) {
 			pdesc = list_entry(pdesc->node.next,
 					   struct mxs_dma_desc, node);
-			writel(mxs_dma_cmd_address(pdesc),
-				apbh->regs + HW_APBHX_CHn_NXTCMDAR(channel));
+			if (apbh_dma_is_imx23(apbh))
+				writel(mxs_dma_cmd_address(pdesc),
+					apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX23(channel));
+			else
+				writel(mxs_dma_cmd_address(pdesc),
+					apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX28(channel));
 		}
-		writel(pchan->pending_num,
-			apbh->regs + HW_APBHX_CHn_SEMA(channel));
+
+		if (apbh_dma_is_imx23(apbh))
+			writel(pchan->pending_num,
+					apbh->regs + HW_APBHX_CHn_SEMA_MX23(channel));
+		else
+			writel(pchan->pending_num,
+					apbh->regs + HW_APBHX_CHn_SEMA_MX28(channel));
+
 		pchan->active_num += pchan->pending_num;
 		pchan->pending_num = 0;
 	} else {
 		pchan->active_num += pchan->pending_num;
 		pchan->pending_num = 0;
-		writel(mxs_dma_cmd_address(pdesc),
-			apbh->regs + HW_APBHX_CHn_NXTCMDAR(channel));
-		writel(pchan->active_num,
-			apbh->regs + HW_APBHX_CHn_SEMA(channel));
-		channel_bit = channel + (apbh_is_old ? BP_APBH_CTRL0_CLKGATE_CHANNEL : 0);
+		if (apbh_dma_is_imx23(apbh)) {
+			writel(mxs_dma_cmd_address(pdesc),
+				apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX23(channel));
+			writel(pchan->active_num,
+				apbh->regs + HW_APBHX_CHn_SEMA_MX23(channel));
+			channel_bit = channel + BP_APBH_CTRL0_CLKGATE_CHANNEL;
+		} else {
+			writel(mxs_dma_cmd_address(pdesc),
+				apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX28(channel));
+			writel(pchan->active_num,
+				apbh->regs + HW_APBHX_CHn_SEMA_MX28(channel));
+			channel_bit = channel;
+		}
 		writel(1 << channel_bit, apbh->regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
 	}
 
@@ -207,7 +235,11 @@ static int mxs_dma_disable(int channel)
 	if (!(pchan->flags & MXS_DMA_FLAGS_BUSY))
 		return -EINVAL;
 
-	channel_bit = channel + (apbh_is_old ? BP_APBH_CTRL0_CLKGATE_CHANNEL : 0);
+	if (apbh_dma_is_imx23(apbh))
+		channel_bit = channel + BP_APBH_CTRL0_CLKGATE_CHANNEL;
+	else
+		channel_bit = channel + 0;
+
 	writel(1 << channel_bit, apbh->regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
 
 	pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
@@ -230,7 +262,7 @@ static int mxs_dma_reset(int channel)
 	if (ret)
 		return ret;
 
-	if (apbh_is_old)
+	if (apbh_dma_is_imx23(apbh))
 		writel(1 << (channel + BP_APBH_CTRL0_RESET_CHANNEL),
 			apbh->regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
 	else
@@ -554,29 +586,27 @@ int mxs_dma_go(int chan)
 /*
  * Initialize the DMA hardware
  */
-int mxs_dma_init(void)
+static int apbh_dma_probe(struct device_d *dev)
 {
 	struct apbh_dma *apbh;
 	struct mxs_dma_chan *pchan;
+	enum mxs_dma_id id;
 	int ret, channel;
-	u32 val;
-	void __iomem *reg;
 
-	apbh = xzalloc(sizeof(*apbh));
-	apbh->regs = (void __iomem *)MXS_APBH_BASE;
-
-	ret = stmp_reset_block(apbh->regs, 0);
+	ret = dev_get_drvdata(dev, (unsigned long *)&id);
 	if (ret)
 		return ret;
 
-	/* HACK: Get CPUID and determine APBH version */
-	val = readl(0x8001c310) >> 16;
-	if (val == 0x2800)
-		reg = apbh->regs + 0x0800;
-	else
-		reg = apbh->regs + 0x03f0;
+	apbh_dma = apbh = xzalloc(sizeof(*apbh));
+	apbh->regs = dev_request_mem_region(dev, 0);
+	if (!apbh->regs)
+		return -EBUSY;
+
+	apbh->id = id;
 
-	apbh_is_old = (readl((void *)reg) >> 24) < 3;
+	ret = stmp_reset_block(apbh->regs, 0);
+	if (ret)
+		return ret;
 
 	writel(BM_APBH_CTRL0_APB_BURST8_EN,
 		apbh->regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
@@ -608,3 +638,20 @@ err:
 		mxs_dma_release(channel);
 	return ret;
 }
+
+static struct platform_device_id apbh_ids[] = {
+	{
+		.name = "imx23-dma-apbh",
+		.driver_data = (unsigned long)IMX23_DMA,
+        }, {
+		.name = "imx28-dma-apbh",
+		.driver_data = (unsigned long)IMX28_DMA,
+        },
+};
+
+static struct driver_d apbh_dma_driver = {
+	.name  = "dma-apbh",
+	.id_table = apbh_ids,
+	.probe = apbh_dma_probe,
+};
+coredevice_platform_driver(apbh_dma_driver);
diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index adb0500..2086f80 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -1147,9 +1147,6 @@ int mxs_nand_hw_init(struct mxs_nand_info *info)
 			goto err2;
 	}
 
-	/* Init the DMA controller. */
-	mxs_dma_init();
-
 	/* Reset the GPMI block. */
 	ret = stmp_reset_block(gpmi_regs + GPMI_CTRL0, 0);
 	if (ret)
diff --git a/include/driver.h b/include/driver.h
index b18318f..7983946 100644
--- a/include/driver.h
+++ b/include/driver.h
@@ -414,6 +414,8 @@ int platform_driver_register(struct driver_d *drv);
 	}						\
 	level##_initcall(drv##_register)
 
+#define coredevice_platform_driver(drv)	\
+	register_driver_macro(coredevice,platform,drv)
 #define device_platform_driver(drv)	\
 	register_driver_macro(device,platform,drv)
 #define console_platform_driver(drv)	\
-- 
1.8.3.2


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[PATCH 06/11] dma: apbh: add devicetree probe support

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/dma/apbh_dma.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index fa4dd34..89948bc 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -649,9 +649,22 @@ static struct platform_device_id apbh_ids[] = {
         },
 };
 
+static __maybe_unused struct of_device_id apbh_dt_ids[] = {
+	{
+		.compatible = "fsl,imx23-dma-apbh",
+		.data = (unsigned long)IMX23_DMA,
+	}, {
+		.compatible = "fsl,imx28-dma-apbh",
+		.data = (unsigned long)IMX28_DMA,
+	}, {
+		/* sentinel */
+	}
+};
+
 static struct driver_d apbh_dma_driver = {
 	.name  = "dma-apbh",
 	.id_table = apbh_ids,
+	.of_compatible = DRV_OF_COMPAT(apbh_dt_ids),
 	.probe = apbh_dma_probe,
 };
 coredevice_platform_driver(apbh_dma_driver);
-- 
1.8.3.2


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[PATCH 07/11] dma: apbh: cleanup includes

[Sascha Hauer]

Several includes are unused, remove them.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/dma/apbh_dma.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 89948bc..665d394 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -15,19 +15,17 @@
  * (at your option) any later version.
  */
 
+#include <dma/apbh-dma.h>
+#include <stmp-device.h>
 #include <linux/list.h>
-
 #include <common.h>
 #include <driver.h>
-#include <init.h>
 #include <malloc.h>
 #include <errno.h>
-#include <dma/apbh-dma.h>
-#include <stmp-device.h>
+#include <init.h>
+#include <io.h>
+
 #include <asm/mmu.h>
-#include <asm/io.h>
-#include <mach/clock.h>
-#include <mach/imx-regs.h>
 
 #define HW_APBHX_CTRL0				0x000
 #define BM_APBH_CTRL0_APB_BURST8_EN		(1 << 29)
-- 
1.8.3.2


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[PATCH 08/11] mtd: nand: gpmi: use io_base instead of MXS_GPMI_BASE

[Sascha Hauer]

we have io_base, so use it instead of hardcoded base
address.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mtd/nand/nand_mxs.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index 2086f80..52a4959 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -408,7 +408,7 @@ static int mxs_nand_device_ready(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;
 	struct mxs_nand_info *nand_info = chip->priv;
-	void __iomem *gpmi_regs = (void *)MXS_GPMI_BASE;
+	void __iomem *gpmi_regs = nand_info->io_base;
 	uint32_t tmp;
 
 	if (nand_info->version > GPMI_VERSION_TYPE_MX23) {
@@ -1130,7 +1130,7 @@ int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
  */
 int mxs_nand_hw_init(struct mxs_nand_info *info)
 {
-	void __iomem *gpmi_regs = (void *)MXS_GPMI_BASE;
+	void __iomem *gpmi_regs = info->io_base;
 	void __iomem *bch_regs = (void __iomem *)MXS_BCH_BASE;
 	int i = 0, ret;
 	u32 val;
@@ -1195,7 +1195,6 @@ static int mxs_nand_probe(struct device_d *dev)
 		return -ENOMEM;
 	}
 
-	/* XXX: Remove u-boot specific access pointers and use io_base instead? */
 	nand_info->io_base = dev_request_mem_region(dev, 0);
 
 	nand_info->clk = clk_get(dev, NULL);
-- 
1.8.3.2


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[PATCH 09/11] mtd: nand: gpmi: cleanup includes

[Sascha Hauer]

remove unused includes and use <io.h> instead of <asm/io.h>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mtd/nand/nand_mxs.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index 52a4959..0611d7a 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -28,12 +28,10 @@
 #include <errno.h>
 #include <driver.h>
 #include <init.h>
+#include <io.h>
 #include <dma/apbh-dma.h>
 #include <stmp-device.h>
 #include <asm/mmu.h>
-#include <asm/io.h>
-#include <mach/clock.h>
-#include <mach/imx-regs.h>
 
 #define	MX28_BLOCK_SFTRST				(1 << 31)
 #define	MX28_BLOCK_CLKGATE				(1 << 30)
-- 
1.8.3.2


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[PATCH 10/11] ARM: mxs: Add convenience wrapper to register mxs_nand device

[Sascha Hauer]

The convenience wrapper also contains the bch resources to
get rid of the hardcoded base in the driver in the next step.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/freescale-mx28-evk/mx28-evk.c |  4 +--
 arch/arm/boards/karo-tx28/tx28.c              |  4 +--
 arch/arm/mach-mxs/include/mach/devices.h      | 47 +++++++++++++++++++++++++++
 3 files changed, 51 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/mach-mxs/include/mach/devices.h

diff --git a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c
index 687d3f7..dfb1878 100644
--- a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c
+++ b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c
@@ -30,6 +30,7 @@
 #include <mach/mci.h>
 #include <mach/fb.h>
 #include <mach/ocotp.h>
+#include <mach/devices.h>
 #include <spi/spi.h>
 
 #include <asm/armlinux.h>
@@ -270,8 +271,7 @@ static int mx28_evk_devices_init(void)
 	add_generic_device("imx28-fec", 0, NULL, IMX_FEC0_BASE, 0x4000,
 			   IORESOURCE_MEM, &fec_info);
 
-	add_generic_device("mxs_nand", 0, NULL, MXS_GPMI_BASE, 0x2000,
-			   IORESOURCE_MEM, NULL);
+	imx28_add_nand();
 
 	spi_register_board_info(mx28evk_spi_board_info,
 			ARRAY_SIZE(mx28evk_spi_board_info));
diff --git a/arch/arm/boards/karo-tx28/tx28.c b/arch/arm/boards/karo-tx28/tx28.c
index 6e8da15..4cacca3 100644
--- a/arch/arm/boards/karo-tx28/tx28.c
+++ b/arch/arm/boards/karo-tx28/tx28.c
@@ -21,6 +21,7 @@
 #include <io.h>
 #include <generated/mach-types.h>
 #include <mach/imx-regs.h>
+#include <mach/devices.h>
 #include <asm/mmu.h>
 
 /* setup the CPU card internal signals */
@@ -92,8 +93,7 @@ static int tx28_devices_init(void)
 
 	base_board_init();
 
-	add_generic_device("mxs_nand", 0, NULL, MXS_GPMI_BASE, 0x2000,
-			   IORESOURCE_MEM, NULL);
+	imx28_add_nand();
 
 	return 0;
 }
diff --git a/arch/arm/mach-mxs/include/mach/devices.h b/arch/arm/mach-mxs/include/mach/devices.h
new file mode 100644
index 0000000..012bfc4
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/devices.h
@@ -0,0 +1,47 @@
+#ifndef __MACH_MXS_DEVICES_H
+#define __MACH_MXS_DEVICES_H
+
+#include <common.h>
+#include <sizes.h>
+#include <xfuncs.h>
+#include <driver.h>
+#include <mach/imx-regs.h>
+
+static inline struct device_d *mxs_add_nand(unsigned long gpmi_base, unsigned long bch_base)
+{
+	struct resource res[] = {
+		{
+			.start = gpmi_base,
+			.end = gpmi_base + SZ_8K - 1,
+			.flags = IORESOURCE_MEM,
+		}, {
+			.start = bch_base,
+			.end = bch_base + SZ_8K - 1,
+			.flags = IORESOURCE_MEM,
+		},
+	};
+
+	struct device_d *dev = xzalloc(sizeof(*dev));
+
+	dev->resource = xzalloc(sizeof(struct resource) * ARRAY_SIZE(res));
+	memcpy(dev->resource, res, sizeof(struct resource) * ARRAY_SIZE(res));
+	dev->num_resources = ARRAY_SIZE(res);
+	strcpy(dev->name, "mxs_nand");
+	dev->id = DEVICE_ID_DYNAMIC;
+
+	platform_device_register(dev);
+
+	return dev;
+};
+
+static inline struct device_d *imx23_add_nand(void)
+{
+	return mxs_add_nand(MXS_GPMI_BASE, MXS_BCH_BASE);
+}
+
+static inline struct device_d *imx28_add_nand(void)
+{
+	return mxs_add_nand(MXS_GPMI_BASE, MXS_BCH_BASE);
+}
+
+#endif /* __MACH_MXS_DEVICES_H */
-- 
1.8.3.2


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[PATCH 11/11] mtd: nand: gpmi: replace MXS_BCH_BASE with driver resources

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mtd/nand/nand_mxs.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index 0611d7a..09ee55e 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -140,6 +140,7 @@
 struct mxs_nand_info {
 	struct nand_chip	nand_chip;
 	void __iomem		*io_base;
+	void __iomem		*bch_base;
 	struct clk		*clk;
 	struct mtd_info		mtd;
 	u32		version;
@@ -297,9 +298,9 @@ static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
 /*
  * Wait for BCH complete IRQ and clear the IRQ
  */
-static int mxs_nand_wait_for_bch_complete(void)
+static int mxs_nand_wait_for_bch_complete(struct mxs_nand_info *nand_info)
 {
-	void __iomem *bch_regs = (void __iomem *)MXS_BCH_BASE;
+	void __iomem *bch_regs = nand_info->bch_base;
 	int timeout = MXS_NAND_BCH_TIMEOUT;
 	int ret;
 
@@ -706,7 +707,7 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
 		goto rtn;
 	}
 
-	ret = mxs_nand_wait_for_bch_complete();
+	ret = mxs_nand_wait_for_bch_complete(nand_info);
 	if (ret) {
 		printf("MXS NAND: BCH read timeout\n");
 		goto rtn;
@@ -806,7 +807,7 @@ static void mxs_nand_ecc_write_page(struct mtd_info *mtd,
 		goto rtn;
 	}
 
-	ret = mxs_nand_wait_for_bch_complete();
+	ret = mxs_nand_wait_for_bch_complete(nand_info);
 	if (ret) {
 		printf("MXS NAND: BCH write timeout\n");
 		goto rtn;
@@ -1038,7 +1039,7 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd)
 {
 	struct nand_chip *nand = mtd->priv;
 	struct mxs_nand_info *nand_info = nand->priv;
-	void __iomem *bch_regs = (void __iomem *)MXS_BCH_BASE;
+	void __iomem *bch_regs = nand_info->bch_base;
 	uint32_t tmp;
 	int ret;
 
@@ -1129,7 +1130,7 @@ int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
 int mxs_nand_hw_init(struct mxs_nand_info *info)
 {
 	void __iomem *gpmi_regs = info->io_base;
-	void __iomem *bch_regs = (void __iomem *)MXS_BCH_BASE;
+	void __iomem *bch_regs = info->bch_base;
 	int i = 0, ret;
 	u32 val;
 
@@ -1194,6 +1195,7 @@ static int mxs_nand_probe(struct device_d *dev)
 	}
 
 	nand_info->io_base = dev_request_mem_region(dev, 0);
+	nand_info->bch_base = dev_request_mem_region(dev, 1);
 
 	nand_info->clk = clk_get(dev, NULL);
 	if (IS_ERR(nand_info->clk))
-- 
1.8.3.2


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