[PATCH 1/4] mxs_spi: unbreak driver

[PATCH 1/4] mxs_spi: unbreak driver

[Eric Bénard]

since the switch to common clock, SPI driver reports :
MXS: Timeout resetting block via register 0x80014000
mxs_spi mxs_spi2: MXS SPI: Timeout waiting for start

The reason is that the clock is not enabled anywhere in
the driver.

Signed-off-by: Eric Bénard <eric@eukrea.com>
---
 drivers/spi/mxs_spi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index a803652..a00784f 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -270,6 +270,7 @@ static int mxs_spi_probe(struct device_d *dev)
 	mxs->clk = clk_get(dev, NULL);
 	if (IS_ERR(mxs->clk))
 		return PTR_ERR(mxs->clk);
+	clk_enable(mxs->clk);
 
 	spi_register_master(master);
 
-- 
1.8.3.1


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[PATCH 2/4] nand_mxs: fix on i.MX28

[Eric Bénard]

when the bootmode is different than NAND (USB for example), the
GPMI clock is not enabled thus we can't probe a NAND flash.

Tested on an i.MX28

Signed-off-by: Eric Bénard <eric@eukrea.com>
---
 drivers/mtd/nand/nand_mxs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index 8e5c83c..d1e4b57 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -1259,6 +1259,7 @@ static int mxs_nand_probe(struct device_d *dev)
 		nand_info->dma_channel_base = 0;
 	} else {
 		nand_info->dma_channel_base = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
+		clk_enable(nand_info->clk);
 	}
 
 	err = mxs_nand_alloc_buffers(nand_info);
-- 
1.8.3.1


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[PATCH 3/4] video/stm: don't fail when the pixel clock is properly set

[Eric Bénard]

the check is wrong as when the clock rate is correctly set
the function will return 0.

Signed-off-by: Eric Bénard <eric@eukrea.com>
---
 drivers/video/stm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/stm.c b/drivers/video/stm.c
index 0875c9b..2603129 100644
--- a/drivers/video/stm.c
+++ b/drivers/video/stm.c
@@ -331,7 +331,7 @@ static int stmfb_activate_var(struct fb_info *fb_info)
 	/** @todo ensure HCLK is active at this point of time! */
 
 	size = clk_set_rate(fbi->clk, PICOS2KHZ(mode->pixclock) * 1000);
-	if (size == 0) {
+	if (size != 0) {
 		dev_dbg(fbi->hw_dev, "Unable to set a valid pixel clock\n");
 		return -EINVAL;
 	}
-- 
1.8.3.1


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[PATCH 4/4] video/stm: enable clock to get the display working

[Eric Bénard]

else the clock is not enabled :
        ref_pix (rate 270000000, disabled)
            lcdif_sel (rate 270000000, disabled)
                lcdif_div (rate 33750000, disabled)
                    lcdif (rate 33750000, disabled)
                        lcdif_comp (rate 33750000, disabled)

tested on i.MX28EVK.

Signed-off-by: Eric Bénard <eric@eukrea.com>
---
 drivers/video/stm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/video/stm.c b/drivers/video/stm.c
index 2603129..fdeaf9c 100644
--- a/drivers/video/stm.c
+++ b/drivers/video/stm.c
@@ -496,6 +496,7 @@ static int stmfb_probe(struct device_d *hw_dev)
 	fbi.clk = clk_get(hw_dev, NULL);
 	if (IS_ERR(fbi.clk))
 		return PTR_ERR(fbi.clk);
+	clk_enable(fbi.clk);
 
 	/* add runtime video info */
 	fbi.info.mode_list = pdata->mode_list;
-- 
1.8.3.1


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