[PATCH 1/4] ARM: Make thumb2 compilation only visible on CPUs that support it

[PATCH 1/4] ARM: Make thumb2 compilation only visible on CPUs that support it

[Sascha Hauer]

Thumb2 can't be used if one of CPU_32v4T, CPU_32v5 or CPU_32v6 is
selected.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 93619d5..ce8d3fd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -216,7 +216,7 @@ config AEABI
 config THUMB2_BAREBOX
 	select ARM_ASM_UNIFIED
 	select AEABI
-	depends on CPU_V7
+	depends on CPU_V7 && !CPU_32v4T && !CPU_32v5 && !CPU_32v6
 	bool "Compile barebox in thumb-2 mode (read help)"
 	help
 	  This enables compilation of barebox in thumb-2 mode which generates
-- 
1.8.5.3


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[PATCH 2/4] ARM: Pass armv7-a AFLAGS to cache-v7

[Sascha Hauer]

The cache-v7 code uses assembler instructions which do not
exist on before v7, so explicitely pass armv7-a to this file
to make the compiler happy.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/cpu/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index c29d030..fb3929c 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -17,7 +17,9 @@ obj-$(CONFIG_CPU_32v5) += cache-armv5.o
 pbl-$(CONFIG_CPU_32v5) += cache-armv5.o
 obj-$(CONFIG_CPU_32v6) += cache-armv6.o
 pbl-$(CONFIG_CPU_32v6) += cache-armv6.o
+AFLAGS_cache-armv7.o       :=-Wa,-march=armv7-a
 obj-$(CONFIG_CPU_32v7) += cache-armv7.o
+AFLAGS_pbl-cache-armv7.o       :=-Wa,-march=armv7-a
 pbl-$(CONFIG_CPU_32v7) += cache-armv7.o
 obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
 
-- 
1.8.5.3


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[PATCH 3/4] ARM: Do not use BUG() in pbl code

[Sascha Hauer]

BUG() uses printf which is not available in pbl, so do not use it here.
This becomes necessary when multiple CPU architectures are compiled in.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/cpu/cache.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/cache.c b/arch/arm/cpu/cache.c
index 223e308..34d3090 100644
--- a/arch/arm/cpu/cache.c
+++ b/arch/arm/cpu/cache.c
@@ -102,7 +102,7 @@ int arm_set_cache_functions(void)
 		break;
 #endif
 	default:
-		BUG();
+		while(1);
 	}
 
 	return 0;
-- 
1.8.5.3


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[PATCH 4/4] ARM: mode cpu_architecture() to common.c

[Sascha Hauer]

It might be needed in pbl code, so move it to a file which is
compiled in pbl mode.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/cpu/common.c | 14 ++++++++++++++
 arch/arm/cpu/cpu.c    | 14 --------------
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
index 40f784f..d5f8929 100644
--- a/arch/arm/cpu/common.c
+++ b/arch/arm/cpu/common.c
@@ -18,6 +18,7 @@
 #include <common.h>
 #include <init.h>
 #include <sizes.h>
+#include <asm/system_info.h>
 #include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
 #include <asm-generic/memory_layout.h>
@@ -64,3 +65,16 @@ void relocate_to_current_adr(void)
 	arm_early_mmu_cache_flush();
 	flush_icache();
 }
+
+#ifdef ARM_MULTIARCH
+
+int __cpu_architecture;
+
+int __pure cpu_architecture(void)
+{
+	if(__cpu_architecture == CPU_ARCH_UNKNOWN)
+		__cpu_architecture = arm_early_get_cpu_architecture();
+
+	return __cpu_architecture;
+}
+#endif
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index f2e698d..895e07e 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -29,7 +29,6 @@
 #include <asm/system.h>
 #include <asm/memory.h>
 #include <asm-generic/memory_layout.h>
-#include <asm/system_info.h>
 #include <asm/cputype.h>
 #include <asm/cache.h>
 #include <asm/ptrace.h>
@@ -146,16 +145,3 @@ static int execute_init(void)
 }
 postcore_initcall(execute_init);
 #endif
-
-#ifdef ARM_MULTIARCH
-
-int __cpu_architecture;
-
-int __pure cpu_architecture(void)
-{
-	if(__cpu_architecture == CPU_ARCH_UNKNOWN)
-		__cpu_architecture = arm_early_get_cpu_architecture();
-
-	return __cpu_architecture;
-}
-#endif
-- 
1.8.5.3


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