[PATCH 01/14] pinctrl: i.MX iomux-v3: Print more context in error message

[PATCH 01/14] pinctrl: i.MX iomux-v3: Print more context in error message

[Sascha Hauer]

When a devicenode has invalid pinctrl settings then printing the
offending node helps debugging it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/pinctrl/imx-iomux-v3.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/imx-iomux-v3.c b/drivers/pinctrl/imx-iomux-v3.c
index 1319690..5dfcde6 100644
--- a/drivers/pinctrl/imx-iomux-v3.c
+++ b/drivers/pinctrl/imx-iomux-v3.c
@@ -117,7 +117,8 @@ static int imx_iomux_v3_set_state(struct pinctrl_device *pdev, struct device_nod
 
 
 	if (!size || size % FSL_PIN_SIZE) {
-		dev_err(iomux->pinctrl.dev, "Invalid fsl,pins property\n");
+		dev_err(iomux->pinctrl.dev, "Invalid fsl,pins property in %s\n",
+				np->full_name);
 		return -EINVAL;
 	}
 
-- 
2.0.0.rc0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 02/14] ARM: i.MX: bbu: remove dcd arguments from bbu registration

[Sascha Hauer]

The i.MX barebox update handlers take an optional dcd table as argument.
This can be used to add the correct dcd data to the image before flashing
it.
This mechanism is quite complicated and largely unused, so remove it. With
this it is only possible to flash the exact image passed to barebox_update,
which is what is mostly done anyway.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/boundarydevices-nitrogen6x/board.c |   2 +-
 arch/arm/boards/datamodul-edm-qmx6/board.c         |   5 +-
 arch/arm/boards/dfi-fs700-m60/board.c              |   4 +-
 arch/arm/boards/efika-mx-smartbook/board.c         |   8 +-
 arch/arm/boards/embest-riotboard/board.c           |   2 +-
 arch/arm/boards/freescale-mx51-babbage/board.c     |   6 +-
 arch/arm/boards/freescale-mx53-qsb/board.c         |   6 +-
 arch/arm/boards/freescale-mx53-vmx53/board.c       |   7 +-
 arch/arm/boards/freescale-mx6-sabrelite/board.c    |   2 +-
 arch/arm/boards/guf-santaro/board.c                |   6 +-
 arch/arm/boards/guf-vincell/board.c                |   5 +-
 arch/arm/boards/karo-tx53/board.c                  |  14 +-
 arch/arm/boards/karo-tx53/dcd-data-1011.h          |  94 --------
 arch/arm/boards/karo-tx53/dcd-data-xx30.h          | 144 -----------
 arch/arm/boards/tqma6x/board.c                     |  24 +-
 arch/arm/mach-imx/imx-bbu-internal.c               | 263 ++++-----------------
 arch/arm/mach-imx/include/mach/bbu.h               |  43 +---
 17 files changed, 71 insertions(+), 564 deletions(-)
 delete mode 100644 arch/arm/boards/karo-tx53/dcd-data-1011.h
 delete mode 100644 arch/arm/boards/karo-tx53/dcd-data-xx30.h

diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/board.c b/arch/arm/boards/boundarydevices-nitrogen6x/board.c
index 1c4b495..95c8567 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6x/board.c
+++ b/arch/arm/boards/boundarydevices-nitrogen6x/board.c
@@ -27,7 +27,7 @@ static int nitrogen6x_devices_init(void)
 		return 0;
 
 	imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
-			BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0);
+			BBU_HANDLER_FLAG_DEFAULT);
 
 	return 0;
 }
diff --git a/arch/arm/boards/datamodul-edm-qmx6/board.c b/arch/arm/boards/datamodul-edm-qmx6/board.c
index fd02d7a..26757eb 100644
--- a/arch/arm/boards/datamodul-edm-qmx6/board.c
+++ b/arch/arm/boards/datamodul-edm-qmx6/board.c
@@ -104,9 +104,8 @@ static int realq7_env_init(void)
 		return 0;
 
 	imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
-		BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0x00907000);
-	imx6_bbu_internal_mmc_register_handler("mmc", "/dev/mmc3.barebox",
-		0, NULL, 0, 0x00907000);
+		BBU_HANDLER_FLAG_DEFAULT);
+	imx6_bbu_internal_mmc_register_handler("mmc", "/dev/mmc3.barebox", 0);
 	return 0;
 }
 late_initcall(realq7_env_init);
diff --git a/arch/arm/boards/dfi-fs700-m60/board.c b/arch/arm/boards/dfi-fs700-m60/board.c
index cefb6ce..e0dc5b2 100644
--- a/arch/arm/boards/dfi-fs700-m60/board.c
+++ b/arch/arm/boards/dfi-fs700-m60/board.c
@@ -111,9 +111,9 @@ static int dfi_fs700_m60_init(void)
 		flag_mmc |= BBU_HANDLER_FLAG_DEFAULT;
 
 	imx6_bbu_internal_mmc_register_handler("mmc", "/dev/mmc3.boot0",
-		flag_mmc, NULL, 0, 0);
+		flag_mmc);
 	imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0",
-		flag_spi, NULL, 0, 0);
+		flag_spi);
 
 	armlinux_set_architecture(MACH_TYPE_MX6Q_SABRESD);
 
diff --git a/arch/arm/boards/efika-mx-smartbook/board.c b/arch/arm/boards/efika-mx-smartbook/board.c
index 1b19acd..59410c1 100644
--- a/arch/arm/boards/efika-mx-smartbook/board.c
+++ b/arch/arm/boards/efika-mx-smartbook/board.c
@@ -238,9 +238,6 @@ static struct gpio_led leds[] = {
 	},
 };
 
-extern char flash_header_imx51_genesi_efikasb_start[];
-extern char flash_header_imx51_genesi_efikasb_end[];
-
 static int efikamx_late_init(void)
 {
 	int i;
@@ -258,10 +255,7 @@ static int efikamx_late_init(void)
 	writew(0x0, MX51_WDOG_BASE_ADDR + 0x8);
 
 	imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc1",
-			BBU_HANDLER_FLAG_DEFAULT,
-			(void *)flash_header_imx51_genesi_efikasb_start,
-			flash_header_imx51_genesi_efikasb_end -
-			flash_header_imx51_genesi_efikasb_start, 0);
+			BBU_HANDLER_FLAG_DEFAULT);
 
 	armlinux_set_architecture(2370);
 	armlinux_set_revision(0x5100 | imx_silicon_revision());
diff --git a/arch/arm/boards/embest-riotboard/board.c b/arch/arm/boards/embest-riotboard/board.c
index 638d0f6..3c28aa1 100644
--- a/arch/arm/boards/embest-riotboard/board.c
+++ b/arch/arm/boards/embest-riotboard/board.c
@@ -70,7 +70,7 @@ static int riotboard_device_init(void)
 	phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup);
 
 	imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc3.barebox",
-			BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0);
+			BBU_HANDLER_FLAG_DEFAULT);
 
 	return 0;
 }
diff --git a/arch/arm/boards/freescale-mx51-babbage/board.c b/arch/arm/boards/freescale-mx51-babbage/board.c
index bfe5338..adb4e65 100644
--- a/arch/arm/boards/freescale-mx51-babbage/board.c
+++ b/arch/arm/boards/freescale-mx51-babbage/board.c
@@ -151,9 +151,6 @@ static void babbage_power_init(void)
 	udelay(200);
 }
 
-extern char flash_header_imx51_babbage_start[];
-extern char flash_header_imx51_babbage_end[];
-
 static int imx51_babbage_late_init(void)
 {
 	if (!of_machine_is_compatible("fsl,imx51-babbage"))
@@ -168,8 +165,7 @@ static int imx51_babbage_late_init(void)
 	armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
 
 	imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0",
-		BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_imx51_babbage_start,
-		flash_header_imx51_babbage_end - flash_header_imx51_babbage_start, 0);
+		BBU_HANDLER_FLAG_DEFAULT);
 
 	return 0;
 }
diff --git a/arch/arm/boards/freescale-mx53-qsb/board.c b/arch/arm/boards/freescale-mx53-qsb/board.c
index 38d1ee6..9a9bffa 100644
--- a/arch/arm/boards/freescale-mx53-qsb/board.c
+++ b/arch/arm/boards/freescale-mx53-qsb/board.c
@@ -76,9 +76,6 @@ static void loco_fec_reset(void)
 
 #define MX53_LOCO_USB_PWREN		IMX_GPIO_NR(7, 8)
 
-extern char flash_header_imx53_loco_start[];
-extern char flash_header_imx53_loco_end[];
-
 static int loco_late_init(void)
 {
 	struct mc13xxx *mc34708;
@@ -162,8 +159,7 @@ static int loco_late_init(void)
 	armlinux_set_architecture(MACH_TYPE_MX53_LOCO);
 
 	imx53_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0",
-		BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_imx53_loco_start,
-		flash_header_imx53_loco_end - flash_header_imx53_loco_start, 0);
+		BBU_HANDLER_FLAG_DEFAULT);
 
 	return 0;
 }
diff --git a/arch/arm/boards/freescale-mx53-vmx53/board.c b/arch/arm/boards/freescale-mx53-vmx53/board.c
index d0cc495..b91bfdf 100644
--- a/arch/arm/boards/freescale-mx53-vmx53/board.c
+++ b/arch/arm/boards/freescale-mx53-vmx53/board.c
@@ -25,9 +25,6 @@
 #include <asm/armlinux.h>
 #include <mach/bbu.h>
 
-extern char flash_header_imx53_vmx53_start[];
-extern char flash_header_imx53_vmx53_end[];
-
 static int vmx53_late_init(void)
 {
 	if (!of_machine_is_compatible("voipac,imx53-dmm-668"))
@@ -39,9 +36,7 @@ static int vmx53_late_init(void)
 	barebox_set_hostname("vmx53");
 
 	imx53_bbu_internal_nand_register_handler("nand",
-		BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_imx53_vmx53_start,
-		flash_header_imx53_vmx53_end - flash_header_imx53_vmx53_start,
-		SZ_512K, 0);
+		BBU_HANDLER_FLAG_DEFAULT, SZ_512K);
 
 	return 0;
 }
diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c b/arch/arm/boards/freescale-mx6-sabrelite/board.c
index f42489f..178fed6 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/board.c
+++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c
@@ -165,7 +165,7 @@ static int sabrelite_devices_init(void)
 	armlinux_set_architecture(3769);
 
 	imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
-			BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0);
+			BBU_HANDLER_FLAG_DEFAULT);
 
 	return 0;
 }
diff --git a/arch/arm/boards/guf-santaro/board.c b/arch/arm/boards/guf-santaro/board.c
index 198c90a..9b5d09d 100644
--- a/arch/arm/boards/guf-santaro/board.c
+++ b/arch/arm/boards/guf-santaro/board.c
@@ -60,10 +60,8 @@ static int santaro_device_init(void)
 		}
 	}
 
-	imx6_bbu_internal_mmc_register_handler("sd", "/dev/mmc1",
-			flag_sd, NULL, 0, 0);
-	imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc3.boot0",
-			flag_emmc, NULL, 0, 0);
+	imx6_bbu_internal_mmc_register_handler("sd", "/dev/mmc1", flag_sd);
+	imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc3.boot0", flag_emmc);
 
 	return 0;
 }
diff --git a/arch/arm/boards/guf-vincell/board.c b/arch/arm/boards/guf-vincell/board.c
index cb09303..45389cd 100644
--- a/arch/arm/boards/guf-vincell/board.c
+++ b/arch/arm/boards/guf-vincell/board.c
@@ -259,9 +259,6 @@ static struct imx_nand_platform_data nand_info = {
 	.flash_bbt	= 1,
 };
 
-static struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
-};
-
 static struct i2c_board_info i2c_devices[] = {
 	{
 		I2C_BOARD_INFO("da9053", 0x48),
@@ -293,7 +290,7 @@ static int vincell_devices_init(void)
 	dev_add_bb_dev("env_raw", "env0");
 
 	imx53_bbu_internal_nand_register_handler("nand",
-		BBU_HANDLER_FLAG_DEFAULT, dcd_entry, sizeof(dcd_entry), 3 * SZ_128K, 0xf8020000);
+		BBU_HANDLER_FLAG_DEFAULT);
 
 	return 0;
 }
diff --git a/arch/arm/boards/karo-tx53/board.c b/arch/arm/boards/karo-tx53/board.c
index b7e7f1c..e5c27aa 100644
--- a/arch/arm/boards/karo-tx53/board.c
+++ b/arch/arm/boards/karo-tx53/board.c
@@ -198,14 +198,6 @@ static inline void tx53_fec_init(void)
 			ARRAY_SIZE(tx53_fec_pads));
 }
 
-#define DCD_NAME_1011 static struct imx_dcd_v2_entry dcd_entry_1011
-
-#include "dcd-data-1011.h"
-
-#define DCD_NAME_XX30 static u32 dcd_entry_xx30
-
-#include "dcd-data-xx30.h"
-
 static int tx53_devices_init(void)
 {
 	imx53_iim_register_fec_ethaddr();
@@ -218,12 +210,10 @@ static int tx53_devices_init(void)
 
 	/* rev xx30 can boot from nand or USB */
 	imx53_bbu_internal_nand_register_handler("nand-xx30",
-		BBU_HANDLER_FLAG_DEFAULT, (void *)dcd_entry_xx30,
-		sizeof(dcd_entry_xx30), SZ_512K, 0);
+		BBU_HANDLER_FLAG_DEFAULT, SZ_512K);
 
 	/* rev 1011 can boot from MMC/SD, other bootsource currently unknown */
-	imx53_bbu_internal_mmc_register_handler("mmc-1011", "/dev/disk0",
-		0, (void *)dcd_entry_1011, sizeof(dcd_entry_1011), 0);
+	imx53_bbu_internal_mmc_register_handler("mmc-1011", "/dev/disk0", 0);
 
 	return 0;
 }
diff --git a/arch/arm/boards/karo-tx53/dcd-data-1011.h b/arch/arm/boards/karo-tx53/dcd-data-1011.h
deleted file mode 100644
index 7034ff8..0000000
--- a/arch/arm/boards/karo-tx53/dcd-data-1011.h
+++ /dev/null
@@ -1,94 +0,0 @@
-DCD_NAME_1011[] = {
-	{ .addr = cpu_to_be32(0x53fd406c), .val = cpu_to_be32(0xffffffff), },
-	{ .addr = cpu_to_be32(0x53fd4070), .val = cpu_to_be32(0xffffffff), },
-	{ .addr = cpu_to_be32(0x53fd4074), .val = cpu_to_be32(0xffffffff), },
-	{ .addr = cpu_to_be32(0x53fd4078), .val = cpu_to_be32(0xffffffff), },
-	{ .addr = cpu_to_be32(0x53fd407c), .val = cpu_to_be32(0xffffffff), },
-	{ .addr = cpu_to_be32(0x53fd4080), .val = cpu_to_be32(0xffffffff), },
-	{ .addr = cpu_to_be32(0x53fd4088), .val = cpu_to_be32(0xffffffff), },
-	{ .addr = cpu_to_be32(0x53fa8174), .val = cpu_to_be32(0x00000011), },
-	{ .addr = cpu_to_be32(0x63fd800c), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00200000), },
-	{ .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00200000), },
-	{ .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00200000), },
-	{ .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00200000), },
-	{ .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00200040), },
-	{ .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00200040), },
-	{ .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00200040), },
-	{ .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00200040), },
-	{ .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00200040), },
-	{ .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00200040), },
-	{ .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00200000), },
-	{ .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00200000), },
-	{ .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00200000), },
-	{ .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00200000), },
-	{ .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00200000), },
-	{ .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00200000), },
-	{ .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00280000), },
-	{ .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00280000), },
-	{ .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00280000), },
-	{ .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00280000), },
-	{ .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000200), },
-	{ .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x06000000), },
-	{ .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x36353b38), },
-	{ .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x49434942), },
-	{ .addr = cpu_to_be32(0x63fd90f8), .val = cpu_to_be32(0x00000800), },
-	{ .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01350138), },
-	{ .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x01380139), },
-	{ .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00001710), },
-	{ .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0x84110000), },
-	{ .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x4d5122d2), },
-	{ .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb6f18a22), },
-	{ .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x00c700db), },
-	{ .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), },
-	{ .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f000e), },
-	{ .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12272000), },
-	{ .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x00030012), },
-	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008010), },
-	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), },
-	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), },
-	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0a528030), },
-	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x03868031), },
-	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00068031), },
-	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), },
-	{ .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), },
-	{ .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00033332), },
-	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00448031), },
-	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008018), },
-	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), },
-	{ .addr = cpu_to_be32(0x53fa8004), .val = cpu_to_be32(0x00194005), },
-	{ .addr = cpu_to_be32(0x53fa819c), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa81a0), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa81a4), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa81a8), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa81ac), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa81b0), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa81b4), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa81b8), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa81dc), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa81e0), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa8228), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa822c), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa8230), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa8234), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa8238), .val = cpu_to_be32(0x00000000), },
-	{ .addr = cpu_to_be32(0x53fa84ec), .val = cpu_to_be32(0x000000e4), },
-	{ .addr = cpu_to_be32(0x53fa84f0), .val = cpu_to_be32(0x000000e4), },
-	{ .addr = cpu_to_be32(0x53fa84f4), .val = cpu_to_be32(0x000000e4), },
-	{ .addr = cpu_to_be32(0x53fa84f8), .val = cpu_to_be32(0x000000e4), },
-	{ .addr = cpu_to_be32(0x53fa84fc), .val = cpu_to_be32(0x000000e4), },
-	{ .addr = cpu_to_be32(0x53fa8500), .val = cpu_to_be32(0x000000e4), },
-	{ .addr = cpu_to_be32(0x53fa8504), .val = cpu_to_be32(0x000000e4), },
-	{ .addr = cpu_to_be32(0x53fa8508), .val = cpu_to_be32(0x000000e4), },
-	{ .addr = cpu_to_be32(0x53fa852c), .val = cpu_to_be32(0x00000004), },
-	{ .addr = cpu_to_be32(0x53fa8530), .val = cpu_to_be32(0x00000004), },
-	{ .addr = cpu_to_be32(0x53fa85a0), .val = cpu_to_be32(0x00000004), },
-	{ .addr = cpu_to_be32(0x53fa85a4), .val = cpu_to_be32(0x00000004), },
-	{ .addr = cpu_to_be32(0x53fa85a8), .val = cpu_to_be32(0x000000e4), },
-	{ .addr = cpu_to_be32(0x53fa85ac), .val = cpu_to_be32(0x000000e4), },
-	{ .addr = cpu_to_be32(0x53fa85b0), .val = cpu_to_be32(0x00000004), },
-};
diff --git a/arch/arm/boards/karo-tx53/dcd-data-xx30.h b/arch/arm/boards/karo-tx53/dcd-data-xx30.h
deleted file mode 100644
index cb982dc..0000000
--- a/arch/arm/boards/karo-tx53/dcd-data-xx30.h
+++ /dev/null
@@ -1,144 +0,0 @@
-
-#define DCD_ITEM(adr, val)	cpu_to_be32(adr), cpu_to_be32(val)
-#define DCD_WR_CMD(len)		cpu_to_be32(0xcc << 24 | (len) << 8 | 0x04)
-#define DCD_CHECK_CMD(a, b, c)	cpu_to_be32(a), cpu_to_be32(b), cpu_to_be32(c)
-
-/*
- * This board uses advanced features of the DCD which do not corporate
- * well with our flash header defines. The DCD consists of commands which
- * have the length econded into them. Normally the DCDs only have a single
- * command (DCD_COMMAND_WRITE_TAG) which is already part of struct
- * imx_flash_header_v2. Now this board uses multiple commands, so we cannot
- * calculate the command length using sizeof(dcd_entry).
- */
-
-DCD_NAME_XX30[] = {
-	DCD_ITEM(0x53fd4068, 0xffcc0fff),
-	DCD_ITEM(0x53fd406c, 0x000fffc3),
-	DCD_ITEM(0x53fd4070, 0x033c0000),
-	DCD_ITEM(0x53fd4074, 0x00000000),
-	DCD_ITEM(0x53fd4078, 0x00000000),
-	DCD_ITEM(0x53fd407c, 0x00fff033),
-	DCD_ITEM(0x53fd4080, 0x0f00030f),
-	DCD_ITEM(0x53fd4084, 0xfff00000),
-	DCD_ITEM(0x53fd4088, 0x00000000),
-	DCD_ITEM(0x53fa8174, 0x00000011),
-	DCD_ITEM(0x53fa8318, 0x00000011),
-	DCD_ITEM(0x63fd800c, 0x00000000),
-	DCD_ITEM(0x53fd4014, 0x00888944),
-	DCD_ITEM(0x53fd4018, 0x00016154),
-	DCD_ITEM(0x53fa8724, 0x04000000),
-	DCD_ITEM(0x53fa86f4, 0x00000000),
-	DCD_ITEM(0x53fa8714, 0x00000000),
-	DCD_ITEM(0x53fa86fc, 0x00000080),
-	DCD_ITEM(0x53fa8710, 0x00000000),
-	DCD_ITEM(0x53fa8708, 0x00000040),
-	DCD_ITEM(0x53fa8584, 0x00280000),
-	DCD_ITEM(0x53fa8594, 0x00280000),
-	DCD_ITEM(0x53fa8560, 0x00280000),
-	DCD_ITEM(0x53fa8554, 0x00280000),
-	DCD_ITEM(0x53fa857c, 0x00a80040),
-	DCD_ITEM(0x53fa8590, 0x00a80040),
-	DCD_ITEM(0x53fa8568, 0x00a80040),
-	DCD_ITEM(0x53fa8558, 0x00a80040),
-	DCD_ITEM(0x53fa8580, 0x00280040),
-	DCD_ITEM(0x53fa8578, 0x00280000),
-	DCD_ITEM(0x53fa8564, 0x00280040),
-	DCD_ITEM(0x53fa8570, 0x00280000),
-	DCD_ITEM(0x53fa858c, 0x000000c0),
-	DCD_ITEM(0x53fa855c, 0x000000c0),
-	DCD_ITEM(0x53fa8574, 0x00280000),
-	DCD_ITEM(0x53fa8588, 0x00280000),
-	DCD_ITEM(0x53fa86f0, 0x00280000),
-	DCD_ITEM(0x53fa8720, 0x00280000),
-	DCD_ITEM(0x53fa8718, 0x00280000),
-	DCD_ITEM(0x53fa871c, 0x00280000),
-	DCD_ITEM(0x53fa8728, 0x00280000),
-	DCD_ITEM(0x53fa872c, 0x00280000),
-	DCD_ITEM(0x63fd904c, 0x001f001f),
-	DCD_ITEM(0x63fd9050, 0x001f001f),
-	DCD_ITEM(0x63fd907c, 0x011e011e),
-	DCD_ITEM(0x63fd9080, 0x011f0120),
-	DCD_ITEM(0x63fd9088, 0x3a393d3b),
-	DCD_ITEM(0x63fd9090, 0x3f3f3f3f),
-	DCD_ITEM(0x63fd9018, 0x00011740),
-	DCD_ITEM(0x63fd9000, 0x83190000),
-	DCD_ITEM(0x63fd900c, 0x3f435316),
-	DCD_ITEM(0x63fd9010, 0xb66e0a63),
-	DCD_ITEM(0x63fd9014, 0x01ff00db),
-	DCD_ITEM(0x63fd902c, 0x000026d2),
-	DCD_ITEM(0x63fd9030, 0x00430f24),
-	DCD_ITEM(0x63fd9008, 0x1b221010),
-	DCD_ITEM(0x63fd9004, 0x00030012),
-	DCD_ITEM(0x63fd901c, 0x00008032),
-	DCD_ITEM(0x63fd901c, 0x00008033),
-	DCD_ITEM(0x63fd901c, 0x00408031),
-	DCD_ITEM(0x63fd901c, 0x055080b0),
-	DCD_ITEM(0x63fd9020, 0x00005800),
-	DCD_ITEM(0x63fd9058, 0x00011112),
-	DCD_ITEM(0x63fd90d0, 0x00000003),
-	DCD_ITEM(0x63fd901c, 0x04008010),
-	DCD_ITEM(0x63fd901c, 0x00008040),
-	DCD_ITEM(0x63fd9040, 0x0539002b),
-	DCD_CHECK_CMD(0xcf000c04, 0x63fd9040, 0x00010000),
-	DCD_WR_CMD(0x24),
-	DCD_ITEM(0x63fd901c, 0x00048033),
-	DCD_ITEM(0x63fd901c, 0x00848231),
-	DCD_ITEM(0x63fd901c, 0x00000000),
-	DCD_ITEM(0x63fd9048, 0x00000001),
-	DCD_CHECK_CMD(0xcf000c04, 0x63fd9048, 0x00000001),
-	DCD_WR_CMD(0x2c),
-	DCD_ITEM(0x63fd901c, 0x00048031),
-	DCD_ITEM(0x63fd901c, 0x00008033),
-	DCD_ITEM(0x63fd901c, 0x04008010),
-	DCD_ITEM(0x63fd901c, 0x00048033),
-	DCD_ITEM(0x63fd907c, 0x90000000),
-	DCD_CHECK_CMD(0xcf000c04, 0x63fd907c, 0x90000000),
-	DCD_WR_CMD(0x2c),
-	DCD_ITEM(0x63fd901c, 0x00008033),
-	DCD_ITEM(0x63fd901c, 0x00000000),
-	DCD_ITEM(0x63fd901c, 0x04008010),
-	DCD_ITEM(0x63fd901c, 0x00048033),
-	DCD_ITEM(0x63fd90a4, 0x00000010),
-	DCD_CHECK_CMD(0xcf000c04, 0x63fd90a4, 0x00000010),
-	DCD_WR_CMD(0x24),
-	DCD_ITEM(0x63fd901c, 0x00008033),
-	DCD_ITEM(0x63fd901c, 0x04008010),
-	DCD_ITEM(0x63fd901c, 0x00048033),
-	DCD_ITEM(0x63fd90a0, 0x00000010),
-	DCD_CHECK_CMD(0xcf000c04, 0x63fd90a0, 0x00000010),
-	DCD_WR_CMD(0x010c),
-	DCD_ITEM(0x63fd901c, 0x00008033),
-	DCD_ITEM(0x63fd901c, 0x00000000),
-	DCD_ITEM(0x53fa8004, 0x00194005),
-	DCD_ITEM(0x53fa819c, 0x00000000),
-	DCD_ITEM(0x53fa81a0, 0x00000000),
-	DCD_ITEM(0x53fa81a4, 0x00000000),
-	DCD_ITEM(0x53fa81a8, 0x00000000),
-	DCD_ITEM(0x53fa81ac, 0x00000000),
-	DCD_ITEM(0x53fa81b0, 0x00000000),
-	DCD_ITEM(0x53fa81b4, 0x00000000),
-	DCD_ITEM(0x53fa81b8, 0x00000000),
-	DCD_ITEM(0x53fa81dc, 0x00000000),
-	DCD_ITEM(0x53fa81e0, 0x00000000),
-	DCD_ITEM(0x53fa8228, 0x00000000),
-	DCD_ITEM(0x53fa822c, 0x00000000),
-	DCD_ITEM(0x53fa8230, 0x00000000),
-	DCD_ITEM(0x53fa8234, 0x00000000),
-	DCD_ITEM(0x53fa8238, 0x00000000),
-	DCD_ITEM(0x53fa84ec, 0x000000e4),
-	DCD_ITEM(0x53fa84f0, 0x000000e4),
-	DCD_ITEM(0x53fa84f4, 0x000000e4),
-	DCD_ITEM(0x53fa84f8, 0x000000e4),
-	DCD_ITEM(0x53fa84fc, 0x000000e4),
-	DCD_ITEM(0x53fa8500, 0x000000e4),
-	DCD_ITEM(0x53fa8504, 0x000000e4),
-	DCD_ITEM(0x53fa8508, 0x000000e4),
-	DCD_ITEM(0x53fa852c, 0x00000004),
-	DCD_ITEM(0x53fa8530, 0x00000004),
-	DCD_ITEM(0x53fa85a0, 0x00000004),
-	DCD_ITEM(0x53fa85a4, 0x00000004),
-	DCD_ITEM(0x53fa85a8, 0x000000e4),
-	DCD_ITEM(0x53fa85ac, 0x000000e4),
-	DCD_ITEM(0x53fa85b0, 0x00000004),
-};
diff --git a/arch/arm/boards/tqma6x/board.c b/arch/arm/boards/tqma6x/board.c
index 30ebf34..6c574ea 100644
--- a/arch/arm/boards/tqma6x/board.c
+++ b/arch/arm/boards/tqma6x/board.c
@@ -98,34 +98,16 @@ static int tqma6x_enet_init(void)
 }
 fs_initcall(tqma6x_enet_init);
 
-extern char flash_header_tqma6dl_start[];
-extern char flash_header_tqma6dl_end[];
-
-extern char flash_header_tqma6q_start[];
-extern char flash_header_tqma6q_end[];
-
 static int tqma6x_env_init(void)
 {
-	void *flash_header_start;
-	void *flash_header_end;
-
-	if (of_machine_is_compatible("tq,tqma6s")) {
-		flash_header_start = (void *)flash_header_tqma6dl_start;
-		flash_header_end = (void *)flash_header_tqma6dl_end;
-	} else if (of_machine_is_compatible("tq,tqma6q")) {
-		flash_header_start = (void *)flash_header_tqma6q_start;
-		flash_header_end = (void *)flash_header_tqma6q_end;
-	} else {
+	if (!of_machine_is_compatible("tq,mba6x"))
 		return 0;
-	}
 
 	devfs_add_partition("m25p0", 0, SZ_512K, DEVFS_PARTITION_FIXED, "m25p0.barebox");
 
 	imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
-		BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_start,
-		flash_header_end - flash_header_start, 0);
-	imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc2.boot0",
-		0, (void *)flash_header_start, flash_header_end - flash_header_start, 0);
+		BBU_HANDLER_FLAG_DEFAULT);
+	imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc2.boot0", 0);
 
 	device_detect_by_name("mmc2");
 
diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c
index 308a0bd..c7cd5b8 100644
--- a/arch/arm/mach-imx/imx-bbu-internal.c
+++ b/arch/arm/mach-imx/imx-bbu-internal.c
@@ -40,9 +40,6 @@
 
 struct imx_internal_bbu_handler {
 	struct bbu_handler handler;
-	const void *dcd;
-	int dcdsize;
-	unsigned long app_dest;
 	unsigned long flash_header_offset;
 	size_t device_size;
 	unsigned long flags;
@@ -130,13 +127,7 @@ static int imx_bbu_internal_v1_update(struct bbu_handler *handler, struct bbu_da
 {
 	struct imx_internal_bbu_handler *imx_handler =
 		container_of(handler, struct imx_internal_bbu_handler, handler);
-	struct imx_flash_header *flash_header;
-	unsigned long flash_header_offset = imx_handler->flash_header_offset;
-	u32 *dcd_image_size;
-	void *imx_pre_image;
-	int imx_pre_image_size = 0x2000;
-	int ret, image_len;
-	void *buf;
+	int ret;
 
 	ret = imx_bbu_check_prereq(data);
 	if (ret)
@@ -144,38 +135,7 @@ static int imx_bbu_internal_v1_update(struct bbu_handler *handler, struct bbu_da
 
 	printf("updating to %s\n", data->devicefile);
 
-	imx_pre_image = xzalloc(imx_pre_image_size);
-	flash_header = imx_pre_image + flash_header_offset;
-
-	flash_header->app_code_jump_vector = imx_handler->app_dest + 0x1000;
-	flash_header->app_code_barker = APP_CODE_BARKER;
-	flash_header->app_code_csf = 0;
-	flash_header->dcd_ptr_ptr = imx_handler->app_dest + flash_header_offset +
-		offsetof(struct imx_flash_header, dcd);
-	flash_header->super_root_key = 0;
-	flash_header->dcd = imx_handler->app_dest + flash_header_offset +
-		offsetof(struct imx_flash_header, dcd_barker);
-	flash_header->app_dest = imx_handler->app_dest;
-	flash_header->dcd_barker = DCD_BARKER;
-	flash_header->dcd_block_len = imx_handler->dcdsize;
-
-	memcpy((void *)flash_header + sizeof(*flash_header), imx_handler->dcd, imx_handler->dcdsize);
-
-	dcd_image_size = (imx_pre_image + flash_header_offset + sizeof(*flash_header) + imx_handler->dcdsize);
-
-	*dcd_image_size = ALIGN(imx_pre_image_size + data->len, 4096);
-
-	/* Create a buffer containing header and image data */
-	image_len = data->len + imx_pre_image_size;
-	buf = xzalloc(image_len);
-	memcpy(buf, imx_pre_image, imx_pre_image_size);
-	memcpy(buf + imx_pre_image_size, data->image, data->len);
-
-	ret = imx_bbu_write_device(imx_handler, data, buf, image_len);
-
-	free(buf);
-
-	free(imx_pre_image);
+	ret = imx_bbu_write_device(imx_handler, data, data->image, data->len);
 
 	return ret;
 }
@@ -337,43 +297,6 @@ out:
 	return ret;
 }
 
-static void imx_bbu_internal_v2_init_flash_header(struct bbu_handler *handler, struct bbu_data *data,
-		void *imx_pre_image, int imx_pre_image_size)
-{
-	struct imx_internal_bbu_handler *imx_handler =
-		container_of(handler, struct imx_internal_bbu_handler, handler);
-	struct imx_flash_header_v2 *flash_header;
-	unsigned long flash_header_offset = imx_handler->flash_header_offset;
-
-	flash_header = imx_pre_image + flash_header_offset;
-
-	flash_header->header.tag = IVT_HEADER_TAG;
-	flash_header->header.length = cpu_to_be16(32);
-	flash_header->header.version = IVT_VERSION;
-
-	flash_header->entry = imx_handler->app_dest + imx_pre_image_size;
-	if (imx_handler->dcdsize)
-		flash_header->dcd_ptr = imx_handler->app_dest + flash_header_offset +
-			offsetof(struct imx_flash_header_v2, dcd);
-	flash_header->boot_data_ptr = imx_handler->app_dest +
-		flash_header_offset + offsetof(struct imx_flash_header_v2, boot_data);
-	flash_header->self = imx_handler->app_dest + flash_header_offset;
-
-	flash_header->boot_data.start = imx_handler->app_dest;
-	flash_header->boot_data.size = ALIGN(imx_pre_image_size +
-			data->len, 4096);
-
-	if (imx_handler->dcdsize) {
-		flash_header->dcd.header.tag = DCD_HEADER_TAG;
-		flash_header->dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) +
-				imx_handler->dcdsize);
-		flash_header->dcd.header.version = DCD_VERSION;
-	}
-
-	/* Add dcd data */
-	memcpy((void *)flash_header + sizeof(*flash_header), imx_handler->dcd, imx_handler->dcdsize);
-}
-
 #define IVT_BARKER		0x402000d1
 
 /*
@@ -391,84 +314,43 @@ static int imx_bbu_internal_v2_update(struct bbu_handler *handler, struct bbu_da
 	int imx_pre_image_size;
 	int ret, image_len;
 	void *buf;
+	uint32_t *barker;
 
 	ret = imx_bbu_check_prereq(data);
 	if (ret)
 		return ret;
 
-	if (imx_handler->dcd) {
-		imx_pre_image_size = 0x2000;
-	} else {
-		uint32_t *barker = data->image + imx_handler->flash_header_offset;
-
-		if (*barker != IVT_BARKER) {
-			printf("Board does not provide DCD data and this image is no imximage\n");
-			return -EINVAL;
-		}
+	barker = data->image + imx_handler->flash_header_offset;
 
-		imx_pre_image_size = 0;
+	if (*barker != IVT_BARKER) {
+		printf("Board does not provide DCD data and this image is no imximage\n");
+		return -EINVAL;
 	}
 
-	if (imx_handler->flags & IMX_INTERNAL_FLAG_NAND)
+	imx_pre_image_size = 0;
+
+	if (imx_handler->flags & IMX_INTERNAL_FLAG_NAND) {
 		/* NAND needs additional space for the DBBT */
 		imx_pre_image_size += 0x6000;
-
-	if (imx_pre_image_size)
 		imx_pre_image = xzalloc(imx_pre_image_size);
 
-	if (imx_handler->dcd)
-		imx_bbu_internal_v2_init_flash_header(handler, data, imx_pre_image, imx_pre_image_size);
-
-	/* Create a buffer containing header and image data */
-	image_len = data->len + imx_pre_image_size;
-	buf = xzalloc(image_len);
-	if (imx_pre_image_size)
+		/* Create a buffer containing header and image data */
+		image_len = data->len + imx_pre_image_size;
+		buf = xzalloc(image_len);
 		memcpy(buf, imx_pre_image, imx_pre_image_size);
-	memcpy(buf + imx_pre_image_size, data->image, data->len);
+		memcpy(buf + imx_pre_image_size, data->image, data->len);
 
-	if (imx_handler->flags & IMX_INTERNAL_FLAG_NAND) {
 		ret = imx_bbu_internal_v2_write_nand_dbbt(imx_handler, data, buf,
 				image_len);
-		goto out_free_buf;
+		free(buf);
+		free(imx_pre_image);
+	} else {
+		ret = imx_bbu_write_device(imx_handler, data, data->image, data->len);
 	}
 
-	ret = imx_bbu_write_device(imx_handler, data, buf, image_len);
-
-out_free_buf:
-	free(buf);
-
-	free(imx_pre_image);
 	return ret;
 }
 
-/*
- * On the i.MX53 the dcd data can contain several commands. Each of them must
- * have its length encoded into it. We can't express that during compile time,
- * so use this function if you are using multiple dcd commands and wish to
- * concatenate them together to a single dcd table with the correct sizes for
- * each command.
- */
-void *imx53_bbu_internal_concat_dcd_table(struct dcd_table *table, int num_entries)
-{
-	int i;
-	unsigned int dcdsize = 0, pos = 0;
-	void *dcdptr;
-
-	for (i = 0; i < num_entries; i++)
-		dcdsize += table[i].size;
-
-	dcdptr = xmalloc(dcdsize);
-
-	for (i = 0; i < num_entries; i++) {
-		u32 *current = dcdptr + pos;
-		memcpy(current, table[i].data, table[i].size);
-		*current |= cpu_to_be32(table[i].size << 8);
-		pos += table[i].size;
-	}
-
-	return dcdptr;
-}
-
 static struct imx_internal_bbu_handler *__init_handler(const char *name, char *devicefile,
 		unsigned long flags)
 {
@@ -499,87 +381,30 @@ static int __register_handler(struct imx_internal_bbu_handler *imx_handler)
  * Register a i.MX51 internal boot update handler for MMC/SD
  */
 int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
-		unsigned long flags, struct imx_dcd_entry *dcd, int dcdsize,
-		unsigned long app_dest)
+		unsigned long flags)
 {
 	struct imx_internal_bbu_handler *imx_handler;
 
 	imx_handler = __init_handler(name, devicefile, flags);
-	imx_handler->dcd = dcd;
-	imx_handler->dcdsize = dcdsize;
 	imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
 
-	if (app_dest)
-		imx_handler->app_dest = app_dest;
-	else
-		imx_handler->app_dest = 0x90000000;
-
 	imx_handler->flags = IMX_INTERNAL_FLAG_KEEP_DOSPART;
 	imx_handler->handler.handler = imx_bbu_internal_v1_update;
 
 	return __register_handler(imx_handler);
 }
 
-#define DCD_WR_CMD(len)		cpu_to_be32(0xcc << 24 | (((len) & 0xffff) << 8) | 0x04)
-
-static int imx53_bbu_internal_init_dcd(struct imx_internal_bbu_handler *imx_handler,
-		void *dcd, int dcdsize)
-{
-	uint32_t *dcd32 = dcd;
-
-	/*
-	 * For boards which do not have a dcd (i.e. they do their SDRAM
-	 * setup in C code)
-	 */
-	if (!dcd || !dcdsize)
-		return 0;
-
-	/*
-	 * The DCD data we have compiled in does not have a DCD_WR_CMD at
-	 * the beginning. Instead it is contained in struct imx_flash_header_v2.
-	 * This is necessary to generate the DCD size at compile time. If
-	 * we are passed such a DCD data here, prepend a DCD_WR_CMD.
-	 */
-	if ((*dcd32 & 0xff0000ff) != DCD_WR_CMD(0)) {
-		__be32 *buf;
-
-		debug("%s: dcd does not have a DCD_WR_CMD. Prepending one\n", __func__);
-
-		buf = xmalloc(dcdsize + sizeof(__be32));
-
-		*buf = DCD_WR_CMD(dcdsize + sizeof(__be32));
-		memcpy(&buf[1], dcd, dcdsize);
-
-		imx_handler->dcd = buf;
-		imx_handler->dcdsize = dcdsize + sizeof(__be32);
-	} else {
-		debug("%s: dcd already has a DCD_WR_CMD. Using original dcd data\n", __func__);
-
-		imx_handler->dcd = dcd;
-		imx_handler->dcdsize = dcdsize;
-	}
-
-	return 0;
-}
-
 /*
  * Register a i.MX53 internal boot update handler for MMC/SD
  */
 int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
-		unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
-		unsigned long app_dest)
+		unsigned long flags)
 {
 	struct imx_internal_bbu_handler *imx_handler;
 
 	imx_handler = __init_handler(name, devicefile, flags);
-	imx53_bbu_internal_init_dcd(imx_handler, dcd, dcdsize);
 	imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
 
-	if (app_dest)
-		imx_handler->app_dest = app_dest;
-	else
-		imx_handler->app_dest = 0x70000000;
-
 	imx_handler->flags = IMX_INTERNAL_FLAG_KEEP_DOSPART;
 	imx_handler->handler.handler = imx_bbu_internal_v2_update;
 
@@ -592,20 +417,13 @@ int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
  * keep a partition table. We have to erase the device beforehand though.
  */
 int imx53_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
-		unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
-		unsigned long app_dest)
+		unsigned long flags)
 {
 	struct imx_internal_bbu_handler *imx_handler;
 
 	imx_handler = __init_handler(name, devicefile, flags);
-	imx53_bbu_internal_init_dcd(imx_handler, dcd, dcdsize);
 	imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
 
-	if (app_dest)
-		imx_handler->app_dest = app_dest;
-	else
-		imx_handler->app_dest = 0x70000000;
-
 	imx_handler->flags = IMX_INTERNAL_FLAG_ERASE;
 	imx_handler->handler.handler = imx_bbu_internal_v2_update;
 
@@ -616,20 +434,13 @@ int imx53_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefi
  * Register a i.MX53 internal boot update handler for NAND
  */
 int imx53_bbu_internal_nand_register_handler(const char *name,
-		unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
-		int partition_size, unsigned long app_dest)
+		unsigned long flags, int partition_size)
 {
 	struct imx_internal_bbu_handler *imx_handler;
 
 	imx_handler = __init_handler(name, NULL, flags);
-	imx53_bbu_internal_init_dcd(imx_handler, dcd, dcdsize);
 	imx_handler->flash_header_offset = 0x400;
 
-	if (app_dest)
-		imx_handler->app_dest = app_dest;
-	else
-		imx_handler->app_dest = 0x70000000;
-
 	imx_handler->handler.handler = imx_bbu_internal_v2_update;
 	imx_handler->flags = IMX_INTERNAL_FLAG_NAND;
 	imx_handler->handler.devicefile = "/dev/nand0";
@@ -642,14 +453,17 @@ int imx53_bbu_internal_nand_register_handler(const char *name,
  * Register a i.MX6 internal boot update handler for MMC/SD
  */
 int imx6_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
-		unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
-		unsigned long app_dest)
+		unsigned long flags)
 {
-	if (!app_dest)
-		app_dest = 0x10000000;
+	struct imx_internal_bbu_handler *imx_handler;
+
+	imx_handler = __init_handler(name, devicefile, flags);
+	imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
+
+	imx_handler->flags = IMX_INTERNAL_FLAG_KEEP_DOSPART;
+	imx_handler->handler.handler = imx_bbu_internal_v2_update;
 
-	return imx53_bbu_internal_mmc_register_handler(name, devicefile,
-		flags, dcd, dcdsize, app_dest);
+	return __register_handler(imx_handler);
 }
 
 /*
@@ -658,12 +472,15 @@ int imx6_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
  * keep a partition table. We have to erase the device beforehand though.
  */
 int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
-		unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
-		unsigned long app_dest)
+		unsigned long flags)
 {
-	if (!app_dest)
-		app_dest = 0x10000000;
+	struct imx_internal_bbu_handler *imx_handler;
+
+	imx_handler = __init_handler(name, devicefile, flags);
+	imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
 
-	return imx53_bbu_internal_spi_i2c_register_handler(name, devicefile,
-		flags, dcd, dcdsize, app_dest);
+	imx_handler->flags = IMX_INTERNAL_FLAG_ERASE;
+	imx_handler->handler.handler = imx_bbu_internal_v2_update;
+
+	return __register_handler(imx_handler);
 }
diff --git a/arch/arm/mach-imx/include/mach/bbu.h b/arch/arm/mach-imx/include/mach/bbu.h
index 1644d85..bf6c7dc 100644
--- a/arch/arm/mach-imx/include/mach/bbu.h
+++ b/arch/arm/mach-imx/include/mach/bbu.h
@@ -10,71 +10,59 @@ struct imx_dcd_v2_entry;
 #ifdef CONFIG_BAREBOX_UPDATE
 
 int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
-		unsigned long flags, struct imx_dcd_entry *, int dcdsize,
-		unsigned long app_dest);
+		unsigned long flags);
 
 int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
-		unsigned long flags, struct imx_dcd_v2_entry *, int dcdsize,
-		unsigned long app_dest);
+		unsigned long flags);
 
 int imx53_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
-		unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
-		unsigned long app_dest);
+		unsigned long flags);
 
 int imx53_bbu_internal_nand_register_handler(const char *name,
-		unsigned long flags, struct imx_dcd_v2_entry *, int dcdsize,
-		int partition_size, unsigned long app_dest);
+		unsigned long flags, int partition_size);
 
 int imx6_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
-		unsigned long flags, struct imx_dcd_v2_entry *, int dcdsize,
-		unsigned long app_dest);
+		unsigned long flags);
 
 int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
-		unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
-		unsigned long app_dest);
+		unsigned long flags);
 
 int imx6_bbu_nand_register_handler(const char *name, unsigned long flags);
 
 #else
 
 static inline int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
-		unsigned long flags, struct imx_dcd_entry *dcd, int dcdsize,
-		unsigned long app_dest)
+		unsigned long flags)
 {
 	return -ENOSYS;
 }
 
 static inline int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
-		unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
-		unsigned long app_dest)
+		unsigned long flags)
 {
 	return -ENOSYS;
 }
 
 static inline int imx53_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
-		unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
-		unsigned long app_dest)
+		unsigned long flags)
 {
 	return -ENOSYS;
 }
 
 static inline int imx53_bbu_internal_nand_register_handler(const char *name,
-		unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
-		int partition_size, unsigned long app_dest)
+		unsigned long flags, int partition_size)
 {
 	return -ENOSYS;
 }
 
 static inline int imx6_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
-		unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
-		unsigned long app_dest)
+		unsigned long flags)
 {
 	return -ENOSYS;
 }
 
 static inline int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
-		unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
-		unsigned long app_dest)
+		unsigned long flags)
 {
 	return -ENOSYS;
 }
@@ -96,11 +84,4 @@ static inline int imx_bbu_external_nand_register_handler(const char *name, char
 }
 #endif
 
-struct dcd_table {
-	void *data;
-	unsigned int size;
-};
-
-void *imx53_bbu_internal_concat_dcd_table(struct dcd_table *table, int num_entries);
-
 #endif
-- 
2.0.0.rc0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 03/14] ARM: tqma53: Add barebox_update support

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/tqma53/board.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boards/tqma53/board.c b/arch/arm/boards/tqma53/board.c
index 958e5ad..8f8a6a4 100644
--- a/arch/arm/boards/tqma53/board.c
+++ b/arch/arm/boards/tqma53/board.c
@@ -20,10 +20,12 @@
 
 #include <asm/armlinux.h>
 #include <generated/mach-types.h>
+#include <mach/bbu.h>
 
 static int tqma53_devices_init(void)
 {
-	char *of_env_path = "/chosen/environment-emmc";
+	char *of_env_path;
+	unsigned bbu_flag_emmc = 0, bbu_flag_sd = 0;
 
 	if (!of_machine_is_compatible("tq,tqma53"))
 		return 0;
@@ -32,8 +34,16 @@ static int tqma53_devices_init(void)
 	barebox_set_hostname("tqma53");
 
 	if (bootsource_get() == BOOTSOURCE_MMC &&
-			bootsource_get_instance() == 1)
+			bootsource_get_instance() == 1) {
 		of_env_path = "/chosen/environment-sd";
+		bbu_flag_sd = BBU_HANDLER_FLAG_DEFAULT;
+	} else {
+		of_env_path = "/chosen/environment-emmc";
+		bbu_flag_emmc = BBU_HANDLER_FLAG_DEFAULT;
+	}
+
+	imx53_bbu_internal_mmc_register_handler("sd", "/dev/mmc1", bbu_flag_sd);
+	imx53_bbu_internal_mmc_register_handler("emmc", "/dev/mmc2", bbu_flag_emmc);
 
 	of_device_enable_path(of_env_path);
 
-- 
2.0.0.rc0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 04/14] ARM: i.MX53: Use clock number defines from dt-bindings

[Sascha Hauer]

i.MX5 has clock number defines in dt-bindings, use them rather
then manually keeping the clock enums in sync.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/clk-imx5.c | 176 ++++++++++++++++++++-----------------------
 1 file changed, 82 insertions(+), 94 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c
index f389653..9d536bc 100644
--- a/arch/arm/mach-imx/clk-imx5.c
+++ b/arch/arm/mach-imx/clk-imx5.c
@@ -16,6 +16,7 @@
 #include <linux/err.h>
 #include <mach/imx51-regs.h>
 #include <mach/imx53-regs.h>
+#include <dt-bindings/clock/imx5-clock.h>
 
 #include "clk.h"
 
@@ -57,20 +58,7 @@
 
 #define CCM_CMEOR	0x84
 
-enum imx5_clks {
-	dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
-	uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
-	emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
-	usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, lp_apm,
-	periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
-	tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
-	esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel,
-	gpc_dvfs, pll1_sw, pll2_sw,
-	pll3_sw, pll4_sw, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
-	clk_max
-};
-
-static struct clk *clks[clk_max];
+static struct clk *clks[IMX5_CLK_END];
 
 /* This is used multiple times */
 static const char *standard_pll_sel[] = {
@@ -138,89 +126,89 @@ static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate
 	writel(0xffffffff, base + CCM_CCGR6);
 	writel(0xffffffff, base + CCM_CCGR7);
 
-	clks[dummy] = clk_fixed("dummy", 0);
-	clks[ckil] = clk_fixed("ckil", rate_ckil);
-	clks[osc] = clk_fixed("osc", rate_osc);
-	clks[ckih1] = clk_fixed("ckih1", rate_ckih1);
-	clks[ckih2] = clk_fixed("ckih2", rate_ckih2);
+	clks[IMX5_CLK_DUMMY] = clk_fixed("dummy", 0);
+	clks[IMX5_CLK_CKIL] = clk_fixed("ckil", rate_ckil);
+	clks[IMX5_CLK_OSC] = clk_fixed("osc", rate_osc);
+	clks[IMX5_CLK_CKIH1] = clk_fixed("ckih1", rate_ckih1);
+	clks[IMX5_CLK_CKIH2] = clk_fixed("ckih2", rate_ckih2);
 
-	clks[lp_apm] = imx_clk_mux("lp_apm", base + CCM_CCSR, 9, 1,
+	clks[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", base + CCM_CCSR, 9, 1,
 				lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
-	clks[periph_apm] = imx_clk_mux("periph_apm", base + CCM_CBCMR, 12, 2,
+	clks[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", base + CCM_CBCMR, 12, 2,
 				periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
-	clks[main_bus] = imx_clk_mux("main_bus", base + CCM_CBCDR, 25, 1,
+	clks[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", base + CCM_CBCDR, 25, 1,
 				main_bus_sel, ARRAY_SIZE(main_bus_sel));
-	clks[per_lp_apm] = imx_clk_mux("per_lp_apm", base + CCM_CBCMR, 1, 1,
+	clks[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", base + CCM_CBCMR, 1, 1,
 				per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
-	clks[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", base + CCM_CBCDR, 6, 2);
-	clks[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", base + CCM_CBCDR, 3, 3);
-	clks[per_podf] = imx_clk_divider("per_podf", "per_pred2", base + CCM_CBCDR, 0, 3);
-	clks[per_root] = imx_clk_mux("per_root", base + CCM_CBCMR, 0, 1,
+	clks[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", base + CCM_CBCDR, 6, 2);
+	clks[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", base + CCM_CBCDR, 3, 3);
+	clks[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", base + CCM_CBCDR, 0, 3);
+	clks[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", base + CCM_CBCMR, 0, 1,
 				per_root_sel, ARRAY_SIZE(per_root_sel));
-	clks[ahb] = imx_clk_divider("ahb", "main_bus", base + CCM_CBCDR, 10, 3);
-	clks[ipg] = imx_clk_divider("ipg", "ahb", base + CCM_CBCDR, 8, 2);
-	clks[axi_a] = imx_clk_divider("axi_a", "main_bus", base + CCM_CBCDR, 16, 3);
-	clks[axi_b] = imx_clk_divider("axi_b", "main_bus", base + CCM_CBCDR, 19, 3);
-	clks[uart_sel] = imx_clk_mux("uart_sel", base + CCM_CSCMR1, 24, 2,
+	clks[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", base + CCM_CBCDR, 10, 3);
+	clks[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + CCM_CBCDR, 8, 2);
+	clks[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", base + CCM_CBCDR, 16, 3);
+	clks[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", base + CCM_CBCDR, 19, 3);
+	clks[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + CCM_CSCMR1, 24, 2,
 				standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-	clks[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", base + CCM_CSCDR1, 3, 3);
-	clks[uart_root] = imx_clk_divider("uart_root", "uart_pred", base + CCM_CSCDR1, 0, 3);
+	clks[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", base + CCM_CSCDR1, 3, 3);
+	clks[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", base + CCM_CSCDR1, 0, 3);
 
-	clks[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", base + CCM_CSCMR1, 20, 2,
+	clks[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", base + CCM_CSCMR1, 20, 2,
 				standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-	clks[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", base + CCM_CSCMR1, 16, 2,
+	clks[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", base + CCM_CSCMR1, 16, 2,
 				standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-	clks[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", base + CCM_CSCDR1, 16, 3);
-	clks[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", base + CCM_CSCDR1, 11, 3);
-	clks[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", base + CCM_CSCDR1, 22, 3);
-	clks[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", base + CCM_CSCDR1, 19, 3);
-	clks[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", base + CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
-	clks[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", base + CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
-
-	clks[emi_sel] = imx_clk_mux("emi_sel", base + CCM_CBCDR, 26, 1,
+	clks[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", base + CCM_CSCDR1, 16, 3);
+	clks[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", base + CCM_CSCDR1, 11, 3);
+	clks[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", base + CCM_CSCDR1, 22, 3);
+	clks[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", base + CCM_CSCDR1, 19, 3);
+	clks[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", base + CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
+	clks[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", base + CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
+
+	clks[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", base + CCM_CBCDR, 26, 1,
 				emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
-	clks[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", base + CCM_CBCDR, 22, 3);
-	clks[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", base + CCM_CBCDR, 13, 3);
-	clks[ecspi_sel] = imx_clk_mux("ecspi_sel", base + CCM_CSCMR1, 4, 2,
+	clks[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", base + CCM_CBCDR, 22, 3);
+	clks[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", base + CCM_CBCDR, 13, 3);
+	clks[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + CCM_CSCMR1, 4, 2,
 				standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-	clks[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", base + CCM_CSCDR2, 25, 3);
-	clks[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", base + CCM_CSCDR2, 19, 6);
-	clks[usboh3_sel] = imx_clk_mux("usboh3_sel", base + CCM_CSCMR1, 22, 2,
+	clks[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", base + CCM_CSCDR2, 25, 3);
+	clks[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", base + CCM_CSCDR2, 19, 6);
+	clks[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", base + CCM_CSCMR1, 22, 2,
 				standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-	clks[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", base + CCM_CSCDR1, 8, 3);
-	clks[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", base + CCM_CSCDR1, 6, 2);
-	clks[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", base + CCM_CDCDR, 3, 3);
-	clks[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", base + CCM_CDCDR, 0, 3);
-	clks[usb_phy_sel] = imx_clk_mux("usb_phy_sel", base + CCM_CSCMR1, 26, 1,
+	clks[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", base + CCM_CSCDR1, 8, 3);
+	clks[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", base + CCM_CSCDR1, 6, 2);
+	clks[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", base + CCM_CDCDR, 3, 3);
+	clks[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", base + CCM_CDCDR, 0, 3);
+	clks[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", base + CCM_CSCMR1, 26, 1,
 				usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
-	clks[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", base + CCM_CACRR, 0, 3);
+	clks[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "pll1_sw", base + CCM_CACRR, 0, 3);
 }
 
 #ifdef CONFIG_ARCH_IMX51
 int __init mx51_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
 			unsigned long rate_ckih1, unsigned long rate_ckih2)
 {
-	clks[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX51_PLL1_BASE_ADDR);
-	clks[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX51_PLL2_BASE_ADDR);
-	clks[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX51_PLL3_BASE_ADDR);
+	clks[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX51_PLL1_BASE_ADDR);
+	clks[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX51_PLL2_BASE_ADDR);
+	clks[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX51_PLL3_BASE_ADDR);
 
 	mx5_clocks_common_init(regs, rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
 
-	clkdev_add_physbase(clks[uart_root], MX51_UART1_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[uart_root], MX51_UART2_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[uart_root], MX51_UART3_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[per_root], MX51_I2C1_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[per_root], MX51_I2C2_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[per_root], MX51_GPT1_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[ipg], MX51_CSPI_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[ecspi_podf], MX51_ECSPI1_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[ecspi_podf], MX51_ECSPI2_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[ipg], MX51_MXC_FEC_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[esdhc_a_podf], MX51_MMC_SDHC1_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[esdhc_b_podf], MX51_MMC_SDHC2_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[esdhc_c_s], MX51_MMC_SDHC3_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[esdhc_d_s], MX51_MMC_SDHC4_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[ipg], MX51_ATA_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX51_UART1_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX51_UART2_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX51_UART3_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_I2C1_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_I2C2_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_GPT1_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_IPG], MX51_CSPI_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_ECSPI_PODF], MX51_ECSPI1_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_ECSPI_PODF], MX51_ECSPI2_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_IPG], MX51_MXC_FEC_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_ESDHC_A_PODF], MX51_MMC_SDHC1_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_ESDHC_B_PODF], MX51_MMC_SDHC2_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_ESDHC_C_SEL], MX51_MMC_SDHC3_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_ESDHC_D_SEL], MX51_MMC_SDHC4_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_IPG], MX51_ATA_BASE_ADDR, NULL);
 
 	return 0;
 }
@@ -261,29 +249,29 @@ core_initcall(imx51_ccm_init);
 int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
 			unsigned long rate_ckih1, unsigned long rate_ckih2)
 {
-	clks[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX53_PLL1_BASE_ADDR);
-	clks[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX53_PLL2_BASE_ADDR);
-	clks[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX53_PLL3_BASE_ADDR);
-	clks[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", (void *)MX53_PLL4_BASE_ADDR);
+	clks[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX53_PLL1_BASE_ADDR);
+	clks[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX53_PLL2_BASE_ADDR);
+	clks[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX53_PLL3_BASE_ADDR);
+	clks[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", (void *)MX53_PLL4_BASE_ADDR);
 
 	mx5_clocks_common_init(regs, rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
 
-	clkdev_add_physbase(clks[uart_root], MX53_UART1_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[uart_root], MX53_UART2_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[uart_root], MX53_UART3_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[per_root], MX53_I2C1_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[per_root], MX53_I2C2_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[per_root], MX53_I2C3_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[per_root], MX53_GPT1_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[ipg], MX53_CSPI_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[ecspi_podf], MX53_ECSPI1_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[ecspi_podf], MX53_ECSPI2_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[ipg], MX53_FEC_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[esdhc_a_podf], MX53_ESDHC1_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[esdhc_c_s], MX53_ESDHC2_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[esdhc_b_podf], MX53_ESDHC3_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[esdhc_d_s], MX53_ESDHC4_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[ahb], MX53_SATA_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART1_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART2_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART3_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_I2C1_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_I2C2_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_I2C3_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_GPT1_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_IPG], MX53_CSPI_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_ECSPI_PODF], MX53_ECSPI1_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_ECSPI_PODF], MX53_ECSPI2_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_IPG], MX53_FEC_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_ESDHC_A_PODF], MX53_ESDHC1_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_ESDHC_C_SEL], MX53_ESDHC2_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_ESDHC_B_PODF], MX53_ESDHC3_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_ESDHC_D_SEL], MX53_ESDHC4_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_AHB], MX53_SATA_BASE_ADDR, NULL);
 
 	return 0;
 }
-- 
2.0.0.rc0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 05/14] ARM: tqma53: Add phy_type property to usb ports

[Sascha Hauer]

The barebox chipidea driver needs this.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/dts/imx53-mba53.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/imx53-mba53.dts b/arch/arm/dts/imx53-mba53.dts
index 9ba5dae..c908c61 100644
--- a/arch/arm/dts/imx53-mba53.dts
+++ b/arch/arm/dts/imx53-mba53.dts
@@ -33,3 +33,11 @@
 		reg = <0x80000 0x80000>;
 	};
 };
+
+&usbh1 {
+	phy_type = "utmi";
+};
+
+&usbotg {
+	phy_type = "utmi";
+};
-- 
2.0.0.rc0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 06/14] ARM: i.MX53: Add pwm support

[Sascha Hauer]

Aliases and clocks are needed to support the i.MX53 PWMs.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/dts/imx53.dtsi      | 7 +++++++
 arch/arm/mach-imx/clk-imx5.c | 4 ++++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi
index 9a766da..bc68012 100644
--- a/arch/arm/dts/imx53.dtsi
+++ b/arch/arm/dts/imx53.dtsi
@@ -1 +1,8 @@
 #include <arm/imx53.dtsi>
+
+/ {
+	aliases {
+		pwm0 = &pwm1;
+		pwm1 = &pwm2;
+	};
+};
diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c
index 9d536bc..8146359 100644
--- a/arch/arm/mach-imx/clk-imx5.c
+++ b/arch/arm/mach-imx/clk-imx5.c
@@ -209,6 +209,8 @@ int __init mx51_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigne
 	clkdev_add_physbase(clks[IMX5_CLK_ESDHC_C_SEL], MX51_MMC_SDHC3_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[IMX5_CLK_ESDHC_D_SEL], MX51_MMC_SDHC4_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[IMX5_CLK_IPG], MX51_ATA_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM1_BASE_ADDR, "per");
+	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM2_BASE_ADDR, "per");
 
 	return 0;
 }
@@ -272,6 +274,8 @@ int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigne
 	clkdev_add_physbase(clks[IMX5_CLK_ESDHC_B_PODF], MX53_ESDHC3_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[IMX5_CLK_ESDHC_D_SEL], MX53_ESDHC4_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[IMX5_CLK_AHB], MX53_SATA_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM1_BASE_ADDR, "per");
+	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM2_BASE_ADDR, "per");
 
 	return 0;
 }
-- 
2.0.0.rc0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 07/14] ARM: i.MX53 tqma53: Set model from devicetree

[Sascha Hauer]

The model is correctly set from the devicetree, no need to do it
from code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/tqma53/board.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/boards/tqma53/board.c b/arch/arm/boards/tqma53/board.c
index 8f8a6a4..055ceeb 100644
--- a/arch/arm/boards/tqma53/board.c
+++ b/arch/arm/boards/tqma53/board.c
@@ -30,7 +30,6 @@ static int tqma53_devices_init(void)
 	if (!of_machine_is_compatible("tq,tqma53"))
 		return 0;
 
-	barebox_set_model("TQ tqma53");
 	barebox_set_hostname("tqma53");
 
 	if (bootsource_get() == BOOTSOURCE_MMC &&
-- 
2.0.0.rc0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 08/14] ARM: i.MX: implement pllv2 set/round_rate support

[Sascha Hauer]

Code straight from the kernel.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/clk-pllv2.c | 66 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c
index 7e087c1..a2b016f 100644
--- a/arch/arm/mach-imx/clk-pllv2.c
+++ b/arch/arm/mach-imx/clk-pllv2.c
@@ -136,8 +136,74 @@ static unsigned long clk_pllv2_recalc_rate(struct clk *clk,
 	return __clk_pllv2_recalc_rate(parent_rate, dp_ctl, dp_op, dp_mfd, dp_mfn);
 }
 
+static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate,
+		u32 *dp_op, u32 *dp_mfd, u32 *dp_mfn)
+{
+	u32 reg;
+	long mfi, pdf, mfn, mfd = 999999;
+	u64 temp64;
+	unsigned long quad_parent_rate;
+
+	quad_parent_rate = 4 * parent_rate;
+	pdf = mfi = -1;
+	while (++pdf < 16 && mfi < 5)
+		mfi = rate * (pdf+1) / quad_parent_rate;
+	if (mfi > 15)
+		return -EINVAL;
+	pdf--;
+
+	temp64 = rate * (pdf + 1) - quad_parent_rate * mfi;
+	do_div(temp64, quad_parent_rate / 1000000);
+	mfn = (long)temp64;
+
+	reg = mfi << 4 | pdf;
+
+	*dp_op = reg;
+	*dp_mfd = mfd;
+	*dp_mfn = mfn;
+
+	return 0;
+}
+
+static int clk_pllv2_set_rate(struct clk *clk, unsigned long rate,
+		unsigned long parent_rate)
+{
+	struct clk_pllv2 *pll = container_of(clk, struct clk_pllv2, clk);
+	void __iomem *pllbase;
+	u32 dp_ctl, dp_op, dp_mfd, dp_mfn;
+	int ret;
+
+	pllbase = pll->reg;
+
+	ret = __clk_pllv2_set_rate(rate, parent_rate, &dp_op, &dp_mfd, &dp_mfn);
+	if (ret)
+		return ret;
+
+	dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+	/* use dpdck0_2 */
+	__raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
+
+	__raw_writel(dp_op, pllbase + MXC_PLL_DP_OP);
+	__raw_writel(dp_mfd, pllbase + MXC_PLL_DP_MFD);
+	__raw_writel(dp_mfn, pllbase + MXC_PLL_DP_MFN);
+
+	return 0;
+}
+
+static long clk_pllv2_round_rate(struct clk *clk, unsigned long rate,
+		unsigned long *prate)
+{
+	u32 dp_op, dp_mfd, dp_mfn;
+
+	__clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn);
+	return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN,
+			dp_op, dp_mfd, dp_mfn);
+}
+
 struct clk_ops clk_pllv2_ops = {
 	.recalc_rate = clk_pllv2_recalc_rate,
+	.round_rate = clk_pllv2_round_rate,
+	.set_rate = clk_pllv2_set_rate,
 };
 
 struct clk *imx_clk_pllv2(const char *name, const char *parent,
-- 
2.0.0.rc0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 09/14] video: i.MX IPUv3: remove debug leftover

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/video/imx-ipu-v3/imx-ldb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/imx-ipu-v3/imx-ldb.c b/drivers/video/imx-ipu-v3/imx-ldb.c
index 7367fbe..bbdbe40 100644
--- a/drivers/video/imx-ipu-v3/imx-ldb.c
+++ b/drivers/video/imx-ipu-v3/imx-ldb.c
@@ -178,7 +178,7 @@ static int imx6q_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di)
 		dev_err(ldb->dev, "failed to set display clock parent: %s\n", strerror(-ret));
 		return ret;
 	}
-printk("%s: %d\n", __func__, di);
+
 	val = readl(gpr3);
 	shift = (imx_ldb_ch->chno == 0) ? 6 : 8;
 	val &= ~(3 << shift);
-- 
2.0.0.rc0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 10/14] video: i.MX IPUv3: Print error as string

[Sascha Hauer]

And add a missing newline.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/video/imx-ipu-v3/ipu-common.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/video/imx-ipu-v3/ipu-common.c b/drivers/video/imx-ipu-v3/ipu-common.c
index ffd6ec1..5f3b0bb 100644
--- a/drivers/video/imx-ipu-v3/ipu-common.c
+++ b/drivers/video/imx-ipu-v3/ipu-common.c
@@ -774,7 +774,7 @@ static int ipu_probe(struct device_d *dev)
 	ipu->clk = clk_get(dev, "bus");
 	if (IS_ERR(ipu->clk)) {
 		ret = PTR_ERR(ipu->clk);
-		dev_err(dev, "clk_get failed with %d", ret);
+		dev_err(dev, "clk_get failed: %s\n", strerror(-ret));
 		return ret;
 	}
 
@@ -788,7 +788,7 @@ static int ipu_probe(struct device_d *dev)
 
 	ret = devtype->reset(ipu);
 	if (ret) {
-		dev_err(dev, "failed to reset: %d\n", ret);
+		dev_err(dev, "failed to reset: %s\n", strerror(-ret));
 		goto out_failed_reset;
 	}
 
-- 
2.0.0.rc0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 11/14] video: i.MX IPUv3: Implement i.MX5 IPU reset support

[Sascha Hauer]

Needed to make the IPU driver work on i.MX5

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/video/imx-ipu-v3/ipu-common.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/video/imx-ipu-v3/ipu-common.c b/drivers/video/imx-ipu-v3/ipu-common.c
index 5f3b0bb..c602363 100644
--- a/drivers/video/imx-ipu-v3/ipu-common.c
+++ b/drivers/video/imx-ipu-v3/ipu-common.c
@@ -22,6 +22,8 @@
 #include <asm/mmu.h>
 #include <mach/generic.h>
 #include <mach/imx6-regs.h>
+#include <mach/imx53-regs.h>
+#include <mach/imx51-regs.h>
 
 #include "imx-ipu-v3.h"
 #include "ipu-prv.h"
@@ -529,6 +531,31 @@ static int imx6_ipu_reset(struct ipu_soc *ipu)
 
 }
 
+static int imx5_ipu_reset(void __iomem *src_base)
+{
+	uint32_t val;
+	int ret;
+
+	val = ipureadl(src_base);
+	val |= (1 << 3);
+	ipuwritel("reset", val, src_base);
+
+	ret = wait_on_timeout(100 * MSECOND, !(readl(src_base) & (1 << 3)));
+
+	return ret;
+
+}
+
+static int imx51_ipu_reset(struct ipu_soc *ipu)
+{
+	return imx5_ipu_reset((void *)MX51_SRC_BASE_ADDR);
+}
+
+static int imx53_ipu_reset(struct ipu_soc *ipu)
+{
+	return imx5_ipu_reset((void *)MX53_SRC_BASE_ADDR);
+}
+
 struct ipu_devtype {
 	const char *name;
 	unsigned long cm_ofs;
@@ -554,6 +581,7 @@ static struct ipu_devtype ipu_type_imx51 = {
 	.dc_tmpl_ofs = 0x1f080000,
 	.vdi_ofs = 0x1e068000,
 	.type = IPUV3EX,
+	.reset = imx51_ipu_reset,
 };
 
 static struct ipu_devtype ipu_type_imx53 = {
@@ -567,6 +595,7 @@ static struct ipu_devtype ipu_type_imx53 = {
 	.dc_tmpl_ofs = 0x07080000,
 	.vdi_ofs = 0x06068000,
 	.type = IPUV3M,
+	.reset = imx53_ipu_reset,
 };
 
 static struct ipu_devtype ipu_type_imx6q = {
-- 
2.0.0.rc0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 12/14] video: i.MX IPUv3 ldb: implement i.MX53 support

[Sascha Hauer]

Configure the clock path correctly for i.MX53.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/video/imx-ipu-v3/imx-ldb.c | 31 ++++++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/video/imx-ipu-v3/imx-ldb.c b/drivers/video/imx-ipu-v3/imx-ldb.c
index bbdbe40..70429eb 100644
--- a/drivers/video/imx-ipu-v3/imx-ldb.c
+++ b/drivers/video/imx-ipu-v3/imx-ldb.c
@@ -190,7 +190,36 @@ static int imx6q_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di)
 
 static int imx53_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di)
 {
-	return -ENOSYS;
+	struct clk *diclk, *ldbclk;
+	struct imx_ldb *ldb = imx_ldb_ch->ldb;
+	int ret, dino;
+	char *clkname;
+
+	dino = di & 0x1;
+
+	clkname = asprintf("ipu_di%d_sel", dino);
+	diclk = clk_lookup(clkname);
+	free(clkname);
+	if (IS_ERR(diclk)) {
+		dev_err(ldb->dev, "failed to get di clk: %s\n", strerror(PTR_ERR(diclk)));
+		return PTR_ERR(diclk);
+	}
+
+	clkname = asprintf("ldb_di%d_div", imx_ldb_ch->chno);
+	ldbclk = clk_lookup(clkname);
+	free(clkname);
+	if (IS_ERR(ldbclk)) {
+		dev_err(ldb->dev, "failed to get ldb clk: %s\n", strerror(PTR_ERR(ldbclk)));
+		return PTR_ERR(ldbclk);
+	}
+
+	ret = clk_set_parent(diclk, ldbclk);
+	if (ret) {
+		dev_err(ldb->dev, "failed to set display clock parent: %s\n", strerror(-ret));
+		return ret;
+	}
+
+	return 0;
 }
 
 static struct imx_ldb_data imx_ldb_data_imx6q = {
-- 
2.0.0.rc0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 13/14] ARM: i.MX5: Add IPU clocks

[Sascha Hauer]

Add the clocks for the IPU on i.MX5. Since these are many only
add them when the driver is enabled.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/clk-imx5.c                | 121 ++++++++++++++++++++++++++++
 arch/arm/mach-imx/include/mach/imx51-regs.h |   2 +
 arch/arm/mach-imx/include/mach/imx53-regs.h |   1 +
 3 files changed, 124 insertions(+)

diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c
index 8146359..1fc028c 100644
--- a/arch/arm/mach-imx/clk-imx5.c
+++ b/arch/arm/mach-imx/clk-imx5.c
@@ -113,6 +113,71 @@ static const char *usb_phy_sel_str[] = {
 	"usb_phy_podf",
 };
 
+static const char *mx51_ipu_di0_sel[] = {
+	"di_pred",
+	"osc",
+	"ckih1",
+	"tve_di",
+};
+
+static const char *mx53_ipu_di0_sel[] = {
+	"di_pred",
+	"osc",
+	"ckih1",
+	"di_pll4_podf",
+	"dummy",
+	"ldb_di0_div",
+};
+
+static const char *mx53_ldb_di0_sel[] = {
+	"pll3_sw",
+	"pll4_sw",
+};
+
+static const char *mx51_ipu_di1_sel[] = {
+	"di_pred",
+	"osc",
+	"ckih1",
+	"tve_di",
+	"ipp_di1",
+};
+
+static const char *mx53_ipu_di1_sel[] = {
+	"di_pred",
+	"osc",
+	"ckih1",
+	"tve_di",
+	"ipp_di1",
+	"ldb_di1_div",
+};
+
+static const char *mx53_ldb_di1_sel[] = {
+	"pll3_sw",
+	"pll4_sw",
+};
+
+static const char *mx51_tve_ext_sel[] = {
+	"osc",
+	"ckih1",
+};
+
+static const char *mx53_tve_ext_sel[] = {
+	"pll4_sw",
+	"ckih1",
+};
+
+static const char *mx51_tve_sel[] = {
+	"tve_pred",
+	"tve_ext_sel",
+};
+
+static const char *ipu_sel[] = {
+	"axi_a",
+	"axi_b",
+	"emi_slow_gate",
+	"ahb",
+};
+
 static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate_ckil,
 		unsigned long rate_osc, unsigned long rate_ckih1,
 		unsigned long rate_ckih2)
@@ -184,7 +249,31 @@ static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate
 	clks[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "pll1_sw", base + CCM_CACRR, 0, 3);
 }
 
+static void mx5_clocks_ipu_init(void __iomem *regs)
+{
+	clks[IMX5_CLK_IPU_SEL]		= imx_clk_mux("ipu_sel", regs + CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
+}
+
 #ifdef CONFIG_ARCH_IMX51
+static void mx51_clocks_ipu_init(void __iomem *regs)
+{
+	clks[IMX5_CLK_IPU_DI0_SEL]	= imx_clk_mux_p("ipu_di0_sel", regs + CCM_CSCMR2, 26, 3,
+						mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
+	clks[IMX5_CLK_IPU_DI1_SEL]	= imx_clk_mux_p("ipu_di1_sel", regs + CCM_CSCMR2, 29, 3,
+						mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
+	clks[IMX5_CLK_TVE_EXT_SEL]	= imx_clk_mux_p("tve_ext_sel", regs + CCM_CSCMR1, 6, 1,
+						mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel));
+	clks[IMX5_CLK_TVE_SEL]		= imx_clk_mux("tve_sel", regs + CCM_CSCMR1, 7, 1,
+						mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
+	clks[IMX5_CLK_TVE_PRED]		= imx_clk_divider("tve_pred", "pll3_sw", regs + CCM_CDCDR, 28, 3);
+
+	mx5_clocks_ipu_init(regs);
+
+	clkdev_add_physbase(clks[IMX5_CLK_IPU_SEL], MX51_IPU_BASE_ADDR, "bus");
+	clkdev_add_physbase(clks[IMX5_CLK_IPU_DI0_SEL], MX51_IPU_BASE_ADDR, "di0");
+	clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX51_IPU_BASE_ADDR, "di1");
+}
+
 int __init mx51_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
 			unsigned long rate_ckih1, unsigned long rate_ckih2)
 {
@@ -212,6 +301,9 @@ int __init mx51_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigne
 	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM1_BASE_ADDR, "per");
 	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM2_BASE_ADDR, "per");
 
+	if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
+		mx51_clocks_ipu_init(regs);
+
 	return 0;
 }
 
@@ -248,6 +340,32 @@ core_initcall(imx51_ccm_init);
 #endif
 
 #ifdef CONFIG_ARCH_IMX53
+static void mx53_clocks_ipu_init(void __iomem *regs)
+{
+	clks[IMX5_CLK_LDB_DI1_DIV_3_5]	= imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
+	clks[IMX5_CLK_LDB_DI1_DIV]	= imx_clk_divider("ldb_di1_div", "ldb_di1_div_3_5", regs + CCM_CSCMR2, 11, 1);
+	clks[IMX5_CLK_LDB_DI1_SEL]	= imx_clk_mux_p("ldb_di1_sel", regs + CCM_CSCMR2, 9, 1,
+						mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel));
+	clks[IMX5_CLK_DI_PLL4_PODF]	= imx_clk_divider("di_pll4_podf", "pll4_sw", regs + CCM_CDCDR, 16, 3);
+	clks[IMX5_CLK_LDB_DI0_DIV_3_5]	= imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
+	clks[IMX5_CLK_LDB_DI0_DIV]	= imx_clk_divider("ldb_di0_div", "ldb_di0_div_3_5", regs + CCM_CSCMR2, 10, 1);
+	clks[IMX5_CLK_LDB_DI0_SEL]	= imx_clk_mux_p("ldb_di0_sel", regs + CCM_CSCMR2, 8, 1,
+						mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel));
+	clks[IMX5_CLK_IPU_DI0_SEL]	= imx_clk_mux_p("ipu_di0_sel", regs + CCM_CSCMR2, 26, 3,
+						mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
+	clks[IMX5_CLK_IPU_DI1_SEL]	= imx_clk_mux_p("ipu_di1_sel", regs + CCM_CSCMR2, 29, 3,
+						mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
+	clks[IMX5_CLK_TVE_EXT_SEL]	= imx_clk_mux_p("tve_ext_sel", regs + CCM_CSCMR1, 6, 1,
+						mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel));
+	clks[IMX5_CLK_TVE_PRED]		= imx_clk_divider("tve_pred", "tve_ext_sel", regs + CCM_CDCDR, 28, 3);
+
+	mx5_clocks_ipu_init(regs);
+
+	clkdev_add_physbase(clks[IMX5_CLK_IPU_SEL], MX53_IPU_BASE_ADDR, "bus");
+	clkdev_add_physbase(clks[IMX5_CLK_IPU_DI0_SEL], MX53_IPU_BASE_ADDR, "di0");
+	clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX53_IPU_BASE_ADDR, "di1");
+}
+
 int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
 			unsigned long rate_ckih1, unsigned long rate_ckih2)
 {
@@ -277,6 +395,9 @@ int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigne
 	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM1_BASE_ADDR, "per");
 	clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM2_BASE_ADDR, "per");
 
+	if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
+		mx53_clocks_ipu_init(regs);
+
 	return 0;
 }
 
diff --git a/arch/arm/mach-imx/include/mach/imx51-regs.h b/arch/arm/mach-imx/include/mach/imx51-regs.h
index 8eb74cd..b6685ce 100644
--- a/arch/arm/mach-imx/include/mach/imx51-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx51-regs.h
@@ -13,6 +13,8 @@
 
 #define MX51_IROM_BASE_ADDR	0x0
 
+#define MX51_IPU_BASE_ADDR	0x40000000
+
 /*
  * AIPS 1
  */
diff --git a/arch/arm/mach-imx/include/mach/imx53-regs.h b/arch/arm/mach-imx/include/mach/imx53-regs.h
index 473b942..9cd7723 100644
--- a/arch/arm/mach-imx/include/mach/imx53-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx53-regs.h
@@ -5,6 +5,7 @@
 
 #define MX53_SATA_BASE_ADDR	0x10000000
 
+#define MX53_IPU_BASE_ADDR	0x18000000
 /*
  * SPBA global module enabled #0
  */
-- 
2.0.0.rc0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 14/14] ARM: dts: i.MX53: Add ipu alias

[Sascha Hauer]

The barebox IPU driver needs it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/dts/imx53.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi
index bc68012..8740b6f 100644
--- a/arch/arm/dts/imx53.dtsi
+++ b/arch/arm/dts/imx53.dtsi
@@ -4,5 +4,6 @@
 	aliases {
 		pwm0 = &pwm1;
 		pwm1 = &pwm2;
+		ipu0 = &ipu;
 	};
 };
-- 
2.0.0.rc0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox