From: Lucas Stach <dev@lynxeye.de>
To: barebox@lists.infradead.org
Subject: [PATCH v2 23/25] ARM: boards: beaver: import BCT cfg
Date: Wed, 14 May 2014 22:45:50 +0200 [thread overview]
Message-ID: <1400100352-13002-23-git-send-email-dev@lynxeye.de> (raw)
In-Reply-To: <1400100352-13002-1-git-send-email-dev@lynxeye.de>
From https://github.com/NVIDIA/cbootimage-configs.git
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/boards/nvidia-beaver/Makefile | 2 +
.../boards/nvidia-beaver/beaver-2gb-emmc.bct.cfg | 819 +++++++++++++++++++++
2 files changed, 821 insertions(+)
create mode 100644 arch/arm/boards/nvidia-beaver/beaver-2gb-emmc.bct.cfg
diff --git a/arch/arm/boards/nvidia-beaver/Makefile b/arch/arm/boards/nvidia-beaver/Makefile
index 2b6c09e2798e..7ade54e8546d 100644
--- a/arch/arm/boards/nvidia-beaver/Makefile
+++ b/arch/arm/boards/nvidia-beaver/Makefile
@@ -1,5 +1,7 @@
CFLAGS_pbl-entry.o := \
-mcpu=arm7tdmi -march=armv4t \
-fno-tree-switch-conversion -fno-jump-tables
+soc := tegra30
lwl-y += entry.o
obj-y += board.o
+extra-y += beaver-2gb-emmc.bct
diff --git a/arch/arm/boards/nvidia-beaver/beaver-2gb-emmc.bct.cfg b/arch/arm/boards/nvidia-beaver/beaver-2gb-emmc.bct.cfg
new file mode 100644
index 000000000000..49f302fc451b
--- /dev/null
+++ b/arch/arm/boards/nvidia-beaver/beaver-2gb-emmc.bct.cfg
@@ -0,0 +1,819 @@
+# Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+# claim that you wrote the original software. If you use this software
+# in a product, an acknowledgment in the product documentation would be
+# appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+# misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+Version = 0x00030001;
+BlockSize = 0x00004000;
+PageSize = 0x00000200;
+PartitionSize = 0x02000000;
+OdmData = 0x800c0000;
+
+DevType[0] = NvBootDevType_Sdmmc;
+DeviceParam[0].SdmmcParams.ClockDivider = 0x00000009;
+DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[0].SdmmcParams.SdController = 0x00000000;
+
+DevType[1] = NvBootDevType_Sdmmc;
+DeviceParam[1].SdmmcParams.ClockDivider = 0x00000009;
+DeviceParam[1].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[1].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[1].SdmmcParams.SdController = 0x00000000;
+
+DevType[2] = NvBootDevType_Sdmmc;
+DeviceParam[2].SdmmcParams.ClockDivider = 0x00000009;
+DeviceParam[2].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[2].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[2].SdmmcParams.SdController = 0x00000000;
+
+DevType[3] = NvBootDevType_Sdmmc;
+DeviceParam[3].SdmmcParams.ClockDivider = 0x00000009;
+DeviceParam[3].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[3].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[3].SdmmcParams.SdController = 0x00000000;
+
+SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
+SDRAM[0].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[0].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[0].PllMInputDivider = 0x0000000c;
+SDRAM[0].PllMFeedbackDivider = 0x00000320;
+SDRAM[0].PllMPostDivider = 0x00000000;
+SDRAM[0].PllMStableTime = 0x0000012c;
+SDRAM[0].EmcClockDivider = 0x00000002;
+SDRAM[0].EmcAutoCalInterval = 0x001fffff;
+SDRAM[0].EmcAutoCalConfig = 0xa0f10000;
+SDRAM[0].EmcAutoCalWait = 0x00000064;
+SDRAM[0].EmcPinProgramWait = 0x00000001;
+SDRAM[0].EmcRc = 0x00000012;
+SDRAM[0].EmcRfc = 0x00000066;
+SDRAM[0].EmcRas = 0x0000000c;
+SDRAM[0].EmcRp = 0x00000004;
+SDRAM[0].EmcR2w = 0x00000003;
+SDRAM[0].EmcW2r = 0x00000008;
+SDRAM[0].EmcR2p = 0x00000002;
+SDRAM[0].EmcW2p = 0x0000000a;
+SDRAM[0].EmcRrd = 0x00000002;
+SDRAM[0].EmcRdRcd = 0x00000004;
+SDRAM[0].EmcWrRcd = 0x00000004;
+SDRAM[0].EmcRext = 0x00000001;
+SDRAM[0].EmcWdv = 0x00000004;
+SDRAM[0].EmcQUseExtra = 0x00000000;
+SDRAM[0].EmcQUse = 0x00000006;
+SDRAM[0].EmcQRst = 0x00000004;
+SDRAM[0].EmcQSafe = 0x0000000a;
+SDRAM[0].EmcRdv = 0x0000000d;
+SDRAM[0].EmcRefresh = 0x00000bf0;
+SDRAM[0].EmcBurstRefreshNum = 0x00000000;
+SDRAM[0].EmcPdEx2Wr = 0x00000001;
+SDRAM[0].EmcPdEx2Rd = 0x00000008;
+SDRAM[0].EmcPChg2Pden = 0x00000001;
+SDRAM[0].EmcAct2Pden = 0x00000000;
+SDRAM[0].EmcAr2Pden = 0x00000008;
+SDRAM[0].EmcRw2Pden = 0x0000000f;
+SDRAM[0].EmcTxsr = 0x0000006c;
+SDRAM[0].EmcTcke = 0x00000004;
+SDRAM[0].EmcTfaw = 0x0000000c;
+SDRAM[0].EmcTrpab = 0x00000000;
+SDRAM[0].EmcTClkStable = 0x00000004;
+SDRAM[0].EmcTClkStop = 0x00000005;
+SDRAM[0].EmcTRefBw = 0x00000c30;
+SDRAM[0].EmcFbioCfg5 = 0x00007088;
+SDRAM[0].EmcFbioCfg6 = 0x00000006;
+SDRAM[0].EmcFbioSpare = 0xe8000000;
+SDRAM[0].EmcMrsResetDllWait = 0x00000000;
+SDRAM[0].EmcMrsResetDll = 0x00000000;
+SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[0].EmcMrs = 0x80000521;
+SDRAM[0].EmcEmrsEmr2 = 0x80200000;
+SDRAM[0].EmcEmrsEmr3 = 0x80300000;
+SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[0].EmcEmrs = 0x80100002;
+SDRAM[0].EmcMrw1 = 0x00000000;
+SDRAM[0].EmcMrw2 = 0x00000000;
+SDRAM[0].EmcMrw3 = 0x00000000;
+SDRAM[0].EmcMrwResetCommand = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[0].EmcAdrCfg = 0x00000080;
+SDRAM[0].McEmemCfg = 0x00000800;
+SDRAM[0].EmcCfg2 = 0x000c0099;
+SDRAM[0].EmcCfgDigDll = 0x001d0084;
+SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[0].EmcCfg = 0x23c00000;
+SDRAM[0].EmcDbg = 0x01000400;
+SDRAM[0].WarmBootWait = 0x00000002;
+SDRAM[0].EmcCttTermCtrl = 0x00000802;
+SDRAM[0].EmcOdtWrite = 0x00000000;
+SDRAM[0].EmcOdtRead = 0x00000000;
+SDRAM[0].EmcZcalWaitCnt = 0x00000040;
+SDRAM[0].EmcZcalMrwCmd = 0x80000000;
+SDRAM[0].EmcDdr2Wait = 0x00000000;
+SDRAM[0].PmcDdrPwr = 0x00000003;
+SDRAM[0].EmcClockSource = 0x00000000;
+SDRAM[0].EmcClockUsePllMUD = 0x00000000;
+SDRAM[0].EmcPinExtraWait = 0x00000000;
+SDRAM[0].EmcTimingControlWait = 0x00000000;
+SDRAM[0].EmcWext = 0x00000000;
+SDRAM[0].EmcCtt = 0x00000000;
+SDRAM[0].EmcCttDuration = 0x00000000;
+SDRAM[0].EmcPreRefreshReqCnt = 0x000002fc;
+SDRAM[0].EmcTxsrDll = 0x00000200;
+SDRAM[0].EmcCfgRsv = 0xff00ff89;
+SDRAM[0].EmcMrwExtra = 0x00000000;
+SDRAM[0].EmcWarmBootMrw1 = 0x00000000;
+SDRAM[0].EmcWarmBootMrw2 = 0x00000000;
+SDRAM[0].EmcWarmBootMrw3 = 0x00000000;
+SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
+SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[0].EmcMrsWaitCnt = 0x0158000c;
+SDRAM[0].EmcCmdQ = 0x10004408;
+SDRAM[0].EmcMc2EmcQ = 0x06000404;
+SDRAM[0].EmcDynSelfRefControl = 0x800018c8;
+SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[0].EmcDevSelect = 0x00000002;
+SDRAM[0].EmcSelDpdCtrl = 0x0004032c;
+SDRAM[0].EmcDllXformDqs0 = 0x00038000;
+SDRAM[0].EmcDllXformDqs1 = 0x00038000;
+SDRAM[0].EmcDllXformDqs2 = 0x00038000;
+SDRAM[0].EmcDllXformDqs3 = 0x00038000;
+SDRAM[0].EmcDllXformDqs4 = 0x00038000;
+SDRAM[0].EmcDllXformDqs5 = 0x00038000;
+SDRAM[0].EmcDllXformDqs6 = 0x00038000;
+SDRAM[0].EmcDllXformDqs7 = 0x00038000;
+SDRAM[0].EmcDllXformQUse0 = 0x00000000;
+SDRAM[0].EmcDllXformQUse1 = 0x00000000;
+SDRAM[0].EmcDllXformQUse2 = 0x00000000;
+SDRAM[0].EmcDllXformQUse3 = 0x00000000;
+SDRAM[0].EmcDllXformQUse4 = 0x00000000;
+SDRAM[0].EmcDllXformQUse5 = 0x00000000;
+SDRAM[0].EmcDllXformQUse6 = 0x00000000;
+SDRAM[0].EmcDllXformQUse7 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000;
+SDRAM[0].EmcDllXformDq0 = 0x00030000;
+SDRAM[0].EmcDllXformDq1 = 0x00030000;
+SDRAM[0].EmcDllXformDq2 = 0x00030000;
+SDRAM[0].EmcDllXformDq3 = 0x00030000;
+SDRAM[0].EmcZcalInterval = 0x00020000;
+SDRAM[0].EmcZcalInitDev0 = 0x80000011;
+SDRAM[0].EmcZcalInitDev1 = 0x00000000;
+SDRAM[0].EmcZcalInitWait = 0x00000002;
+SDRAM[0].EmcZcalColdBootEnable = 0x00000001;
+SDRAM[0].EmcZcalWarmBootEnable = 0x00000001;
+SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x000a00ab;
+SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000011;
+SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[0].EmcMrsExtra = 0x80000521;
+SDRAM[0].EmcWarmBootMrs = 0x80100002;
+SDRAM[0].EmcWarmBootEmrs = 0x80000521;
+SDRAM[0].EmcWarmBootEmr2 = 0x80200000;
+SDRAM[0].EmcWarmBootEmr3 = 0x80300000;
+SDRAM[0].EmcWarmBootMrsExtra = 0x80100002;
+SDRAM[0].EmcClkenOverride = 0x00000000;
+SDRAM[0].EmcExtraRefreshNum = 0x00000002;
+SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[0].PmcVddpSel = 0x00000002;
+SDRAM[0].PmcDdrCfg = 0x00000002;
+SDRAM[0].PmcIoDpdReq = 0x80800000;
+SDRAM[0].PmcENoVttGen = 0x00000000;
+SDRAM[0].PmcNoIoPower = 0x00000000;
+SDRAM[0].EmcXm2CmdPadCtrl = 0x000002a0;
+SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0800013d;
+SDRAM[0].EmcXm2DqsPadCtrl3 = 0x08000021;
+SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[0].EmcXm2ClkPadCtrl = 0x77fff884;
+SDRAM[0].EmcXm2CompPadCtrl = 0x01f1f508;
+SDRAM[0].EmcXm2VttGenPadCtrl = 0x05057404;
+SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x54000007;
+SDRAM[0].EmcXm2QUsePadCtrl = 0x080001e8;
+SDRAM[0].McEmemAdrCfg = 0x00000000;
+SDRAM[0].McEmemAdrCfgDev0 = 0x00090303;
+SDRAM[0].McEmemAdrCfgDev1 = 0x00090303;
+SDRAM[0].McEmemArbCfg = 0x00000006;
+SDRAM[0].McEmemArbOutstandingReq = 0x80000048;
+SDRAM[0].McEmemArbTimingRcd = 0x00000001;
+SDRAM[0].McEmemArbTimingRp = 0x00000002;
+SDRAM[0].McEmemArbTimingRc = 0x00000009;
+SDRAM[0].McEmemArbTimingRas = 0x00000005;
+SDRAM[0].McEmemArbTimingFaw = 0x00000005;
+SDRAM[0].McEmemArbTimingRrd = 0x00000001;
+SDRAM[0].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[0].McEmemArbTimingWap2Pre = 0x00000008;
+SDRAM[0].McEmemArbTimingR2R = 0x00000002;
+SDRAM[0].McEmemArbTimingW2W = 0x00000002;
+SDRAM[0].McEmemArbTimingR2W = 0x00000003;
+SDRAM[0].McEmemArbTimingW2R = 0x00000006;
+SDRAM[0].McEmemArbDaTurns = 0x06030202;
+SDRAM[0].McEmemArbDaCovers = 0x000d0709;
+SDRAM[0].McEmemArbMisc0 = 0x7086120a;
+SDRAM[0].McEmemArbMisc1 = 0x78000000;
+SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[0].McEmemArbOverride = 0x00000080;
+SDRAM[0].McEmemArbRsv = 0xff00ff00;
+SDRAM[0].McClkenOverride = 0x00000000;
+
+SDRAM[1].MemoryType = NvBootMemoryType_Ddr3;
+SDRAM[1].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[1].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[1].PllMInputDivider = 0x0000000c;
+SDRAM[1].PllMFeedbackDivider = 0x00000320;
+SDRAM[1].PllMPostDivider = 0x00000000;
+SDRAM[1].PllMStableTime = 0x0000012c;
+SDRAM[1].EmcClockDivider = 0x00000002;
+SDRAM[1].EmcAutoCalInterval = 0x001fffff;
+SDRAM[1].EmcAutoCalConfig = 0xa0f10000;
+SDRAM[1].EmcAutoCalWait = 0x00000064;
+SDRAM[1].EmcPinProgramWait = 0x00000001;
+SDRAM[1].EmcRc = 0x00000012;
+SDRAM[1].EmcRfc = 0x00000066;
+SDRAM[1].EmcRas = 0x0000000c;
+SDRAM[1].EmcRp = 0x00000004;
+SDRAM[1].EmcR2w = 0x00000003;
+SDRAM[1].EmcW2r = 0x00000008;
+SDRAM[1].EmcR2p = 0x00000002;
+SDRAM[1].EmcW2p = 0x0000000a;
+SDRAM[1].EmcRrd = 0x00000002;
+SDRAM[1].EmcRdRcd = 0x00000004;
+SDRAM[1].EmcWrRcd = 0x00000004;
+SDRAM[1].EmcRext = 0x00000001;
+SDRAM[1].EmcWdv = 0x00000004;
+SDRAM[1].EmcQUseExtra = 0x00000000;
+SDRAM[1].EmcQUse = 0x00000006;
+SDRAM[1].EmcQRst = 0x00000004;
+SDRAM[1].EmcQSafe = 0x0000000a;
+SDRAM[1].EmcRdv = 0x0000000d;
+SDRAM[1].EmcRefresh = 0x00000bf0;
+SDRAM[1].EmcBurstRefreshNum = 0x00000000;
+SDRAM[1].EmcPdEx2Wr = 0x00000001;
+SDRAM[1].EmcPdEx2Rd = 0x00000008;
+SDRAM[1].EmcPChg2Pden = 0x00000001;
+SDRAM[1].EmcAct2Pden = 0x00000000;
+SDRAM[1].EmcAr2Pden = 0x00000008;
+SDRAM[1].EmcRw2Pden = 0x0000000f;
+SDRAM[1].EmcTxsr = 0x0000006c;
+SDRAM[1].EmcTcke = 0x00000004;
+SDRAM[1].EmcTfaw = 0x0000000c;
+SDRAM[1].EmcTrpab = 0x00000000;
+SDRAM[1].EmcTClkStable = 0x00000004;
+SDRAM[1].EmcTClkStop = 0x00000005;
+SDRAM[1].EmcTRefBw = 0x00000c30;
+SDRAM[1].EmcFbioCfg5 = 0x00007088;
+SDRAM[1].EmcFbioCfg6 = 0x00000006;
+SDRAM[1].EmcFbioSpare = 0xe8000000;
+SDRAM[1].EmcMrsResetDllWait = 0x00000000;
+SDRAM[1].EmcMrsResetDll = 0x00000000;
+SDRAM[1].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[1].EmcMrs = 0x80000521;
+SDRAM[1].EmcEmrsEmr2 = 0x80200000;
+SDRAM[1].EmcEmrsEmr3 = 0x80300000;
+SDRAM[1].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[1].EmcEmrs = 0x80100002;
+SDRAM[1].EmcMrw1 = 0x00000000;
+SDRAM[1].EmcMrw2 = 0x00000000;
+SDRAM[1].EmcMrw3 = 0x00000000;
+SDRAM[1].EmcMrwResetCommand = 0x00000000;
+SDRAM[1].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[1].EmcAdrCfg = 0x00000080;
+SDRAM[1].McEmemCfg = 0x00000800;
+SDRAM[1].EmcCfg2 = 0x000c0099;
+SDRAM[1].EmcCfgDigDll = 0x001d0084;
+SDRAM[1].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[1].EmcCfg = 0x23c00000;
+SDRAM[1].EmcDbg = 0x01000400;
+SDRAM[1].WarmBootWait = 0x00000002;
+SDRAM[1].EmcCttTermCtrl = 0x00000802;
+SDRAM[1].EmcOdtWrite = 0x00000000;
+SDRAM[1].EmcOdtRead = 0x00000000;
+SDRAM[1].EmcZcalWaitCnt = 0x00000040;
+SDRAM[1].EmcZcalMrwCmd = 0x80000000;
+SDRAM[1].EmcDdr2Wait = 0x00000000;
+SDRAM[1].PmcDdrPwr = 0x00000003;
+SDRAM[1].EmcClockSource = 0x00000000;
+SDRAM[1].EmcClockUsePllMUD = 0x00000000;
+SDRAM[1].EmcPinExtraWait = 0x00000000;
+SDRAM[1].EmcTimingControlWait = 0x00000000;
+SDRAM[1].EmcWext = 0x00000000;
+SDRAM[1].EmcCtt = 0x00000000;
+SDRAM[1].EmcCttDuration = 0x00000000;
+SDRAM[1].EmcPreRefreshReqCnt = 0x000002fc;
+SDRAM[1].EmcTxsrDll = 0x00000200;
+SDRAM[1].EmcCfgRsv = 0xff00ff89;
+SDRAM[1].EmcMrwExtra = 0x00000000;
+SDRAM[1].EmcWarmBootMrw1 = 0x00000000;
+SDRAM[1].EmcWarmBootMrw2 = 0x00000000;
+SDRAM[1].EmcWarmBootMrw3 = 0x00000000;
+SDRAM[1].EmcWarmBootMrwExtra = 0x00000000;
+SDRAM[1].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[1].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[1].EmcMrsWaitCnt = 0x0158000c;
+SDRAM[1].EmcCmdQ = 0x10004408;
+SDRAM[1].EmcMc2EmcQ = 0x06000404;
+SDRAM[1].EmcDynSelfRefControl = 0x800018c8;
+SDRAM[1].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[1].EmcDevSelect = 0x00000002;
+SDRAM[1].EmcSelDpdCtrl = 0x0004032c;
+SDRAM[1].EmcDllXformDqs0 = 0x00038000;
+SDRAM[1].EmcDllXformDqs1 = 0x00038000;
+SDRAM[1].EmcDllXformDqs2 = 0x00038000;
+SDRAM[1].EmcDllXformDqs3 = 0x00038000;
+SDRAM[1].EmcDllXformDqs4 = 0x00038000;
+SDRAM[1].EmcDllXformDqs5 = 0x00038000;
+SDRAM[1].EmcDllXformDqs6 = 0x00038000;
+SDRAM[1].EmcDllXformDqs7 = 0x00038000;
+SDRAM[1].EmcDllXformQUse0 = 0x00000000;
+SDRAM[1].EmcDllXformQUse1 = 0x00000000;
+SDRAM[1].EmcDllXformQUse2 = 0x00000000;
+SDRAM[1].EmcDllXformQUse3 = 0x00000000;
+SDRAM[1].EmcDllXformQUse4 = 0x00000000;
+SDRAM[1].EmcDllXformQUse5 = 0x00000000;
+SDRAM[1].EmcDllXformQUse6 = 0x00000000;
+SDRAM[1].EmcDllXformQUse7 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs0 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs1 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs2 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs3 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs4 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs5 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs6 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs7 = 0x00000000;
+SDRAM[1].EmcDllXformDq0 = 0x00030000;
+SDRAM[1].EmcDllXformDq1 = 0x00030000;
+SDRAM[1].EmcDllXformDq2 = 0x00030000;
+SDRAM[1].EmcDllXformDq3 = 0x00030000;
+SDRAM[1].EmcZcalInterval = 0x00020000;
+SDRAM[1].EmcZcalInitDev0 = 0x80000011;
+SDRAM[1].EmcZcalInitDev1 = 0x00000000;
+SDRAM[1].EmcZcalInitWait = 0x00000002;
+SDRAM[1].EmcZcalColdBootEnable = 0x00000001;
+SDRAM[1].EmcZcalWarmBootEnable = 0x00000001;
+SDRAM[1].EmcMrwLpddr2ZcalWarmBoot = 0x000a00ab;
+SDRAM[1].EmcZqCalDdr3WarmBoot = 0x00000011;
+SDRAM[1].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[1].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[1].EmcMrsExtra = 0x80000521;
+SDRAM[1].EmcWarmBootMrs = 0x80100002;
+SDRAM[1].EmcWarmBootEmrs = 0x80000521;
+SDRAM[1].EmcWarmBootEmr2 = 0x80200000;
+SDRAM[1].EmcWarmBootEmr3 = 0x80300000;
+SDRAM[1].EmcWarmBootMrsExtra = 0x80100002;
+SDRAM[1].EmcClkenOverride = 0x00000000;
+SDRAM[1].EmcExtraRefreshNum = 0x00000002;
+SDRAM[1].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[1].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[1].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[1].PmcVddpSel = 0x00000002;
+SDRAM[1].PmcDdrCfg = 0x00000002;
+SDRAM[1].PmcIoDpdReq = 0x80800000;
+SDRAM[1].PmcENoVttGen = 0x00000000;
+SDRAM[1].PmcNoIoPower = 0x00000000;
+SDRAM[1].EmcXm2CmdPadCtrl = 0x000002a0;
+SDRAM[1].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[1].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[1].EmcXm2DqsPadCtrl2 = 0x0800013d;
+SDRAM[1].EmcXm2DqsPadCtrl3 = 0x08000021;
+SDRAM[1].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[1].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[1].EmcXm2ClkPadCtrl = 0x77fff884;
+SDRAM[1].EmcXm2CompPadCtrl = 0x01f1f508;
+SDRAM[1].EmcXm2VttGenPadCtrl = 0x05057404;
+SDRAM[1].EmcXm2VttGenPadCtrl2 = 0x54000007;
+SDRAM[1].EmcXm2QUsePadCtrl = 0x080001e8;
+SDRAM[1].McEmemAdrCfg = 0x00000000;
+SDRAM[1].McEmemAdrCfgDev0 = 0x00090303;
+SDRAM[1].McEmemAdrCfgDev1 = 0x00090303;
+SDRAM[1].McEmemArbCfg = 0x00000006;
+SDRAM[1].McEmemArbOutstandingReq = 0x80000048;
+SDRAM[1].McEmemArbTimingRcd = 0x00000001;
+SDRAM[1].McEmemArbTimingRp = 0x00000002;
+SDRAM[1].McEmemArbTimingRc = 0x00000009;
+SDRAM[1].McEmemArbTimingRas = 0x00000005;
+SDRAM[1].McEmemArbTimingFaw = 0x00000005;
+SDRAM[1].McEmemArbTimingRrd = 0x00000001;
+SDRAM[1].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[1].McEmemArbTimingWap2Pre = 0x00000008;
+SDRAM[1].McEmemArbTimingR2R = 0x00000002;
+SDRAM[1].McEmemArbTimingW2W = 0x00000002;
+SDRAM[1].McEmemArbTimingR2W = 0x00000003;
+SDRAM[1].McEmemArbTimingW2R = 0x00000006;
+SDRAM[1].McEmemArbDaTurns = 0x06030202;
+SDRAM[1].McEmemArbDaCovers = 0x000d0709;
+SDRAM[1].McEmemArbMisc0 = 0x7086120a;
+SDRAM[1].McEmemArbMisc1 = 0x78000000;
+SDRAM[1].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[1].McEmemArbOverride = 0x00000080;
+SDRAM[1].McEmemArbRsv = 0xff00ff00;
+SDRAM[1].McClkenOverride = 0x00000000;
+
+SDRAM[2].MemoryType = NvBootMemoryType_Ddr3;
+SDRAM[2].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[2].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[2].PllMInputDivider = 0x0000000c;
+SDRAM[2].PllMFeedbackDivider = 0x00000320;
+SDRAM[2].PllMPostDivider = 0x00000000;
+SDRAM[2].PllMStableTime = 0x0000012c;
+SDRAM[2].EmcClockDivider = 0x00000002;
+SDRAM[2].EmcAutoCalInterval = 0x001fffff;
+SDRAM[2].EmcAutoCalConfig = 0xa0f10000;
+SDRAM[2].EmcAutoCalWait = 0x00000064;
+SDRAM[2].EmcPinProgramWait = 0x00000001;
+SDRAM[2].EmcRc = 0x00000012;
+SDRAM[2].EmcRfc = 0x00000066;
+SDRAM[2].EmcRas = 0x0000000c;
+SDRAM[2].EmcRp = 0x00000004;
+SDRAM[2].EmcR2w = 0x00000003;
+SDRAM[2].EmcW2r = 0x00000008;
+SDRAM[2].EmcR2p = 0x00000002;
+SDRAM[2].EmcW2p = 0x0000000a;
+SDRAM[2].EmcRrd = 0x00000002;
+SDRAM[2].EmcRdRcd = 0x00000004;
+SDRAM[2].EmcWrRcd = 0x00000004;
+SDRAM[2].EmcRext = 0x00000001;
+SDRAM[2].EmcWdv = 0x00000004;
+SDRAM[2].EmcQUseExtra = 0x00000000;
+SDRAM[2].EmcQUse = 0x00000006;
+SDRAM[2].EmcQRst = 0x00000004;
+SDRAM[2].EmcQSafe = 0x0000000a;
+SDRAM[2].EmcRdv = 0x0000000d;
+SDRAM[2].EmcRefresh = 0x00000bf0;
+SDRAM[2].EmcBurstRefreshNum = 0x00000000;
+SDRAM[2].EmcPdEx2Wr = 0x00000001;
+SDRAM[2].EmcPdEx2Rd = 0x00000008;
+SDRAM[2].EmcPChg2Pden = 0x00000001;
+SDRAM[2].EmcAct2Pden = 0x00000000;
+SDRAM[2].EmcAr2Pden = 0x00000008;
+SDRAM[2].EmcRw2Pden = 0x0000000f;
+SDRAM[2].EmcTxsr = 0x0000006c;
+SDRAM[2].EmcTcke = 0x00000004;
+SDRAM[2].EmcTfaw = 0x0000000c;
+SDRAM[2].EmcTrpab = 0x00000000;
+SDRAM[2].EmcTClkStable = 0x00000004;
+SDRAM[2].EmcTClkStop = 0x00000005;
+SDRAM[2].EmcTRefBw = 0x00000c30;
+SDRAM[2].EmcFbioCfg5 = 0x00007088;
+SDRAM[2].EmcFbioCfg6 = 0x00000006;
+SDRAM[2].EmcFbioSpare = 0xe8000000;
+SDRAM[2].EmcMrsResetDllWait = 0x00000000;
+SDRAM[2].EmcMrsResetDll = 0x00000000;
+SDRAM[2].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[2].EmcMrs = 0x80000521;
+SDRAM[2].EmcEmrsEmr2 = 0x80200000;
+SDRAM[2].EmcEmrsEmr3 = 0x80300000;
+SDRAM[2].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[2].EmcEmrs = 0x80100002;
+SDRAM[2].EmcMrw1 = 0x00000000;
+SDRAM[2].EmcMrw2 = 0x00000000;
+SDRAM[2].EmcMrw3 = 0x00000000;
+SDRAM[2].EmcMrwResetCommand = 0x00000000;
+SDRAM[2].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[2].EmcAdrCfg = 0x00000080;
+SDRAM[2].McEmemCfg = 0x00000800;
+SDRAM[2].EmcCfg2 = 0x000c0099;
+SDRAM[2].EmcCfgDigDll = 0x001d0084;
+SDRAM[2].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[2].EmcCfg = 0x23c00000;
+SDRAM[2].EmcDbg = 0x01000400;
+SDRAM[2].WarmBootWait = 0x00000002;
+SDRAM[2].EmcCttTermCtrl = 0x00000802;
+SDRAM[2].EmcOdtWrite = 0x00000000;
+SDRAM[2].EmcOdtRead = 0x00000000;
+SDRAM[2].EmcZcalWaitCnt = 0x00000040;
+SDRAM[2].EmcZcalMrwCmd = 0x80000000;
+SDRAM[2].EmcDdr2Wait = 0x00000000;
+SDRAM[2].PmcDdrPwr = 0x00000003;
+SDRAM[2].EmcClockSource = 0x00000000;
+SDRAM[2].EmcClockUsePllMUD = 0x00000000;
+SDRAM[2].EmcPinExtraWait = 0x00000000;
+SDRAM[2].EmcTimingControlWait = 0x00000000;
+SDRAM[2].EmcWext = 0x00000000;
+SDRAM[2].EmcCtt = 0x00000000;
+SDRAM[2].EmcCttDuration = 0x00000000;
+SDRAM[2].EmcPreRefreshReqCnt = 0x000002fc;
+SDRAM[2].EmcTxsrDll = 0x00000200;
+SDRAM[2].EmcCfgRsv = 0xff00ff89;
+SDRAM[2].EmcMrwExtra = 0x00000000;
+SDRAM[2].EmcWarmBootMrw1 = 0x00000000;
+SDRAM[2].EmcWarmBootMrw2 = 0x00000000;
+SDRAM[2].EmcWarmBootMrw3 = 0x00000000;
+SDRAM[2].EmcWarmBootMrwExtra = 0x00000000;
+SDRAM[2].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[2].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[2].EmcMrsWaitCnt = 0x0158000c;
+SDRAM[2].EmcCmdQ = 0x10004408;
+SDRAM[2].EmcMc2EmcQ = 0x06000404;
+SDRAM[2].EmcDynSelfRefControl = 0x800018c8;
+SDRAM[2].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[2].EmcDevSelect = 0x00000002;
+SDRAM[2].EmcSelDpdCtrl = 0x0004032c;
+SDRAM[2].EmcDllXformDqs0 = 0x00038000;
+SDRAM[2].EmcDllXformDqs1 = 0x00038000;
+SDRAM[2].EmcDllXformDqs2 = 0x00038000;
+SDRAM[2].EmcDllXformDqs3 = 0x00038000;
+SDRAM[2].EmcDllXformDqs4 = 0x00038000;
+SDRAM[2].EmcDllXformDqs5 = 0x00038000;
+SDRAM[2].EmcDllXformDqs6 = 0x00038000;
+SDRAM[2].EmcDllXformDqs7 = 0x00038000;
+SDRAM[2].EmcDllXformQUse0 = 0x00000000;
+SDRAM[2].EmcDllXformQUse1 = 0x00000000;
+SDRAM[2].EmcDllXformQUse2 = 0x00000000;
+SDRAM[2].EmcDllXformQUse3 = 0x00000000;
+SDRAM[2].EmcDllXformQUse4 = 0x00000000;
+SDRAM[2].EmcDllXformQUse5 = 0x00000000;
+SDRAM[2].EmcDllXformQUse6 = 0x00000000;
+SDRAM[2].EmcDllXformQUse7 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs0 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs1 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs2 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs3 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs4 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs5 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs6 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs7 = 0x00000000;
+SDRAM[2].EmcDllXformDq0 = 0x00030000;
+SDRAM[2].EmcDllXformDq1 = 0x00030000;
+SDRAM[2].EmcDllXformDq2 = 0x00030000;
+SDRAM[2].EmcDllXformDq3 = 0x00030000;
+SDRAM[2].EmcZcalInterval = 0x00020000;
+SDRAM[2].EmcZcalInitDev0 = 0x80000011;
+SDRAM[2].EmcZcalInitDev1 = 0x00000000;
+SDRAM[2].EmcZcalInitWait = 0x00000002;
+SDRAM[2].EmcZcalColdBootEnable = 0x00000001;
+SDRAM[2].EmcZcalWarmBootEnable = 0x00000001;
+SDRAM[2].EmcMrwLpddr2ZcalWarmBoot = 0x000a00ab;
+SDRAM[2].EmcZqCalDdr3WarmBoot = 0x00000011;
+SDRAM[2].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[2].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[2].EmcMrsExtra = 0x80000521;
+SDRAM[2].EmcWarmBootMrs = 0x80100002;
+SDRAM[2].EmcWarmBootEmrs = 0x80000521;
+SDRAM[2].EmcWarmBootEmr2 = 0x80200000;
+SDRAM[2].EmcWarmBootEmr3 = 0x80300000;
+SDRAM[2].EmcWarmBootMrsExtra = 0x80100002;
+SDRAM[2].EmcClkenOverride = 0x00000000;
+SDRAM[2].EmcExtraRefreshNum = 0x00000002;
+SDRAM[2].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[2].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[2].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[2].PmcVddpSel = 0x00000002;
+SDRAM[2].PmcDdrCfg = 0x00000002;
+SDRAM[2].PmcIoDpdReq = 0x80800000;
+SDRAM[2].PmcENoVttGen = 0x00000000;
+SDRAM[2].PmcNoIoPower = 0x00000000;
+SDRAM[2].EmcXm2CmdPadCtrl = 0x000002a0;
+SDRAM[2].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[2].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[2].EmcXm2DqsPadCtrl2 = 0x0800013d;
+SDRAM[2].EmcXm2DqsPadCtrl3 = 0x08000021;
+SDRAM[2].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[2].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[2].EmcXm2ClkPadCtrl = 0x77fff884;
+SDRAM[2].EmcXm2CompPadCtrl = 0x01f1f508;
+SDRAM[2].EmcXm2VttGenPadCtrl = 0x05057404;
+SDRAM[2].EmcXm2VttGenPadCtrl2 = 0x54000007;
+SDRAM[2].EmcXm2QUsePadCtrl = 0x080001e8;
+SDRAM[2].McEmemAdrCfg = 0x00000000;
+SDRAM[2].McEmemAdrCfgDev0 = 0x00090303;
+SDRAM[2].McEmemAdrCfgDev1 = 0x00090303;
+SDRAM[2].McEmemArbCfg = 0x00000006;
+SDRAM[2].McEmemArbOutstandingReq = 0x80000048;
+SDRAM[2].McEmemArbTimingRcd = 0x00000001;
+SDRAM[2].McEmemArbTimingRp = 0x00000002;
+SDRAM[2].McEmemArbTimingRc = 0x00000009;
+SDRAM[2].McEmemArbTimingRas = 0x00000005;
+SDRAM[2].McEmemArbTimingFaw = 0x00000005;
+SDRAM[2].McEmemArbTimingRrd = 0x00000001;
+SDRAM[2].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[2].McEmemArbTimingWap2Pre = 0x00000008;
+SDRAM[2].McEmemArbTimingR2R = 0x00000002;
+SDRAM[2].McEmemArbTimingW2W = 0x00000002;
+SDRAM[2].McEmemArbTimingR2W = 0x00000003;
+SDRAM[2].McEmemArbTimingW2R = 0x00000006;
+SDRAM[2].McEmemArbDaTurns = 0x06030202;
+SDRAM[2].McEmemArbDaCovers = 0x000d0709;
+SDRAM[2].McEmemArbMisc0 = 0x7086120a;
+SDRAM[2].McEmemArbMisc1 = 0x78000000;
+SDRAM[2].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[2].McEmemArbOverride = 0x00000080;
+SDRAM[2].McEmemArbRsv = 0xff00ff00;
+SDRAM[2].McClkenOverride = 0x00000000;
+
+SDRAM[3].MemoryType = NvBootMemoryType_Ddr3;
+SDRAM[3].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[3].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[3].PllMInputDivider = 0x0000000c;
+SDRAM[3].PllMFeedbackDivider = 0x00000320;
+SDRAM[3].PllMPostDivider = 0x00000000;
+SDRAM[3].PllMStableTime = 0x0000012c;
+SDRAM[3].EmcClockDivider = 0x00000002;
+SDRAM[3].EmcAutoCalInterval = 0x001fffff;
+SDRAM[3].EmcAutoCalConfig = 0xa0f10000;
+SDRAM[3].EmcAutoCalWait = 0x00000064;
+SDRAM[3].EmcPinProgramWait = 0x00000001;
+SDRAM[3].EmcRc = 0x00000012;
+SDRAM[3].EmcRfc = 0x00000066;
+SDRAM[3].EmcRas = 0x0000000c;
+SDRAM[3].EmcRp = 0x00000004;
+SDRAM[3].EmcR2w = 0x00000003;
+SDRAM[3].EmcW2r = 0x00000008;
+SDRAM[3].EmcR2p = 0x00000002;
+SDRAM[3].EmcW2p = 0x0000000a;
+SDRAM[3].EmcRrd = 0x00000002;
+SDRAM[3].EmcRdRcd = 0x00000004;
+SDRAM[3].EmcWrRcd = 0x00000004;
+SDRAM[3].EmcRext = 0x00000001;
+SDRAM[3].EmcWdv = 0x00000004;
+SDRAM[3].EmcQUseExtra = 0x00000000;
+SDRAM[3].EmcQUse = 0x00000006;
+SDRAM[3].EmcQRst = 0x00000004;
+SDRAM[3].EmcQSafe = 0x0000000a;
+SDRAM[3].EmcRdv = 0x0000000d;
+SDRAM[3].EmcRefresh = 0x00000bf0;
+SDRAM[3].EmcBurstRefreshNum = 0x00000000;
+SDRAM[3].EmcPdEx2Wr = 0x00000001;
+SDRAM[3].EmcPdEx2Rd = 0x00000008;
+SDRAM[3].EmcPChg2Pden = 0x00000001;
+SDRAM[3].EmcAct2Pden = 0x00000000;
+SDRAM[3].EmcAr2Pden = 0x00000008;
+SDRAM[3].EmcRw2Pden = 0x0000000f;
+SDRAM[3].EmcTxsr = 0x0000006c;
+SDRAM[3].EmcTcke = 0x00000004;
+SDRAM[3].EmcTfaw = 0x0000000c;
+SDRAM[3].EmcTrpab = 0x00000000;
+SDRAM[3].EmcTClkStable = 0x00000004;
+SDRAM[3].EmcTClkStop = 0x00000005;
+SDRAM[3].EmcTRefBw = 0x00000c30;
+SDRAM[3].EmcFbioCfg5 = 0x00007088;
+SDRAM[3].EmcFbioCfg6 = 0x00000006;
+SDRAM[3].EmcFbioSpare = 0xe8000000;
+SDRAM[3].EmcMrsResetDllWait = 0x00000000;
+SDRAM[3].EmcMrsResetDll = 0x00000000;
+SDRAM[3].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[3].EmcMrs = 0x80000521;
+SDRAM[3].EmcEmrsEmr2 = 0x80200000;
+SDRAM[3].EmcEmrsEmr3 = 0x80300000;
+SDRAM[3].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[3].EmcEmrs = 0x80100002;
+SDRAM[3].EmcMrw1 = 0x00000000;
+SDRAM[3].EmcMrw2 = 0x00000000;
+SDRAM[3].EmcMrw3 = 0x00000000;
+SDRAM[3].EmcMrwResetCommand = 0x00000000;
+SDRAM[3].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[3].EmcAdrCfg = 0x00000080;
+SDRAM[3].McEmemCfg = 0x00000800;
+SDRAM[3].EmcCfg2 = 0x000c0099;
+SDRAM[3].EmcCfgDigDll = 0x001d0084;
+SDRAM[3].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[3].EmcCfg = 0x23c00000;
+SDRAM[3].EmcDbg = 0x01000400;
+SDRAM[3].WarmBootWait = 0x00000002;
+SDRAM[3].EmcCttTermCtrl = 0x00000802;
+SDRAM[3].EmcOdtWrite = 0x00000000;
+SDRAM[3].EmcOdtRead = 0x00000000;
+SDRAM[3].EmcZcalWaitCnt = 0x00000040;
+SDRAM[3].EmcZcalMrwCmd = 0x80000000;
+SDRAM[3].EmcDdr2Wait = 0x00000000;
+SDRAM[3].PmcDdrPwr = 0x00000003;
+SDRAM[3].EmcClockSource = 0x00000000;
+SDRAM[3].EmcClockUsePllMUD = 0x00000000;
+SDRAM[3].EmcPinExtraWait = 0x00000000;
+SDRAM[3].EmcTimingControlWait = 0x00000000;
+SDRAM[3].EmcWext = 0x00000000;
+SDRAM[3].EmcCtt = 0x00000000;
+SDRAM[3].EmcCttDuration = 0x00000000;
+SDRAM[3].EmcPreRefreshReqCnt = 0x000002fc;
+SDRAM[3].EmcTxsrDll = 0x00000200;
+SDRAM[3].EmcCfgRsv = 0xff00ff89;
+SDRAM[3].EmcMrwExtra = 0x00000000;
+SDRAM[3].EmcWarmBootMrw1 = 0x00000000;
+SDRAM[3].EmcWarmBootMrw2 = 0x00000000;
+SDRAM[3].EmcWarmBootMrw3 = 0x00000000;
+SDRAM[3].EmcWarmBootMrwExtra = 0x00000000;
+SDRAM[3].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[3].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[3].EmcMrsWaitCnt = 0x0158000c;
+SDRAM[3].EmcCmdQ = 0x10004408;
+SDRAM[3].EmcMc2EmcQ = 0x06000404;
+SDRAM[3].EmcDynSelfRefControl = 0x800018c8;
+SDRAM[3].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[3].EmcDevSelect = 0x00000002;
+SDRAM[3].EmcSelDpdCtrl = 0x0004032c;
+SDRAM[3].EmcDllXformDqs0 = 0x00038000;
+SDRAM[3].EmcDllXformDqs1 = 0x00038000;
+SDRAM[3].EmcDllXformDqs2 = 0x00038000;
+SDRAM[3].EmcDllXformDqs3 = 0x00038000;
+SDRAM[3].EmcDllXformDqs4 = 0x00038000;
+SDRAM[3].EmcDllXformDqs5 = 0x00038000;
+SDRAM[3].EmcDllXformDqs6 = 0x00038000;
+SDRAM[3].EmcDllXformDqs7 = 0x00038000;
+SDRAM[3].EmcDllXformQUse0 = 0x00000000;
+SDRAM[3].EmcDllXformQUse1 = 0x00000000;
+SDRAM[3].EmcDllXformQUse2 = 0x00000000;
+SDRAM[3].EmcDllXformQUse3 = 0x00000000;
+SDRAM[3].EmcDllXformQUse4 = 0x00000000;
+SDRAM[3].EmcDllXformQUse5 = 0x00000000;
+SDRAM[3].EmcDllXformQUse6 = 0x00000000;
+SDRAM[3].EmcDllXformQUse7 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs0 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs1 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs2 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs3 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs4 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs5 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs6 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs7 = 0x00000000;
+SDRAM[3].EmcDllXformDq0 = 0x00030000;
+SDRAM[3].EmcDllXformDq1 = 0x00030000;
+SDRAM[3].EmcDllXformDq2 = 0x00030000;
+SDRAM[3].EmcDllXformDq3 = 0x00030000;
+SDRAM[3].EmcZcalInterval = 0x00020000;
+SDRAM[3].EmcZcalInitDev0 = 0x80000011;
+SDRAM[3].EmcZcalInitDev1 = 0x00000000;
+SDRAM[3].EmcZcalInitWait = 0x00000002;
+SDRAM[3].EmcZcalColdBootEnable = 0x00000001;
+SDRAM[3].EmcZcalWarmBootEnable = 0x00000001;
+SDRAM[3].EmcMrwLpddr2ZcalWarmBoot = 0x000a00ab;
+SDRAM[3].EmcZqCalDdr3WarmBoot = 0x00000011;
+SDRAM[3].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[3].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[3].EmcMrsExtra = 0x80000521;
+SDRAM[3].EmcWarmBootMrs = 0x80100002;
+SDRAM[3].EmcWarmBootEmrs = 0x80000521;
+SDRAM[3].EmcWarmBootEmr2 = 0x80200000;
+SDRAM[3].EmcWarmBootEmr3 = 0x80300000;
+SDRAM[3].EmcWarmBootMrsExtra = 0x80100002;
+SDRAM[3].EmcClkenOverride = 0x00000000;
+SDRAM[3].EmcExtraRefreshNum = 0x00000002;
+SDRAM[3].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[3].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[3].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[3].PmcVddpSel = 0x00000002;
+SDRAM[3].PmcDdrCfg = 0x00000002;
+SDRAM[3].PmcIoDpdReq = 0x80800000;
+SDRAM[3].PmcENoVttGen = 0x00000000;
+SDRAM[3].PmcNoIoPower = 0x00000000;
+SDRAM[3].EmcXm2CmdPadCtrl = 0x000002a0;
+SDRAM[3].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[3].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[3].EmcXm2DqsPadCtrl2 = 0x0800013d;
+SDRAM[3].EmcXm2DqsPadCtrl3 = 0x08000021;
+SDRAM[3].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[3].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[3].EmcXm2ClkPadCtrl = 0x77fff884;
+SDRAM[3].EmcXm2CompPadCtrl = 0x01f1f508;
+SDRAM[3].EmcXm2VttGenPadCtrl = 0x05057404;
+SDRAM[3].EmcXm2VttGenPadCtrl2 = 0x54000007;
+SDRAM[3].EmcXm2QUsePadCtrl = 0x080001e8;
+SDRAM[3].McEmemAdrCfg = 0x00000000;
+SDRAM[3].McEmemAdrCfgDev0 = 0x00090303;
+SDRAM[3].McEmemAdrCfgDev1 = 0x00090303;
+SDRAM[3].McEmemArbCfg = 0x00000006;
+SDRAM[3].McEmemArbOutstandingReq = 0x80000048;
+SDRAM[3].McEmemArbTimingRcd = 0x00000001;
+SDRAM[3].McEmemArbTimingRp = 0x00000002;
+SDRAM[3].McEmemArbTimingRc = 0x00000009;
+SDRAM[3].McEmemArbTimingRas = 0x00000005;
+SDRAM[3].McEmemArbTimingFaw = 0x00000005;
+SDRAM[3].McEmemArbTimingRrd = 0x00000001;
+SDRAM[3].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[3].McEmemArbTimingWap2Pre = 0x00000008;
+SDRAM[3].McEmemArbTimingR2R = 0x00000002;
+SDRAM[3].McEmemArbTimingW2W = 0x00000002;
+SDRAM[3].McEmemArbTimingR2W = 0x00000003;
+SDRAM[3].McEmemArbTimingW2R = 0x00000006;
+SDRAM[3].McEmemArbDaTurns = 0x06030202;
+SDRAM[3].McEmemArbDaCovers = 0x000d0709;
+SDRAM[3].McEmemArbMisc0 = 0x7086120a;
+SDRAM[3].McEmemArbMisc1 = 0x78000000;
+SDRAM[3].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[3].McEmemArbOverride = 0x00000080;
+SDRAM[3].McEmemArbRsv = 0xff00ff00;
+SDRAM[3].McClkenOverride = 0x00000000;
--
1.9.0
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next prev parent reply other threads:[~2014-05-14 20:48 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-14 20:45 [PATCH v2 01/25] reset: add reset controller framework Lucas Stach
2014-05-14 20:45 ` [PATCH v2 02/25] tegra: lowlevel: add function to fetch chipid Lucas Stach
2014-05-14 20:45 ` [PATCH v2 03/25] reset: add tegra reset controller Lucas Stach
2014-05-14 20:45 ` [PATCH v2 04/25] clk: tegra: reset UARTS from clock controller Lucas Stach
2014-05-14 20:45 ` [PATCH v2 05/25] mci: tegra: add reset control Lucas Stach
2014-05-14 20:45 ` [PATCH v2 06/25] clk: tegra: remove device reset hack Lucas Stach
2014-05-14 20:45 ` [PATCH v2 07/25] clk: tegra: allow to register clocks with 16 bit divider Lucas Stach
2014-05-14 20:45 ` [PATCH v2 08/25] clk: tegra30: register i2c clocks Lucas Stach
2014-05-14 20:45 ` [PATCH v2 09/25] clk: tegra20: " Lucas Stach
2014-05-14 20:45 ` [PATCH v2 10/25] i2c: add Tegra driver Lucas Stach
2014-05-14 20:45 ` [PATCH v2 11/25] ARM: tegra: beaver: activate sdmmc1 voltage rail Lucas Stach
2014-05-14 20:45 ` [PATCH v2 12/25] ARM: tegra: beaver: adjust pinmux to make sdmmc1 work Lucas Stach
2014-05-14 20:45 ` [PATCH v2 13/25] mci: tegra: apply pad autocalibration on T30 Lucas Stach
2014-05-14 20:45 ` [PATCH v2 14/25] mci: tegra: don't set 8bit mode unconditionally Lucas Stach
2014-05-14 20:45 ` [PATCH v2 15/25] pinctrl: tegra30: parse drive groups Lucas Stach
2014-05-14 20:45 ` [PATCH v2 16/25] scripts: tegra: import cbootimage Lucas Stach
2014-05-14 20:45 ` [PATCH v2 17/25] tegra: cbootimage: remove noisy output Lucas Stach
2014-05-14 20:45 ` [PATCH v2 18/25] Makefile.lib: add rule to built Tegra BCTs Lucas Stach
2014-05-14 20:45 ` [PATCH v2 19/25] images: add Tegra20 image build rules Lucas Stach
2014-05-14 20:45 ` [PATCH v2 20/25] images: add Tegra30 " Lucas Stach
2014-05-14 20:45 ` [PATCH v2 21/25] ARM: boards: colibri t20: import BCT cfgs Lucas Stach
2014-05-14 20:45 ` [PATCH v2 22/25] images: tegra: build all Toradex Colibri images Lucas Stach
2014-05-14 20:45 ` Lucas Stach [this message]
2014-05-14 20:45 ` [PATCH v2 24/25] images: tegra: build NVidia Beaver image Lucas Stach
2014-05-14 20:45 ` [PATCH v2 25/25] images: tegra: rename ac100 image Lucas Stach
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