From: Franck Jullien <franck.jullien@gmail.com>
To: barebox@lists.infradead.org
Subject: [PATCH 1/3] openrisc: update SPR registers definition
Date: Wed, 21 May 2014 23:32:27 +0200 [thread overview]
Message-ID: <1400707949-16521-1-git-send-email-franck.jullien@gmail.com> (raw)
The OpenRISC architecture specification v1.0 defines
new SPR registers. This patch adds registers definition
for group 0 and update bit definitions for the CPU
configuration register.
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
---
arch/openrisc/include/asm/spr-defs.h | 13 ++++++++++++-
1 files changed, 12 insertions(+), 1 deletions(-)
diff --git a/arch/openrisc/include/asm/spr-defs.h b/arch/openrisc/include/asm/spr-defs.h
index cb0cdfa..b3b08db 100644
--- a/arch/openrisc/include/asm/spr-defs.h
+++ b/arch/openrisc/include/asm/spr-defs.h
@@ -49,6 +49,11 @@
#define SPR_ICCFGR (SPRGROUP_SYS + 6)
#define SPR_DCFGR (SPRGROUP_SYS + 7)
#define SPR_PCCFGR (SPRGROUP_SYS + 8)
+#define SPR_VR2 (SPRGROUP_SYS + 9)
+#define SPR_AVR (SPRGROUP_SYS + 10)
+#define SPR_EVBAR (SPRGROUP_SYS + 11)
+#define SPR_AECR (SPRGROUP_SYS + 12)
+#define SPR_AESR (SPRGROUP_SYS + 13)
#define SPR_NPC (SPRGROUP_SYS + 16)
#define SPR_SR (SPRGROUP_SYS + 17)
#define SPR_PPC (SPRGROUP_SYS + 18)
@@ -164,7 +169,13 @@
#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */
#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */
#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */
-#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */
+#define SPR_CPUCFGR_ND 0x00000400 /* No delay slot */
+#define SPR_CPUCFGR_AVRP 0x00000800 /* Arch. Version Register present */
+#define SPR_CPUCFGR_EVBARP 0x00001000 /* Exception Vector Base Address Register (EVBAR) present */
+#define SPR_CPUCFGR_ISRP 0x00002000 /* Implementation-Specific Registers (ISR0-7) present */
+#define SPR_CPUCFGR_AECSRP 0x00004000 /* Arithmetic Exception Control Register (AECR) and */
+ /* Arithmetic Exception Status Register (AESR) presents */
+#define SPR_CPUCFGR_RES 0xffffc000 /* Reserved */
/*
* Bit definitions for the Debug configuration register and other
--
1.7.1
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next reply other threads:[~2014-05-21 21:32 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-21 21:32 Franck Jullien [this message]
2014-05-21 21:32 ` [PATCH 2/3] openrisc: fix relocation code Franck Jullien
2014-05-21 21:32 ` [PATCH 3/3] openrisc: update cpuinfo Franck Jullien
2014-05-22 6:07 ` [PATCH 1/3] openrisc: update SPR registers definition Sascha Hauer
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