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* [PATCH 00/30] Tegra K1 support
@ 2014-06-03 20:34 Lucas Stach
  2014-06-03 20:34 ` [PATCH 01/30] mci: implement non-removable property Lucas Stach
                   ` (30 more replies)
  0 siblings, 31 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:34 UTC (permalink / raw)
  To: barebox

This is the next big round of Tegra updates, featuring
Tegra K1 support. The series is based on -next as it has
quite some dependencies on the earlier Tegra series.

The first 4 patches are some general useful additions,
all others are adding K1 aka Tegra124 support. I've
verified booting a Linux kernel to the rootfs panic.

The series is regression free on Tegra30.

Lucas Stach (30):
  mci: implement non-removable property
  tegra: lowlevel-dvc: use __always_inline macro
  tegra: pmc: add Tegra30 compatible
  tegra: pmc: add command to get into RCM
  tegra: lowlevel: setup an early stack
  tegra: add Tegra124 id to lowlevel functions
  tegra: lowlevel: fix ODMdata fetch on Tegra124
  tegra: recognize Tegra124 in maincomplex startup
  tegra: recognize Tegra124 in common initcalls
  tegra: add Tegra124 and AS3722 PMIC to lowlevel-dvc
  tegra: disable IDDQ for PLL_X on Tegra124
  tegra: power up additional partitions on Tegra124
  tegra: fix MESLECT clock enable
  tegra: change cpu internal reset layout for Tegra124
  tegra: add Tegra124 PLL_X rate setup
  tegra: apply cluster switch logic to all SoCs >=T30
  tegra: hardcode entry address for main cluster
  tegra: setup L2 cache on Tegra124
  tegra: add architectural timer init
  tegra: add Tegra124 Kconfig symbol
  pinctrl: tegra30: introduce drvdata
  pinctrl: tegra: add Tegra124 support
  clk: tegra: allow variable sized muxes
  clk: tegra: don't bug out on zero PLL postdiv
  clk: tegra: add Tegra124 driver
  mci: tegra: add Tegra124 compatible
  tegra: pmc: add Tegra124 compatible
  images: add Tegra124 image build rules
  tegra: add NVIDIA Jetson-TK1 board support
  tegra: refresh defconfig

 arch/arm/boards/Makefile                           |    1 +
 arch/arm/boards/nvidia-jetson-tk1/Makefile         |    7 +
 arch/arm/boards/nvidia-jetson-tk1/entry.c          |   39 +
 .../nvidia-jetson-tk1/jetson-tk1-2gb-emmc.bct.cfg  | 1287 ++++++++++++++
 arch/arm/configs/tegra_v7_defconfig                |   22 +-
 arch/arm/dts/Makefile                              |    4 +-
 arch/arm/dts/tegra124-jetson-tk1.dts               | 1828 ++++++++++++++++++++
 arch/arm/dts/tegra124.dtsi                         |    1 +
 arch/arm/mach-tegra/Kconfig                        |    8 +
 arch/arm/mach-tegra/include/mach/iomap.h           |    3 +
 arch/arm/mach-tegra/include/mach/lowlevel-dvc.h    |   61 +-
 arch/arm/mach-tegra/include/mach/lowlevel.h        |   58 +-
 arch/arm/mach-tegra/include/mach/tegra114-sysctr.h |   30 +
 arch/arm/mach-tegra/include/mach/tegra124-car.h    |   19 +
 arch/arm/mach-tegra/include/mach/tegra20-pmc.h     |    4 +
 arch/arm/mach-tegra/include/mach/tegra30-car.h     |    2 +
 arch/arm/mach-tegra/tegra20-pmc.c                  |   24 +
 arch/arm/mach-tegra/tegra20.c                      |   31 +-
 arch/arm/mach-tegra/tegra_avp_init.c               |   82 +-
 arch/arm/mach-tegra/tegra_maincomplex_init.c       |   14 +-
 drivers/clk/tegra/Makefile                         |    1 +
 drivers/clk/tegra/clk-periph.c                     |    6 +-
 drivers/clk/tegra/clk-pll.c                        |    2 -
 drivers/clk/tegra/clk-tegra124.c                   |  349 ++++
 drivers/mci/mci-core.c                             |    5 +-
 drivers/mci/tegra-sdmmc.c                          |    2 +
 drivers/pinctrl/Kconfig                            |    2 +-
 drivers/pinctrl/pinctrl-tegra30.c                  |  299 +++-
 images/.gitignore                                  |    2 +
 images/Makefile                                    |    2 +-
 images/Makefile.tegra                              |   19 +
 include/mci.h                                      |    1 +
 32 files changed, 4149 insertions(+), 66 deletions(-)
 create mode 100644 arch/arm/boards/nvidia-jetson-tk1/Makefile
 create mode 100644 arch/arm/boards/nvidia-jetson-tk1/entry.c
 create mode 100644 arch/arm/boards/nvidia-jetson-tk1/jetson-tk1-2gb-emmc.bct.cfg
 create mode 100644 arch/arm/dts/tegra124-jetson-tk1.dts
 create mode 100644 arch/arm/dts/tegra124.dtsi
 create mode 100644 arch/arm/mach-tegra/include/mach/tegra114-sysctr.h
 create mode 100644 arch/arm/mach-tegra/include/mach/tegra124-car.h
 create mode 100644 drivers/clk/tegra/clk-tegra124.c

-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 01/30] mci: implement non-removable property
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
@ 2014-06-03 20:34 ` Lucas Stach
  2014-06-03 20:34 ` [PATCH 02/30] tegra: lowlevel-dvc: use __always_inline macro Lucas Stach
                   ` (29 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:34 UTC (permalink / raw)
  To: barebox

There is no need to check the card-detect status
for non-removable devices.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 drivers/mci/mci-core.c | 5 ++++-
 include/mci.h          | 1 +
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
index 282d239..ce6e590 100644
--- a/drivers/mci/mci-core.c
+++ b/drivers/mci/mci-core.c
@@ -1572,7 +1572,8 @@ static int mci_card_probe(struct mci *mci)
 	struct mci_host *host = mci->host;
 	int i, rc, disknum, ret;
 
-	if (host->card_present && !host->card_present(host)) {
+	if (host->card_present && !host->card_present(host) &&
+	    !host->non_removable) {
 		dev_err(&mci->dev, "no card inserted\n");
 		return -ENODEV;
 	}
@@ -1839,4 +1840,6 @@ void mci_of_parse(struct mci_host *host)
 			host->dsr_val = dsr_val;
 		}
 	}
+
+	host->non_removable = of_property_read_bool(np, "non-removable");
 }
diff --git a/include/mci.h b/include/mci.h
index f2c6fd1..c5ab5b3 100644
--- a/include/mci.h
+++ b/include/mci.h
@@ -302,6 +302,7 @@ struct mci_host {
 	unsigned max_req_size;
 	unsigned dsr_val;	/**< optional dsr value */
 	int use_dsr;		/**< optional dsr usage flag */
+	bool non_removable;	/**< device is non removable */
 	struct regulator *supply;
 
 	/** init the host interface */
-- 
1.9.3


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* [PATCH 02/30] tegra: lowlevel-dvc: use __always_inline macro
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
  2014-06-03 20:34 ` [PATCH 01/30] mci: implement non-removable property Lucas Stach
@ 2014-06-03 20:34 ` Lucas Stach
  2014-06-03 20:34 ` [PATCH 03/30] tegra: pmc: add Tegra30 compatible Lucas Stach
                   ` (28 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:34 UTC (permalink / raw)
  To: barebox

Cleaner code.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/lowlevel-dvc.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
index 32f10d7..9ae8784 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
@@ -59,7 +59,7 @@ void tegra_dvc_write_data(u32 data, u32 config)
 	writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void tegra30_tps65911_cpu_rail_enable(void)
 {
 	tegra_dvc_write_addr(0x5a, 2);
@@ -71,7 +71,7 @@ void tegra30_tps65911_cpu_rail_enable(void)
 	tegra_ll_delay_usec(10 * 1000);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void tegra30_tps62366a_ramp_vddcore(void)
 {
 	tegra_dvc_write_addr(0xc0, 2);
@@ -80,7 +80,7 @@ void tegra30_tps62366a_ramp_vddcore(void)
 	tegra_ll_delay_usec(1000);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void tegra30_tps62361b_ramp_vddcore(void)
 {
 	tegra_dvc_write_addr(0xc0, 2);
-- 
1.9.3


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* [PATCH 03/30] tegra: pmc: add Tegra30 compatible
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
  2014-06-03 20:34 ` [PATCH 01/30] mci: implement non-removable property Lucas Stach
  2014-06-03 20:34 ` [PATCH 02/30] tegra: lowlevel-dvc: use __always_inline macro Lucas Stach
@ 2014-06-03 20:34 ` Lucas Stach
  2014-06-03 20:34 ` [PATCH 04/30] tegra: pmc: add command to get into RCM Lucas Stach
                   ` (27 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:34 UTC (permalink / raw)
  To: barebox

Allows reset command to work on T30.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/tegra20-pmc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-tegra/tegra20-pmc.c b/arch/arm/mach-tegra/tegra20-pmc.c
index b7d84d8..1069df9 100644
--- a/arch/arm/mach-tegra/tegra20-pmc.c
+++ b/arch/arm/mach-tegra/tegra20-pmc.c
@@ -51,6 +51,8 @@ static __maybe_unused struct of_device_id tegra20_pmc_dt_ids[] = {
 	{
 		.compatible = "nvidia,tegra20-pmc",
 	}, {
+		.compatible = "nvidia,tegra30-pmc",
+	}, {
 		/* sentinel */
 	}
 };
-- 
1.9.3


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* [PATCH 04/30] tegra: pmc: add command to get into RCM
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (2 preceding siblings ...)
  2014-06-03 20:34 ` [PATCH 03/30] tegra: pmc: add Tegra30 compatible Lucas Stach
@ 2014-06-03 20:34 ` Lucas Stach
  2014-06-03 20:34 ` [PATCH 05/30] tegra: lowlevel: setup an early stack Lucas Stach
                   ` (26 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:34 UTC (permalink / raw)
  To: barebox

In RCM aka recovery mode the BootROM waits for a
usbloader to take over control. On most boards this
is triggered by holding a physical switch which may
be inconvinient at times. Add a command to switch
into RCM from software.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/tegra20-pmc.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/mach-tegra/tegra20-pmc.c b/arch/arm/mach-tegra/tegra20-pmc.c
index 1069df9..37496ac 100644
--- a/arch/arm/mach-tegra/tegra20-pmc.c
+++ b/arch/arm/mach-tegra/tegra20-pmc.c
@@ -20,6 +20,7 @@
  */
 
 #include <common.h>
+#include <command.h>
 #include <init.h>
 #include <io.h>
 
@@ -47,6 +48,14 @@ static int tegra20_pmc_probe(struct device_d *dev)
 	return 0;
 }
 
+static int do_tegrarcm(int argc, char *argv[])
+{
+	writel(2, pmc_base + PMC_SCRATCH(0));
+	reset_cpu(0);
+
+	return 0;
+}
+
 static __maybe_unused struct of_device_id tegra20_pmc_dt_ids[] = {
 	{
 		.compatible = "nvidia,tegra20-pmc",
@@ -68,3 +77,14 @@ static int tegra20_pmc_init(void)
 	return platform_driver_register(&tegra20_pmc_driver);
 }
 coredevice_initcall(tegra20_pmc_init);
+
+BAREBOX_CMD_HELP_START(tegrarcm)
+BAREBOX_CMD_HELP_TEXT("Get into recovery mode without using a physical switch\n")
+BAREBOX_CMD_HELP_END
+
+BAREBOX_CMD_START(tegrarcm)
+	.cmd		= do_tegrarcm,
+	BAREBOX_CMD_DESC("Usage: tegrarcm")
+	BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP)
+	BAREBOX_CMD_HELP(cmd_tegrarcm_help)
+BAREBOX_CMD_END
-- 
1.9.3


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* [PATCH 05/30] tegra: lowlevel: setup an early stack
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (3 preceding siblings ...)
  2014-06-03 20:34 ` [PATCH 04/30] tegra: pmc: add command to get into RCM Lucas Stach
@ 2014-06-03 20:34 ` Lucas Stach
  2014-06-03 20:34 ` [PATCH 06/30] tegra: add Tegra124 id to lowlevel functions Lucas Stach
                   ` (25 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:34 UTC (permalink / raw)
  To: barebox

Even the lowlevel functions are growing to a
size where having a stack seem beneficial.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/lowlevel.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h
index 1026518..80d65a6 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -272,6 +272,8 @@ void tegra_cpu_lowlevel_setup(void)
 	r &= ~0x1f;
 	r |= 0xd3;
 	__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
+
+	arm_setup_stack(TEGRA_IRAM_BASE + SZ_256K - 8);
 	tegra_ll_delay_setup();
 }
 
-- 
1.9.3


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* [PATCH 06/30] tegra: add Tegra124 id to lowlevel functions
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (4 preceding siblings ...)
  2014-06-03 20:34 ` [PATCH 05/30] tegra: lowlevel: setup an early stack Lucas Stach
@ 2014-06-03 20:34 ` Lucas Stach
  2014-06-03 20:34 ` [PATCH 07/30] tegra: lowlevel: fix ODMdata fetch on Tegra124 Lucas Stach
                   ` (24 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:34 UTC (permalink / raw)
  To: barebox

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/lowlevel.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h
index 80d65a6..662508a 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -67,6 +67,8 @@ enum tegra_chiptype {
 	TEGRA_UNK_REV = -1,
 	TEGRA20 = 0,
 	TEGRA30 = 1,
+	TEGRA114 = 2,
+	TEGRA124 = 3,
 };
 
 static __always_inline
@@ -87,6 +89,8 @@ enum tegra_chiptype tegra_get_chiptype(void)
 		return TEGRA20;
 	case 0x30:
 		return TEGRA30;
+	case 0x40:
+		return TEGRA124;
 	default:
 		return TEGRA_UNK_REV;
 	}
@@ -99,6 +103,7 @@ int tegra_get_num_cores(void)
 	case TEGRA20:
 		return 2;
 	case TEGRA30:
+	case TEGRA124:
 		return 4;
 	default:
 		return 0;
@@ -213,6 +218,7 @@ int tegra_get_pllp_rate(void)
 	case TEGRA20:
 		return 216000000;
 	case TEGRA30:
+	case TEGRA124:
 		return 408000000;
 	default:
 		return 0;
-- 
1.9.3


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* [PATCH 07/30] tegra: lowlevel: fix ODMdata fetch on Tegra124
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (5 preceding siblings ...)
  2014-06-03 20:34 ` [PATCH 06/30] tegra: add Tegra124 id to lowlevel functions Lucas Stach
@ 2014-06-03 20:34 ` Lucas Stach
  2014-06-03 20:34 ` [PATCH 08/30] tegra: recognize Tegra124 in maincomplex startup Lucas Stach
                   ` (23 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:34 UTC (permalink / raw)
  To: barebox

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/lowlevel.h | 50 ++++++++++++++++++++---------
 1 file changed, 35 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h
index 662508a..c65be0b 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -31,8 +31,9 @@
 
 /* Bootinfotable */
 
-#define NV_BIT_BCTSIZE		0x38	/* size of the BCT in IRAM */
-#define NV_BIT_BCTPTR		0x3C	/* location of the BCT in IRAM */
+/* location of the BCT in IRAM */
+#define NV_BIT_BCTPTR_T20	0x3c
+#define NV_BIT_BCTPTR_T114	0x4c
 
 /* ODM data */
 #define BCT_ODMDATA_OFFSET	12	/* offset from the _end_ of the BCT */
@@ -45,19 +46,6 @@
 #define T20_ODMDATA_UARTID_SHIFT	15
 #define T20_ODMDATA_UARTID_MASK		(7 << T20_ODMDATA_UARTID_SHIFT)
 
-static __always_inline
-u32 tegra_get_odmdata(void)
-{
-	u32 bctsize, bctptr, odmdata;
-
-	bctsize = cpu_readl(TEGRA_IRAM_BASE + NV_BIT_BCTSIZE);
-	bctptr = cpu_readl(TEGRA_IRAM_BASE + NV_BIT_BCTPTR);
-
-	odmdata = cpu_readl(bctptr + bctsize - BCT_ODMDATA_OFFSET);
-
-	return odmdata;
-}
-
 /* chip ID */
 #define APB_MISC_HIDREV			0x804
 #define HIDREV_CHIPID_SHIFT		8
@@ -97,6 +85,38 @@ enum tegra_chiptype tegra_get_chiptype(void)
 }
 
 static __always_inline
+u32 tegra_get_odmdata(void)
+{
+	u32 bctptr_offset, bctptr, odmdata_offset;
+	enum tegra_chiptype chiptype = tegra_get_chiptype();
+
+	switch(chiptype) {
+	case TEGRA20:
+		bctptr_offset = NV_BIT_BCTPTR_T20;
+		odmdata_offset = 4068;
+		break;
+	case TEGRA30:
+		bctptr_offset = NV_BIT_BCTPTR_T20;
+		odmdata_offset = 6116;
+		break;
+	case TEGRA114:
+		bctptr_offset = NV_BIT_BCTPTR_T114;
+		odmdata_offset = 1752;
+		break;
+	case TEGRA124:
+		bctptr_offset = NV_BIT_BCTPTR_T114;
+		odmdata_offset = 1704;
+		break;
+	default:
+		return 0;
+	}
+
+	bctptr = cpu_readl(TEGRA_IRAM_BASE + bctptr_offset);
+
+	return cpu_readl(bctptr + odmdata_offset);
+}
+
+static __always_inline
 int tegra_get_num_cores(void)
 {
 	switch (tegra_get_chiptype()) {
-- 
1.9.3


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* [PATCH 08/30] tegra: recognize Tegra124 in maincomplex startup
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (6 preceding siblings ...)
  2014-06-03 20:34 ` [PATCH 07/30] tegra: lowlevel: fix ODMdata fetch on Tegra124 Lucas Stach
@ 2014-06-03 20:34 ` Lucas Stach
  2014-06-03 20:34 ` [PATCH 09/30] tegra: recognize Tegra124 in common initcalls Lucas Stach
                   ` (22 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:34 UTC (permalink / raw)
  To: barebox

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/tegra_maincomplex_init.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-tegra/tegra_maincomplex_init.c b/arch/arm/mach-tegra/tegra_maincomplex_init.c
index 2a85f26..83ad33d 100644
--- a/arch/arm/mach-tegra/tegra_maincomplex_init.c
+++ b/arch/arm/mach-tegra/tegra_maincomplex_init.c
@@ -42,6 +42,7 @@ void tegra_maincomplex_entry(void)
 		ramsize = tegra20_get_ramsize();
 		break;
 	case TEGRA30:
+	case TEGRA124:
 		rambase = SZ_2G;
 		ramsize = tegra30_get_ramsize();
 		break;
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 09/30] tegra: recognize Tegra124 in common initcalls
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (7 preceding siblings ...)
  2014-06-03 20:34 ` [PATCH 08/30] tegra: recognize Tegra124 in maincomplex startup Lucas Stach
@ 2014-06-03 20:34 ` Lucas Stach
  2014-06-03 20:34 ` [PATCH 10/30] tegra: add Tegra124 and AS3722 PMIC to lowlevel-dvc Lucas Stach
                   ` (21 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:34 UTC (permalink / raw)
  To: barebox

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/tegra20.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
index 0773972..752bbb0 100644
--- a/arch/arm/mach-tegra/tegra20.c
+++ b/arch/arm/mach-tegra/tegra20.c
@@ -30,7 +30,8 @@ static int tegra_add_debug_console(void)
 	unsigned long base = 0;
 
 	if (!of_machine_is_compatible("nvidia,tegra20") &&
-	    !of_machine_is_compatible("nvidia,tegra30"))
+	    !of_machine_is_compatible("nvidia,tegra30") &&
+	    !of_machine_is_compatible("nvidia,tegra124"))
 		return 0;
 
 	/* figure out which UART to use */
@@ -74,7 +75,8 @@ mem_initcall(tegra20_mem_init);
 
 static int tegra30_mem_init(void)
 {
-	if (!of_machine_is_compatible("nvidia,tegra30"))
+	if (!of_machine_is_compatible("nvidia,tegra30") &&
+	    !of_machine_is_compatible("nvidia,tegra124"))
 		return 0;
 
 	arm_add_mem_device("ram0", SZ_2G, tegra30_get_ramsize());
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 10/30] tegra: add Tegra124 and AS3722 PMIC to lowlevel-dvc
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (8 preceding siblings ...)
  2014-06-03 20:34 ` [PATCH 09/30] tegra: recognize Tegra124 in common initcalls Lucas Stach
@ 2014-06-03 20:34 ` Lucas Stach
  2014-06-03 20:34 ` [PATCH 11/30] tegra: disable IDDQ for PLL_X on Tegra124 Lucas Stach
                   ` (20 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:34 UTC (permalink / raw)
  To: barebox

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/lowlevel-dvc.h | 55 +++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
index 9ae8784..1deae4e 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
@@ -40,6 +40,22 @@ void tegra_dvc_init(void)
 	writel(CRC_RST_DEV_H_DVC, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_H_CLR);
 }
 
+static __always_inline
+void tegra124_dvc_pinmux(void)
+{
+	u32 val;
+
+	/* disable tristate for pin PWR_I2C_SCL_PZ6 */
+	val = readl(TEGRA_APB_MISC_BASE + 0x32b4);
+	val &= ~(1 << 4);
+	writel(val, TEGRA_APB_MISC_BASE + 0x32b4);
+
+	/* disable tristate for pin PWR_I2C_SDA_PZ7 */
+	val = readl(TEGRA_APB_MISC_BASE + 0x32b8);
+	val &= ~(1 << 4);
+	writel(val, TEGRA_APB_MISC_BASE + 0x32b8);
+}
+
 #define TEGRA_I2C_CNFG		0x00
 #define TEGRA_I2C_CMD_ADDR0	0x04
 #define TEGRA_I2C_CMD_DATA1	0x0c
@@ -88,3 +104,42 @@ void tegra30_tps62361b_ramp_vddcore(void)
 	tegra_dvc_write_data(0x4603, TEGRA_I2C_SEND_2_BYTES);
 	tegra_ll_delay_usec(1000);
 }
+
+static __always_inline
+void tegra124_as3722_enable_essential_rails(u32 sd0voltage)
+{
+	/*
+	 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_dvc_write_addr(0x80, 2);
+	tegra_dvc_write_data(sd0voltage | 0x00, TEGRA_I2C_SEND_2_BYTES);
+	tegra_ll_delay_usec(10 * 1000);
+
+	/*
+	 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_dvc_write_addr(0x80, 2);
+	tegra_dvc_write_data(0x2800 | 0x06, TEGRA_I2C_SEND_2_BYTES);
+	tegra_ll_delay_usec(10 * 1000);
+
+	/*
+	 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.2V, then enable the VDD regulator.
+	 */
+	tegra_dvc_write_addr(0x80, 2);
+	tegra_dvc_write_data(0x1000 | 0x12, TEGRA_I2C_SEND_2_BYTES);
+	tegra_ll_delay_usec(10 * 1000);
+
+	/*
+	 * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
+	 * First set it to bypass 3.3V straight thru, then enable the regulator
+	 *
+	 * NOTE: We do this early because doing it later seems to hose the CPU
+	 * power rail/partition startup. Need to debug.
+	 */
+	tegra_dvc_write_addr(0x80, 2);
+	tegra_dvc_write_data(0x3f00 | 0x16, TEGRA_I2C_SEND_2_BYTES);
+	tegra_ll_delay_usec(10 * 1000);
+}
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 11/30] tegra: disable IDDQ for PLL_X on Tegra124
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (9 preceding siblings ...)
  2014-06-03 20:34 ` [PATCH 10/30] tegra: add Tegra124 and AS3722 PMIC to lowlevel-dvc Lucas Stach
@ 2014-06-03 20:34 ` Lucas Stach
  2014-06-03 20:34 ` [PATCH 12/30] tegra: power up additional partitions " Lucas Stach
                   ` (19 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:34 UTC (permalink / raw)
  To: barebox

This is an additional power down control.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/tegra124-car.h | 19 +++++++++++++++++++
 arch/arm/mach-tegra/tegra_avp_init.c            |  9 +++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 arch/arm/mach-tegra/include/mach/tegra124-car.h

diff --git a/arch/arm/mach-tegra/include/mach/tegra124-car.h b/arch/arm/mach-tegra/include/mach/tegra124-car.h
new file mode 100644
index 0000000..1fb924d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra124-car.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Register definitions */
+#define CRC_PLLX_MISC_3			0x518
+#define CRC_PLLX_MISC_3_IDDQ		(1 << 3)
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c
index 53e81d9..cc8b0e2 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -25,6 +25,7 @@
 #include <mach/tegra20-pmc.h>
 #include <mach/tegra30-car.h>
 #include <mach/tegra30-flow.h>
+#include <mach/tegra124-car.h>
 
 /* instruct the PMIC to enable the CPU power rail */
 static void enable_maincomplex_powerrail(void)
@@ -107,6 +108,14 @@ static void init_pllx(void)
 
 	chiptype = tegra_get_chiptype();
 
+	/* disable IDDQ on T124 */
+	if (chiptype == TEGRA124) {
+		reg = readl(TEGRA_CLK_RESET_BASE + CRC_PLLX_MISC_3);
+		reg &= ~CRC_PLLX_MISC_3_IDDQ;
+		writel(reg, TEGRA_CLK_RESET_BASE + CRC_PLLX_MISC_3);
+		tegra_ll_delay_usec(2);
+	}
+
 	osc_freq = (readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL) &
 		    CRC_OSC_CTRL_OSC_FREQ_MASK) >> CRC_OSC_CTRL_OSC_FREQ_SHIFT;
 
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 12/30] tegra: power up additional partitions on Tegra124
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (10 preceding siblings ...)
  2014-06-03 20:34 ` [PATCH 11/30] tegra: disable IDDQ for PLL_X on Tegra124 Lucas Stach
@ 2014-06-03 20:34 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 13/30] tegra: fix MESLECT clock enable Lucas Stach
                   ` (18 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:34 UTC (permalink / raw)
  To: barebox

Those 3 are needed to power CPU0 from the CPUG cluster.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/tegra20-pmc.h |  4 ++++
 arch/arm/mach-tegra/tegra_avp_init.c           | 24 ++++++++++++++++++------
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-tegra/include/mach/tegra20-pmc.h b/arch/arm/mach-tegra/include/mach/tegra20-pmc.h
index 3a05e0f..30ac065 100644
--- a/arch/arm/mach-tegra/include/mach/tegra20-pmc.h
+++ b/arch/arm/mach-tegra/include/mach/tegra20-pmc.h
@@ -66,4 +66,8 @@
 #define PMC_PWRGATE_STATUS_TD		(1 << 1)
 #define PMC_PWRGATE_STATUS_CPU		(1 << 0)
 
+#define PMC_PARTID_CRAIL		0
+#define PMC_PARTID_CE0			14
+#define PMC_PARTID_C0NC			15
+
 #define PMC_SCRATCH(i)			(0x050 + 0x4*i)
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c
index cc8b0e2..3d21963 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -197,26 +197,38 @@ static void start_cpu0_clocks(void)
 	tegra_ll_delay_usec(300);
 }
 
-static void maincomplex_powerup(void)
+static void power_up_partition(u32 partid)
 {
 	u32 reg;
 
-	if (!(readl(TEGRA_PMC_BASE + PMC_PWRGATE_STATUS) &
-	      PMC_PWRGATE_STATUS_CPU)) {
-		writel(PMC_PWRGATE_TOGGLE_START | PMC_PWRGATE_TOGGLE_PARTID_CPU,
+	if (!(readl(TEGRA_PMC_BASE + PMC_PWRGATE_STATUS) & (1 << partid))) {
+		writel(PMC_PWRGATE_TOGGLE_START | partid,
 		       TEGRA_PMC_BASE + PMC_PWRGATE_TOGGLE);
 
 		while (!(readl(TEGRA_PMC_BASE + PMC_PWRGATE_STATUS) &
-			 PMC_PWRGATE_STATUS_CPU));
+			(1 << partid)));
 
 		reg = readl(TEGRA_PMC_BASE + PMC_REMOVE_CLAMPING_CMD);
-		reg |= PMC_REMOVE_CLAMPING_CMD_CPU;
+		reg |= (1 << partid);
 		writel(reg, TEGRA_PMC_BASE + PMC_REMOVE_CLAMPING_CMD);
 
 		tegra_ll_delay_usec(1000);
 	}
 }
 
+static void maincomplex_powerup(void)
+{
+	/* main cpu rail */
+	power_up_partition(PMC_PARTID_CRAIL);
+
+	if (tegra_get_chiptype() >= TEGRA114) {
+		/* fast cluster uncore part */
+		power_up_partition(PMC_PARTID_C0NC);
+		/* fast cluster cpu0 part */
+		power_up_partition(PMC_PARTID_CE0);
+	}
+}
+
 static void tegra_cluster_switch_hp(void)
 {
 	u32 reg;
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 13/30] tegra: fix MESLECT clock enable
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (11 preceding siblings ...)
  2014-06-03 20:34 ` [PATCH 12/30] tegra: power up additional partitions " Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 14/30] tegra: change cpu internal reset layout for Tegra124 Lucas Stach
                   ` (17 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

Don't disable clk to unrelated devices in the process.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/tegra30-car.h | 2 ++
 arch/arm/mach-tegra/tegra_avp_init.c           | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/include/mach/tegra30-car.h b/arch/arm/mach-tegra/include/mach/tegra30-car.h
index 286a2a6..c8f6c9f 100644
--- a/arch/arm/mach-tegra/include/mach/tegra30-car.h
+++ b/arch/arm/mach-tegra/include/mach/tegra30-car.h
@@ -31,3 +31,5 @@
 #define CRC_RST_DEV_V_MSELECT		(1 << 3)
 
 #define CRC_RST_DEV_V_CLR		0x434
+
+#define CRC_CLK_OUT_ENB_V_SET		0x440
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c
index 3d21963..d25c1dd 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -177,7 +177,7 @@ static void start_cpu0_clocks(void)
 		       CRC_CLK_SOURCE_MSEL_SRC_SHIFT),
 		       TEGRA_CLK_RESET_BASE + CRC_CLK_SOURCE_MSEL);
 		writel(CRC_CLK_OUT_ENB_V_MSELECT,
-		       TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_V);
+		       TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_V_SET);
 		tegra_ll_delay_usec(3);
 		writel(CRC_RST_DEV_V_MSELECT,
 		       TEGRA_CLK_RESET_BASE + CRC_RST_DEV_V_CLR);
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 14/30] tegra: change cpu internal reset layout for Tegra124
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (12 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 13/30] tegra: fix MESLECT clock enable Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 15/30] tegra: add Tegra124 PLL_X rate setup Lucas Stach
                   ` (16 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/tegra_avp_init.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c
index d25c1dd..61cfa05 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -43,8 +43,12 @@ static void assert_maincomplex_reset(int num_cores)
 	u32 mask = 0;
 	int i;
 
-	for (i = 0; i < num_cores; i++)
-		mask |= 0x1111 << i;
+	for (i = 0; i < num_cores; i++) {
+		if (tegra_get_chiptype() >= TEGRA114)
+			mask |= 0x111001 << i;
+		else
+			mask |= 0x1111 << i;
+	}
 
 	writel(mask, TEGRA_CLK_RESET_BASE + CRC_RST_CPU_CMPLX_SET);
 	writel(CRC_RST_DEV_L_CPU, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_L_SET);
@@ -53,7 +57,14 @@ static void assert_maincomplex_reset(int num_cores)
 /* release reset state of the first core of the main CPU complex */
 static void deassert_cpu0_reset(void)
 {
-	writel(0x1111, TEGRA_CLK_RESET_BASE + CRC_RST_CPU_CMPLX_CLR);
+	u32 reg;
+
+	if (tegra_get_chiptype() >= TEGRA114)
+		reg = 0x21fff00f;
+	else
+		reg = 0x1111;
+
+	writel(reg, TEGRA_CLK_RESET_BASE + CRC_RST_CPU_CMPLX_CLR);
 	writel(CRC_RST_DEV_L_CPU, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_L_CLR);
 }
 
@@ -185,7 +196,7 @@ static void start_cpu0_clocks(void)
 
 	/* deassert clock stop for cpu 0 */
 	reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX);
-	reg &= ~CRC_CLK_CPU_CMPLX_CPU0_CLK_STP;
+	reg &= ~(0xf << 8);
 	writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX);
 
 	/* enable main CPU complex clock */
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 15/30] tegra: add Tegra124 PLL_X rate setup
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (13 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 14/30] tegra: change cpu internal reset layout for Tegra124 Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 16/30] tegra: apply cluster switch logic to all SoCs >=T30 Lucas Stach
                   ` (15 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/tegra_avp_init.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c
index 61cfa05..be35843 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -104,6 +104,14 @@ static struct pll_config pllx_config_table[][4] = {
 		{600,  12, 0, 8 },
 		{600,  26, 0, 8 },
 	}, /* TEGRA 30 */
+	{
+	}, /* TEGRA 114 */
+	{
+		{ 108,  1, 1, 0 },
+		{  73,  1, 1, 0 },
+		{ 116,  1, 1, 0 },
+		{ 108,  2, 1, 0 },
+	}, /* TEGRA 124 */
 };
 
 static void init_pllx(void)
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 16/30] tegra: apply cluster switch logic to all SoCs >=T30
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (14 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 15/30] tegra: add Tegra124 PLL_X rate setup Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 17/30] tegra: hardcode entry address for main cluster Lucas Stach
                   ` (14 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/tegra_avp_init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c
index be35843..63ccfb5 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -262,7 +262,7 @@ void tegra_avp_reset_vector(uint32_t boarddata)
 	int num_cores;
 
 	/* we want to bring up the high performance CPU complex */
-	if (tegra_get_chiptype() == TEGRA30)
+	if (tegra_get_chiptype() >= TEGRA30)
 		tegra_cluster_switch_hp();
 
 	/* get the number of cores in the main CPU complex of the current SoC */
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 17/30] tegra: hardcode entry address for main cluster
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (15 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 16/30] tegra: apply cluster switch logic to all SoCs >=T30 Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 18/30] tegra: setup L2 cache on Tegra124 Lucas Stach
                   ` (13 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

I don't know why get_runtime_offset fails on T124 yet,
but this is a safe workaround, with the nice side-effect
of fixing second stage barebox loading.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/tegra_avp_init.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c
index 63ccfb5..619fecf 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -260,6 +260,10 @@ static void tegra_cluster_switch_hp(void)
 void tegra_avp_reset_vector(uint32_t boarddata)
 {
 	int num_cores;
+	unsigned int entry_address = 0;
+
+	if (tegra_cpu_is_maincomplex())
+		tegra_maincomplex_entry();
 
 	/* we want to bring up the high performance CPU complex */
 	if (tegra_get_chiptype() >= TEGRA30)
@@ -274,8 +278,18 @@ void tegra_avp_reset_vector(uint32_t boarddata)
 	stop_maincomplex_clocks(num_cores);
 
 	/* set start address for the main CPU complex processors */
-	writel(tegra_maincomplex_entry - get_runtime_offset(),
-	       TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
+	switch (tegra_get_chiptype()) {
+	case TEGRA20:
+		entry_address = 0x108000;
+		break;
+	case TEGRA30:
+	case TEGRA124:
+		entry_address = 0x80108000;
+		break;
+	default:
+		break;
+	}
+	writel(entry_address, TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
 
 	/* put boarddata in scratch reg, for main CPU to fetch after startup */
 	writel(boarddata, TEGRA_PMC_BASE + PMC_SCRATCH(10));
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 18/30] tegra: setup L2 cache on Tegra124
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (16 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 17/30] tegra: hardcode entry address for main cluster Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 19/30] tegra: add architectural timer init Lucas Stach
                   ` (12 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

Set SRAM latency to 3 clock cycles.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/tegra_maincomplex_init.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/tegra_maincomplex_init.c b/arch/arm/mach-tegra/tegra_maincomplex_init.c
index 83ad33d..17490a4 100644
--- a/arch/arm/mach-tegra/tegra_maincomplex_init.c
+++ b/arch/arm/mach-tegra/tegra_maincomplex_init.c
@@ -25,6 +25,8 @@
 void tegra_maincomplex_entry(void)
 {
 	uint32_t rambase, ramsize;
+	enum tegra_chiptype chiptype;
+	u32 reg = 0;
 
 	arm_cpu_lowlevel_init();
 
@@ -36,7 +38,16 @@ void tegra_maincomplex_entry(void)
 	       TEGRA_CLK_RESET_BASE + CRC_CCLK_BURST_POLICY);
 	writel(CRC_SUPER_CDIV_ENB, TEGRA_CLK_RESET_BASE + CRC_SUPER_CCLK_DIV);
 
-	switch (tegra_get_chiptype()) {
+	chiptype = tegra_get_chiptype();
+
+	if (chiptype >= TEGRA114) {
+		asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
+		reg &= ~7;
+		reg |= 2;
+		asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
+	}
+
+	switch (chiptype) {
 	case TEGRA20:
 		rambase = 0x0;
 		ramsize = tegra20_get_ramsize();
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 19/30] tegra: add architectural timer init
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (17 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 18/30] tegra: setup L2 cache on Tegra124 Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 20/30] tegra: add Tegra124 Kconfig symbol Lucas Stach
                   ` (11 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

If the bootloader doesn't init the architectural timer
on Cortex A15 Linux falls over when trying to boot.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/iomap.h           |  3 +++
 arch/arm/mach-tegra/include/mach/tegra114-sysctr.h | 30 ++++++++++++++++++++++
 arch/arm/mach-tegra/tegra20.c                      | 25 ++++++++++++++++++
 3 files changed, 58 insertions(+)
 create mode 100644 arch/arm/mach-tegra/include/mach/tegra114-sysctr.h

diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index b74e5d2..cdaab6a 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -257,6 +257,9 @@
 #define TEGRA_CSITE_BASE		0x70040000
 #define TEGRA_CSITE_SIZE		SZ_256K
 
+#define TEGRA_SYSCTR0_BASE		0x700F0000
+#define TEGRA_SYSCTR0_SIZE		SZ_64K
+
 #define TEGRA_USB_BASE			0xC5000000
 #define TEGRA_USB_SIZE			SZ_16K
 
diff --git a/arch/arm/mach-tegra/include/mach/tegra114-sysctr.h b/arch/arm/mach-tegra/include/mach/tegra114-sysctr.h
new file mode 100644
index 0000000..45d17c4
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra114-sysctr.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Register definitions */
+#define TEGRA_SYSCTR0_CNTCR		0x00
+#define TEGRA_SYSCTR0_CNTCR_ENABLE	(1 << 0)
+#define TEGRA_SYSCTR0_CNTCR_HDBG	(1 << 1)
+
+#define TEGRA_SYSCTR0_CNTSR		0x04
+
+#define TEGRA_SYSCTR0_CNTCV0		0x08
+
+#define TEGRA_SYSCTR0_CNTCV1		0x0c
+
+#define TEGRA_SYSCTR0_CNTFID0		0x20
+
+#define TEGRA_SYSCTR0_CNTFID1		0x24
diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
index 752bbb0..dcc55ae 100644
--- a/arch/arm/mach-tegra/tegra20.c
+++ b/arch/arm/mach-tegra/tegra20.c
@@ -20,6 +20,7 @@
 #include <asm/memory.h>
 #include <mach/iomap.h>
 #include <mach/lowlevel.h>
+#include <mach/tegra114-sysctr.h>
 
 static struct NS16550_plat debug_uart = {
 	.shift = 2,
@@ -84,3 +85,27 @@ static int tegra30_mem_init(void)
 	return 0;
 }
 mem_initcall(tegra30_mem_init);
+
+static int tegra114_architected_timer_init(void)
+{
+	u32 freq, reg;
+
+	if (!of_machine_is_compatible("nvidia,tegra114") &&
+	    !of_machine_is_compatible("nvidia,tegra124"))
+		return 0;
+
+	freq = tegra_get_osc_clock();
+
+	/* ARM CNTFRQ */
+	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
+
+	/* Tegra specific SYSCTR */
+	writel(freq, TEGRA_SYSCTR0_BASE + TEGRA_SYSCTR0_CNTFID0);
+
+	reg = readl(TEGRA_SYSCTR0_BASE + TEGRA_SYSCTR0_CNTCR);
+	reg |= TEGRA_SYSCTR0_CNTCR_ENABLE | TEGRA_SYSCTR0_CNTCR_HDBG;
+	writel(reg, TEGRA_SYSCTR0_BASE + TEGRA_SYSCTR0_CNTCR);
+
+	return 0;
+}
+coredevice_initcall(tegra114_architected_timer_init);
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 20/30] tegra: add Tegra124 Kconfig symbol
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (18 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 19/30] tegra: add architectural timer init Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 21/30] pinctrl: tegra30: introduce drvdata Lucas Stach
                   ` (10 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 5e2b4cb..a895fd7 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -50,6 +50,9 @@ config ARCH_TEGRA_3x_SOC
 	bool
 	select PINCTRL_TEGRA30
 
+config ARCH_TEGRA_124_SOC
+	bool
+
 menu "select Tegra boards to be built"
 
 config MACH_TORADEX_COLIBRI_T20
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 21/30] pinctrl: tegra30: introduce drvdata
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (19 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 20/30] tegra: add Tegra124 Kconfig symbol Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 22/30] pinctrl: tegra: add Tegra124 support Lucas Stach
                   ` (9 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

Access pin and drivegroups through a drvdata pointer.
This allows to insert other groups for SoCs with a
similar bit layout easily.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 drivers/pinctrl/pinctrl-tegra30.c | 48 +++++++++++++++++++++++++++------------
 1 file changed, 34 insertions(+), 14 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index 888bf04..d1e87a7 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -23,21 +23,24 @@
 #include <malloc.h>
 #include <pinctrl.h>
 
+struct pinctrl_tegra30_drvdata;
+
 struct pinctrl_tegra30 {
 	struct {
 		u32 __iomem *ctrl;
 		u32 __iomem *mux;
 	} regs;
 	struct pinctrl_device pinctrl;
+	struct pinctrl_tegra30_drvdata *drvdata;
 };
 
-struct tegra30_pingroup {
+struct tegra_pingroup {
 	const char *name;
 	const char *funcs[4];
 	u16 reg;
 };
 
-struct tegra30_drive_pingroup {
+struct tegra_drive_pingroup {
 	const char *name;
 	u16 reg;
 	u32 hsm_bit:5;
@@ -54,6 +57,13 @@ struct tegra30_drive_pingroup {
 	u32 slwf_width:6;
 };
 
+struct pinctrl_tegra30_drvdata {
+	const struct tegra_pingroup *pingrps;
+	const unsigned int num_pingrps;
+	const struct tegra_drive_pingroup *drvgrps;
+	const unsigned int num_drvgrps;
+};
+
 #define PG(pg_name, f0, f1, f2, f3, offset)		\
 	{						\
 		.name = #pg_name,			\
@@ -80,7 +90,7 @@ struct tegra30_drive_pingroup {
 		.slwf_width = slwf_w,			\
 	}
 
-static const struct tegra30_pingroup tegra30_groups[] = {
+static const struct tegra_pingroup tegra30_pin_groups[] = {
 	/* name,                 f0,        f1,        f2,        f3,           reg  */
 	PG(clk_32k_out_pa0,      blink,     rsvd2,     rsvd3,     rsvd4,        0x31c),
 	PG(uart3_cts_n_pa1,      uartc,     rsvd2,     gmi,       rsvd4,        0x17c),
@@ -333,7 +343,7 @@ static const struct tegra30_pingroup tegra30_groups[] = {
 	PG(pwr_int_n,            pwr_int_n, rsvd2,     rsvd3,     rsvd4,        0x32c),
 };
 
-static const struct tegra30_drive_pingroup tegra30_drive_groups[] = {
+static const struct tegra_drive_pingroup tegra30_drive_groups[] = {
 	DRV_PG(ao1,   0x868,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
 	DRV_PG(ao2,   0x86c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
 	DRV_PG(at1,   0x870,  2,  3,  4,  14,  5,  19,  5,  24,  2,  28,  2),
@@ -377,11 +387,18 @@ static const struct tegra30_drive_pingroup tegra30_drive_groups[] = {
 	DRV_PG(vi1,   0x8c8, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
 };
 
+static const struct pinctrl_tegra30_drvdata tegra30_drvdata = {
+	.pingrps = tegra30_pin_groups,
+	.num_pingrps = ARRAY_SIZE(tegra30_pin_groups),
+	.drvgrps = tegra30_drive_groups,
+	.num_drvgrps = ARRAY_SIZE(tegra30_drive_groups),
+};
+
 static int pinctrl_tegra30_set_drvstate(struct pinctrl_tegra30 *ctrl,
                                         struct device_node *np)
 {
 	const char *pins = NULL;
-	const struct tegra30_drive_pingroup *group = NULL;
+	const struct tegra_drive_pingroup *group = NULL;
 	int hsm = -1, schmitt = -1, pds = -1, pus = -1, srr = -1, srf = -1;
 	int i;
 	u32 __iomem *regaddr;
@@ -390,14 +407,14 @@ static int pinctrl_tegra30_set_drvstate(struct pinctrl_tegra30 *ctrl,
 	if (of_property_read_string(np, "nvidia,pins", &pins))
 		return 0;
 
-	for (i = 0; i < ARRAY_SIZE(tegra30_drive_groups); i++) {
-		if (!strcmp(pins, tegra30_drive_groups[i].name)) {
-			group = &tegra30_drive_groups[i];
+	for (i = 0; i < ctrl->drvdata->num_drvgrps; i++) {
+		if (!strcmp(pins, ctrl->drvdata->drvgrps[i].name)) {
+			group = &ctrl->drvdata->drvgrps[i];
 			break;
 		}
 	}
 	/* if no matching drivegroup is found */
-	if (i == ARRAY_SIZE(tegra30_groups))
+	if (i == ctrl->drvdata->num_drvgrps)
 		return 0;
 
 	regaddr = ctrl->regs.ctrl + (group->reg >> 2);
@@ -529,7 +546,7 @@ static int pinctrl_tegra30_set_state(struct pinctrl_device *pdev,
 	struct device_node *childnode;
 	int pull = -1, tri = -1, in = -1, od = -1, ior = -1, i, j, k;
 	const char *pins, *func = NULL;
-	const struct tegra30_pingroup *group;
+	const struct tegra_pingroup *group = NULL;
 
 	/*
 	 * At first look if the node we are pointed at has children,
@@ -551,14 +568,14 @@ static int pinctrl_tegra30_set_state(struct pinctrl_device *pdev,
 		if (of_property_read_string_index(np, "nvidia,pins", i, &pins))
 			break;
 
-		for (j = 0; j < ARRAY_SIZE(tegra30_groups); j++) {
-			if (!strcmp(pins, tegra30_groups[j].name)) {
-				group = &tegra30_groups[j];
+		for (j = 0; j < ctrl->drvdata->num_pingrps; j++) {
+			if (!strcmp(pins, ctrl->drvdata->pingrps[j].name)) {
+				group = &ctrl->drvdata->pingrps[j];
 				break;
 			}
 		}
 		/* if no matching pingroup is found */
-		if (j == ARRAY_SIZE(tegra30_groups)) {
+		if (j == ctrl->drvdata->num_pingrps) {
 			/* see if we can find a drivegroup */
 			if (pinctrl_tegra30_set_drvstate(ctrl, np))
 				continue;
@@ -629,6 +646,8 @@ static int pinctrl_tegra30_probe(struct device_d *dev)
 		}
 	}
 
+	dev_get_drvdata(dev, (unsigned long *)&ctrl->drvdata);
+
 	ctrl->pinctrl.dev = dev;
 	ctrl->pinctrl.ops = &pinctrl_tegra30_ops;
 
@@ -642,6 +661,7 @@ static int pinctrl_tegra30_probe(struct device_d *dev)
 static __maybe_unused struct of_device_id pinctrl_tegra30_dt_ids[] = {
 	{
 		.compatible = "nvidia,tegra30-pinmux",
+		.data = (unsigned long)&tegra30_drvdata,
 	}, {
 		/* sentinel */
 	}
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 22/30] pinctrl: tegra: add Tegra124 support
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (20 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 21/30] pinctrl: tegra30: introduce drvdata Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 23/30] clk: tegra: allow variable sized muxes Lucas Stach
                   ` (8 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

We can reuse the Tegra30 pinctrl driver, as the bit
layout is the same. Just add the pin and drivegroups
and some compile-time magic to avoid bloat.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/Kconfig       |   1 +
 drivers/pinctrl/Kconfig           |   2 +-
 drivers/pinctrl/pinctrl-tegra30.c | 251 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 253 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index a895fd7..ea2e045 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -52,6 +52,7 @@ config ARCH_TEGRA_3x_SOC
 
 config ARCH_TEGRA_124_SOC
 	bool
+	select PINCTRL_TEGRA30
 
 menu "select Tegra boards to be built"
 
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b9b66f9..421525b 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -45,4 +45,4 @@ config PINCTRL_TEGRA30
 	select PINCTRL
 	bool
 	help
-	  The pinmux controller found on the Tegra 30 line of SoCs.
+	  The pinmux controller found on the Tegra 30+ line of SoCs.
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index d1e87a7..5cacfae 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -394,6 +394,250 @@ static const struct pinctrl_tegra30_drvdata tegra30_drvdata = {
 	.num_drvgrps = ARRAY_SIZE(tegra30_drive_groups),
 };
 
+static const struct tegra_pingroup tegra124_pin_groups[] = {
+	PG(ulpi_data0_po1,         spi3,       hsi,        uarta,        ulpi,       0x000),
+	PG(ulpi_data1_po2,         spi3,       hsi,        uarta,        ulpi,       0x004),
+	PG(ulpi_data2_po3,         spi3,       hsi,        uarta,        ulpi,       0x008),
+	PG(ulpi_data3_po4,         spi3,       hsi,        uarta,        ulpi,       0x00c),
+	PG(ulpi_data4_po5,         spi2,       hsi,        uarta,        ulpi,       0x010),
+	PG(ulpi_data5_po6,         spi2,       hsi,        uarta,        ulpi,       0x014),
+	PG(ulpi_data6_po7,         spi2,       hsi,        uarta,        ulpi,       0x018),
+	PG(ulpi_data7_po0,         spi2,       hsi,        uarta,        ulpi,       0x01c),
+	PG(ulpi_clk_py0,           spi1,       spi5,       uartd,        ulpi,       0x020),
+	PG(ulpi_dir_py1,           spi1,       spi5,       uartd,        ulpi,       0x024),
+	PG(ulpi_nxt_py2,           spi1,       spi5,       uartd,        ulpi,       0x028),
+	PG(ulpi_stp_py3,           spi1,       spi5,       uartd,        ulpi,       0x02c),
+	PG(dap3_fs_pp0,            i2s2,       spi5,       displaya,     displayb,   0x030),
+	PG(dap3_din_pp1,           i2s2,       spi5,       displaya,     displayb,   0x034),
+	PG(dap3_dout_pp2,          i2s2,       spi5,       displaya,     rsvd4,      0x038),
+	PG(dap3_sclk_pp3,          i2s2,       spi5,       rsvd3,        displayb,   0x03c),
+	PG(pv0,                    rsvd1,      rsvd2,      rsvd3,        rsvd4,      0x040),
+	PG(pv1,                    rsvd1,      rsvd2,      rsvd3,        rsvd4,      0x044),
+	PG(sdmmc1_clk_pz0,         sdmmc1,     clk12,      rsvd3,        rsvd4,      0x048),
+	PG(sdmmc1_cmd_pz1,         sdmmc1,     spdif,      spi4,         uarta,      0x04c),
+	PG(sdmmc1_dat3_py4,        sdmmc1,     spdif,      spi4,         uarta,      0x050),
+	PG(sdmmc1_dat2_py5,        sdmmc1,     pwm0,       spi4,         uarta,      0x054),
+	PG(sdmmc1_dat1_py6,        sdmmc1,     pwm1,       spi4,         uarta,      0x058),
+	PG(sdmmc1_dat0_py7,        sdmmc1,     rsvd2,      spi4,         uarta,      0x05c),
+	PG(clk2_out_pw5,           extperiph2, rsvd2,      rsvd3,        rsvd4,      0x068),
+	PG(clk2_req_pcc5,          dap,        rsvd2,      rsvd3,        rsvd4,      0x06c),
+	PG(hdmi_int_pn7,           rsvd1,      rsvd2,      rsvd3,        rsvd4,      0x110),
+	PG(ddc_scl_pv4,            i2c4,       rsvd2,      rsvd3,        rsvd4,      0x114),
+	PG(ddc_sda_pv5,            i2c4,       rsvd2,      rsvd3,        rsvd4,      0x118),
+	PG(uart2_rxd_pc3,          irda,       spdif,      uarta,        spi4,       0x164),
+	PG(uart2_txd_pc2,          irda,       spdif,      uarta,        spi4,       0x168),
+	PG(uart2_rts_n_pj6,        uarta,      uartb,      gmi,          spi4,       0x16c),
+	PG(uart2_cts_n_pj5,        uarta,      uartb,      gmi,          spi4,       0x170),
+	PG(uart3_txd_pw6,          uartc,      rsvd2,      gmi,          spi4,       0x174),
+	PG(uart3_rxd_pw7,          uartc,      rsvd2,      gmi,          spi4,       0x178),
+	PG(uart3_cts_n_pa1,        uartc,      sdmmc1,     dtv,          gmi,        0x17c),
+	PG(uart3_rts_n_pc0,        uartc,      pwm0,       dtv,          gmi,        0x180),
+	PG(pu0,                    owr,        uarta,      gmi,          rsvd4,      0x184),
+	PG(pu1,                    rsvd1,      uarta,      gmi,          rsvd4,      0x188),
+	PG(pu2,                    rsvd1,      uarta,      gmi,          rsvd4,      0x18c),
+	PG(pu3,                    pwm0,       uarta,      gmi,          displayb,   0x190),
+	PG(pu4,                    pwm1,       uarta,      gmi,          displayb,   0x194),
+	PG(pu5,                    pwm2,       uarta,      gmi,          displayb,   0x198),
+	PG(pu6,                    pwm3,       uarta,      rsvd3,        gmi,        0x19c),
+	PG(gen1_i2c_sda_pc5,       i2c1,       rsvd2,      rsvd3,        rsvd4,      0x1a0),
+	PG(gen1_i2c_scl_pc4,       i2c1,       rsvd2,      rsvd3,        rsvd4,      0x1a4),
+	PG(dap4_fs_pp4,            i2s3,       gmi,        dtv,          rsvd4,      0x1a8),
+	PG(dap4_din_pp5,           i2s3,       gmi,        rsvd3,        rsvd4,      0x1ac),
+	PG(dap4_dout_pp6,          i2s3,       gmi,        dtv,          rsvd4,      0x1b0),
+	PG(dap4_sclk_pp7,          i2s3,       gmi,        rsvd3,        rsvd4,      0x1b4),
+	PG(clk3_out_pee0,          extperiph3, rsvd2,      rsvd3,        rsvd4,      0x1b8),
+	PG(clk3_req_pee1,          dev3,       rsvd2,      rsvd3,        rsvd4,      0x1bc),
+	PG(pc7,                    rsvd1,      rsvd2,      gmi,          gmi_alt,    0x1c0),
+	PG(pi5,                    sdmmc2,     rsvd2,      gmi,          rsvd4,      0x1c4),
+	PG(pi7,                    rsvd1,      trace,      gmi,          dtv,        0x1c8),
+	PG(pk0,                    rsvd1,      sdmmc3,     gmi,          soc,        0x1cc),
+	PG(pk1,                    sdmmc2,     trace,      gmi,          rsvd4,      0x1d0),
+	PG(pj0,                    rsvd1,      rsvd2,      gmi,          usb,        0x1d4),
+	PG(pj2,                    rsvd1,      rsvd2,      gmi,          soc,        0x1d8),
+	PG(pk3,                    sdmmc2,     trace,      gmi,          ccla,       0x1dc),
+	PG(pk4,                    sdmmc2,     rsvd2,      gmi,          gmi_alt,    0x1e0),
+	PG(pk2,                    rsvd1,      rsvd2,      gmi,          rsvd4,      0x1e4),
+	PG(pi3,                    rsvd1,      rsvd2,      gmi,          spi4,       0x1e8),
+	PG(pi6,                    rsvd1,      rsvd2,      gmi,          sdmmc2,     0x1ec),
+	PG(pg0,                    rsvd1,      rsvd2,      gmi,          rsvd4,      0x1f0),
+	PG(pg1,                    rsvd1,      rsvd2,      gmi,          rsvd4,      0x1f4),
+	PG(pg2,                    rsvd1,      trace,      gmi,          rsvd4,      0x1f8),
+	PG(pg3,                    rsvd1,      trace,      gmi,          rsvd4,      0x1fc),
+	PG(pg4,                    rsvd1,      tmds,       gmi,          spi4,       0x200),
+	PG(pg5,                    rsvd1,      rsvd2,      gmi,          spi4,       0x204),
+	PG(pg6,                    rsvd1,      rsvd2,      gmi,          spi4,       0x208),
+	PG(pg7,                    rsvd1,      rsvd2,      gmi,          spi4,       0x20c),
+	PG(ph0,                    pwm0,       trace,      gmi,          dtv,        0x210),
+	PG(ph1,                    pwm1,       tmds,       gmi,          displaya,   0x214),
+	PG(ph2,                    pwm2,       tmds,       gmi,          cldvfs,     0x218),
+	PG(ph3,                    pwm3,       spi4,       gmi,          cldvfs,     0x21c),
+	PG(ph4,                    sdmmc2,     rsvd2,      gmi,          rsvd4,      0x220),
+	PG(ph5,                    sdmmc2,     rsvd2,      gmi,          rsvd4,      0x224),
+	PG(ph6,                    sdmmc2,     trace,      gmi,          dtv,        0x228),
+	PG(ph7,                    sdmmc2,     trace,      gmi,          dtv,        0x22c),
+	PG(pj7,                    uartd,      rsvd2,      gmi,          gmi_alt,    0x230),
+	PG(pb0,                    uartd,      rsvd2,      gmi,          rsvd4,      0x234),
+	PG(pb1,                    uartd,      rsvd2,      gmi,          rsvd4,      0x238),
+	PG(pk7,                    uartd,      rsvd2,      gmi,          rsvd4,      0x23c),
+	PG(pi0,                    rsvd1,      rsvd2,      gmi,          rsvd4,      0x240),
+	PG(pi1,                    rsvd1,      rsvd2,      gmi,          rsvd4,      0x244),
+	PG(pi2,                    sdmmc2,     trace,      gmi,          rsvd4,      0x248),
+	PG(pi4,                    spi4,       trace,      gmi,          displaya,   0x24c),
+	PG(gen2_i2c_scl_pt5,       i2c2,       rsvd2,      gmi,          rsvd4,      0x250),
+	PG(gen2_i2c_sda_pt6,       i2c2,       rsvd2,      gmi,          rsvd4,      0x254),
+	PG(sdmmc4_clk_pcc4,        sdmmc4,     rsvd2,      gmi,          rsvd4,      0x258),
+	PG(sdmmc4_cmd_pt7,         sdmmc4,     rsvd2,      gmi,          rsvd4,      0x25c),
+	PG(sdmmc4_dat0_paa0,       sdmmc4,     spi3,       gmi,          rsvd4,      0x260),
+	PG(sdmmc4_dat1_paa1,       sdmmc4,     spi3,       gmi,          rsvd4,      0x264),
+	PG(sdmmc4_dat2_paa2,       sdmmc4,     spi3,       gmi,          rsvd4,      0x268),
+	PG(sdmmc4_dat3_paa3,       sdmmc4,     spi3,       gmi,          rsvd4,      0x26c),
+	PG(sdmmc4_dat4_paa4,       sdmmc4,     spi3,       gmi,          rsvd4,      0x270),
+	PG(sdmmc4_dat5_paa5,       sdmmc4,     spi3,       rsvd3,        rsvd4,      0x274),
+	PG(sdmmc4_dat6_paa6,       sdmmc4,     spi3,       gmi,          rsvd4,      0x278),
+	PG(sdmmc4_dat7_paa7,       sdmmc4,     rsvd2,      gmi,          rsvd4,      0x27c),
+	PG(cam_mclk_pcc0,          vi,         vi_alt1,    vi_alt3,      sdmmc2,     0x284),
+	PG(pcc1,                   i2s4,       rsvd2,      rsvd3,        sdmmc2,     0x288),
+	PG(pbb0,                   vgp6,       vimclk2,    sdmmc2,       vimclk2_alt,0x28c),
+	PG(cam_i2c_scl_pbb1,       vgp1,       i2c3,       rsvd3,        sdmmc2,     0x290),
+	PG(cam_i2c_sda_pbb2,       vgp2,       i2c3,       rsvd3,        sdmmc2,     0x294),
+	PG(pbb3,                   vgp3,       displaya,   displayb,     sdmmc2,     0x298),
+	PG(pbb4,                   vgp4,       displaya,   displayb,     sdmmc2,     0x29c),
+	PG(pbb5,                   vgp5,       displaya,   rsvd3,        sdmmc2,     0x2a0),
+	PG(pbb6,                   i2s4,       rsvd2,      displayb,     sdmmc2,     0x2a4),
+	PG(pbb7,                   i2s4,       rsvd2,      rsvd3,        sdmmc2,     0x2a8),
+	PG(pcc2,                   i2s4,       rsvd2,      sdmmc3,       sdmmc2,     0x2ac),
+	PG(jtag_rtck,              rtck,       rsvd2,      rsvd3,        rsvd4,      0x2b0),
+	PG(pwr_i2c_scl_pz6,        i2cpwr,     rsvd2,      rsvd3,        rsvd4,      0x2b4),
+	PG(pwr_i2c_sda_pz7,        i2cpwr,     rsvd2,      rsvd3,        rsvd4,      0x2b8),
+	PG(kb_row0_pr0,            kbc,        rsvd2,      rsvd3,        rsvd4,      0x2bc),
+	PG(kb_row1_pr1,            kbc,        rsvd2,      rsvd3,        rsvd4,      0x2c0),
+	PG(kb_row2_pr2,            kbc,        rsvd2,      rsvd3,        rsvd4,      0x2c4),
+	PG(kb_row3_pr3,            kbc,        displaya,   sys,          displayb,   0x2c8),
+	PG(kb_row4_pr4,            kbc,        displaya,   rsvd3,        displayb,   0x2cc),
+	PG(kb_row5_pr5,            kbc,        displaya,   rsvd3,        displayb,   0x2d0),
+	PG(kb_row6_pr6,            kbc,        displaya,   displaya_alt, displayb,   0x2d4),
+	PG(kb_row7_pr7,            kbc,        rsvd2,      cldvfs,       uarta,      0x2d8),
+	PG(kb_row8_ps0,            kbc,        rsvd2,      cldvfs,       uarta,      0x2dc),
+	PG(kb_row9_ps1,            kbc,        rsvd2,      rsvd3,        uarta,      0x2e0),
+	PG(kb_row10_ps2,           kbc,        rsvd2,      rsvd3,        uarta,      0x2e4),
+	PG(kb_row11_ps3,           kbc,        rsvd2,      rsvd3,        irda,       0x2e8),
+	PG(kb_row12_ps4,           kbc,        rsvd2,      rsvd3,        irda,       0x2ec),
+	PG(kb_row13_ps5,           kbc,        rsvd2,      spi2,         rsvd4,      0x2f0),
+	PG(kb_row14_ps6,           kbc,        rsvd2,      spi2,         rsvd4,      0x2f4),
+	PG(kb_row15_ps7,           kbc,        soc,        rsvd3,        rsvd4,      0x2f8),
+	PG(kb_col0_pq0,            kbc,        rsvd2,      spi2,         rsvd4,      0x2fc),
+	PG(kb_col1_pq1,            kbc,        rsvd2,      spi2,         rsvd4,      0x300),
+	PG(kb_col2_pq2,            kbc,        rsvd2,      spi2,         rsvd4,      0x304),
+	PG(kb_col3_pq3,            kbc,        displaya,   pwm2,         uarta,      0x308),
+	PG(kb_col4_pq4,            kbc,        owr,        sdmmc3,       uarta,      0x30c),
+	PG(kb_col5_pq5,            kbc,        rsvd2,      sdmmc3,       rsvd4,      0x310),
+	PG(kb_col6_pq6,            kbc,        rsvd2,      spi2,         uartd,      0x314),
+	PG(kb_col7_pq7,            kbc,        rsvd2,      spi2,         uartd,      0x318),
+	PG(clk_32k_out_pa0,        blink,      soc,        rsvd3,        rsvd4,      0x31c),
+	PG(core_pwr_req,           pwron,      rsvd2,      rsvd3,        rsvd4,      0x324),
+	PG(cpu_pwr_req,            cpu,        rsvd2,      rsvd3,        rsvd4,      0x328),
+	PG(pwr_int_n,              pmi,        rsvd2,      rsvd3,        rsvd4,      0x32c),
+	PG(clk_32k_in,             clk,        rsvd2,      rsvd3,        rsvd4,      0x330),
+	PG(owr,                    owr,        rsvd2,      rsvd3,        rsvd4,      0x334),
+	PG(dap1_fs_pn0,            i2s0,       hda,        gmi,          rsvd4,      0x338),
+	PG(dap1_din_pn1,           i2s0,       hda,        gmi,          rsvd4,      0x33c),
+	PG(dap1_dout_pn2,          i2s0,       hda,        gmi,          sata,       0x340),
+	PG(dap1_sclk_pn3,          i2s0,       hda,        gmi,          rsvd4,      0x344),
+	PG(dap_mclk1_req_pee2,     dap,        dap1,       sata,         rsvd4,      0x348),
+	PG(dap_mclk1_pw4,          extperiph1, dap2,       rsvd3,        rsvd4,      0x34c),
+	PG(spdif_in_pk6,           spdif,      rsvd2,      rsvd3,        i2c3,       0x350),
+	PG(spdif_out_pk5,          spdif,      rsvd2,      rsvd3,        i2c3,       0x354),
+	PG(dap2_fs_pa2,            i2s1,       hda,        gmi,          rsvd4,      0x358),
+	PG(dap2_din_pa4,           i2s1,       hda,        gmi,          rsvd4,      0x35c),
+	PG(dap2_dout_pa5,          i2s1,       hda,        gmi,          rsvd4,      0x360),
+	PG(dap2_sclk_pa3,          i2s1,       hda,        gmi,          rsvd4,      0x364),
+	PG(dvfs_pwm_px0,           spi6,       cldvfs,     gmi,          rsvd4,      0x368),
+	PG(gpio_x1_aud_px1,        spi6,       rsvd2,      gmi,          rsvd4,      0x36c),
+	PG(gpio_x3_aud_px3,        spi6,       spi1,       gmi,          rsvd4,      0x370),
+	PG(dvfs_clk_px2,           spi6,       cldvfs,     gmi,          rsvd4,      0x374),
+	PG(gpio_x4_aud_px4,        gmi,        spi1,       spi2,         dap2,       0x378),
+	PG(gpio_x5_aud_px5,        gmi,        spi1,       spi2,         rsvd4,      0x37c),
+	PG(gpio_x6_aud_px6,        spi6,       spi1,       spi2,         gmi,        0x380),
+	PG(gpio_x7_aud_px7,        rsvd1,      spi1,       spi2,         rsvd4,      0x384),
+	PG(sdmmc3_clk_pa6,         sdmmc3,     rsvd2,      rsvd3,        spi3,       0x390),
+	PG(sdmmc3_cmd_pa7,         sdmmc3,     pwm3,       uarta,        spi3,       0x394),
+	PG(sdmmc3_dat0_pb7,        sdmmc3,     rsvd2,      rsvd3,        spi3,       0x398),
+	PG(sdmmc3_dat1_pb6,        sdmmc3,     pwm2,       uarta,        spi3,       0x39c),
+	PG(sdmmc3_dat2_pb5,        sdmmc3,     pwm1,       displaya,     spi3,       0x3a0),
+	PG(sdmmc3_dat3_pb4,        sdmmc3,     pwm0,       displayb,     spi3,       0x3a4),
+	PG(pex_l0_rst_n_pdd1,      pe0,        rsvd2,      rsvd3,        rsvd4,      0x3bc),
+	PG(pex_l0_clkreq_n_pdd2,   pe0,        rsvd2,      rsvd3,        rsvd4,      0x3c0),
+	PG(pex_wake_n_pdd3,        pe,         rsvd2,      rsvd3,        rsvd4,      0x3c4),
+	PG(pex_l1_rst_n_pdd5,      pe1,        rsvd2,      rsvd3,        rsvd4,      0x3cc),
+	PG(pex_l1_clkreq_n_pdd6,   pe1,        rsvd2,      rsvd3,        rsvd4,      0x3d0),
+	PG(hdmi_cec_pee3,          cec,        rsvd2,      rsvd3,        rsvd4,      0x3e0),
+	PG(sdmmc1_wp_n_pv3,        sdmmc1,     clk12,      spi4,         uarta,      0x3e4),
+	PG(sdmmc3_cd_n_pv2,        sdmmc3,     owr,        rsvd3,        rsvd4,      0x3e8),
+	PG(gpio_w2_aud_pw2,        spi6,       rsvd2,      spi2,         i2c1,       0x3ec),
+	PG(gpio_w3_aud_pw3,        spi6,       spi1,       spi2,         i2c1,       0x3f0),
+	PG(usb_vbus_en0_pn4,       usb,        rsvd2,      rsvd3,        rsvd4,      0x3f4),
+	PG(usb_vbus_en1_pn5,       usb,        rsvd2,      rsvd3,        rsvd4,      0x3f8),
+	PG(sdmmc3_clk_lb_in_pee5,  sdmmc3,     rsvd2,      rsvd3,        rsvd4,      0x3fc),
+	PG(sdmmc3_clk_lb_out_pee4, sdmmc3,     rsvd2,      rsvd3,        rsvd4,      0x400),
+	PG(gmi_clk_lb,             sdmmc2,     rsvd2,      gmi,          rsvd4,      0x404),
+	PG(reset_out_n,            rsvd1,      rsvd2,      rsvd3,        reset_out_n,0x408),
+	PG(kb_row16_pt0,           kbc,        rsvd2,      rsvd3,        uartc,      0x40c),
+	PG(kb_row17_pt1,           kbc,        rsvd2,      rsvd3,        uartc,      0x410),
+	PG(usb_vbus_en2_pff1,      usb,        rsvd2,      rsvd3,        rsvd4,      0x414),
+	PG(pff2,                   sata,       rsvd2,      rsvd3,        rsvd4,      0x418),
+	PG(dp_hpd_pff0,            dp,         rsvd2,      rsvd3,        rsvd4,      0x430),
+};
+
+static const struct tegra_drive_pingroup tegra124_drive_groups[] = {
+	DRV_PG(ao1,   0x868,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(ao2,   0x86c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(at1,   0x870,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2),
+	DRV_PG(at2,   0x874,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2),
+	DRV_PG(at3,   0x878,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2),
+	DRV_PG(at4,   0x87c,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2),
+	DRV_PG(at5,   0x880,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
+	DRV_PG(cdev1, 0x884,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(cdev2, 0x888,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(dap1,  0x890,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(dap2,  0x894,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(dap3,  0x898,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(dap4,  0x89c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(dbg,   0x8a0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(sdio3, 0x8b0,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2),
+	DRV_PG(spi,   0x8b4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(uaa,   0x8b8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(uab,   0x8bc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(uart2, 0x8c0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(uart3, 0x8c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(sdio1, 0x8ec,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2),
+	DRV_PG(ddc,   0x8fc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(gma,   0x900,  2,  3,  4,  14,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(gme,   0x910,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
+	DRV_PG(gmf,   0x914,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
+	DRV_PG(gmg,   0x918,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
+	DRV_PG(gmh,   0x91c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
+	DRV_PG(owr,   0x920,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(uda,   0x924,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(gpv,   0x928,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(dev3,  0x92c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(cec,   0x938,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(at6,   0x994,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2),
+	DRV_PG(dap5,  0x998,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(usb_vbus_en, 0x99c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(ao3,   0x9a8,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1),
+	DRV_PG(ao0,   0x9b0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(hv0,   0x9b4,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1),
+	DRV_PG(sdio4, 0x9c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(ao4,   0x9c8,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2),
+};
+
+static const struct pinctrl_tegra30_drvdata tegra124_drvdata = {
+	.pingrps = tegra124_pin_groups,
+	.num_pingrps = ARRAY_SIZE(tegra124_pin_groups),
+	.drvgrps = tegra124_drive_groups,
+	.num_drvgrps = ARRAY_SIZE(tegra124_drive_groups),
+};
+
 static int pinctrl_tegra30_set_drvstate(struct pinctrl_tegra30 *ctrl,
                                         struct device_node *np)
 {
@@ -660,9 +904,16 @@ static int pinctrl_tegra30_probe(struct device_d *dev)
 
 static __maybe_unused struct of_device_id pinctrl_tegra30_dt_ids[] = {
 	{
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
 		.compatible = "nvidia,tegra30-pinmux",
 		.data = (unsigned long)&tegra30_drvdata,
 	}, {
+#endif
+#ifdef CONFIG_ARCH_TEGRA_124_SOC
+		.compatible = "nvidia,tegra124-pinmux",
+		.data = (unsigned long)&tegra124_drvdata,
+	}, {
+#endif
 		/* sentinel */
 	}
 };
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 23/30] clk: tegra: allow variable sized muxes
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (21 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 22/30] pinctrl: tegra: add Tegra124 support Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 24/30] clk: tegra: don't bug out on zero PLL postdiv Lucas Stach
                   ` (7 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

Tegra124 extended the mux by 1bit to allow for
more PLL sources.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 drivers/clk/tegra/clk-periph.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index e4e5412..fd1e2ed 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -21,6 +21,7 @@
 #include <malloc.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/log2.h>
 
 #include "clk.h"
 
@@ -113,6 +114,7 @@ static struct clk *_tegra_clk_register_periph(const char *name,
 {
 	struct tegra_clk_periph *periph;
 	int ret, gate_offs, rst_offs;
+	u8 mux_size = order_base_2(num_parents);
 
 	periph = kzalloc(sizeof(*periph), GFP_KERNEL);
 	if (!periph) {
@@ -121,8 +123,8 @@ static struct clk *_tegra_clk_register_periph(const char *name,
 		goto out_periph;
 	}
 
-	periph->mux = clk_mux_alloc(NULL, clk_base + reg_offset, 30, 2,
-				    parent_names, num_parents, 0);
+	periph->mux = clk_mux_alloc(NULL, clk_base + reg_offset, 32 - mux_size,
+				    mux_size, parent_names, num_parents, 0);
 	if (!periph->mux)
 		goto out_mux;
 
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 24/30] clk: tegra: don't bug out on zero PLL postdiv
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (22 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 23/30] clk: tegra: allow variable sized muxes Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 25/30] clk: tegra: add Tegra124 driver Lucas Stach
                   ` (6 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

As the real value is 2^p a input value of 0 is
actually valid.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 drivers/clk/tegra/clk-pll.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index f3257c4..c18c67f 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -196,8 +196,6 @@ static int _get_table_rate(struct clk *hw,
 	if (sel->input_rate == 0)
 		return -EINVAL;
 
-	BUG_ON(sel->p < 1);
-
 	cfg->input_rate = sel->input_rate;
 	cfg->output_rate = sel->output_rate;
 	cfg->m = sel->m;
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 25/30] clk: tegra: add Tegra124 driver
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (23 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 24/30] clk: tegra: don't bug out on zero PLL postdiv Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 26/30] mci: tegra: add Tegra124 compatible Lucas Stach
                   ` (5 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 drivers/clk/tegra/Makefile       |   1 +
 drivers/clk/tegra/clk-tegra124.c | 349 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 350 insertions(+)
 create mode 100644 drivers/clk/tegra/clk-tegra124.c

diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index 7317f22..75569c7 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -6,3 +6,4 @@ obj-y	+= clk-pll-out.o
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= clk-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= clk-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124.o
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
new file mode 100644
index 0000000..1e89bee
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -0,0 +1,349 @@
+/*
+ * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * Based on the Linux Tegra clock code
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <dt-bindings/clock/tegra124-car.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <mach/lowlevel.h>
+#include <mach/tegra20-car.h>
+#include <mach/tegra30-car.h>
+
+#include "clk.h"
+
+static void __iomem *car_base;
+
+static struct clk *clks[TEGRA124_CLK_CLK_MAX];
+static struct clk_onecell_data clk_data;
+
+static unsigned int get_pll_ref_div(void)
+{
+	u32 osc_ctrl = readl(car_base + CRC_OSC_CTRL);
+
+	return 1U << ((osc_ctrl & CRC_OSC_CTRL_PLL_REF_DIV_MASK) >>
+		      CRC_OSC_CTRL_PLL_REF_DIV_SHIFT);
+}
+
+static void tegra124_osc_clk_init(void)
+{
+	clks[TEGRA124_CLK_CLK_M] = clk_fixed("clk_m", tegra_get_osc_clock());
+	clks[TEGRA124_CLK_CLK_32K] = clk_fixed("clk_32k", 32768);
+
+	clks[TEGRA124_CLK_PLL_REF] = clk_fixed_factor("pll_ref", "clk_m", 1,
+						      get_pll_ref_div(), 0);
+}
+
+/* PLL frequency tables */
+static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
+	{ 12000000, 624000000, 104, 1, 2},
+	{ 12000000, 600000000, 100, 1, 2},
+	{ 13000000, 600000000,  92, 1, 2},	/* actual: 598.0 MHz */
+	{ 16800000, 600000000,  71, 1, 2},	/* actual: 596.4 MHz */
+	{ 19200000, 600000000,  62, 1, 2},	/* actual: 595.2 MHz */
+	{ 26000000, 600000000,  92, 2, 2},	/* actual: 598.0 MHz */
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
+	{12000000, 408000000, 408, 12, 0, 8},
+	{13000000, 408000000, 408, 13, 0, 8},
+	{16800000, 408000000, 340, 14, 0, 8},
+	{19200000, 408000000, 340, 16, 0, 8},
+	{26000000, 408000000, 408, 26, 0, 8},
+	{0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
+	{12000000, 800000000, 66, 1, 1},	/* actual: 792.0 MHz */
+	{13000000, 800000000, 61, 1, 1},	/* actual: 793.0 MHz */
+	{16800000, 800000000, 47, 1, 1},	/* actual: 789.6 MHz */
+	{19200000, 800000000, 41, 1, 1},	/* actual: 787.2 MHz */
+	{26000000, 800000000, 61, 2, 1},	/* actual: 793.0 MHz */
+	{0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
+	/* 1 GHz */
+	{12000000, 1000000000, 83, 0, 1},	/* actual: 996.0 MHz */
+	{13000000, 1000000000, 76, 0, 1},	/* actual: 988.0 MHz */
+	{16800000, 1000000000, 59, 0, 1},	/* actual: 991.2 MHz */
+	{19200000, 1000000000, 52, 0, 1},	/* actual: 998.4 MHz */
+	{26000000, 1000000000, 76, 1, 1},	/* actual: 988.0 MHz */
+	{0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
+	{12000000, 480000000, 960, 12, 2, 12},
+	{13000000, 480000000, 960, 13, 2, 12},
+	{16800000, 480000000, 400, 7, 2, 5},
+	{19200000, 480000000, 200, 4, 2, 3},
+	{26000000, 480000000, 960, 26, 2, 12},
+	{0, 0, 0, 0, 0, 0},
+};
+
+/* PLL parameters */
+static struct tegra_clk_pll_params pll_c_params = {
+	.input_min = 12000000,
+	.input_max = 800000000,
+	.cf_min = 12000000,
+	.cf_max = 19200000,	/* s/w policy, h/w capability 50 MHz */
+	.vco_min = 600000000,
+	.vco_max = 1400000000,
+	.base_reg = CRC_PLLC_BASE,
+	.misc_reg = CRC_PLLC_MISC,
+	.lock_bit_idx = CRC_PLL_BASE_LOCK,
+	.lock_enable_bit_idx = CRC_PLL_MISC_LOCK_ENABLE,
+	.lock_delay = 300,
+};
+
+static struct tegra_clk_pll_params pll_p_params = {
+	.input_min = 2000000,
+	.input_max = 31000000,
+	.cf_min = 1000000,
+	.cf_max = 6000000,
+	.vco_min = 200000000,
+	.vco_max = 700000000,
+	.base_reg = CRC_PLLP_BASE,
+	.misc_reg = CRC_PLLP_MISC,
+	.lock_bit_idx = CRC_PLL_BASE_LOCK,
+	.lock_enable_bit_idx = CRC_PLL_MISC_LOCK_ENABLE,
+	.lock_delay = 300,
+};
+
+static struct tegra_clk_pll_params pll_m_params = {
+	.input_min = 12000000,
+	.input_max = 500000000,
+	.cf_min = 12000000,
+	.cf_max = 19200000,	/* s/w policy, h/w capability 50 MHz */
+	.vco_min = 400000000,
+	.vco_max = 1066000000,
+	.base_reg = CRC_PLLM_BASE,
+	.misc_reg = CRC_PLLM_MISC,
+	.lock_bit_idx = CRC_PLL_BASE_LOCK,
+	.lock_enable_bit_idx = CRC_PLL_MISC_LOCK_ENABLE,
+	.lock_delay = 300,
+};
+
+static struct tegra_clk_pll_params pll_x_params = {
+	.input_min = 12000000,
+	.input_max = 800000000,
+	.cf_min = 12000000,
+	.cf_max = 19200000,	/* s/w policy, h/w capability 50 MHz */
+	.vco_min = 700000000,
+	.vco_max = 3000000000UL,
+	.base_reg = CRC_PLLX_BASE,
+	.misc_reg = CRC_PLLX_MISC,
+	.lock_bit_idx = CRC_PLL_BASE_LOCK,
+	.lock_enable_bit_idx = CRC_PLL_MISC_LOCK_ENABLE,
+	.lock_delay = 300,
+};
+
+static struct tegra_clk_pll_params pll_u_params = {
+	.input_min = 2000000,
+	.input_max = 40000000,
+	.cf_min = 1000000,
+	.cf_max = 6000000,
+	.vco_min = 48000000,
+	.vco_max = 960000000,
+	.base_reg = CRC_PLLU_BASE,
+	.misc_reg = CRC_PLLU_MISC,
+	.lock_bit_idx = CRC_PLL_BASE_LOCK,
+	.lock_enable_bit_idx = CRC_PLLDU_MISC_LOCK_ENABLE,
+	.lock_delay = 1000,
+};
+
+static void tegra124_pll_init(void)
+{
+	/* PLLC */
+	clks[TEGRA124_CLK_PLL_C] = tegra_clk_register_pll("pll_c", "pll_ref",
+			car_base, 0, 0, &pll_c_params, TEGRA_PLL_HAS_CPCON,
+			pll_c_freq_table);
+
+	clks[TEGRA124_CLK_PLL_C_OUT1] = tegra_clk_register_pll_out("pll_c_out1",
+			"pll_c", car_base + CRC_PLLC_OUT, 0,
+			TEGRA_DIVIDER_ROUND_UP);
+
+	/* PLLP */
+	clks[TEGRA124_CLK_PLL_P] = tegra_clk_register_pll("pll_p", "pll_ref",
+			car_base, 0, 408000000, &pll_p_params, TEGRA_PLL_FIXED |
+			TEGRA_PLL_HAS_CPCON, pll_p_freq_table);
+
+	clks[TEGRA124_CLK_PLL_P_OUT1] = tegra_clk_register_pll_out("pll_p_out1",
+			"pll_p", car_base + CRC_PLLP_OUTA, 0,
+			TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
+
+	clks[TEGRA124_CLK_PLL_P_OUT2] = tegra_clk_register_pll_out("pll_p_out2",
+			"pll_p", car_base + CRC_PLLP_OUTA, 16,
+			TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
+
+	clks[TEGRA124_CLK_PLL_P_OUT3] = tegra_clk_register_pll_out("pll_p_out3",
+			"pll_p", car_base + CRC_PLLP_OUTB, 0,
+			TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
+
+	clks[TEGRA124_CLK_PLL_P_OUT4] = tegra_clk_register_pll_out("pll_p_out4",
+			"pll_p", car_base + CRC_PLLP_OUTB, 16,
+			TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
+
+	/* PLLM */
+	clks[TEGRA124_CLK_PLL_M] = tegra_clk_register_pll("pll_m", "pll_ref",
+			car_base, 0, 0, &pll_m_params, TEGRA_PLL_HAS_CPCON,
+			pll_m_freq_table);
+
+	clks[TEGRA124_CLK_PLL_M_OUT1] = tegra_clk_register_pll_out("pll_m_out1",
+			"pll_m", car_base + CRC_PLLM_OUT, 0,
+			TEGRA_DIVIDER_ROUND_UP);
+
+	/* PLLX */
+	clks[TEGRA124_CLK_PLL_X] = tegra_clk_register_pll("pll_x", "pll_ref",
+			car_base, 0, 0, &pll_x_params, TEGRA_PLL_HAS_CPCON,
+			pll_x_freq_table);
+
+	/* PLLU */
+	clks[TEGRA124_CLK_PLL_U] = tegra_clk_register_pll("pll_u", "pll_ref",
+			car_base, 0, 0, &pll_u_params, TEGRA_PLLU |
+			TEGRA_PLL_HAS_CPCON, pll_u_freq_table);
+}
+
+static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c2", "pll_c", "pll_c3",
+					"pll_m", "rsvd", "clk_m"};
+
+static void tegra124_periph_init(void)
+{
+	/* peripheral clocks without a divider */
+	clks[TEGRA124_CLK_UARTA] = tegra_clk_register_periph_nodiv("uarta",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTA, TEGRA124_CLK_UARTA,
+			TEGRA_PERIPH_ON_APB);
+	clks[TEGRA124_CLK_UARTB] = tegra_clk_register_periph_nodiv("uartb",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTB, 7,
+			TEGRA_PERIPH_ON_APB);
+	clks[TEGRA124_CLK_UARTC] = tegra_clk_register_periph_nodiv("uartc",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTC, TEGRA124_CLK_UARTC,
+			TEGRA_PERIPH_ON_APB);
+	clks[TEGRA124_CLK_UARTD] = tegra_clk_register_periph_nodiv("uartd",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTD, TEGRA124_CLK_UARTD,
+			TEGRA_PERIPH_ON_APB);
+
+	/* peripheral clocks with a divider */
+	clks[TEGRA124_CLK_MSELECT] = tegra_clk_register_periph("mselect",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_MSEL, TEGRA124_CLK_MSELECT, 1);
+
+	clks[TEGRA124_CLK_SDMMC1] = tegra_clk_register_periph("sdmmc1",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_SDMMC1, TEGRA124_CLK_SDMMC1, 1);
+	clks[TEGRA124_CLK_SDMMC2] = tegra_clk_register_periph("sdmmc2",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_SDMMC2, TEGRA124_CLK_SDMMC2, 1);
+	clks[TEGRA124_CLK_SDMMC3] = tegra_clk_register_periph("sdmmc3",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_SDMMC3, TEGRA124_CLK_SDMMC3, 1);
+	clks[TEGRA124_CLK_SDMMC4] = tegra_clk_register_periph("sdmmc4",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_SDMMC4, TEGRA124_CLK_SDMMC4, 1);
+
+	clks[TEGRA124_CLK_I2C1] = tegra_clk_register_periph_div16("i2c1",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_I2C1, TEGRA124_CLK_I2C1, 1);
+	clks[TEGRA124_CLK_I2C2] = tegra_clk_register_periph_div16("i2c2",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_I2C2, TEGRA124_CLK_I2C2, 1);
+	clks[TEGRA124_CLK_I2C3] = tegra_clk_register_periph_div16("i2c3",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_I2C3, TEGRA124_CLK_I2C3, 1);
+	clks[TEGRA124_CLK_I2C4] = tegra_clk_register_periph_div16("i2c4",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_I2C4, TEGRA124_CLK_I2C4, 1);
+	clks[TEGRA124_CLK_I2C5] = tegra_clk_register_periph_div16("i2c5",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_DVC, TEGRA124_CLK_I2C5, 1);
+}
+
+static struct tegra_clk_init_table init_table[] = {
+	//{TEGRA124_CLK_PLL_P,		TEGRA124_CLK_CLK_MAX,	408000000,	1},
+	{TEGRA124_CLK_PLL_P_OUT1,	TEGRA124_CLK_CLK_MAX,	9600000,	1},
+	{TEGRA124_CLK_PLL_P_OUT2,	TEGRA124_CLK_CLK_MAX,	48000000,	1},
+	{TEGRA124_CLK_PLL_P_OUT3,	TEGRA124_CLK_CLK_MAX,	102000000,	1},
+	{TEGRA124_CLK_PLL_P_OUT4,	TEGRA124_CLK_CLK_MAX,	204000000,	1},
+	{TEGRA124_CLK_MSELECT,		TEGRA124_CLK_PLL_P,	204000000,	1},
+	{TEGRA124_CLK_UARTA,		TEGRA124_CLK_PLL_P,	0,		1},
+	{TEGRA124_CLK_UARTB,		TEGRA124_CLK_PLL_P,	0,		1},
+	{TEGRA124_CLK_UARTC,		TEGRA124_CLK_PLL_P,	0,		1},
+	{TEGRA124_CLK_UARTD,		TEGRA124_CLK_PLL_P,	0,		1},
+	{TEGRA124_CLK_SDMMC1,		TEGRA124_CLK_PLL_P,	48000000,	0},
+	{TEGRA124_CLK_SDMMC2,		TEGRA124_CLK_PLL_P,	48000000,	0},
+	{TEGRA124_CLK_SDMMC3,		TEGRA124_CLK_PLL_P,	48000000,	0},
+	{TEGRA124_CLK_SDMMC4,		TEGRA124_CLK_PLL_P,	48000000,	0},
+	{TEGRA124_CLK_CLK_MAX,		TEGRA124_CLK_CLK_MAX,	0,	0}, /* sentinel */
+};
+
+static int tegra124_car_probe(struct device_d *dev)
+{
+	car_base = dev_request_mem_region(dev, 0);
+	if (!car_base)
+		return -EBUSY;
+
+	tegra124_osc_clk_init();
+	tegra124_pll_init();
+	tegra124_periph_init();
+
+	tegra_init_from_table(init_table, clks, TEGRA124_CLK_CLK_MAX);
+
+	/* speed up system bus */
+	writel(CRC_SCLK_BURST_POLICY_SYS_STATE_RUN <<
+	       CRC_SCLK_BURST_POLICY_SYS_STATE_SHIFT |
+	       CRC_SCLK_BURST_POLICY_SRC_PLLP_OUT4 <<
+	       CRC_SCLK_BURST_POLICY_RUN_SRC_SHIFT,
+	       car_base + CRC_SCLK_BURST_POLICY);
+
+	clk_data.clks = clks;
+	clk_data.clk_num = ARRAY_SIZE(clks);
+	of_clk_add_provider(dev->device_node, of_clk_src_onecell_get,
+			    &clk_data);
+
+	tegra_clk_init_rst_controller(car_base, dev->device_node, 6 * 32);
+	tegra_clk_reset_uarts();
+
+	return 0;
+}
+
+static __maybe_unused struct of_device_id tegra124_car_dt_ids[] = {
+	{
+		.compatible = "nvidia,tegra124-car",
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct driver_d tegra124_car_driver = {
+	.probe	= tegra124_car_probe,
+	.name	= "tegra124-car",
+	.of_compatible = DRV_OF_COMPAT(tegra124_car_dt_ids),
+};
+
+static int tegra124_car_init(void)
+{
+	return platform_driver_register(&tegra124_car_driver);
+}
+postcore_initcall(tegra124_car_init);
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 26/30] mci: tegra: add Tegra124 compatible
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (24 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 25/30] clk: tegra: add Tegra124 driver Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 27/30] tegra: pmc: " Lucas Stach
                   ` (4 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

The controller is similar enough to the ones found
on earlier generation SoCs to not need any additional
changes.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 drivers/mci/tegra-sdmmc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mci/tegra-sdmmc.c b/drivers/mci/tegra-sdmmc.c
index 62cf730..08b9dac 100644
--- a/drivers/mci/tegra-sdmmc.c
+++ b/drivers/mci/tegra-sdmmc.c
@@ -481,6 +481,8 @@ static int tegra_sdmmc_probe(struct device_d *dev)
 
 static __maybe_unused struct of_device_id tegra_sdmmc_compatible[] = {
 	{
+		.compatible = "nvidia,tegra124-sdhci",
+	}, {
 		.compatible = "nvidia,tegra30-sdhci",
 	}, {
 		.compatible = "nvidia,tegra20-sdhci",
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 27/30] tegra: pmc: add Tegra124 compatible
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (25 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 26/30] mci: tegra: add Tegra124 compatible Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 28/30] images: add Tegra124 image build rules Lucas Stach
                   ` (3 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/tegra20-pmc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-tegra/tegra20-pmc.c b/arch/arm/mach-tegra/tegra20-pmc.c
index 37496ac..94167d6 100644
--- a/arch/arm/mach-tegra/tegra20-pmc.c
+++ b/arch/arm/mach-tegra/tegra20-pmc.c
@@ -62,6 +62,8 @@ static __maybe_unused struct of_device_id tegra20_pmc_dt_ids[] = {
 	}, {
 		.compatible = "nvidia,tegra30-pmc",
 	}, {
+		.compatible = "nvidia,tegra124-pmc",
+	}, {
 		/* sentinel */
 	}
 };
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 28/30] images: add Tegra124 image build rules
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (26 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 27/30] tegra: pmc: " Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 29/30] tegra: add NVIDIA Jetson-TK1 board support Lucas Stach
                   ` (2 subsequent siblings)
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

Allows to build persistent images for the Tegra124
line of SoCs.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 images/.gitignore     | 2 ++
 images/Makefile       | 2 +-
 images/Makefile.tegra | 9 +++++++++
 3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/images/.gitignore b/images/.gitignore
index 42991af..ec9e3c0 100644
--- a/images/.gitignore
+++ b/images/.gitignore
@@ -12,6 +12,8 @@
 *.t20img.cfg
 *.t30img
 *.t30img.cfg
+*.t124img
+*.t124img.cfg
 pbl.lds
 barebox.x
 barebox.z
diff --git a/images/Makefile b/images/Makefile
index b050dbf..740c197 100644
--- a/images/Makefile
+++ b/images/Makefile
@@ -118,5 +118,5 @@ images: $(addprefix $(obj)/, $(image-y)) FORCE
 
 clean-files := *.pbl *.pblb *.pblx *.map start_*.imximg *.img barebox.z start_*.kwbimg \
 	start_*.kwbuartimg *.socfpgaimg *.mlo *.t20img *.t20img.cfg *.t30img \
-	*.t30img.cfg
+	*.t30img.cfg *.t124img *.t124img.cfg
 clean-files += pbl.lds
diff --git a/images/Makefile.tegra b/images/Makefile.tegra
index f22c2d3..0d76062 100644
--- a/images/Makefile.tegra
+++ b/images/Makefile.tegra
@@ -19,6 +19,15 @@ quiet_cmd_tegra30_image = T30IMG  $@
 $(obj)/%.t30img: $(obj)/% FORCE
 	$(call if_changed,tegra30_image)
 
+quiet_cmd_tegra124_image = T124IMG  $@
+      cmd_tegra124_image = echo "Version = 0x00400001;Bctcopy = 1; \
+                                Bctfile = $(BCT_$(@F)); \
+                                BootLoader = $(subst .t124img,,$@),0x80108000,0x80108000,Complete;" \
+                                > $@.cfg; \
+                          $(objtree)/scripts/tegra/cbootimage -s tegra124 $@.cfg $@
+$(obj)/%.t124img: $(obj)/% FORCE
+	$(call if_changed,tegra124_image)
+
 board = $(srctree)/arch/$(ARCH)/boards
 
 # ----------------------- Tegra20 based boards ---------------------------
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 29/30] tegra: add NVIDIA Jetson-TK1 board support
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (27 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 28/30] images: add Tegra124 image build rules Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-03 20:35 ` [PATCH 30/30] tegra: refresh defconfig Lucas Stach
  2014-06-04  5:22 ` [PATCH 00/30] Tegra K1 support Sascha Hauer
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/boards/Makefile                           |    1 +
 arch/arm/boards/nvidia-jetson-tk1/Makefile         |    7 +
 arch/arm/boards/nvidia-jetson-tk1/entry.c          |   39 +
 .../nvidia-jetson-tk1/jetson-tk1-2gb-emmc.bct.cfg  | 1287 ++++++++++++++
 arch/arm/dts/Makefile                              |    4 +-
 arch/arm/dts/tegra124-jetson-tk1.dts               | 1828 ++++++++++++++++++++
 arch/arm/dts/tegra124.dtsi                         |    1 +
 arch/arm/mach-tegra/Kconfig                        |    4 +
 images/Makefile.tegra                              |   10 +
 9 files changed, 3180 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boards/nvidia-jetson-tk1/Makefile
 create mode 100644 arch/arm/boards/nvidia-jetson-tk1/entry.c
 create mode 100644 arch/arm/boards/nvidia-jetson-tk1/jetson-tk1-2gb-emmc.bct.cfg
 create mode 100644 arch/arm/dts/tegra124-jetson-tk1.dts
 create mode 100644 arch/arm/dts/tegra124.dtsi

diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 91e0f30..39a5f31 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_MACH_MX6Q_ARM2)			+= freescale-mx6-arm2/
 obj-$(CONFIG_MACH_NESO)				+= guf-neso/
 obj-$(CONFIG_MACH_NOMADIK_8815NHK)		+= nhk8815/
 obj-$(CONFIG_MACH_NVIDIA_BEAVER)		+= nvidia-beaver/
+obj-$(CONFIG_MACH_NVIDIA_JETSON)		+= nvidia-jetson-tk1/
 obj-$(CONFIG_MACH_NXDB500)			+= netx/
 obj-$(CONFIG_MACH_OMAP343xSDP)			+= omap343xdsp/
 obj-$(CONFIG_MACH_OMAP3EVM)			+= omap3evm/
diff --git a/arch/arm/boards/nvidia-jetson-tk1/Makefile b/arch/arm/boards/nvidia-jetson-tk1/Makefile
new file mode 100644
index 0000000..f1e4620
--- /dev/null
+++ b/arch/arm/boards/nvidia-jetson-tk1/Makefile
@@ -0,0 +1,7 @@
+CFLAGS_pbl-entry.o := \
+	-mcpu=arm7tdmi -march=armv4t \
+	-fno-tree-switch-conversion -fno-jump-tables
+soc := tegra124
+lwl-y += entry.o
+#obj-y += board.o
+extra-y += jetson-tk1-2gb-emmc.bct
diff --git a/arch/arm/boards/nvidia-jetson-tk1/entry.c b/arch/arm/boards/nvidia-jetson-tk1/entry.c
new file mode 100644
index 0000000..76c95a8
--- /dev/null
+++ b/arch/arm/boards/nvidia-jetson-tk1/entry.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <sizes.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+#include <mach/lowlevel.h>
+#include <mach/lowlevel-dvc.h>
+
+extern char __dtb_tegra124_jetson_tk1_start[];
+
+ENTRY_FUNCTION(start_nvidia_jetson, r0, r1, r2)
+{
+	uint32_t fdt;
+
+	tegra_cpu_lowlevel_setup();
+
+	tegra_dvc_init();
+	tegra124_dvc_pinmux();
+	tegra124_as3722_enable_essential_rails(0x3c00);
+
+	fdt = (uint32_t)__dtb_tegra124_jetson_tk1_start - get_runtime_offset();
+
+	tegra_avp_reset_vector(fdt);
+}
diff --git a/arch/arm/boards/nvidia-jetson-tk1/jetson-tk1-2gb-emmc.bct.cfg b/arch/arm/boards/nvidia-jetson-tk1/jetson-tk1-2gb-emmc.bct.cfg
new file mode 100644
index 0000000..4bac7b0
--- /dev/null
+++ b/arch/arm/boards/nvidia-jetson-tk1/jetson-tk1-2gb-emmc.bct.cfg
@@ -0,0 +1,1287 @@
+# Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+#    claim that you wrote the original software. If you use this software
+#    in a product, an acknowledgment in the product documentation would be
+#    appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+#    misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+Version       = 0x00400001;
+BlockSize     = 0x00004000;
+PageSize      = 0x00000200;
+PartitionSize = 0x01000000;
+OdmData       = 0x800d8000;
+
+DevType[0] = NvBootDevType_Sdmmc;
+DeviceParam[0].SdmmcParams.ClockDivider           = 0x00000009;
+DeviceParam[0].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[0].SdmmcParams.MultiPageSupport       = 0x00000000;
+
+DevType[1] = NvBootDevType_Sdmmc;
+DeviceParam[1].SdmmcParams.ClockDivider           = 0x00000009;
+DeviceParam[1].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[1].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[1].SdmmcParams.MultiPageSupport       = 0x00000000;
+
+DevType[2] = NvBootDevType_Sdmmc;
+DeviceParam[2].SdmmcParams.ClockDivider           = 0x00000009;
+DeviceParam[2].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[2].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[2].SdmmcParams.MultiPageSupport       = 0x00000000;
+
+DevType[3] = NvBootDevType_Sdmmc;
+DeviceParam[3].SdmmcParams.ClockDivider           = 0x00000009;
+DeviceParam[3].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[3].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[3].SdmmcParams.MultiPageSupport       = 0x00000000;
+
+SDRAM[0].MemoryType                               = NvBootMemoryType_Ddr3;
+SDRAM[0].PllMInputDivider                         = 0x00000001;
+SDRAM[0].PllMFeedbackDivider                      = 0x0000004d;
+SDRAM[0].PllMStableTime                           = 0x0000012c;
+SDRAM[0].PllMSetupControl                         = 0x00000000;
+SDRAM[0].PllMSelectDiv2                           = 0x00000000;
+SDRAM[0].PllMPDLshiftPh45                         = 0x00000001;
+SDRAM[0].PllMPDLshiftPh90                         = 0x00000001;
+SDRAM[0].PllMPDLshiftPh135                        = 0x00000001;
+SDRAM[0].PllMKCP                                  = 0x00000000;
+SDRAM[0].PllMKVCO                                 = 0x00000000;
+SDRAM[0].EmcBctSpare0                             = 0x00000000;
+SDRAM[0].EmcBctSpare1                             = 0x00000000;
+SDRAM[0].EmcBctSpare2                             = 0x00000000;
+SDRAM[0].EmcBctSpare3                             = 0x00000000;
+SDRAM[0].EmcBctSpare4                             = 0x00000000;
+SDRAM[0].EmcBctSpare5                             = 0x00000000;
+SDRAM[0].EmcBctSpare6                             = 0x00000000;
+SDRAM[0].EmcBctSpare7                             = 0x00000000;
+SDRAM[0].EmcBctSpare8                             = 0x00000000;
+SDRAM[0].EmcBctSpare9                             = 0x00000000;
+SDRAM[0].EmcBctSpare10                            = 0x00000000;
+SDRAM[0].EmcBctSpare11                            = 0x00000000;
+SDRAM[0].EmcClockSource                           = 0x80000000;
+SDRAM[0].EmcAutoCalInterval                       = 0x001fffff;
+SDRAM[0].EmcAutoCalConfig                         = 0xa1430303;
+SDRAM[0].EmcAutoCalConfig2                        = 0x00000000;
+SDRAM[0].EmcAutoCalConfig3                        = 0x00000000;
+SDRAM[0].EmcAutoCalWait                           = 0x00000190;
+SDRAM[0].EmcAdrCfg                                = 0x00000000;
+SDRAM[0].EmcPinProgramWait                        = 0x00000001;
+SDRAM[0].EmcPinExtraWait                          = 0x00000000;
+SDRAM[0].EmcTimingControlWait                     = 0x00000000;
+SDRAM[0].EmcRc                                    = 0x0000002b;
+SDRAM[0].EmcRfc                                   = 0x000000f0;
+SDRAM[0].EmcRfcSlr                                = 0x00000000;
+SDRAM[0].EmcRas                                   = 0x0000001e;
+SDRAM[0].EmcRp                                    = 0x0000000b;
+SDRAM[0].EmcR2r                                   = 0x00000000;
+SDRAM[0].EmcW2w                                   = 0x00000000;
+SDRAM[0].EmcR2w                                   = 0x00000009;
+SDRAM[0].EmcW2r                                   = 0x0000000f;
+SDRAM[0].EmcR2p                                   = 0x00000005;
+SDRAM[0].EmcW2p                                   = 0x00000016;
+SDRAM[0].EmcRdRcd                                 = 0x0000000b;
+SDRAM[0].EmcWrRcd                                 = 0x0000000b;
+SDRAM[0].EmcRrd                                   = 0x00000004;
+SDRAM[0].EmcRext                                  = 0x00000002;
+SDRAM[0].EmcWext                                  = 0x00000000;
+SDRAM[0].EmcWdv                                   = 0x00000007;
+SDRAM[0].EmcWdvMask                               = 0x00000007;
+SDRAM[0].EmcQUse                                  = 0x0000000d;
+SDRAM[0].EmcQuseWidth                             = 0x00000002;
+SDRAM[0].EmcIbdly                                 = 0x00000000;
+SDRAM[0].EmcEInput                                = 0x00000002;
+SDRAM[0].EmcEInputDuration                        = 0x0000000f;
+SDRAM[0].EmcPutermExtra                           = 0x000a0000;
+SDRAM[0].EmcPutermWidth                           = 0x00000004;
+SDRAM[0].EmcPutermAdj                             = 0x00000000;
+SDRAM[0].EmcCdbCntl1                              = 0x00000000;
+SDRAM[0].EmcCdbCntl2                              = 0x00000000;
+SDRAM[0].EmcCdbCntl3                              = 0x00000000;
+SDRAM[0].EmcQRst                                  = 0x00000001;
+SDRAM[0].EmcQSafe                                 = 0x00000016;
+SDRAM[0].EmcRdv                                   = 0x0000001a;
+SDRAM[0].EmcRdvMask                               = 0x0000001c;
+SDRAM[0].EmcQpop                                  = 0x00000011;
+SDRAM[0].EmcCtt                                   = 0x00000000;
+SDRAM[0].EmcCttDuration                           = 0x00000004;
+SDRAM[0].EmcRefresh                               = 0x00001be7;
+SDRAM[0].EmcBurstRefreshNum                       = 0x00000000;
+SDRAM[0].EmcPreRefreshReqCnt                      = 0x000006f9;
+SDRAM[0].EmcPdEx2Wr                               = 0x00000004;
+SDRAM[0].EmcPdEx2Rd                               = 0x00000015;
+SDRAM[0].EmcPChg2Pden                             = 0x00000001;
+SDRAM[0].EmcAct2Pden                              = 0x00000000;
+SDRAM[0].EmcAr2Pden                               = 0x000000e7;
+SDRAM[0].EmcRw2Pden                               = 0x0000001b;
+SDRAM[0].EmcTxsr                                  = 0x000000fb;
+SDRAM[0].EmcTxsrDll                               = 0x00000200;
+SDRAM[0].EmcTcke                                  = 0x00000006;
+SDRAM[0].EmcTckesr                                = 0x00000007;
+SDRAM[0].EmcTpd                                   = 0x00000006;
+SDRAM[0].EmcTfaw                                  = 0x00000022;
+SDRAM[0].EmcTrpab                                 = 0x00000000;
+SDRAM[0].EmcTClkStable                            = 0x0000000a;
+SDRAM[0].EmcTClkStop                              = 0x0000000a;
+SDRAM[0].EmcTRefBw                                = 0x00001c28;
+SDRAM[0].EmcFbioCfg5                              = 0x104ab898;
+SDRAM[0].EmcFbioCfg6                              = 0x00000000;
+SDRAM[0].EmcFbioSpare                             = 0x00000000;
+SDRAM[0].EmcCfgRsv                                = 0xff00ff00;
+SDRAM[0].EmcMrs                                   = 0x80000f15;
+SDRAM[0].EmcEmrs                                  = 0x80100002;
+SDRAM[0].EmcEmrs2                                 = 0x80200020;
+SDRAM[0].EmcEmrs3                                 = 0x80300000;
+SDRAM[0].EmcMrw1                                  = 0x00000000;
+SDRAM[0].EmcMrw2                                  = 0x00000000;
+SDRAM[0].EmcMrw3                                  = 0x00000000;
+SDRAM[0].EmcMrw4                                  = 0x00000000;
+SDRAM[0].EmcMrwExtra                              = 0x00000000;
+SDRAM[0].EmcWarmBootMrwExtra                      = 0x00000000;
+SDRAM[0].EmcWarmBootExtraModeRegWriteEnable       = 0x00000000;
+SDRAM[0].EmcExtraModeRegWriteEnable               = 0x00000000;
+SDRAM[0].EmcMrwResetCommand                       = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait                     = 0x00000000;
+SDRAM[0].EmcMrsWaitCnt                            = 0x00cd000e;
+SDRAM[0].EmcMrsWaitCnt2                           = 0x00cd000e;
+SDRAM[0].EmcCfg                                   = 0x73300000;
+SDRAM[0].EmcCfg2                                  = 0x0000089d;
+SDRAM[0].EmcCfgPipe                               = 0x00004080;
+SDRAM[0].EmcDbg                                   = 0x01000c00;
+SDRAM[0].EmcCmdQ                                  = 0x10004408;
+SDRAM[0].EmcMc2EmcQ                               = 0x06000404;
+SDRAM[0].EmcDynSelfRefControl                     = 0x800037ea;
+SDRAM[0].AhbArbitrationXbarCtrlMemInitDone        = 0x00000001;
+SDRAM[0].EmcCfgDigDll                             = 0xe00400b1;
+SDRAM[0].EmcCfgDigDllPeriod                       = 0x00008000;
+SDRAM[0].EmcDevSelect                             = 0x00000002;
+SDRAM[0].EmcSelDpdCtrl                            = 0x00040000;
+SDRAM[0].EmcDllXformDqs0                          = 0x007f800a;
+SDRAM[0].EmcDllXformDqs1                          = 0x007f800a;
+SDRAM[0].EmcDllXformDqs2                          = 0x007f800a;
+SDRAM[0].EmcDllXformDqs3                          = 0x007f800a;
+SDRAM[0].EmcDllXformDqs4                          = 0x007f800a;
+SDRAM[0].EmcDllXformDqs5                          = 0x007f800a;
+SDRAM[0].EmcDllXformDqs6                          = 0x007f800a;
+SDRAM[0].EmcDllXformDqs7                          = 0x007f800a;
+SDRAM[0].EmcDllXformDqs8                          = 0x007f800a;
+SDRAM[0].EmcDllXformDqs9                          = 0x007f800a;
+SDRAM[0].EmcDllXformDqs10                         = 0x007f800a;
+SDRAM[0].EmcDllXformDqs11                         = 0x007f800a;
+SDRAM[0].EmcDllXformDqs12                         = 0x007f800a;
+SDRAM[0].EmcDllXformDqs13                         = 0x007f800a;
+SDRAM[0].EmcDllXformDqs14                         = 0x007f800a;
+SDRAM[0].EmcDllXformDqs15                         = 0x007f800a;
+SDRAM[0].EmcDllXformQUse0                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse1                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse2                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse3                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse4                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse5                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse6                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse7                         = 0x00000000;
+SDRAM[0].EmcDllXformAddr0                         = 0x0002c000;
+SDRAM[0].EmcDllXformAddr1                         = 0x0002c000;
+SDRAM[0].EmcDllXformAddr2                         = 0x00000000;
+SDRAM[0].EmcDllXformAddr3                         = 0x0002c000;
+SDRAM[0].EmcDllXformAddr4                         = 0x0002c000;
+SDRAM[0].EmcDllXformAddr5                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse8                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse9                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse10                        = 0x00000000;
+SDRAM[0].EmcDllXformQUse11                        = 0x00000000;
+SDRAM[0].EmcDllXformQUse12                        = 0x00000000;
+SDRAM[0].EmcDllXformQUse13                        = 0x00000000;
+SDRAM[0].EmcDllXformQUse14                        = 0x00000000;
+SDRAM[0].EmcDllXformQUse15                        = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs0                         = 0x00000005;
+SDRAM[0].EmcDliTrimTxDqs1                         = 0x00000005;
+SDRAM[0].EmcDliTrimTxDqs2                         = 0x00000005;
+SDRAM[0].EmcDliTrimTxDqs3                         = 0x00000005;
+SDRAM[0].EmcDliTrimTxDqs4                         = 0x00000005;
+SDRAM[0].EmcDliTrimTxDqs5                         = 0x00000005;
+SDRAM[0].EmcDliTrimTxDqs6                         = 0x00000005;
+SDRAM[0].EmcDliTrimTxDqs7                         = 0x00000005;
+SDRAM[0].EmcDliTrimTxDqs8                         = 0x00000005;
+SDRAM[0].EmcDliTrimTxDqs9                         = 0x00000005;
+SDRAM[0].EmcDliTrimTxDqs10                        = 0x00000005;
+SDRAM[0].EmcDliTrimTxDqs11                        = 0x00000005;
+SDRAM[0].EmcDliTrimTxDqs12                        = 0x00000005;
+SDRAM[0].EmcDliTrimTxDqs13                        = 0x00000005;
+SDRAM[0].EmcDliTrimTxDqs14                        = 0x00000005;
+SDRAM[0].EmcDliTrimTxDqs15                        = 0x00000005;
+SDRAM[0].EmcDllXformDq0                           = 0x00000008;
+SDRAM[0].EmcDllXformDq1                           = 0x00000008;
+SDRAM[0].EmcDllXformDq2                           = 0x00000008;
+SDRAM[0].EmcDllXformDq3                           = 0x00000008;
+SDRAM[0].EmcDllXformDq4                           = 0x00000008;
+SDRAM[0].EmcDllXformDq5                           = 0x00000008;
+SDRAM[0].EmcDllXformDq6                           = 0x00000008;
+SDRAM[0].EmcDllXformDq7                           = 0x00000008;
+SDRAM[0].WarmBootWait                             = 0x00000002;
+SDRAM[0].EmcCttTermCtrl                           = 0x00000802;
+SDRAM[0].EmcOdtWrite                              = 0x00000000;
+SDRAM[0].EmcOdtRead                               = 0x00000000;
+SDRAM[0].EmcZcalInterval                          = 0x00020000;
+SDRAM[0].EmcZcalWaitCnt                           = 0x0000004c;
+SDRAM[0].EmcZcalMrwCmd                            = 0x80000000;
+SDRAM[0].EmcMrsResetDll                           = 0x00000000;
+SDRAM[0].EmcZcalInitDev0                          = 0x80000011;
+SDRAM[0].EmcZcalInitDev1                          = 0x00000000;
+SDRAM[0].EmcZcalInitWait                          = 0x00000001;
+SDRAM[0].EmcZcalWarmColdBootEnables               = 0x00000003;
+SDRAM[0].EmcMrwLpddr2ZcalWarmBoot                 = 0x040a00ab;
+SDRAM[0].EmcZqCalDdr3WarmBoot                     = 0x00000000;
+SDRAM[0].EmcZcalWarmBootWait                      = 0x00000001;
+SDRAM[0].EmcMrsWarmBootEnable                     = 0x00000001;
+SDRAM[0].EmcMrsResetDllWait                       = 0x00000000;
+SDRAM[0].EmcMrsExtra                              = 0x80000f15;
+SDRAM[0].EmcWarmBootMrsExtra                      = 0x80100002;
+SDRAM[0].EmcEmrsDdr2DllEnable                     = 0x00000000;
+SDRAM[0].EmcMrsDdr2DllReset                       = 0x00000000;
+SDRAM[0].EmcEmrsDdr2OcdCalib                      = 0x00000000;
+SDRAM[0].EmcDdr2Wait                              = 0x00000000;
+SDRAM[0].EmcClkenOverride                         = 0x00000000;
+SDRAM[0].McDisExtraSnapLevels                     = 0x00000000;
+SDRAM[0].EmcExtraRefreshNum                       = 0x00000002;
+SDRAM[0].EmcClkenOverrideAllWarmBoot              = 0x00000000;
+SDRAM[0].McClkenOverrideAllWarmBoot               = 0x00000000;
+SDRAM[0].EmcCfgDigDllPeriodWarmBoot               = 0x00000003;
+SDRAM[0].PmcVddpSel                               = 0x00000002;
+SDRAM[0].PmcVddpSelWait                           = 0x00000002;
+SDRAM[0].PmcDdrPwr                                = 0x00000003;
+SDRAM[0].PmcDdrCfg                                = 0x00002002;
+SDRAM[0].PmcIoDpd3Req                             = 0x4fff2f97;
+SDRAM[0].PmcIoDpd3ReqWait                         = 0x00000000;
+SDRAM[0].PmcRegShort                              = 0x00000000;
+SDRAM[0].PmcNoIoPower                             = 0x00000000;
+SDRAM[0].PmcPorDpdCtrlWait                        = 0x00000000;
+SDRAM[0].EmcXm2CmdPadCtrl                         = 0x100002a0;
+SDRAM[0].EmcXm2CmdPadCtrl2                        = 0x770c0000;
+SDRAM[0].EmcXm2CmdPadCtrl3                        = 0x050c0000;
+SDRAM[0].EmcXm2CmdPadCtrl4                        = 0x00000000;
+SDRAM[0].EmcXm2CmdPadCtrl5                        = 0x00111111;
+SDRAM[0].EmcXm2DqsPadCtrl                         = 0x770c1414;
+SDRAM[0].EmcXm2DqsPadCtrl2                        = 0x0120113d;
+SDRAM[0].EmcXm2DqsPadCtrl3                        = 0x5d75d720;
+SDRAM[0].EmcXm2DqsPadCtrl4                        = 0x00514514;
+SDRAM[0].EmcXm2DqsPadCtrl5                        = 0x00514514;
+SDRAM[0].EmcXm2DqsPadCtrl6                        = 0x5d75d700;
+SDRAM[0].EmcXm2DqPadCtrl                          = 0x770c2990;
+SDRAM[0].EmcXm2DqPadCtrl2                         = 0x00000000;
+SDRAM[0].EmcXm2DqPadCtrl3                         = 0x00000000;
+SDRAM[0].EmcXm2ClkPadCtrl                         = 0x77ffc085;
+SDRAM[0].EmcXm2ClkPadCtrl2                        = 0x00000000;
+SDRAM[0].EmcXm2CompPadCtrl                        = 0x81f1f108;
+SDRAM[0].EmcXm2VttGenPadCtrl                      = 0x07070004;
+SDRAM[0].EmcXm2VttGenPadCtrl2                     = 0x00000000;
+SDRAM[0].EmcXm2VttGenPadCtrl3                     = 0x016eeeee;
+SDRAM[0].EmcAcpdControl                           = 0x00000000;
+SDRAM[0].EmcSwizzleRank0ByteCfg                   = 0x00003120;
+SDRAM[0].EmcSwizzleRank0Byte0                     = 0x25143067;
+SDRAM[0].EmcSwizzleRank0Byte1                     = 0x45367102;
+SDRAM[0].EmcSwizzleRank0Byte2                     = 0x47106253;
+SDRAM[0].EmcSwizzleRank0Byte3                     = 0x04362175;
+SDRAM[0].EmcSwizzleRank1ByteCfg                   = 0x00003120;
+SDRAM[0].EmcSwizzleRank1Byte0                     = 0x71546032;
+SDRAM[0].EmcSwizzleRank1Byte1                     = 0x35104276;
+SDRAM[0].EmcSwizzleRank1Byte2                     = 0x27043615;
+SDRAM[0].EmcSwizzleRank1Byte3                     = 0x72306145;
+SDRAM[0].EmcDsrVttgenDrv                          = 0x0606003f;
+SDRAM[0].EmcTxdsrvttgen                           = 0x00000000;
+SDRAM[0].EmcBgbiasCtl0                            = 0x00000000;
+SDRAM[0].McEmemAdrCfg                             = 0x00000000;
+SDRAM[0].McEmemAdrCfgDev0                         = 0x00080303;
+SDRAM[0].McEmemAdrCfgDev1                         = 0x00080303;
+SDRAM[0].McEmemAdrCfgBankMask0                    = 0x00001248;
+SDRAM[0].McEmemAdrCfgBankMask1                    = 0x00002490;
+SDRAM[0].McEmemAdrCfgBankMask2                    = 0x00000920;
+SDRAM[0].McEmemAdrCfgBankSwizzle3                 = 0x00000001;
+SDRAM[0].McEmemCfg                                = 0x00000800;
+SDRAM[0].McEmemArbCfg                             = 0x0e00000d;
+SDRAM[0].McEmemArbOutstandingReq                  = 0x80000040;
+SDRAM[0].McEmemArbTimingRcd                       = 0x00000005;
+SDRAM[0].McEmemArbTimingRp                        = 0x00000006;
+SDRAM[0].McEmemArbTimingRc                        = 0x00000016;
+SDRAM[0].McEmemArbTimingRas                       = 0x0000000e;
+SDRAM[0].McEmemArbTimingFaw                       = 0x00000011;
+SDRAM[0].McEmemArbTimingRrd                       = 0x00000002;
+SDRAM[0].McEmemArbTimingRap2Pre                   = 0x00000004;
+SDRAM[0].McEmemArbTimingWap2Pre                   = 0x0000000e;
+SDRAM[0].McEmemArbTimingR2R                       = 0x00000002;
+SDRAM[0].McEmemArbTimingW2W                       = 0x00000002;
+SDRAM[0].McEmemArbTimingR2W                       = 0x00000006;
+SDRAM[0].McEmemArbTimingW2R                       = 0x00000009;
+SDRAM[0].McEmemArbDaTurns                         = 0x09060202;
+SDRAM[0].McEmemArbDaCovers                        = 0x001a1016;
+SDRAM[0].McEmemArbMisc0                           = 0x734e2a17;
+SDRAM[0].McEmemArbMisc1                           = 0x70000f02;
+SDRAM[0].McEmemArbRing1Throttle                   = 0x001f0000;
+SDRAM[0].McEmemArbOverride                        = 0x10000000;
+SDRAM[0].McEmemArbOverride1                       = 0x00000000;
+SDRAM[0].McEmemArbRsv                             = 0xff00ff00;
+SDRAM[0].McClkenOverride                          = 0x00000000;
+SDRAM[0].McStatControl                            = 0x00000000;
+SDRAM[0].McDisplaySnapRing                        = 0x00000003;
+SDRAM[0].McVideoProtectBom                        = 0xfff00000;
+SDRAM[0].McVideoProtectBomAdrHi                   = 0x00000000;
+SDRAM[0].McVideoProtectSizeMb                     = 0x00000000;
+SDRAM[0].McVideoProtectVprOverride                = 0xe4bac743;
+SDRAM[0].McVideoProtectVprOverride1               = 0x00000013;
+SDRAM[0].McVideoProtectGpuOverride0               = 0x00000000;
+SDRAM[0].McVideoProtectGpuOverride1               = 0x00000000;
+SDRAM[0].McSecCarveoutBom                         = 0xfff00000;
+SDRAM[0].McSecCarveoutAdrHi                       = 0x00000000;
+SDRAM[0].McSecCarveoutSizeMb                      = 0x00000000;
+SDRAM[0].McVideoProtectWriteAccess                = 0x00000000;
+SDRAM[0].McSecCarveoutProtectWriteAccess          = 0x00000000;
+SDRAM[0].EmcCaTrainingEnable                      = 0x00000000;
+SDRAM[0].EmcCaTrainingTimingCntl1                 = 0x1f7df7df;
+SDRAM[0].EmcCaTrainingTimingCntl2                 = 0x0000001f;
+SDRAM[0].SwizzleRankByteEncode                    = 0x0000006f;
+SDRAM[0].BootRomPatchControl                      = 0x00000000;
+SDRAM[0].BootRomPatchData                         = 0x00000000;
+SDRAM[0].McMtsCarveoutBom                         = 0xfff00000;
+SDRAM[0].McMtsCarveoutAdrHi                       = 0x00000000;
+SDRAM[0].McMtsCarveoutSizeMb                      = 0x00000000;
+SDRAM[0].McMtsCarveoutRegCtrl                     = 0x00000000;
+
+SDRAM[1].MemoryType                               = NvBootMemoryType_Ddr3;
+SDRAM[1].PllMInputDivider                         = 0x00000001;
+SDRAM[1].PllMFeedbackDivider                      = 0x0000004d;
+SDRAM[1].PllMStableTime                           = 0x0000012c;
+SDRAM[1].PllMSetupControl                         = 0x00000000;
+SDRAM[1].PllMSelectDiv2                           = 0x00000000;
+SDRAM[1].PllMPDLshiftPh45                         = 0x00000001;
+SDRAM[1].PllMPDLshiftPh90                         = 0x00000001;
+SDRAM[1].PllMPDLshiftPh135                        = 0x00000001;
+SDRAM[1].PllMKCP                                  = 0x00000000;
+SDRAM[1].PllMKVCO                                 = 0x00000000;
+SDRAM[1].EmcBctSpare0                             = 0x00000000;
+SDRAM[1].EmcBctSpare1                             = 0x00000000;
+SDRAM[1].EmcBctSpare2                             = 0x00000000;
+SDRAM[1].EmcBctSpare3                             = 0x00000000;
+SDRAM[1].EmcBctSpare4                             = 0x00000000;
+SDRAM[1].EmcBctSpare5                             = 0x00000000;
+SDRAM[1].EmcBctSpare6                             = 0x00000000;
+SDRAM[1].EmcBctSpare7                             = 0x00000000;
+SDRAM[1].EmcBctSpare8                             = 0x00000000;
+SDRAM[1].EmcBctSpare9                             = 0x00000000;
+SDRAM[1].EmcBctSpare10                            = 0x00000000;
+SDRAM[1].EmcBctSpare11                            = 0x00000000;
+SDRAM[1].EmcClockSource                           = 0x80000000;
+SDRAM[1].EmcAutoCalInterval                       = 0x001fffff;
+SDRAM[1].EmcAutoCalConfig                         = 0xa1430303;
+SDRAM[1].EmcAutoCalConfig2                        = 0x00000000;
+SDRAM[1].EmcAutoCalConfig3                        = 0x00000000;
+SDRAM[1].EmcAutoCalWait                           = 0x00000190;
+SDRAM[1].EmcAdrCfg                                = 0x00000000;
+SDRAM[1].EmcPinProgramWait                        = 0x00000001;
+SDRAM[1].EmcPinExtraWait                          = 0x00000000;
+SDRAM[1].EmcTimingControlWait                     = 0x00000000;
+SDRAM[1].EmcRc                                    = 0x0000002b;
+SDRAM[1].EmcRfc                                   = 0x000000f0;
+SDRAM[1].EmcRfcSlr                                = 0x00000000;
+SDRAM[1].EmcRas                                   = 0x0000001e;
+SDRAM[1].EmcRp                                    = 0x0000000b;
+SDRAM[1].EmcR2r                                   = 0x00000000;
+SDRAM[1].EmcW2w                                   = 0x00000000;
+SDRAM[1].EmcR2w                                   = 0x00000009;
+SDRAM[1].EmcW2r                                   = 0x0000000f;
+SDRAM[1].EmcR2p                                   = 0x00000005;
+SDRAM[1].EmcW2p                                   = 0x00000016;
+SDRAM[1].EmcRdRcd                                 = 0x0000000b;
+SDRAM[1].EmcWrRcd                                 = 0x0000000b;
+SDRAM[1].EmcRrd                                   = 0x00000004;
+SDRAM[1].EmcRext                                  = 0x00000002;
+SDRAM[1].EmcWext                                  = 0x00000000;
+SDRAM[1].EmcWdv                                   = 0x00000007;
+SDRAM[1].EmcWdvMask                               = 0x00000007;
+SDRAM[1].EmcQUse                                  = 0x0000000d;
+SDRAM[1].EmcQuseWidth                             = 0x00000002;
+SDRAM[1].EmcIbdly                                 = 0x00000000;
+SDRAM[1].EmcEInput                                = 0x00000002;
+SDRAM[1].EmcEInputDuration                        = 0x0000000f;
+SDRAM[1].EmcPutermExtra                           = 0x000a0000;
+SDRAM[1].EmcPutermWidth                           = 0x00000004;
+SDRAM[1].EmcPutermAdj                             = 0x00000000;
+SDRAM[1].EmcCdbCntl1                              = 0x00000000;
+SDRAM[1].EmcCdbCntl2                              = 0x00000000;
+SDRAM[1].EmcCdbCntl3                              = 0x00000000;
+SDRAM[1].EmcQRst                                  = 0x00000001;
+SDRAM[1].EmcQSafe                                 = 0x00000016;
+SDRAM[1].EmcRdv                                   = 0x0000001a;
+SDRAM[1].EmcRdvMask                               = 0x0000001c;
+SDRAM[1].EmcQpop                                  = 0x00000011;
+SDRAM[1].EmcCtt                                   = 0x00000000;
+SDRAM[1].EmcCttDuration                           = 0x00000004;
+SDRAM[1].EmcRefresh                               = 0x00001be7;
+SDRAM[1].EmcBurstRefreshNum                       = 0x00000000;
+SDRAM[1].EmcPreRefreshReqCnt                      = 0x000006f9;
+SDRAM[1].EmcPdEx2Wr                               = 0x00000004;
+SDRAM[1].EmcPdEx2Rd                               = 0x00000015;
+SDRAM[1].EmcPChg2Pden                             = 0x00000001;
+SDRAM[1].EmcAct2Pden                              = 0x00000000;
+SDRAM[1].EmcAr2Pden                               = 0x000000e7;
+SDRAM[1].EmcRw2Pden                               = 0x0000001b;
+SDRAM[1].EmcTxsr                                  = 0x000000fb;
+SDRAM[1].EmcTxsrDll                               = 0x00000200;
+SDRAM[1].EmcTcke                                  = 0x00000006;
+SDRAM[1].EmcTckesr                                = 0x00000007;
+SDRAM[1].EmcTpd                                   = 0x00000006;
+SDRAM[1].EmcTfaw                                  = 0x00000022;
+SDRAM[1].EmcTrpab                                 = 0x00000000;
+SDRAM[1].EmcTClkStable                            = 0x0000000a;
+SDRAM[1].EmcTClkStop                              = 0x0000000a;
+SDRAM[1].EmcTRefBw                                = 0x00001c28;
+SDRAM[1].EmcFbioCfg5                              = 0x104ab898;
+SDRAM[1].EmcFbioCfg6                              = 0x00000000;
+SDRAM[1].EmcFbioSpare                             = 0x00000000;
+SDRAM[1].EmcCfgRsv                                = 0xff00ff00;
+SDRAM[1].EmcMrs                                   = 0x80000f15;
+SDRAM[1].EmcEmrs                                  = 0x80100002;
+SDRAM[1].EmcEmrs2                                 = 0x80200020;
+SDRAM[1].EmcEmrs3                                 = 0x80300000;
+SDRAM[1].EmcMrw1                                  = 0x00000000;
+SDRAM[1].EmcMrw2                                  = 0x00000000;
+SDRAM[1].EmcMrw3                                  = 0x00000000;
+SDRAM[1].EmcMrw4                                  = 0x00000000;
+SDRAM[1].EmcMrwExtra                              = 0x00000000;
+SDRAM[1].EmcWarmBootMrwExtra                      = 0x00000000;
+SDRAM[1].EmcWarmBootExtraModeRegWriteEnable       = 0x00000000;
+SDRAM[1].EmcExtraModeRegWriteEnable               = 0x00000000;
+SDRAM[1].EmcMrwResetCommand                       = 0x00000000;
+SDRAM[1].EmcMrwResetNInitWait                     = 0x00000000;
+SDRAM[1].EmcMrsWaitCnt                            = 0x00cd000e;
+SDRAM[1].EmcMrsWaitCnt2                           = 0x00cd000e;
+SDRAM[1].EmcCfg                                   = 0x73300000;
+SDRAM[1].EmcCfg2                                  = 0x0000089d;
+SDRAM[1].EmcCfgPipe                               = 0x00004080;
+SDRAM[1].EmcDbg                                   = 0x01000c00;
+SDRAM[1].EmcCmdQ                                  = 0x10004408;
+SDRAM[1].EmcMc2EmcQ                               = 0x06000404;
+SDRAM[1].EmcDynSelfRefControl                     = 0x800037ea;
+SDRAM[1].AhbArbitrationXbarCtrlMemInitDone        = 0x00000001;
+SDRAM[1].EmcCfgDigDll                             = 0xe00400b1;
+SDRAM[1].EmcCfgDigDllPeriod                       = 0x00008000;
+SDRAM[1].EmcDevSelect                             = 0x00000002;
+SDRAM[1].EmcSelDpdCtrl                            = 0x00040000;
+SDRAM[1].EmcDllXformDqs0                          = 0x007f800a;
+SDRAM[1].EmcDllXformDqs1                          = 0x007f800a;
+SDRAM[1].EmcDllXformDqs2                          = 0x007f800a;
+SDRAM[1].EmcDllXformDqs3                          = 0x007f800a;
+SDRAM[1].EmcDllXformDqs4                          = 0x007f800a;
+SDRAM[1].EmcDllXformDqs5                          = 0x007f800a;
+SDRAM[1].EmcDllXformDqs6                          = 0x007f800a;
+SDRAM[1].EmcDllXformDqs7                          = 0x007f800a;
+SDRAM[1].EmcDllXformDqs8                          = 0x007f800a;
+SDRAM[1].EmcDllXformDqs9                          = 0x007f800a;
+SDRAM[1].EmcDllXformDqs10                         = 0x007f800a;
+SDRAM[1].EmcDllXformDqs11                         = 0x007f800a;
+SDRAM[1].EmcDllXformDqs12                         = 0x007f800a;
+SDRAM[1].EmcDllXformDqs13                         = 0x007f800a;
+SDRAM[1].EmcDllXformDqs14                         = 0x007f800a;
+SDRAM[1].EmcDllXformDqs15                         = 0x007f800a;
+SDRAM[1].EmcDllXformQUse0                         = 0x00000000;
+SDRAM[1].EmcDllXformQUse1                         = 0x00000000;
+SDRAM[1].EmcDllXformQUse2                         = 0x00000000;
+SDRAM[1].EmcDllXformQUse3                         = 0x00000000;
+SDRAM[1].EmcDllXformQUse4                         = 0x00000000;
+SDRAM[1].EmcDllXformQUse5                         = 0x00000000;
+SDRAM[1].EmcDllXformQUse6                         = 0x00000000;
+SDRAM[1].EmcDllXformQUse7                         = 0x00000000;
+SDRAM[1].EmcDllXformAddr0                         = 0x0002c000;
+SDRAM[1].EmcDllXformAddr1                         = 0x0002c000;
+SDRAM[1].EmcDllXformAddr2                         = 0x00000000;
+SDRAM[1].EmcDllXformAddr3                         = 0x0002c000;
+SDRAM[1].EmcDllXformAddr4                         = 0x0002c000;
+SDRAM[1].EmcDllXformAddr5                         = 0x00000000;
+SDRAM[1].EmcDllXformQUse8                         = 0x00000000;
+SDRAM[1].EmcDllXformQUse9                         = 0x00000000;
+SDRAM[1].EmcDllXformQUse10                        = 0x00000000;
+SDRAM[1].EmcDllXformQUse11                        = 0x00000000;
+SDRAM[1].EmcDllXformQUse12                        = 0x00000000;
+SDRAM[1].EmcDllXformQUse13                        = 0x00000000;
+SDRAM[1].EmcDllXformQUse14                        = 0x00000000;
+SDRAM[1].EmcDllXformQUse15                        = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs0                         = 0x00000005;
+SDRAM[1].EmcDliTrimTxDqs1                         = 0x00000005;
+SDRAM[1].EmcDliTrimTxDqs2                         = 0x00000005;
+SDRAM[1].EmcDliTrimTxDqs3                         = 0x00000005;
+SDRAM[1].EmcDliTrimTxDqs4                         = 0x00000005;
+SDRAM[1].EmcDliTrimTxDqs5                         = 0x00000005;
+SDRAM[1].EmcDliTrimTxDqs6                         = 0x00000005;
+SDRAM[1].EmcDliTrimTxDqs7                         = 0x00000005;
+SDRAM[1].EmcDliTrimTxDqs8                         = 0x00000005;
+SDRAM[1].EmcDliTrimTxDqs9                         = 0x00000005;
+SDRAM[1].EmcDliTrimTxDqs10                        = 0x00000005;
+SDRAM[1].EmcDliTrimTxDqs11                        = 0x00000005;
+SDRAM[1].EmcDliTrimTxDqs12                        = 0x00000005;
+SDRAM[1].EmcDliTrimTxDqs13                        = 0x00000005;
+SDRAM[1].EmcDliTrimTxDqs14                        = 0x00000005;
+SDRAM[1].EmcDliTrimTxDqs15                        = 0x00000005;
+SDRAM[1].EmcDllXformDq0                           = 0x00000008;
+SDRAM[1].EmcDllXformDq1                           = 0x00000008;
+SDRAM[1].EmcDllXformDq2                           = 0x00000008;
+SDRAM[1].EmcDllXformDq3                           = 0x00000008;
+SDRAM[1].EmcDllXformDq4                           = 0x00000008;
+SDRAM[1].EmcDllXformDq5                           = 0x00000008;
+SDRAM[1].EmcDllXformDq6                           = 0x00000008;
+SDRAM[1].EmcDllXformDq7                           = 0x00000008;
+SDRAM[1].WarmBootWait                             = 0x00000002;
+SDRAM[1].EmcCttTermCtrl                           = 0x00000802;
+SDRAM[1].EmcOdtWrite                              = 0x00000000;
+SDRAM[1].EmcOdtRead                               = 0x00000000;
+SDRAM[1].EmcZcalInterval                          = 0x00020000;
+SDRAM[1].EmcZcalWaitCnt                           = 0x0000004c;
+SDRAM[1].EmcZcalMrwCmd                            = 0x80000000;
+SDRAM[1].EmcMrsResetDll                           = 0x00000000;
+SDRAM[1].EmcZcalInitDev0                          = 0x80000011;
+SDRAM[1].EmcZcalInitDev1                          = 0x00000000;
+SDRAM[1].EmcZcalInitWait                          = 0x00000001;
+SDRAM[1].EmcZcalWarmColdBootEnables               = 0x00000003;
+SDRAM[1].EmcMrwLpddr2ZcalWarmBoot                 = 0x040a00ab;
+SDRAM[1].EmcZqCalDdr3WarmBoot                     = 0x00000000;
+SDRAM[1].EmcZcalWarmBootWait                      = 0x00000001;
+SDRAM[1].EmcMrsWarmBootEnable                     = 0x00000001;
+SDRAM[1].EmcMrsResetDllWait                       = 0x00000000;
+SDRAM[1].EmcMrsExtra                              = 0x80000f15;
+SDRAM[1].EmcWarmBootMrsExtra                      = 0x80100002;
+SDRAM[1].EmcEmrsDdr2DllEnable                     = 0x00000000;
+SDRAM[1].EmcMrsDdr2DllReset                       = 0x00000000;
+SDRAM[1].EmcEmrsDdr2OcdCalib                      = 0x00000000;
+SDRAM[1].EmcDdr2Wait                              = 0x00000000;
+SDRAM[1].EmcClkenOverride                         = 0x00000000;
+SDRAM[1].McDisExtraSnapLevels                     = 0x00000000;
+SDRAM[1].EmcExtraRefreshNum                       = 0x00000002;
+SDRAM[1].EmcClkenOverrideAllWarmBoot              = 0x00000000;
+SDRAM[1].McClkenOverrideAllWarmBoot               = 0x00000000;
+SDRAM[1].EmcCfgDigDllPeriodWarmBoot               = 0x00000003;
+SDRAM[1].PmcVddpSel                               = 0x00000002;
+SDRAM[1].PmcVddpSelWait                           = 0x00000002;
+SDRAM[1].PmcDdrPwr                                = 0x00000003;
+SDRAM[1].PmcDdrCfg                                = 0x00002002;
+SDRAM[1].PmcIoDpd3Req                             = 0x4fff2f97;
+SDRAM[1].PmcIoDpd3ReqWait                         = 0x00000000;
+SDRAM[1].PmcRegShort                              = 0x00000000;
+SDRAM[1].PmcNoIoPower                             = 0x00000000;
+SDRAM[1].PmcPorDpdCtrlWait                        = 0x00000000;
+SDRAM[1].EmcXm2CmdPadCtrl                         = 0x100002a0;
+SDRAM[1].EmcXm2CmdPadCtrl2                        = 0x770c0000;
+SDRAM[1].EmcXm2CmdPadCtrl3                        = 0x050c0000;
+SDRAM[1].EmcXm2CmdPadCtrl4                        = 0x00000000;
+SDRAM[1].EmcXm2CmdPadCtrl5                        = 0x00111111;
+SDRAM[1].EmcXm2DqsPadCtrl                         = 0x770c1414;
+SDRAM[1].EmcXm2DqsPadCtrl2                        = 0x0120113d;
+SDRAM[1].EmcXm2DqsPadCtrl3                        = 0x5d75d720;
+SDRAM[1].EmcXm2DqsPadCtrl4                        = 0x00514514;
+SDRAM[1].EmcXm2DqsPadCtrl5                        = 0x00514514;
+SDRAM[1].EmcXm2DqsPadCtrl6                        = 0x5d75d700;
+SDRAM[1].EmcXm2DqPadCtrl                          = 0x770c2990;
+SDRAM[1].EmcXm2DqPadCtrl2                         = 0x00000000;
+SDRAM[1].EmcXm2DqPadCtrl3                         = 0x00000000;
+SDRAM[1].EmcXm2ClkPadCtrl                         = 0x77ffc085;
+SDRAM[1].EmcXm2ClkPadCtrl2                        = 0x00000000;
+SDRAM[1].EmcXm2CompPadCtrl                        = 0x81f1f108;
+SDRAM[1].EmcXm2VttGenPadCtrl                      = 0x07070004;
+SDRAM[1].EmcXm2VttGenPadCtrl2                     = 0x00000000;
+SDRAM[1].EmcXm2VttGenPadCtrl3                     = 0x016eeeee;
+SDRAM[1].EmcAcpdControl                           = 0x00000000;
+SDRAM[1].EmcSwizzleRank0ByteCfg                   = 0x00003120;
+SDRAM[1].EmcSwizzleRank0Byte0                     = 0x25143067;
+SDRAM[1].EmcSwizzleRank0Byte1                     = 0x45367102;
+SDRAM[1].EmcSwizzleRank0Byte2                     = 0x47106253;
+SDRAM[1].EmcSwizzleRank0Byte3                     = 0x04362175;
+SDRAM[1].EmcSwizzleRank1ByteCfg                   = 0x00003120;
+SDRAM[1].EmcSwizzleRank1Byte0                     = 0x71546032;
+SDRAM[1].EmcSwizzleRank1Byte1                     = 0x35104276;
+SDRAM[1].EmcSwizzleRank1Byte2                     = 0x27043615;
+SDRAM[1].EmcSwizzleRank1Byte3                     = 0x72306145;
+SDRAM[1].EmcDsrVttgenDrv                          = 0x0606003f;
+SDRAM[1].EmcTxdsrvttgen                           = 0x00000000;
+SDRAM[1].EmcBgbiasCtl0                            = 0x00000000;
+SDRAM[1].McEmemAdrCfg                             = 0x00000000;
+SDRAM[1].McEmemAdrCfgDev0                         = 0x00080303;
+SDRAM[1].McEmemAdrCfgDev1                         = 0x00080303;
+SDRAM[1].McEmemAdrCfgBankMask0                    = 0x00001248;
+SDRAM[1].McEmemAdrCfgBankMask1                    = 0x00002490;
+SDRAM[1].McEmemAdrCfgBankMask2                    = 0x00000920;
+SDRAM[1].McEmemAdrCfgBankSwizzle3                 = 0x00000001;
+SDRAM[1].McEmemCfg                                = 0x00000800;
+SDRAM[1].McEmemArbCfg                             = 0x0e00000d;
+SDRAM[1].McEmemArbOutstandingReq                  = 0x80000040;
+SDRAM[1].McEmemArbTimingRcd                       = 0x00000005;
+SDRAM[1].McEmemArbTimingRp                        = 0x00000006;
+SDRAM[1].McEmemArbTimingRc                        = 0x00000016;
+SDRAM[1].McEmemArbTimingRas                       = 0x0000000e;
+SDRAM[1].McEmemArbTimingFaw                       = 0x00000011;
+SDRAM[1].McEmemArbTimingRrd                       = 0x00000002;
+SDRAM[1].McEmemArbTimingRap2Pre                   = 0x00000004;
+SDRAM[1].McEmemArbTimingWap2Pre                   = 0x0000000e;
+SDRAM[1].McEmemArbTimingR2R                       = 0x00000002;
+SDRAM[1].McEmemArbTimingW2W                       = 0x00000002;
+SDRAM[1].McEmemArbTimingR2W                       = 0x00000006;
+SDRAM[1].McEmemArbTimingW2R                       = 0x00000009;
+SDRAM[1].McEmemArbDaTurns                         = 0x09060202;
+SDRAM[1].McEmemArbDaCovers                        = 0x001a1016;
+SDRAM[1].McEmemArbMisc0                           = 0x734e2a17;
+SDRAM[1].McEmemArbMisc1                           = 0x70000f02;
+SDRAM[1].McEmemArbRing1Throttle                   = 0x001f0000;
+SDRAM[1].McEmemArbOverride                        = 0x10000000;
+SDRAM[1].McEmemArbOverride1                       = 0x00000000;
+SDRAM[1].McEmemArbRsv                             = 0xff00ff00;
+SDRAM[1].McClkenOverride                          = 0x00000000;
+SDRAM[1].McStatControl                            = 0x00000000;
+SDRAM[1].McDisplaySnapRing                        = 0x00000003;
+SDRAM[1].McVideoProtectBom                        = 0xfff00000;
+SDRAM[1].McVideoProtectBomAdrHi                   = 0x00000000;
+SDRAM[1].McVideoProtectSizeMb                     = 0x00000000;
+SDRAM[1].McVideoProtectVprOverride                = 0xe4bac743;
+SDRAM[1].McVideoProtectVprOverride1               = 0x00000013;
+SDRAM[1].McVideoProtectGpuOverride0               = 0x00000000;
+SDRAM[1].McVideoProtectGpuOverride1               = 0x00000000;
+SDRAM[1].McSecCarveoutBom                         = 0xfff00000;
+SDRAM[1].McSecCarveoutAdrHi                       = 0x00000000;
+SDRAM[1].McSecCarveoutSizeMb                      = 0x00000000;
+SDRAM[1].McVideoProtectWriteAccess                = 0x00000000;
+SDRAM[1].McSecCarveoutProtectWriteAccess          = 0x00000000;
+SDRAM[1].EmcCaTrainingEnable                      = 0x00000000;
+SDRAM[1].EmcCaTrainingTimingCntl1                 = 0x1f7df7df;
+SDRAM[1].EmcCaTrainingTimingCntl2                 = 0x0000001f;
+SDRAM[1].SwizzleRankByteEncode                    = 0x0000006f;
+SDRAM[1].BootRomPatchControl                      = 0x00000000;
+SDRAM[1].BootRomPatchData                         = 0x00000000;
+SDRAM[1].McMtsCarveoutBom                         = 0xfff00000;
+SDRAM[1].McMtsCarveoutAdrHi                       = 0x00000000;
+SDRAM[1].McMtsCarveoutSizeMb                      = 0x00000000;
+SDRAM[1].McMtsCarveoutRegCtrl                     = 0x00000000;
+
+SDRAM[2].MemoryType                               = NvBootMemoryType_Ddr3;
+SDRAM[2].PllMInputDivider                         = 0x00000001;
+SDRAM[2].PllMFeedbackDivider                      = 0x0000004d;
+SDRAM[2].PllMStableTime                           = 0x0000012c;
+SDRAM[2].PllMSetupControl                         = 0x00000000;
+SDRAM[2].PllMSelectDiv2                           = 0x00000000;
+SDRAM[2].PllMPDLshiftPh45                         = 0x00000001;
+SDRAM[2].PllMPDLshiftPh90                         = 0x00000001;
+SDRAM[2].PllMPDLshiftPh135                        = 0x00000001;
+SDRAM[2].PllMKCP                                  = 0x00000000;
+SDRAM[2].PllMKVCO                                 = 0x00000000;
+SDRAM[2].EmcBctSpare0                             = 0x00000000;
+SDRAM[2].EmcBctSpare1                             = 0x00000000;
+SDRAM[2].EmcBctSpare2                             = 0x00000000;
+SDRAM[2].EmcBctSpare3                             = 0x00000000;
+SDRAM[2].EmcBctSpare4                             = 0x00000000;
+SDRAM[2].EmcBctSpare5                             = 0x00000000;
+SDRAM[2].EmcBctSpare6                             = 0x00000000;
+SDRAM[2].EmcBctSpare7                             = 0x00000000;
+SDRAM[2].EmcBctSpare8                             = 0x00000000;
+SDRAM[2].EmcBctSpare9                             = 0x00000000;
+SDRAM[2].EmcBctSpare10                            = 0x00000000;
+SDRAM[2].EmcBctSpare11                            = 0x00000000;
+SDRAM[2].EmcClockSource                           = 0x80000000;
+SDRAM[2].EmcAutoCalInterval                       = 0x001fffff;
+SDRAM[2].EmcAutoCalConfig                         = 0xa1430303;
+SDRAM[2].EmcAutoCalConfig2                        = 0x00000000;
+SDRAM[2].EmcAutoCalConfig3                        = 0x00000000;
+SDRAM[2].EmcAutoCalWait                           = 0x00000190;
+SDRAM[2].EmcAdrCfg                                = 0x00000000;
+SDRAM[2].EmcPinProgramWait                        = 0x00000001;
+SDRAM[2].EmcPinExtraWait                          = 0x00000000;
+SDRAM[2].EmcTimingControlWait                     = 0x00000000;
+SDRAM[2].EmcRc                                    = 0x0000002b;
+SDRAM[2].EmcRfc                                   = 0x000000f0;
+SDRAM[2].EmcRfcSlr                                = 0x00000000;
+SDRAM[2].EmcRas                                   = 0x0000001e;
+SDRAM[2].EmcRp                                    = 0x0000000b;
+SDRAM[2].EmcR2r                                   = 0x00000000;
+SDRAM[2].EmcW2w                                   = 0x00000000;
+SDRAM[2].EmcR2w                                   = 0x00000009;
+SDRAM[2].EmcW2r                                   = 0x0000000f;
+SDRAM[2].EmcR2p                                   = 0x00000005;
+SDRAM[2].EmcW2p                                   = 0x00000016;
+SDRAM[2].EmcRdRcd                                 = 0x0000000b;
+SDRAM[2].EmcWrRcd                                 = 0x0000000b;
+SDRAM[2].EmcRrd                                   = 0x00000004;
+SDRAM[2].EmcRext                                  = 0x00000002;
+SDRAM[2].EmcWext                                  = 0x00000000;
+SDRAM[2].EmcWdv                                   = 0x00000007;
+SDRAM[2].EmcWdvMask                               = 0x00000007;
+SDRAM[2].EmcQUse                                  = 0x0000000d;
+SDRAM[2].EmcQuseWidth                             = 0x00000002;
+SDRAM[2].EmcIbdly                                 = 0x00000000;
+SDRAM[2].EmcEInput                                = 0x00000002;
+SDRAM[2].EmcEInputDuration                        = 0x0000000f;
+SDRAM[2].EmcPutermExtra                           = 0x000a0000;
+SDRAM[2].EmcPutermWidth                           = 0x00000004;
+SDRAM[2].EmcPutermAdj                             = 0x00000000;
+SDRAM[2].EmcCdbCntl1                              = 0x00000000;
+SDRAM[2].EmcCdbCntl2                              = 0x00000000;
+SDRAM[2].EmcCdbCntl3                              = 0x00000000;
+SDRAM[2].EmcQRst                                  = 0x00000001;
+SDRAM[2].EmcQSafe                                 = 0x00000016;
+SDRAM[2].EmcRdv                                   = 0x0000001a;
+SDRAM[2].EmcRdvMask                               = 0x0000001c;
+SDRAM[2].EmcQpop                                  = 0x00000011;
+SDRAM[2].EmcCtt                                   = 0x00000000;
+SDRAM[2].EmcCttDuration                           = 0x00000004;
+SDRAM[2].EmcRefresh                               = 0x00001be7;
+SDRAM[2].EmcBurstRefreshNum                       = 0x00000000;
+SDRAM[2].EmcPreRefreshReqCnt                      = 0x000006f9;
+SDRAM[2].EmcPdEx2Wr                               = 0x00000004;
+SDRAM[2].EmcPdEx2Rd                               = 0x00000015;
+SDRAM[2].EmcPChg2Pden                             = 0x00000001;
+SDRAM[2].EmcAct2Pden                              = 0x00000000;
+SDRAM[2].EmcAr2Pden                               = 0x000000e7;
+SDRAM[2].EmcRw2Pden                               = 0x0000001b;
+SDRAM[2].EmcTxsr                                  = 0x000000fb;
+SDRAM[2].EmcTxsrDll                               = 0x00000200;
+SDRAM[2].EmcTcke                                  = 0x00000006;
+SDRAM[2].EmcTckesr                                = 0x00000007;
+SDRAM[2].EmcTpd                                   = 0x00000006;
+SDRAM[2].EmcTfaw                                  = 0x00000022;
+SDRAM[2].EmcTrpab                                 = 0x00000000;
+SDRAM[2].EmcTClkStable                            = 0x0000000a;
+SDRAM[2].EmcTClkStop                              = 0x0000000a;
+SDRAM[2].EmcTRefBw                                = 0x00001c28;
+SDRAM[2].EmcFbioCfg5                              = 0x104ab898;
+SDRAM[2].EmcFbioCfg6                              = 0x00000000;
+SDRAM[2].EmcFbioSpare                             = 0x00000000;
+SDRAM[2].EmcCfgRsv                                = 0xff00ff00;
+SDRAM[2].EmcMrs                                   = 0x80000f15;
+SDRAM[2].EmcEmrs                                  = 0x80100002;
+SDRAM[2].EmcEmrs2                                 = 0x80200020;
+SDRAM[2].EmcEmrs3                                 = 0x80300000;
+SDRAM[2].EmcMrw1                                  = 0x00000000;
+SDRAM[2].EmcMrw2                                  = 0x00000000;
+SDRAM[2].EmcMrw3                                  = 0x00000000;
+SDRAM[2].EmcMrw4                                  = 0x00000000;
+SDRAM[2].EmcMrwExtra                              = 0x00000000;
+SDRAM[2].EmcWarmBootMrwExtra                      = 0x00000000;
+SDRAM[2].EmcWarmBootExtraModeRegWriteEnable       = 0x00000000;
+SDRAM[2].EmcExtraModeRegWriteEnable               = 0x00000000;
+SDRAM[2].EmcMrwResetCommand                       = 0x00000000;
+SDRAM[2].EmcMrwResetNInitWait                     = 0x00000000;
+SDRAM[2].EmcMrsWaitCnt                            = 0x00cd000e;
+SDRAM[2].EmcMrsWaitCnt2                           = 0x00cd000e;
+SDRAM[2].EmcCfg                                   = 0x73300000;
+SDRAM[2].EmcCfg2                                  = 0x0000089d;
+SDRAM[2].EmcCfgPipe                               = 0x00004080;
+SDRAM[2].EmcDbg                                   = 0x01000c00;
+SDRAM[2].EmcCmdQ                                  = 0x10004408;
+SDRAM[2].EmcMc2EmcQ                               = 0x06000404;
+SDRAM[2].EmcDynSelfRefControl                     = 0x800037ea;
+SDRAM[2].AhbArbitrationXbarCtrlMemInitDone        = 0x00000001;
+SDRAM[2].EmcCfgDigDll                             = 0xe00400b1;
+SDRAM[2].EmcCfgDigDllPeriod                       = 0x00008000;
+SDRAM[2].EmcDevSelect                             = 0x00000002;
+SDRAM[2].EmcSelDpdCtrl                            = 0x00040000;
+SDRAM[2].EmcDllXformDqs0                          = 0x007f800a;
+SDRAM[2].EmcDllXformDqs1                          = 0x007f800a;
+SDRAM[2].EmcDllXformDqs2                          = 0x007f800a;
+SDRAM[2].EmcDllXformDqs3                          = 0x007f800a;
+SDRAM[2].EmcDllXformDqs4                          = 0x007f800a;
+SDRAM[2].EmcDllXformDqs5                          = 0x007f800a;
+SDRAM[2].EmcDllXformDqs6                          = 0x007f800a;
+SDRAM[2].EmcDllXformDqs7                          = 0x007f800a;
+SDRAM[2].EmcDllXformDqs8                          = 0x007f800a;
+SDRAM[2].EmcDllXformDqs9                          = 0x007f800a;
+SDRAM[2].EmcDllXformDqs10                         = 0x007f800a;
+SDRAM[2].EmcDllXformDqs11                         = 0x007f800a;
+SDRAM[2].EmcDllXformDqs12                         = 0x007f800a;
+SDRAM[2].EmcDllXformDqs13                         = 0x007f800a;
+SDRAM[2].EmcDllXformDqs14                         = 0x007f800a;
+SDRAM[2].EmcDllXformDqs15                         = 0x007f800a;
+SDRAM[2].EmcDllXformQUse0                         = 0x00000000;
+SDRAM[2].EmcDllXformQUse1                         = 0x00000000;
+SDRAM[2].EmcDllXformQUse2                         = 0x00000000;
+SDRAM[2].EmcDllXformQUse3                         = 0x00000000;
+SDRAM[2].EmcDllXformQUse4                         = 0x00000000;
+SDRAM[2].EmcDllXformQUse5                         = 0x00000000;
+SDRAM[2].EmcDllXformQUse6                         = 0x00000000;
+SDRAM[2].EmcDllXformQUse7                         = 0x00000000;
+SDRAM[2].EmcDllXformAddr0                         = 0x0002c000;
+SDRAM[2].EmcDllXformAddr1                         = 0x0002c000;
+SDRAM[2].EmcDllXformAddr2                         = 0x00000000;
+SDRAM[2].EmcDllXformAddr3                         = 0x0002c000;
+SDRAM[2].EmcDllXformAddr4                         = 0x0002c000;
+SDRAM[2].EmcDllXformAddr5                         = 0x00000000;
+SDRAM[2].EmcDllXformQUse8                         = 0x00000000;
+SDRAM[2].EmcDllXformQUse9                         = 0x00000000;
+SDRAM[2].EmcDllXformQUse10                        = 0x00000000;
+SDRAM[2].EmcDllXformQUse11                        = 0x00000000;
+SDRAM[2].EmcDllXformQUse12                        = 0x00000000;
+SDRAM[2].EmcDllXformQUse13                        = 0x00000000;
+SDRAM[2].EmcDllXformQUse14                        = 0x00000000;
+SDRAM[2].EmcDllXformQUse15                        = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs0                         = 0x00000005;
+SDRAM[2].EmcDliTrimTxDqs1                         = 0x00000005;
+SDRAM[2].EmcDliTrimTxDqs2                         = 0x00000005;
+SDRAM[2].EmcDliTrimTxDqs3                         = 0x00000005;
+SDRAM[2].EmcDliTrimTxDqs4                         = 0x00000005;
+SDRAM[2].EmcDliTrimTxDqs5                         = 0x00000005;
+SDRAM[2].EmcDliTrimTxDqs6                         = 0x00000005;
+SDRAM[2].EmcDliTrimTxDqs7                         = 0x00000005;
+SDRAM[2].EmcDliTrimTxDqs8                         = 0x00000005;
+SDRAM[2].EmcDliTrimTxDqs9                         = 0x00000005;
+SDRAM[2].EmcDliTrimTxDqs10                        = 0x00000005;
+SDRAM[2].EmcDliTrimTxDqs11                        = 0x00000005;
+SDRAM[2].EmcDliTrimTxDqs12                        = 0x00000005;
+SDRAM[2].EmcDliTrimTxDqs13                        = 0x00000005;
+SDRAM[2].EmcDliTrimTxDqs14                        = 0x00000005;
+SDRAM[2].EmcDliTrimTxDqs15                        = 0x00000005;
+SDRAM[2].EmcDllXformDq0                           = 0x00000008;
+SDRAM[2].EmcDllXformDq1                           = 0x00000008;
+SDRAM[2].EmcDllXformDq2                           = 0x00000008;
+SDRAM[2].EmcDllXformDq3                           = 0x00000008;
+SDRAM[2].EmcDllXformDq4                           = 0x00000008;
+SDRAM[2].EmcDllXformDq5                           = 0x00000008;
+SDRAM[2].EmcDllXformDq6                           = 0x00000008;
+SDRAM[2].EmcDllXformDq7                           = 0x00000008;
+SDRAM[2].WarmBootWait                             = 0x00000002;
+SDRAM[2].EmcCttTermCtrl                           = 0x00000802;
+SDRAM[2].EmcOdtWrite                              = 0x00000000;
+SDRAM[2].EmcOdtRead                               = 0x00000000;
+SDRAM[2].EmcZcalInterval                          = 0x00020000;
+SDRAM[2].EmcZcalWaitCnt                           = 0x0000004c;
+SDRAM[2].EmcZcalMrwCmd                            = 0x80000000;
+SDRAM[2].EmcMrsResetDll                           = 0x00000000;
+SDRAM[2].EmcZcalInitDev0                          = 0x80000011;
+SDRAM[2].EmcZcalInitDev1                          = 0x00000000;
+SDRAM[2].EmcZcalInitWait                          = 0x00000001;
+SDRAM[2].EmcZcalWarmColdBootEnables               = 0x00000003;
+SDRAM[2].EmcMrwLpddr2ZcalWarmBoot                 = 0x040a00ab;
+SDRAM[2].EmcZqCalDdr3WarmBoot                     = 0x00000000;
+SDRAM[2].EmcZcalWarmBootWait                      = 0x00000001;
+SDRAM[2].EmcMrsWarmBootEnable                     = 0x00000001;
+SDRAM[2].EmcMrsResetDllWait                       = 0x00000000;
+SDRAM[2].EmcMrsExtra                              = 0x80000f15;
+SDRAM[2].EmcWarmBootMrsExtra                      = 0x80100002;
+SDRAM[2].EmcEmrsDdr2DllEnable                     = 0x00000000;
+SDRAM[2].EmcMrsDdr2DllReset                       = 0x00000000;
+SDRAM[2].EmcEmrsDdr2OcdCalib                      = 0x00000000;
+SDRAM[2].EmcDdr2Wait                              = 0x00000000;
+SDRAM[2].EmcClkenOverride                         = 0x00000000;
+SDRAM[2].McDisExtraSnapLevels                     = 0x00000000;
+SDRAM[2].EmcExtraRefreshNum                       = 0x00000002;
+SDRAM[2].EmcClkenOverrideAllWarmBoot              = 0x00000000;
+SDRAM[2].McClkenOverrideAllWarmBoot               = 0x00000000;
+SDRAM[2].EmcCfgDigDllPeriodWarmBoot               = 0x00000003;
+SDRAM[2].PmcVddpSel                               = 0x00000002;
+SDRAM[2].PmcVddpSelWait                           = 0x00000002;
+SDRAM[2].PmcDdrPwr                                = 0x00000003;
+SDRAM[2].PmcDdrCfg                                = 0x00002002;
+SDRAM[2].PmcIoDpd3Req                             = 0x4fff2f97;
+SDRAM[2].PmcIoDpd3ReqWait                         = 0x00000000;
+SDRAM[2].PmcRegShort                              = 0x00000000;
+SDRAM[2].PmcNoIoPower                             = 0x00000000;
+SDRAM[2].PmcPorDpdCtrlWait                        = 0x00000000;
+SDRAM[2].EmcXm2CmdPadCtrl                         = 0x100002a0;
+SDRAM[2].EmcXm2CmdPadCtrl2                        = 0x770c0000;
+SDRAM[2].EmcXm2CmdPadCtrl3                        = 0x050c0000;
+SDRAM[2].EmcXm2CmdPadCtrl4                        = 0x00000000;
+SDRAM[2].EmcXm2CmdPadCtrl5                        = 0x00111111;
+SDRAM[2].EmcXm2DqsPadCtrl                         = 0x770c1414;
+SDRAM[2].EmcXm2DqsPadCtrl2                        = 0x0120113d;
+SDRAM[2].EmcXm2DqsPadCtrl3                        = 0x5d75d720;
+SDRAM[2].EmcXm2DqsPadCtrl4                        = 0x00514514;
+SDRAM[2].EmcXm2DqsPadCtrl5                        = 0x00514514;
+SDRAM[2].EmcXm2DqsPadCtrl6                        = 0x5d75d700;
+SDRAM[2].EmcXm2DqPadCtrl                          = 0x770c2990;
+SDRAM[2].EmcXm2DqPadCtrl2                         = 0x00000000;
+SDRAM[2].EmcXm2DqPadCtrl3                         = 0x00000000;
+SDRAM[2].EmcXm2ClkPadCtrl                         = 0x77ffc085;
+SDRAM[2].EmcXm2ClkPadCtrl2                        = 0x00000000;
+SDRAM[2].EmcXm2CompPadCtrl                        = 0x81f1f108;
+SDRAM[2].EmcXm2VttGenPadCtrl                      = 0x07070004;
+SDRAM[2].EmcXm2VttGenPadCtrl2                     = 0x00000000;
+SDRAM[2].EmcXm2VttGenPadCtrl3                     = 0x016eeeee;
+SDRAM[2].EmcAcpdControl                           = 0x00000000;
+SDRAM[2].EmcSwizzleRank0ByteCfg                   = 0x00003120;
+SDRAM[2].EmcSwizzleRank0Byte0                     = 0x25143067;
+SDRAM[2].EmcSwizzleRank0Byte1                     = 0x45367102;
+SDRAM[2].EmcSwizzleRank0Byte2                     = 0x47106253;
+SDRAM[2].EmcSwizzleRank0Byte3                     = 0x04362175;
+SDRAM[2].EmcSwizzleRank1ByteCfg                   = 0x00003120;
+SDRAM[2].EmcSwizzleRank1Byte0                     = 0x71546032;
+SDRAM[2].EmcSwizzleRank1Byte1                     = 0x35104276;
+SDRAM[2].EmcSwizzleRank1Byte2                     = 0x27043615;
+SDRAM[2].EmcSwizzleRank1Byte3                     = 0x72306145;
+SDRAM[2].EmcDsrVttgenDrv                          = 0x0606003f;
+SDRAM[2].EmcTxdsrvttgen                           = 0x00000000;
+SDRAM[2].EmcBgbiasCtl0                            = 0x00000000;
+SDRAM[2].McEmemAdrCfg                             = 0x00000000;
+SDRAM[2].McEmemAdrCfgDev0                         = 0x00080303;
+SDRAM[2].McEmemAdrCfgDev1                         = 0x00080303;
+SDRAM[2].McEmemAdrCfgBankMask0                    = 0x00001248;
+SDRAM[2].McEmemAdrCfgBankMask1                    = 0x00002490;
+SDRAM[2].McEmemAdrCfgBankMask2                    = 0x00000920;
+SDRAM[2].McEmemAdrCfgBankSwizzle3                 = 0x00000001;
+SDRAM[2].McEmemCfg                                = 0x00000800;
+SDRAM[2].McEmemArbCfg                             = 0x0e00000d;
+SDRAM[2].McEmemArbOutstandingReq                  = 0x80000040;
+SDRAM[2].McEmemArbTimingRcd                       = 0x00000005;
+SDRAM[2].McEmemArbTimingRp                        = 0x00000006;
+SDRAM[2].McEmemArbTimingRc                        = 0x00000016;
+SDRAM[2].McEmemArbTimingRas                       = 0x0000000e;
+SDRAM[2].McEmemArbTimingFaw                       = 0x00000011;
+SDRAM[2].McEmemArbTimingRrd                       = 0x00000002;
+SDRAM[2].McEmemArbTimingRap2Pre                   = 0x00000004;
+SDRAM[2].McEmemArbTimingWap2Pre                   = 0x0000000e;
+SDRAM[2].McEmemArbTimingR2R                       = 0x00000002;
+SDRAM[2].McEmemArbTimingW2W                       = 0x00000002;
+SDRAM[2].McEmemArbTimingR2W                       = 0x00000006;
+SDRAM[2].McEmemArbTimingW2R                       = 0x00000009;
+SDRAM[2].McEmemArbDaTurns                         = 0x09060202;
+SDRAM[2].McEmemArbDaCovers                        = 0x001a1016;
+SDRAM[2].McEmemArbMisc0                           = 0x734e2a17;
+SDRAM[2].McEmemArbMisc1                           = 0x70000f02;
+SDRAM[2].McEmemArbRing1Throttle                   = 0x001f0000;
+SDRAM[2].McEmemArbOverride                        = 0x10000000;
+SDRAM[2].McEmemArbOverride1                       = 0x00000000;
+SDRAM[2].McEmemArbRsv                             = 0xff00ff00;
+SDRAM[2].McClkenOverride                          = 0x00000000;
+SDRAM[2].McStatControl                            = 0x00000000;
+SDRAM[2].McDisplaySnapRing                        = 0x00000003;
+SDRAM[2].McVideoProtectBom                        = 0xfff00000;
+SDRAM[2].McVideoProtectBomAdrHi                   = 0x00000000;
+SDRAM[2].McVideoProtectSizeMb                     = 0x00000000;
+SDRAM[2].McVideoProtectVprOverride                = 0xe4bac743;
+SDRAM[2].McVideoProtectVprOverride1               = 0x00000013;
+SDRAM[2].McVideoProtectGpuOverride0               = 0x00000000;
+SDRAM[2].McVideoProtectGpuOverride1               = 0x00000000;
+SDRAM[2].McSecCarveoutBom                         = 0xfff00000;
+SDRAM[2].McSecCarveoutAdrHi                       = 0x00000000;
+SDRAM[2].McSecCarveoutSizeMb                      = 0x00000000;
+SDRAM[2].McVideoProtectWriteAccess                = 0x00000000;
+SDRAM[2].McSecCarveoutProtectWriteAccess          = 0x00000000;
+SDRAM[2].EmcCaTrainingEnable                      = 0x00000000;
+SDRAM[2].EmcCaTrainingTimingCntl1                 = 0x1f7df7df;
+SDRAM[2].EmcCaTrainingTimingCntl2                 = 0x0000001f;
+SDRAM[2].SwizzleRankByteEncode                    = 0x0000006f;
+SDRAM[2].BootRomPatchControl                      = 0x00000000;
+SDRAM[2].BootRomPatchData                         = 0x00000000;
+SDRAM[2].McMtsCarveoutBom                         = 0xfff00000;
+SDRAM[2].McMtsCarveoutAdrHi                       = 0x00000000;
+SDRAM[2].McMtsCarveoutSizeMb                      = 0x00000000;
+SDRAM[2].McMtsCarveoutRegCtrl                     = 0x00000000;
+
+SDRAM[3].MemoryType                               = NvBootMemoryType_Ddr3;
+SDRAM[3].PllMInputDivider                         = 0x00000001;
+SDRAM[3].PllMFeedbackDivider                      = 0x0000004d;
+SDRAM[3].PllMStableTime                           = 0x0000012c;
+SDRAM[3].PllMSetupControl                         = 0x00000000;
+SDRAM[3].PllMSelectDiv2                           = 0x00000000;
+SDRAM[3].PllMPDLshiftPh45                         = 0x00000001;
+SDRAM[3].PllMPDLshiftPh90                         = 0x00000001;
+SDRAM[3].PllMPDLshiftPh135                        = 0x00000001;
+SDRAM[3].PllMKCP                                  = 0x00000000;
+SDRAM[3].PllMKVCO                                 = 0x00000000;
+SDRAM[3].EmcBctSpare0                             = 0x00000000;
+SDRAM[3].EmcBctSpare1                             = 0x00000000;
+SDRAM[3].EmcBctSpare2                             = 0x00000000;
+SDRAM[3].EmcBctSpare3                             = 0x00000000;
+SDRAM[3].EmcBctSpare4                             = 0x00000000;
+SDRAM[3].EmcBctSpare5                             = 0x00000000;
+SDRAM[3].EmcBctSpare6                             = 0x00000000;
+SDRAM[3].EmcBctSpare7                             = 0x00000000;
+SDRAM[3].EmcBctSpare8                             = 0x00000000;
+SDRAM[3].EmcBctSpare9                             = 0x00000000;
+SDRAM[3].EmcBctSpare10                            = 0x00000000;
+SDRAM[3].EmcBctSpare11                            = 0x00000000;
+SDRAM[3].EmcClockSource                           = 0x80000000;
+SDRAM[3].EmcAutoCalInterval                       = 0x001fffff;
+SDRAM[3].EmcAutoCalConfig                         = 0xa1430303;
+SDRAM[3].EmcAutoCalConfig2                        = 0x00000000;
+SDRAM[3].EmcAutoCalConfig3                        = 0x00000000;
+SDRAM[3].EmcAutoCalWait                           = 0x00000190;
+SDRAM[3].EmcAdrCfg                                = 0x00000000;
+SDRAM[3].EmcPinProgramWait                        = 0x00000001;
+SDRAM[3].EmcPinExtraWait                          = 0x00000000;
+SDRAM[3].EmcTimingControlWait                     = 0x00000000;
+SDRAM[3].EmcRc                                    = 0x0000002b;
+SDRAM[3].EmcRfc                                   = 0x000000f0;
+SDRAM[3].EmcRfcSlr                                = 0x00000000;
+SDRAM[3].EmcRas                                   = 0x0000001e;
+SDRAM[3].EmcRp                                    = 0x0000000b;
+SDRAM[3].EmcR2r                                   = 0x00000000;
+SDRAM[3].EmcW2w                                   = 0x00000000;
+SDRAM[3].EmcR2w                                   = 0x00000009;
+SDRAM[3].EmcW2r                                   = 0x0000000f;
+SDRAM[3].EmcR2p                                   = 0x00000005;
+SDRAM[3].EmcW2p                                   = 0x00000016;
+SDRAM[3].EmcRdRcd                                 = 0x0000000b;
+SDRAM[3].EmcWrRcd                                 = 0x0000000b;
+SDRAM[3].EmcRrd                                   = 0x00000004;
+SDRAM[3].EmcRext                                  = 0x00000002;
+SDRAM[3].EmcWext                                  = 0x00000000;
+SDRAM[3].EmcWdv                                   = 0x00000007;
+SDRAM[3].EmcWdvMask                               = 0x00000007;
+SDRAM[3].EmcQUse                                  = 0x0000000d;
+SDRAM[3].EmcQuseWidth                             = 0x00000002;
+SDRAM[3].EmcIbdly                                 = 0x00000000;
+SDRAM[3].EmcEInput                                = 0x00000002;
+SDRAM[3].EmcEInputDuration                        = 0x0000000f;
+SDRAM[3].EmcPutermExtra                           = 0x000a0000;
+SDRAM[3].EmcPutermWidth                           = 0x00000004;
+SDRAM[3].EmcPutermAdj                             = 0x00000000;
+SDRAM[3].EmcCdbCntl1                              = 0x00000000;
+SDRAM[3].EmcCdbCntl2                              = 0x00000000;
+SDRAM[3].EmcCdbCntl3                              = 0x00000000;
+SDRAM[3].EmcQRst                                  = 0x00000001;
+SDRAM[3].EmcQSafe                                 = 0x00000016;
+SDRAM[3].EmcRdv                                   = 0x0000001a;
+SDRAM[3].EmcRdvMask                               = 0x0000001c;
+SDRAM[3].EmcQpop                                  = 0x00000011;
+SDRAM[3].EmcCtt                                   = 0x00000000;
+SDRAM[3].EmcCttDuration                           = 0x00000004;
+SDRAM[3].EmcRefresh                               = 0x00001be7;
+SDRAM[3].EmcBurstRefreshNum                       = 0x00000000;
+SDRAM[3].EmcPreRefreshReqCnt                      = 0x000006f9;
+SDRAM[3].EmcPdEx2Wr                               = 0x00000004;
+SDRAM[3].EmcPdEx2Rd                               = 0x00000015;
+SDRAM[3].EmcPChg2Pden                             = 0x00000001;
+SDRAM[3].EmcAct2Pden                              = 0x00000000;
+SDRAM[3].EmcAr2Pden                               = 0x000000e7;
+SDRAM[3].EmcRw2Pden                               = 0x0000001b;
+SDRAM[3].EmcTxsr                                  = 0x000000fb;
+SDRAM[3].EmcTxsrDll                               = 0x00000200;
+SDRAM[3].EmcTcke                                  = 0x00000006;
+SDRAM[3].EmcTckesr                                = 0x00000007;
+SDRAM[3].EmcTpd                                   = 0x00000006;
+SDRAM[3].EmcTfaw                                  = 0x00000022;
+SDRAM[3].EmcTrpab                                 = 0x00000000;
+SDRAM[3].EmcTClkStable                            = 0x0000000a;
+SDRAM[3].EmcTClkStop                              = 0x0000000a;
+SDRAM[3].EmcTRefBw                                = 0x00001c28;
+SDRAM[3].EmcFbioCfg5                              = 0x104ab898;
+SDRAM[3].EmcFbioCfg6                              = 0x00000000;
+SDRAM[3].EmcFbioSpare                             = 0x00000000;
+SDRAM[3].EmcCfgRsv                                = 0xff00ff00;
+SDRAM[3].EmcMrs                                   = 0x80000f15;
+SDRAM[3].EmcEmrs                                  = 0x80100002;
+SDRAM[3].EmcEmrs2                                 = 0x80200020;
+SDRAM[3].EmcEmrs3                                 = 0x80300000;
+SDRAM[3].EmcMrw1                                  = 0x00000000;
+SDRAM[3].EmcMrw2                                  = 0x00000000;
+SDRAM[3].EmcMrw3                                  = 0x00000000;
+SDRAM[3].EmcMrw4                                  = 0x00000000;
+SDRAM[3].EmcMrwExtra                              = 0x00000000;
+SDRAM[3].EmcWarmBootMrwExtra                      = 0x00000000;
+SDRAM[3].EmcWarmBootExtraModeRegWriteEnable       = 0x00000000;
+SDRAM[3].EmcExtraModeRegWriteEnable               = 0x00000000;
+SDRAM[3].EmcMrwResetCommand                       = 0x00000000;
+SDRAM[3].EmcMrwResetNInitWait                     = 0x00000000;
+SDRAM[3].EmcMrsWaitCnt                            = 0x00cd000e;
+SDRAM[3].EmcMrsWaitCnt2                           = 0x00cd000e;
+SDRAM[3].EmcCfg                                   = 0x73300000;
+SDRAM[3].EmcCfg2                                  = 0x0000089d;
+SDRAM[3].EmcCfgPipe                               = 0x00004080;
+SDRAM[3].EmcDbg                                   = 0x01000c00;
+SDRAM[3].EmcCmdQ                                  = 0x10004408;
+SDRAM[3].EmcMc2EmcQ                               = 0x06000404;
+SDRAM[3].EmcDynSelfRefControl                     = 0x800037ea;
+SDRAM[3].AhbArbitrationXbarCtrlMemInitDone        = 0x00000001;
+SDRAM[3].EmcCfgDigDll                             = 0xe00400b1;
+SDRAM[3].EmcCfgDigDllPeriod                       = 0x00008000;
+SDRAM[3].EmcDevSelect                             = 0x00000002;
+SDRAM[3].EmcSelDpdCtrl                            = 0x00040000;
+SDRAM[3].EmcDllXformDqs0                          = 0x007f800a;
+SDRAM[3].EmcDllXformDqs1                          = 0x007f800a;
+SDRAM[3].EmcDllXformDqs2                          = 0x007f800a;
+SDRAM[3].EmcDllXformDqs3                          = 0x007f800a;
+SDRAM[3].EmcDllXformDqs4                          = 0x007f800a;
+SDRAM[3].EmcDllXformDqs5                          = 0x007f800a;
+SDRAM[3].EmcDllXformDqs6                          = 0x007f800a;
+SDRAM[3].EmcDllXformDqs7                          = 0x007f800a;
+SDRAM[3].EmcDllXformDqs8                          = 0x007f800a;
+SDRAM[3].EmcDllXformDqs9                          = 0x007f800a;
+SDRAM[3].EmcDllXformDqs10                         = 0x007f800a;
+SDRAM[3].EmcDllXformDqs11                         = 0x007f800a;
+SDRAM[3].EmcDllXformDqs12                         = 0x007f800a;
+SDRAM[3].EmcDllXformDqs13                         = 0x007f800a;
+SDRAM[3].EmcDllXformDqs14                         = 0x007f800a;
+SDRAM[3].EmcDllXformDqs15                         = 0x007f800a;
+SDRAM[3].EmcDllXformQUse0                         = 0x00000000;
+SDRAM[3].EmcDllXformQUse1                         = 0x00000000;
+SDRAM[3].EmcDllXformQUse2                         = 0x00000000;
+SDRAM[3].EmcDllXformQUse3                         = 0x00000000;
+SDRAM[3].EmcDllXformQUse4                         = 0x00000000;
+SDRAM[3].EmcDllXformQUse5                         = 0x00000000;
+SDRAM[3].EmcDllXformQUse6                         = 0x00000000;
+SDRAM[3].EmcDllXformQUse7                         = 0x00000000;
+SDRAM[3].EmcDllXformAddr0                         = 0x0002c000;
+SDRAM[3].EmcDllXformAddr1                         = 0x0002c000;
+SDRAM[3].EmcDllXformAddr2                         = 0x00000000;
+SDRAM[3].EmcDllXformAddr3                         = 0x0002c000;
+SDRAM[3].EmcDllXformAddr4                         = 0x0002c000;
+SDRAM[3].EmcDllXformAddr5                         = 0x00000000;
+SDRAM[3].EmcDllXformQUse8                         = 0x00000000;
+SDRAM[3].EmcDllXformQUse9                         = 0x00000000;
+SDRAM[3].EmcDllXformQUse10                        = 0x00000000;
+SDRAM[3].EmcDllXformQUse11                        = 0x00000000;
+SDRAM[3].EmcDllXformQUse12                        = 0x00000000;
+SDRAM[3].EmcDllXformQUse13                        = 0x00000000;
+SDRAM[3].EmcDllXformQUse14                        = 0x00000000;
+SDRAM[3].EmcDllXformQUse15                        = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs0                         = 0x00000005;
+SDRAM[3].EmcDliTrimTxDqs1                         = 0x00000005;
+SDRAM[3].EmcDliTrimTxDqs2                         = 0x00000005;
+SDRAM[3].EmcDliTrimTxDqs3                         = 0x00000005;
+SDRAM[3].EmcDliTrimTxDqs4                         = 0x00000005;
+SDRAM[3].EmcDliTrimTxDqs5                         = 0x00000005;
+SDRAM[3].EmcDliTrimTxDqs6                         = 0x00000005;
+SDRAM[3].EmcDliTrimTxDqs7                         = 0x00000005;
+SDRAM[3].EmcDliTrimTxDqs8                         = 0x00000005;
+SDRAM[3].EmcDliTrimTxDqs9                         = 0x00000005;
+SDRAM[3].EmcDliTrimTxDqs10                        = 0x00000005;
+SDRAM[3].EmcDliTrimTxDqs11                        = 0x00000005;
+SDRAM[3].EmcDliTrimTxDqs12                        = 0x00000005;
+SDRAM[3].EmcDliTrimTxDqs13                        = 0x00000005;
+SDRAM[3].EmcDliTrimTxDqs14                        = 0x00000005;
+SDRAM[3].EmcDliTrimTxDqs15                        = 0x00000005;
+SDRAM[3].EmcDllXformDq0                           = 0x00000008;
+SDRAM[3].EmcDllXformDq1                           = 0x00000008;
+SDRAM[3].EmcDllXformDq2                           = 0x00000008;
+SDRAM[3].EmcDllXformDq3                           = 0x00000008;
+SDRAM[3].EmcDllXformDq4                           = 0x00000008;
+SDRAM[3].EmcDllXformDq5                           = 0x00000008;
+SDRAM[3].EmcDllXformDq6                           = 0x00000008;
+SDRAM[3].EmcDllXformDq7                           = 0x00000008;
+SDRAM[3].WarmBootWait                             = 0x00000002;
+SDRAM[3].EmcCttTermCtrl                           = 0x00000802;
+SDRAM[3].EmcOdtWrite                              = 0x00000000;
+SDRAM[3].EmcOdtRead                               = 0x00000000;
+SDRAM[3].EmcZcalInterval                          = 0x00020000;
+SDRAM[3].EmcZcalWaitCnt                           = 0x0000004c;
+SDRAM[3].EmcZcalMrwCmd                            = 0x80000000;
+SDRAM[3].EmcMrsResetDll                           = 0x00000000;
+SDRAM[3].EmcZcalInitDev0                          = 0x80000011;
+SDRAM[3].EmcZcalInitDev1                          = 0x00000000;
+SDRAM[3].EmcZcalInitWait                          = 0x00000001;
+SDRAM[3].EmcZcalWarmColdBootEnables               = 0x00000003;
+SDRAM[3].EmcMrwLpddr2ZcalWarmBoot                 = 0x040a00ab;
+SDRAM[3].EmcZqCalDdr3WarmBoot                     = 0x00000000;
+SDRAM[3].EmcZcalWarmBootWait                      = 0x00000001;
+SDRAM[3].EmcMrsWarmBootEnable                     = 0x00000001;
+SDRAM[3].EmcMrsResetDllWait                       = 0x00000000;
+SDRAM[3].EmcMrsExtra                              = 0x80000f15;
+SDRAM[3].EmcWarmBootMrsExtra                      = 0x80100002;
+SDRAM[3].EmcEmrsDdr2DllEnable                     = 0x00000000;
+SDRAM[3].EmcMrsDdr2DllReset                       = 0x00000000;
+SDRAM[3].EmcEmrsDdr2OcdCalib                      = 0x00000000;
+SDRAM[3].EmcDdr2Wait                              = 0x00000000;
+SDRAM[3].EmcClkenOverride                         = 0x00000000;
+SDRAM[3].McDisExtraSnapLevels                     = 0x00000000;
+SDRAM[3].EmcExtraRefreshNum                       = 0x00000002;
+SDRAM[3].EmcClkenOverrideAllWarmBoot              = 0x00000000;
+SDRAM[3].McClkenOverrideAllWarmBoot               = 0x00000000;
+SDRAM[3].EmcCfgDigDllPeriodWarmBoot               = 0x00000003;
+SDRAM[3].PmcVddpSel                               = 0x00000002;
+SDRAM[3].PmcVddpSelWait                           = 0x00000002;
+SDRAM[3].PmcDdrPwr                                = 0x00000003;
+SDRAM[3].PmcDdrCfg                                = 0x00002002;
+SDRAM[3].PmcIoDpd3Req                             = 0x4fff2f97;
+SDRAM[3].PmcIoDpd3ReqWait                         = 0x00000000;
+SDRAM[3].PmcRegShort                              = 0x00000000;
+SDRAM[3].PmcNoIoPower                             = 0x00000000;
+SDRAM[3].PmcPorDpdCtrlWait                        = 0x00000000;
+SDRAM[3].EmcXm2CmdPadCtrl                         = 0x100002a0;
+SDRAM[3].EmcXm2CmdPadCtrl2                        = 0x770c0000;
+SDRAM[3].EmcXm2CmdPadCtrl3                        = 0x050c0000;
+SDRAM[3].EmcXm2CmdPadCtrl4                        = 0x00000000;
+SDRAM[3].EmcXm2CmdPadCtrl5                        = 0x00111111;
+SDRAM[3].EmcXm2DqsPadCtrl                         = 0x770c1414;
+SDRAM[3].EmcXm2DqsPadCtrl2                        = 0x0120113d;
+SDRAM[3].EmcXm2DqsPadCtrl3                        = 0x5d75d720;
+SDRAM[3].EmcXm2DqsPadCtrl4                        = 0x00514514;
+SDRAM[3].EmcXm2DqsPadCtrl5                        = 0x00514514;
+SDRAM[3].EmcXm2DqsPadCtrl6                        = 0x5d75d700;
+SDRAM[3].EmcXm2DqPadCtrl                          = 0x770c2990;
+SDRAM[3].EmcXm2DqPadCtrl2                         = 0x00000000;
+SDRAM[3].EmcXm2DqPadCtrl3                         = 0x00000000;
+SDRAM[3].EmcXm2ClkPadCtrl                         = 0x77ffc085;
+SDRAM[3].EmcXm2ClkPadCtrl2                        = 0x00000000;
+SDRAM[3].EmcXm2CompPadCtrl                        = 0x81f1f108;
+SDRAM[3].EmcXm2VttGenPadCtrl                      = 0x07070004;
+SDRAM[3].EmcXm2VttGenPadCtrl2                     = 0x00000000;
+SDRAM[3].EmcXm2VttGenPadCtrl3                     = 0x016eeeee;
+SDRAM[3].EmcAcpdControl                           = 0x00000000;
+SDRAM[3].EmcSwizzleRank0ByteCfg                   = 0x00003120;
+SDRAM[3].EmcSwizzleRank0Byte0                     = 0x25143067;
+SDRAM[3].EmcSwizzleRank0Byte1                     = 0x45367102;
+SDRAM[3].EmcSwizzleRank0Byte2                     = 0x47106253;
+SDRAM[3].EmcSwizzleRank0Byte3                     = 0x04362175;
+SDRAM[3].EmcSwizzleRank1ByteCfg                   = 0x00003120;
+SDRAM[3].EmcSwizzleRank1Byte0                     = 0x71546032;
+SDRAM[3].EmcSwizzleRank1Byte1                     = 0x35104276;
+SDRAM[3].EmcSwizzleRank1Byte2                     = 0x27043615;
+SDRAM[3].EmcSwizzleRank1Byte3                     = 0x72306145;
+SDRAM[3].EmcDsrVttgenDrv                          = 0x0606003f;
+SDRAM[3].EmcTxdsrvttgen                           = 0x00000000;
+SDRAM[3].EmcBgbiasCtl0                            = 0x00000000;
+SDRAM[3].McEmemAdrCfg                             = 0x00000000;
+SDRAM[3].McEmemAdrCfgDev0                         = 0x00080303;
+SDRAM[3].McEmemAdrCfgDev1                         = 0x00080303;
+SDRAM[3].McEmemAdrCfgBankMask0                    = 0x00001248;
+SDRAM[3].McEmemAdrCfgBankMask1                    = 0x00002490;
+SDRAM[3].McEmemAdrCfgBankMask2                    = 0x00000920;
+SDRAM[3].McEmemAdrCfgBankSwizzle3                 = 0x00000001;
+SDRAM[3].McEmemCfg                                = 0x00000800;
+SDRAM[3].McEmemArbCfg                             = 0x0e00000d;
+SDRAM[3].McEmemArbOutstandingReq                  = 0x80000040;
+SDRAM[3].McEmemArbTimingRcd                       = 0x00000005;
+SDRAM[3].McEmemArbTimingRp                        = 0x00000006;
+SDRAM[3].McEmemArbTimingRc                        = 0x00000016;
+SDRAM[3].McEmemArbTimingRas                       = 0x0000000e;
+SDRAM[3].McEmemArbTimingFaw                       = 0x00000011;
+SDRAM[3].McEmemArbTimingRrd                       = 0x00000002;
+SDRAM[3].McEmemArbTimingRap2Pre                   = 0x00000004;
+SDRAM[3].McEmemArbTimingWap2Pre                   = 0x0000000e;
+SDRAM[3].McEmemArbTimingR2R                       = 0x00000002;
+SDRAM[3].McEmemArbTimingW2W                       = 0x00000002;
+SDRAM[3].McEmemArbTimingR2W                       = 0x00000006;
+SDRAM[3].McEmemArbTimingW2R                       = 0x00000009;
+SDRAM[3].McEmemArbDaTurns                         = 0x09060202;
+SDRAM[3].McEmemArbDaCovers                        = 0x001a1016;
+SDRAM[3].McEmemArbMisc0                           = 0x734e2a17;
+SDRAM[3].McEmemArbMisc1                           = 0x70000f02;
+SDRAM[3].McEmemArbRing1Throttle                   = 0x001f0000;
+SDRAM[3].McEmemArbOverride                        = 0x10000000;
+SDRAM[3].McEmemArbOverride1                       = 0x00000000;
+SDRAM[3].McEmemArbRsv                             = 0xff00ff00;
+SDRAM[3].McClkenOverride                          = 0x00000000;
+SDRAM[3].McStatControl                            = 0x00000000;
+SDRAM[3].McDisplaySnapRing                        = 0x00000003;
+SDRAM[3].McVideoProtectBom                        = 0xfff00000;
+SDRAM[3].McVideoProtectBomAdrHi                   = 0x00000000;
+SDRAM[3].McVideoProtectSizeMb                     = 0x00000000;
+SDRAM[3].McVideoProtectVprOverride                = 0xe4bac743;
+SDRAM[3].McVideoProtectVprOverride1               = 0x00000013;
+SDRAM[3].McVideoProtectGpuOverride0               = 0x00000000;
+SDRAM[3].McVideoProtectGpuOverride1               = 0x00000000;
+SDRAM[3].McSecCarveoutBom                         = 0xfff00000;
+SDRAM[3].McSecCarveoutAdrHi                       = 0x00000000;
+SDRAM[3].McSecCarveoutSizeMb                      = 0x00000000;
+SDRAM[3].McVideoProtectWriteAccess                = 0x00000000;
+SDRAM[3].McSecCarveoutProtectWriteAccess          = 0x00000000;
+SDRAM[3].EmcCaTrainingEnable                      = 0x00000000;
+SDRAM[3].EmcCaTrainingTimingCntl1                 = 0x1f7df7df;
+SDRAM[3].EmcCaTrainingTimingCntl2                 = 0x0000001f;
+SDRAM[3].SwizzleRankByteEncode                    = 0x0000006f;
+SDRAM[3].BootRomPatchControl                      = 0x00000000;
+SDRAM[3].BootRomPatchData                         = 0x00000000;
+SDRAM[3].McMtsCarveoutBom                         = 0xfff00000;
+SDRAM[3].McMtsCarveoutAdrHi                       = 0x00000000;
+SDRAM[3].McMtsCarveoutSizeMb                      = 0x00000000;
+SDRAM[3].McMtsCarveoutRegCtrl                     = 0x00000000;
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 63d59f7..ef65302 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -37,7 +37,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb \
 dtb-$(CONFIG_ARCH_TEGRA) += \
 	tegra20-colibri-iris.dtb \
 	tegra20-paz00.dtb \
-	tegra30-beaver.dtb
+	tegra30-beaver.dtb \
+	tegra124-jetson-tk1.dtb
 
 BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME))
 obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
@@ -50,6 +51,7 @@ pbl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o
 pbl-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o
 pbl-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o
 pbl-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o
+pbl-$(CONFIG_MACH_NVIDIA_JETSON) += tegra124-jetson-tk1.dtb.o
 pbl-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore.dtb.o
 pbl-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o
 pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o
diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts
new file mode 100644
index 0000000..16082c0
--- /dev/null
+++ b/arch/arm/dts/tegra124-jetson-tk1.dts
@@ -0,0 +1,1828 @@
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra124.dtsi"
+
+/ {
+	model = "NVIDIA Tegra124 Jetson TK1";
+	compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
+
+	aliases {
+		rtc0 = "/i2c@0,7000d000/pmic@40";
+		rtc1 = "/rtc@0,7000e000";
+	};
+
+	memory {
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+
+	host1x@0,50000000 {
+		hdmi@0,54280000 {
+			status = "okay";
+
+			hdmi-supply = <&vdd_5v0_hdmi>;
+			pll-supply = <&vdd_hdmi_pll>;
+			vdd-supply = <&vdd_3v3_hdmi>;
+
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+			nvidia,hpd-gpio =
+				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	pinmux: pinmux@0,70000868 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			clk_32k_out_pa0 {
+				nvidia,pins = "clk_32k_out_pa0";
+				nvidia,function = "soc";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			uart3_cts_n_pa1 {
+				nvidia,pins = "uart3_cts_n_pa1";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap2_fs_pa2 {
+				nvidia,pins = "dap2_fs_pa2";
+				nvidia,function = "i2s1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap2_sclk_pa3 {
+				nvidia,pins = "dap2_sclk_pa3";
+				nvidia,function = "i2s1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap2_din_pa4 {
+				nvidia,pins = "dap2_din_pa4";
+				nvidia,function = "i2s1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap2_dout_pa5 {
+				nvidia,pins = "dap2_dout_pa5";
+				nvidia,function = "i2s1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3_clk_pa6 {
+				nvidia,pins = "sdmmc3_clk_pa6";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			sdmmc3_cmd_pa7 {
+				nvidia,pins = "sdmmc3_cmd_pa7";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pb0 {
+				nvidia,pins = "pb0";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pb1 {
+				nvidia,pins = "pb1";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3_dat3_pb4 {
+				nvidia,pins = "sdmmc3_dat3_pb4";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3_dat2_pb5 {
+				nvidia,pins = "sdmmc3_dat2_pb5";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3_dat1_pb6 {
+				nvidia,pins = "sdmmc3_dat1_pb6";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3_dat0_pb7 {
+				nvidia,pins = "sdmmc3_dat0_pb7";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			uart3_rts_n_pc0 {
+				nvidia,pins = "uart3_rts_n_pc0";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			uart2_txd_pc2 {
+				nvidia,pins = "uart2_txd_pc2";
+				nvidia,function = "irda";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			uart2_rxd_pc3 {
+				nvidia,pins = "uart2_rxd_pc3";
+				nvidia,function = "irda";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gen1_i2c_scl_pc4 {
+				nvidia,pins = "gen1_i2c_scl_pc4";
+				nvidia,function = "i2c1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			gen1_i2c_sda_pc5 {
+				nvidia,pins = "gen1_i2c_sda_pc5";
+				nvidia,function = "i2c1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			pc7 {
+				nvidia,pins = "pc7";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pg0 {
+				nvidia,pins = "pg0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pg1 {
+				nvidia,pins = "pg1";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pg2 {
+				nvidia,pins = "pg2";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pg3 {
+				nvidia,pins = "pg3";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pg4 {
+				nvidia,pins = "pg4";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pg5 {
+				nvidia,pins = "pg5";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pg6 {
+				nvidia,pins = "pg6";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pg7 {
+				nvidia,pins = "pg7";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			ph0 {
+				nvidia,pins = "ph0";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ph1 {
+				nvidia,pins = "ph1";
+				nvidia,function = "pwm1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ph2 {
+				nvidia,pins = "ph2";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ph3 {
+				nvidia,pins = "ph3";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ph4 {
+				nvidia,pins = "ph4";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			ph5 {
+				nvidia,pins = "ph5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ph6 {
+				nvidia,pins = "ph6";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			ph7 {
+				nvidia,pins = "ph7";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pi0 {
+				nvidia,pins = "pi0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pi1 {
+				nvidia,pins = "pi1";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pi2 {
+				nvidia,pins = "pi2";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pi3 {
+				nvidia,pins = "pi3";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pi4 {
+				nvidia,pins = "pi4";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pi5 {
+				nvidia,pins = "pi5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pi6 {
+				nvidia,pins = "pi6";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pi7 {
+				nvidia,pins = "pi7";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pj0 {
+				nvidia,pins = "pj0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pj2 {
+				nvidia,pins = "pj2";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			uart2_cts_n_pj5 {
+				nvidia,pins = "uart2_cts_n_pj5";
+				nvidia,function = "uartb";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			uart2_rts_n_pj6 {
+				nvidia,pins = "uart2_rts_n_pj6";
+				nvidia,function = "uartb";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pj7 {
+				nvidia,pins = "pj7";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pk0 {
+				nvidia,pins = "pk0";
+				nvidia,function = "soc";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pk1 {
+				nvidia,pins = "pk1";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pk2 {
+				nvidia,pins = "pk2";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pk3 {
+				nvidia,pins = "pk3";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pk4 {
+				nvidia,pins = "pk4";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			spdif_out_pk5 {
+				nvidia,pins = "spdif_out_pk5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			spdif_in_pk6 {
+				nvidia,pins = "spdif_in_pk6";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pk7 {
+				nvidia,pins = "pk7";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap1_fs_pn0 {
+				nvidia,pins = "dap1_fs_pn0";
+				nvidia,function = "i2s0";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap1_din_pn1 {
+				nvidia,pins = "dap1_din_pn1";
+				nvidia,function = "i2s0";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap1_dout_pn2 {
+				nvidia,pins = "dap1_dout_pn2";
+				nvidia,function = "sata";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap1_sclk_pn3 {
+				nvidia,pins = "dap1_sclk_pn3";
+				nvidia,function = "i2s0";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			usb_vbus_en0_pn4 {
+				nvidia,pins = "usb_vbus_en0_pn4";
+				nvidia,function = "usb";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			usb_vbus_en1_pn5 {
+				nvidia,pins = "usb_vbus_en1_pn5";
+				nvidia,function = "usb";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			hdmi_int_pn7 {
+				nvidia,pins = "hdmi_int_pn7";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi_data7_po0 {
+				nvidia,pins = "ulpi_data7_po0";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			ulpi_data0_po1 {
+				nvidia,pins = "ulpi_data0_po1";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			ulpi_data1_po2 {
+				nvidia,pins = "ulpi_data1_po2";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			ulpi_data2_po3 {
+				nvidia,pins = "ulpi_data2_po3";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			ulpi_data3_po4 {
+				nvidia,pins = "ulpi_data3_po4";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			ulpi_data4_po5 {
+				nvidia,pins = "ulpi_data4_po5";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			ulpi_data5_po6 {
+				nvidia,pins = "ulpi_data5_po6";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi_data6_po7 {
+				nvidia,pins = "ulpi_data6_po7";
+				nvidia,function = "ulpi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap3_fs_pp0 {
+				nvidia,pins = "dap3_fs_pp0";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap3_din_pp1 {
+				nvidia,pins = "dap3_din_pp1";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap3_dout_pp2 {
+				nvidia,pins = "dap3_dout_pp2";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap3_sclk_pp3 {
+				nvidia,pins = "dap3_sclk_pp3";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap4_fs_pp4 {
+				nvidia,pins = "dap4_fs_pp4";
+				nvidia,function = "i2s3";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap4_din_pp5 {
+				nvidia,pins = "dap4_din_pp5";
+				nvidia,function = "i2s3";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap4_dout_pp6 {
+				nvidia,pins = "dap4_dout_pp6";
+				nvidia,function = "i2s3";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap4_sclk_pp7 {
+				nvidia,pins = "dap4_sclk_pp7";
+				nvidia,function = "i2s3";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_col0_pq0 {
+				nvidia,pins = "kb_col0_pq0";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_col1_pq1 {
+				nvidia,pins = "kb_col1_pq1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_col2_pq2 {
+				nvidia,pins = "kb_col2_pq2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_col3_pq3 {
+				nvidia,pins = "kb_col3_pq3";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_col4_pq4 {
+				nvidia,pins = "kb_col4_pq4";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_col5_pq5 {
+				nvidia,pins = "kb_col5_pq5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_col6_pq6 {
+				nvidia,pins = "kb_col6_pq6";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_col7_pq7 {
+				nvidia,pins = "kb_col7_pq7";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_row0_pr0 {
+				nvidia,pins = "kb_row0_pr0";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row1_pr1 {
+				nvidia,pins = "kb_row1_pr1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row2_pr2 {
+				nvidia,pins = "kb_row2_pr2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row3_pr3 {
+				nvidia,pins = "kb_row3_pr3";
+				nvidia,function = "sys";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row4_pr4 {
+				nvidia,pins = "kb_row4_pr4";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_row5_pr5 {
+				nvidia,pins = "kb_row5_pr5";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row6_pr6 {
+				nvidia,pins = "kb_row6_pr6";
+				nvidia,function = "displaya_alt";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_row7_pr7 {
+				nvidia,pins = "kb_row7_pr7";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_row8_ps0 {
+				nvidia,pins = "kb_row8_ps0";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_row9_ps1 {
+				nvidia,pins = "kb_row9_ps1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row10_ps2 {
+				nvidia,pins = "kb_row10_ps2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_row11_ps3 {
+				nvidia,pins = "kb_row11_ps3";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row12_ps4 {
+				nvidia,pins = "kb_row12_ps4";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row13_ps5 {
+				nvidia,pins = "kb_row13_ps5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_row14_ps6 {
+				nvidia,pins = "kb_row14_ps6";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row15_ps7 {
+				nvidia,pins = "kb_row15_ps7";
+				nvidia,function = "soc";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			kb_row16_pt0 {
+				nvidia,pins = "kb_row16_pt0";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row17_pt1 {
+				nvidia,pins = "kb_row17_pt1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gen2_i2c_scl_pt5 {
+				nvidia,pins = "gen2_i2c_scl_pt5";
+				nvidia,function = "i2c2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			gen2_i2c_sda_pt6 {
+				nvidia,pins = "gen2_i2c_sda_pt6";
+				nvidia,function = "i2c2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_cmd_pt7 {
+				nvidia,pins = "sdmmc4_cmd_pt7";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pu0 {
+				nvidia,pins = "pu0";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pu1 {
+				nvidia,pins = "pu1";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pu2 {
+				nvidia,pins = "pu2";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pu3 {
+				nvidia,pins = "pu3";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pu4 {
+				nvidia,pins = "pu4";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pu5 {
+				nvidia,pins = "pu5";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pu6 {
+				nvidia,pins = "pu6";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pv0 {
+				nvidia,pins = "pv0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pv1 {
+				nvidia,pins = "pv1";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3_cd_n_pv2 {
+				nvidia,pins = "sdmmc3_cd_n_pv2";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc1_wp_n_pv3 {
+				nvidia,pins = "sdmmc1_wp_n_pv3";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ddc_scl_pv4 {
+				nvidia,pins = "ddc_scl_pv4";
+				nvidia,function = "i2c4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+			};
+			ddc_sda_pv5 {
+				nvidia,pins = "ddc_sda_pv5";
+				nvidia,function = "i2c4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+			};
+			gpio_w2_aud_pw2 {
+				nvidia,pins = "gpio_w2_aud_pw2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gpio_w3_aud_pw3 {
+				nvidia,pins = "gpio_w3_aud_pw3";
+				nvidia,function = "spi6";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dap_mclk1_pw4 {
+				nvidia,pins = "dap_mclk1_pw4";
+				nvidia,function = "extperiph1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			clk2_out_pw5 {
+				nvidia,pins = "clk2_out_pw5";
+				nvidia,function = "extperiph2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			uart3_txd_pw6 {
+				nvidia,pins = "uart3_txd_pw6";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			uart3_rxd_pw7 {
+				nvidia,pins = "uart3_rxd_pw7";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dvfs_pwm_px0 {
+				nvidia,pins = "dvfs_pwm_px0";
+				nvidia,function = "cldvfs";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gpio_x1_aud_px1 {
+				nvidia,pins = "gpio_x1_aud_px1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dvfs_clk_px2 {
+				nvidia,pins = "dvfs_clk_px2";
+				nvidia,function = "cldvfs";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gpio_x3_aud_px3 {
+				nvidia,pins = "gpio_x3_aud_px3";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gpio_x4_aud_px4 {
+				nvidia,pins = "gpio_x4_aud_px4";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			gpio_x5_aud_px5 {
+				nvidia,pins = "gpio_x5_aud_px5";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gpio_x6_aud_px6 {
+				nvidia,pins = "gpio_x6_aud_px6";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			gpio_x7_aud_px7 {
+				nvidia,pins = "gpio_x7_aud_px7";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi_clk_py0 {
+				nvidia,pins = "ulpi_clk_py0";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi_dir_py1 {
+				nvidia,pins = "ulpi_dir_py1";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			ulpi_nxt_py2 {
+				nvidia,pins = "ulpi_nxt_py2";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			ulpi_stp_py3 {
+				nvidia,pins = "ulpi_stp_py3";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			sdmmc1_dat3_py4 {
+				nvidia,pins = "sdmmc1_dat3_py4";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc1_dat2_py5 {
+				nvidia,pins = "sdmmc1_dat2_py5";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc1_dat1_py6 {
+				nvidia,pins = "sdmmc1_dat1_py6";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc1_dat0_py7 {
+				nvidia,pins = "sdmmc1_dat0_py7";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc1_clk_pz0 {
+				nvidia,pins = "sdmmc1_clk_pz0";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc1_cmd_pz1 {
+				nvidia,pins = "sdmmc1_cmd_pz1";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pwr_i2c_scl_pz6 {
+				nvidia,pins = "pwr_i2c_scl_pz6";
+				nvidia,function = "i2cpwr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			pwr_i2c_sda_pz7 {
+				nvidia,pins = "pwr_i2c_sda_pz7";
+				nvidia,function = "i2cpwr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_dat0_paa0 {
+				nvidia,pins = "sdmmc4_dat0_paa0";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_dat1_paa1 {
+				nvidia,pins = "sdmmc4_dat1_paa1";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_dat2_paa2 {
+				nvidia,pins = "sdmmc4_dat2_paa2";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_dat3_paa3 {
+				nvidia,pins = "sdmmc4_dat3_paa3";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_dat4_paa4 {
+				nvidia,pins = "sdmmc4_dat4_paa4";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_dat5_paa5 {
+				nvidia,pins = "sdmmc4_dat5_paa5";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_dat6_paa6 {
+				nvidia,pins = "sdmmc4_dat6_paa6";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_dat7_paa7 {
+				nvidia,pins = "sdmmc4_dat7_paa7";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pbb0 {
+				nvidia,pins = "pbb0";
+				nvidia,function = "vimclk2_alt";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			cam_i2c_scl_pbb1 {
+				nvidia,pins = "cam_i2c_scl_pbb1";
+				nvidia,function = "i2c3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			cam_i2c_sda_pbb2 {
+				nvidia,pins = "cam_i2c_sda_pbb2";
+				nvidia,function = "i2c3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			pbb3 {
+				nvidia,pins = "pbb3";
+				nvidia,function = "vgp3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pbb4 {
+				nvidia,pins = "pbb4";
+				nvidia,function = "vgp4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pbb5 {
+				nvidia,pins = "pbb5";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pbb6 {
+				nvidia,pins = "pbb6";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pbb7 {
+				nvidia,pins = "pbb7";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			cam_mclk_pcc0 {
+				nvidia,pins = "cam_mclk_pcc0";
+				nvidia,function = "vi_alt3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pcc1 {
+				nvidia,pins = "pcc1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pcc2 {
+				nvidia,pins = "pcc2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4_clk_pcc4 {
+				nvidia,pins = "sdmmc4_clk_pcc4";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			clk2_req_pcc5 {
+				nvidia,pins = "clk2_req_pcc5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			clk3_out_pee0 {
+				nvidia,pins = "clk3_out_pee0";
+				nvidia,function = "extperiph3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			clk3_req_pee1 {
+				nvidia,pins = "clk3_req_pee1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			dap_mclk1_req_pee2 {
+				nvidia,pins = "dap_mclk1_req_pee2";
+				nvidia,function = "sata";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			hdmi_cec_pee3 {
+				nvidia,pins = "hdmi_cec_pee3";
+				nvidia,function = "cec";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3_clk_lb_out_pee4 {
+				nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3_clk_lb_in_pee5 {
+				nvidia,pins = "sdmmc3_clk_lb_in_pee5";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			dp_hpd_pff0 {
+				nvidia,pins = "dp_hpd_pff0";
+				nvidia,function = "dp";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			usb_vbus_en2_pff1 {
+				nvidia,pins = "usb_vbus_en2_pff1";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+			pff2 {
+				nvidia,pins = "pff2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+			core_pwr_req {
+				nvidia,pins = "core_pwr_req";
+				nvidia,function = "pwron";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			cpu_pwr_req {
+				nvidia,pins = "cpu_pwr_req";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pwr_int_n {
+				nvidia,pins = "pwr_int_n";
+				nvidia,function = "pmi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			reset_out_n {
+				nvidia,pins = "reset_out_n";
+				nvidia,function = "reset_out_n";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			owr {
+				nvidia,pins = "owr";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+			};
+			clk_32k_in {
+				nvidia,pins = "clk_32k_in";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			jtag_rtck {
+				nvidia,pins = "jtag_rtck";
+				nvidia,function = "rtck";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+		};
+	};
+
+	/* DB9 serial port */
+	serial@0,70006300 {
+		status = "okay";
+	};
+
+	/* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */
+	i2c@0,7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+
+		rt5639: audio-codec@1c {
+			compatible = "realtek,rt5639";
+			reg = <0x1c>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+			realtek,ldo1-en-gpios =
+				<&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+		};
+
+		temperature-sensor@4c {
+			compatible = "ti,tmp451";
+			reg = <0x4c>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
+		};
+
+		eeprom@56 {
+			compatible = "atmel,24c02";
+			reg = <0x56>;
+			pagesize = <8>;
+		};
+	};
+
+	/* Expansion GEN2_I2C_* */
+	i2c@0,7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/* Expansion CAM_I2C_* */
+	i2c@0,7000c500 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/* HDMI DDC */
+	hdmi_ddc: i2c@0,7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/* Expansion PWR_I2C_*, on-board components */
+	i2c@0,7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		pmic: pmic@40 {
+			compatible = "ams,as3722";
+			reg = <0x40>;
+			interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+
+			ams,system-power-controller;
+
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&as3722_default>;
+
+			as3722_default: pinmux {
+				gpio0 {
+					pins = "gpio0";
+					function = "gpio";
+					bias-pull-down;
+				};
+
+				gpio1_2_4_7 {
+					pins = "gpio1", "gpio2", "gpio4", "gpio7";
+					function = "gpio";
+					bias-pull-up;
+				};
+
+				gpio3_5_6 {
+					pins = "gpio3", "gpio5", "gpio6";
+					bias-high-impedance;
+				};
+			};
+
+			regulators {
+				vsup-sd2-supply = <&vdd_5v0_sys>;
+				vsup-sd3-supply = <&vdd_5v0_sys>;
+				vsup-sd4-supply = <&vdd_5v0_sys>;
+				vsup-sd5-supply = <&vdd_5v0_sys>;
+				vin-ldo0-supply = <&vdd_1v35_lp0>;
+				vin-ldo1-6-supply = <&vdd_3v3_run>;
+				vin-ldo2-5-7-supply = <&vddio_1v8>;
+				vin-ldo3-4-supply = <&vdd_3v3_sys>;
+				vin-ldo9-10-supply = <&vdd_5v0_sys>;
+				vin-ldo11-supply = <&vdd_3v3_run>;
+
+				sd0 {
+					regulator-name = "+VDD_CPU_AP";
+					regulator-min-microvolt = <700000>;
+					regulator-max-microvolt = <1400000>;
+					regulator-min-microamp = <3500000>;
+					regulator-max-microamp = <3500000>;
+					regulator-always-on;
+					regulator-boot-on;
+					ams,external-control = <2>;
+				};
+
+				sd1 {
+					regulator-name = "+VDD_CORE";
+					regulator-min-microvolt = <700000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-min-microamp = <2500000>;
+					regulator-max-microamp = <2500000>;
+					regulator-always-on;
+					regulator-boot-on;
+					ams,external-control = <1>;
+				};
+
+				vdd_1v35_lp0: sd2 {
+					regulator-name = "+1.35V_LP0(sd2)";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				sd3 {
+					regulator-name = "+1.35V_LP0(sd3)";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				vdd_1v05_run: sd4 {
+					regulator-name = "+1.05V_RUN";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+				};
+
+				vddio_1v8: sd5 {
+					regulator-name = "+1.8V_VDDIO";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				sd6 {
+					regulator-name = "+VDD_GPU_AP";
+					regulator-min-microvolt = <650000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-min-microamp = <3500000>;
+					regulator-max-microamp = <3500000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				ldo0 {
+					regulator-name = "+1.05V_RUN_AVDD";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+					regulator-boot-on;
+					regulator-always-on;
+					ams,external-control = <1>;
+				};
+
+				ldo1 {
+					regulator-name = "+1.8V_RUN_CAM";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				ldo2 {
+					regulator-name = "+1.2V_GEN_AVDD";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				ldo3 {
+					regulator-name = "+1.05V_LP0_VDD_RTC";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-boot-on;
+					regulator-always-on;
+					ams,enable-tracking;
+				};
+
+				ldo4 {
+					regulator-name = "+2.8V_RUN_CAM";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+
+				ldo5 {
+					regulator-name = "+1.2V_RUN_CAM_FRONT";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				vddio_sdmmc3: ldo6 {
+					regulator-name = "+VDDIO_SDMMC3";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				ldo7 {
+					regulator-name = "+1.05V_RUN_CAM_REAR";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+				};
+
+				ldo9 {
+					regulator-name = "+3.3V_RUN_TOUCH";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+
+				ldo10 {
+					regulator-name = "+2.8V_RUN_CAM_AF";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+
+				ldo11 {
+					regulator-name = "+1.8V_RUN_VPP_FUSE";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+			};
+		};
+	};
+
+	/* Expansion TS_SPI_* */
+	spi@0,7000d400 {
+		status = "okay";
+	};
+
+	/* Internal SPI */
+	spi@0,7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+		spi-flash@0 {
+			compatible = "winbond,w25q32dw";
+			reg = <0>;
+			spi-max-frequency = <20000000>;
+		};
+	};
+
+	pmc@0,7000e400 {
+		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <1>;
+		nvidia,cpu-pwr-good-time = <500>;
+		nvidia,cpu-pwr-off-time = <300>;
+		nvidia,core-pwr-good-time = <641 3845>;
+		nvidia,core-pwr-off-time = <61036>;
+		nvidia,core-power-req-active-high;
+		nvidia,sys-clock-req-active-high;
+	};
+
+	/* SD card */
+	sdhci@0,700b0400 {
+		status = "okay";
+		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+		power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+		wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
+		bus-width = <4>;
+		vqmmc-supply = <&vddio_sdmmc3>;
+	};
+
+	/* eMMC */
+	sdhci@0,700b0600 {
+		status = "okay";
+		bus-width = <8>;
+		non-removable;
+	};
+
+	ahub@0,70300000 {
+		i2s@0,70301100 {
+			status = "okay";
+		};
+	};
+
+	/* mini-PCIe USB */
+	usb@0,7d004000 {
+		status = "okay";
+	};
+
+	usb-phy@0,7d004000 {
+		status = "okay";
+	};
+
+	/* USB A connector */
+	usb@0,7d008000 {
+		status = "okay";
+	};
+
+	usb-phy@0,7d008000 {
+		status = "okay";
+		vbus-supply = <&vdd_usb3_vbus>;
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		clk32k_in: clock@0 {
+			compatible = "fixed-clock";
+			reg = <0>;
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		power {
+			label = "Power";
+			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+			debounce-interval = <10>;
+			gpio-key,wakeup;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_mux: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "+VDD_MUX";
+			regulator-min-microvolt = <12000000>;
+			regulator-max-microvolt = <12000000>;
+			regulator-always-on;
+			regulator-boot-on;
+		};
+
+		vdd_5v0_sys: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "+5V_SYS";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+			regulator-boot-on;
+			vin-supply = <&vdd_mux>;
+		};
+
+		vdd_3v3_sys: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "+3.3V_SYS";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			regulator-boot-on;
+			vin-supply = <&vdd_mux>;
+		};
+
+		vdd_3v3_run: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "+3.3V_RUN";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_3v3_sys>;
+		};
+
+		vdd_3v3_hdmi: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			vin-supply = <&vdd_3v3_run>;
+		};
+
+		vdd_usb1_vbus: regulator@7 {
+			compatible = "regulator-fixed";
+			reg = <7>;
+			regulator-name = "+USB0_VBUS_SW";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			gpio-open-drain;
+			vin-supply = <&vdd_5v0_sys>;
+		};
+
+		vdd_usb3_vbus: regulator@8 {
+			compatible = "regulator-fixed";
+			reg = <8>;
+			regulator-name = "+5V_USB_HS";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			gpio-open-drain;
+			vin-supply = <&vdd_5v0_sys>;
+		};
+
+		vdd_3v3_lp0: regulator@10 {
+			compatible = "regulator-fixed";
+			reg = <10>;
+			regulator-name = "+3.3V_LP0";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_3v3_sys>;
+		};
+
+		vdd_hdmi_pll: regulator@11 {
+			compatible = "regulator-fixed";
+			reg = <11>;
+			regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
+			regulator-min-microvolt = <1050000>;
+			regulator-max-microvolt = <1050000>;
+			gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+			vin-supply = <&vdd_1v05_run>;
+		};
+
+		vdd_5v0_hdmi: regulator@12 {
+			compatible = "regulator-fixed";
+			reg = <12>;
+			regulator-name = "+5V_HDMI_CON";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_5v0_sys>;
+		};
+	};
+
+	sound {
+		compatible = "nvidia,tegra-audio-rt5640-jetson-tk1",
+			     "nvidia,tegra-audio-rt5640";
+		nvidia,model = "NVIDIA Tegra Jetson TK1";
+
+		nvidia,audio-routing =
+			"Headphones", "HPOR",
+			"Headphones", "HPOL",
+			"Mic Jack", "MICBIAS1",
+			"IN2P", "Mic Jack";
+
+		nvidia,i2s-controller = <&tegra_i2s1>;
+		nvidia,audio-codec = <&rt5639>;
+
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>;
+
+		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA124_CLK_EXTERN1>;
+		clock-names = "pll_a", "pll_a_out0", "mclk";
+	};
+};
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi
new file mode 100644
index 0000000..7d0fafa
--- /dev/null
+++ b/arch/arm/dts/tegra124.dtsi
@@ -0,0 +1 @@
+#include <arm/tegra124.dtsi>
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index ea2e045..7214eca 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -70,6 +70,10 @@ config MACH_NVIDIA_BEAVER
 	select I2C
 	select I2C_TEGRA
 
+config MACH_NVIDIA_JETSON
+	bool "NVIDIA Jetson TK1"
+	select ARCH_TEGRA_124_SOC
+
 endmenu
 
 # ---------------------------------------------------------
diff --git a/images/Makefile.tegra b/images/Makefile.tegra
index 0d76062..4f876e4 100644
--- a/images/Makefile.tegra
+++ b/images/Makefile.tegra
@@ -82,3 +82,13 @@ pblx-$(CONFIG_MACH_NVIDIA_BEAVER) += start_nvidia_beaver
 BCT_start_nvidia_beaver.pblx.t30img = $(board)/nvidia-beaver/beaver-2gb-emmc.bct
 FILE_barebox-tegra30-nvidia-beaver-emmc.img = start_nvidia_beaver.pblx.t30img
 image-$(CONFIG_MACH_NVIDIA_BEAVER) += barebox-tegra30-nvidia-beaver-emmc.img
+
+# ----------------------- Tegra124 based boards --------------------------
+pblx-$(CONFIG_MACH_NVIDIA_JETSON) += start_nvidia_jetson
+FILE_barebox-tegra124-nvidia-jetson-tk1-usbloader.img = start_nvidia_jetson.pblx
+image-$(CONFIG_MACH_NVIDIA_JETSON) += barebox-tegra124-nvidia-jetson-tk1-usbloader.img
+
+pblx-$(CONFIG_MACH_NVIDIA_JETSON) += start_nvidia_jetson
+BCT_start_nvidia_jetson.pblx.t124img = $(board)/nvidia-jetson-tk1/jetson-tk1-2gb-emmc.bct
+FILE_barebox-tegra124-nvidia-jetson-tk1-emmc.img = start_nvidia_jetson.pblx.t124img
+image-$(CONFIG_MACH_NVIDIA_JETSON) += barebox-tegra124-nvidia-jetson-tk1-emmc.img
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH 30/30] tegra: refresh defconfig
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (28 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 29/30] tegra: add NVIDIA Jetson-TK1 board support Lucas Stach
@ 2014-06-03 20:35 ` Lucas Stach
  2014-06-04  5:22 ` [PATCH 00/30] Tegra K1 support Sascha Hauer
  30 siblings, 0 replies; 32+ messages in thread
From: Lucas Stach @ 2014-06-03 20:35 UTC (permalink / raw)
  To: barebox

Mainly for Jetson TK1 support, but -next moved
some stuff around. Also enable some filesystems.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/configs/tegra_v7_defconfig | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/arch/arm/configs/tegra_v7_defconfig b/arch/arm/configs/tegra_v7_defconfig
index 83d2851..22f5765 100644
--- a/arch/arm/configs/tegra_v7_defconfig
+++ b/arch/arm/configs/tegra_v7_defconfig
@@ -2,37 +2,41 @@ CONFIG_ARCH_TEGRA=y
 CONFIG_MACH_TORADEX_COLIBRI_T20=y
 CONFIG_MACH_TOSHIBA_AC100=y
 CONFIG_MACH_NVIDIA_BEAVER=y
+CONFIG_MACH_NVIDIA_JETSON=y
 CONFIG_AEABI=y
-CONFIG_CMD_ARM_MMUINFO=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
 CONFIG_MMU=y
 CONFIG_STACK_SIZE=0x10000
 CONFIG_MALLOC_SIZE=0x4000000
 CONFIG_KALLSYMS=y
-CONFIG_LONGHELP=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
 CONFIG_MENU=y
 CONFIG_BLSPEC=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_MEMINFO=y
+CONFIG_LONGHELP=y
 CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_ARM_MMUINFO=y
 CONFIG_CMD_BOOTM_INITRD=y
 CONFIG_CMD_BOOTM_OFTREE=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_RESET=y
-CONFIG_CMD_OFTREE=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_EDIT=y
 CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_GPIO=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DETECT=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_OFTREE=y
 CONFIG_DRIVER_SERIAL_NS16550=y
 CONFIG_MCI=y
 CONFIG_MCI_MMC_BOOT_PARTITIONS=y
 CONFIG_MCI_TEGRA=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_LFN=y
-- 
1.9.3


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^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH 00/30] Tegra K1 support
  2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
                   ` (29 preceding siblings ...)
  2014-06-03 20:35 ` [PATCH 30/30] tegra: refresh defconfig Lucas Stach
@ 2014-06-04  5:22 ` Sascha Hauer
  30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2014-06-04  5:22 UTC (permalink / raw)
  To: Lucas Stach; +Cc: barebox

On Tue, Jun 03, 2014 at 10:34:47PM +0200, Lucas Stach wrote:
> This is the next big round of Tegra updates, featuring
> Tegra K1 support. The series is based on -next as it has
> quite some dependencies on the earlier Tegra series.
> 
> The first 4 patches are some general useful additions,
> all others are adding K1 aka Tegra124 support. I've
> verified booting a Linux kernel to the rootfs panic.
> 
> The series is regression free on Tegra30.
> 
> Lucas Stach (30):
>   mci: implement non-removable property
>   tegra: lowlevel-dvc: use __always_inline macro
>   tegra: pmc: add Tegra30 compatible
>   tegra: pmc: add command to get into RCM
>   tegra: lowlevel: setup an early stack
>   tegra: add Tegra124 id to lowlevel functions
>   tegra: lowlevel: fix ODMdata fetch on Tegra124
>   tegra: recognize Tegra124 in maincomplex startup
>   tegra: recognize Tegra124 in common initcalls
>   tegra: add Tegra124 and AS3722 PMIC to lowlevel-dvc
>   tegra: disable IDDQ for PLL_X on Tegra124
>   tegra: power up additional partitions on Tegra124
>   tegra: fix MESLECT clock enable
>   tegra: change cpu internal reset layout for Tegra124
>   tegra: add Tegra124 PLL_X rate setup
>   tegra: apply cluster switch logic to all SoCs >=T30
>   tegra: hardcode entry address for main cluster
>   tegra: setup L2 cache on Tegra124
>   tegra: add architectural timer init
>   tegra: add Tegra124 Kconfig symbol
>   pinctrl: tegra30: introduce drvdata
>   pinctrl: tegra: add Tegra124 support
>   clk: tegra: allow variable sized muxes
>   clk: tegra: don't bug out on zero PLL postdiv
>   clk: tegra: add Tegra124 driver
>   mci: tegra: add Tegra124 compatible
>   tegra: pmc: add Tegra124 compatible
>   images: add Tegra124 image build rules
>   tegra: add NVIDIA Jetson-TK1 board support
>   tegra: refresh defconfig

Applied, thanks

Sascha

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^ permalink raw reply	[flat|nested] 32+ messages in thread

end of thread, other threads:[~2014-06-04  5:22 UTC | newest]

Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-06-03 20:34 [PATCH 00/30] Tegra K1 support Lucas Stach
2014-06-03 20:34 ` [PATCH 01/30] mci: implement non-removable property Lucas Stach
2014-06-03 20:34 ` [PATCH 02/30] tegra: lowlevel-dvc: use __always_inline macro Lucas Stach
2014-06-03 20:34 ` [PATCH 03/30] tegra: pmc: add Tegra30 compatible Lucas Stach
2014-06-03 20:34 ` [PATCH 04/30] tegra: pmc: add command to get into RCM Lucas Stach
2014-06-03 20:34 ` [PATCH 05/30] tegra: lowlevel: setup an early stack Lucas Stach
2014-06-03 20:34 ` [PATCH 06/30] tegra: add Tegra124 id to lowlevel functions Lucas Stach
2014-06-03 20:34 ` [PATCH 07/30] tegra: lowlevel: fix ODMdata fetch on Tegra124 Lucas Stach
2014-06-03 20:34 ` [PATCH 08/30] tegra: recognize Tegra124 in maincomplex startup Lucas Stach
2014-06-03 20:34 ` [PATCH 09/30] tegra: recognize Tegra124 in common initcalls Lucas Stach
2014-06-03 20:34 ` [PATCH 10/30] tegra: add Tegra124 and AS3722 PMIC to lowlevel-dvc Lucas Stach
2014-06-03 20:34 ` [PATCH 11/30] tegra: disable IDDQ for PLL_X on Tegra124 Lucas Stach
2014-06-03 20:34 ` [PATCH 12/30] tegra: power up additional partitions " Lucas Stach
2014-06-03 20:35 ` [PATCH 13/30] tegra: fix MESLECT clock enable Lucas Stach
2014-06-03 20:35 ` [PATCH 14/30] tegra: change cpu internal reset layout for Tegra124 Lucas Stach
2014-06-03 20:35 ` [PATCH 15/30] tegra: add Tegra124 PLL_X rate setup Lucas Stach
2014-06-03 20:35 ` [PATCH 16/30] tegra: apply cluster switch logic to all SoCs >=T30 Lucas Stach
2014-06-03 20:35 ` [PATCH 17/30] tegra: hardcode entry address for main cluster Lucas Stach
2014-06-03 20:35 ` [PATCH 18/30] tegra: setup L2 cache on Tegra124 Lucas Stach
2014-06-03 20:35 ` [PATCH 19/30] tegra: add architectural timer init Lucas Stach
2014-06-03 20:35 ` [PATCH 20/30] tegra: add Tegra124 Kconfig symbol Lucas Stach
2014-06-03 20:35 ` [PATCH 21/30] pinctrl: tegra30: introduce drvdata Lucas Stach
2014-06-03 20:35 ` [PATCH 22/30] pinctrl: tegra: add Tegra124 support Lucas Stach
2014-06-03 20:35 ` [PATCH 23/30] clk: tegra: allow variable sized muxes Lucas Stach
2014-06-03 20:35 ` [PATCH 24/30] clk: tegra: don't bug out on zero PLL postdiv Lucas Stach
2014-06-03 20:35 ` [PATCH 25/30] clk: tegra: add Tegra124 driver Lucas Stach
2014-06-03 20:35 ` [PATCH 26/30] mci: tegra: add Tegra124 compatible Lucas Stach
2014-06-03 20:35 ` [PATCH 27/30] tegra: pmc: " Lucas Stach
2014-06-03 20:35 ` [PATCH 28/30] images: add Tegra124 image build rules Lucas Stach
2014-06-03 20:35 ` [PATCH 29/30] tegra: add NVIDIA Jetson-TK1 board support Lucas Stach
2014-06-03 20:35 ` [PATCH 30/30] tegra: refresh defconfig Lucas Stach
2014-06-04  5:22 ` [PATCH 00/30] Tegra K1 support Sascha Hauer

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