[PATCH 6/7] MIPS: dts: qemu-malta.dts: use i2c-gpio for accessing CBUS FPGA I2C bus

[Antony Pavlov <antonynpavlov@gmail.com>]

Also we can enable m24c02 eeprom chip in dts-file e.g.

    &i2c0 {
            status = "okay";

            eeprom: m24c02@50 {
                    compatible = "spd";
                    reg = <0x50>;
            };
    };

Alas! qemu mips malta spd m24c02 eeprom chip emulation is not perfect:
the block read operation does not work properly.

Here is an example.

If we read eeprom content byte-by-byte then there is no problem:

    barebox:/ for i in 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f ;
    > do i2c_read -b 0 -a 0x50 -r $i -c 1 ; done
    0x01
    0x75
    0x54
    0x00
    0x82
    0x08
    0x00
    0x01

Compare this output with content of qemu.git/hw/mips/mips_malta.c:

    static eeprom24c0x_t spd_eeprom = {
        .contents = {
            ...
            /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,

But if we read several bytes at once the we have data corruption:

    barebox:/ i2c_read -b 0 -a 0x50 -r 0x8 -c 8
    0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/dts/qemu-malta.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/mips/dts/qemu-malta.dts b/arch/mips/dts/qemu-malta.dts
index 204007d..cc1c960 100644
--- a/arch/mips/dts/qemu-malta.dts
+++ b/arch/mips/dts/qemu-malta.dts
@@ -32,6 +32,18 @@
 		#gpio-cells = <2>;
 	};
 
+	i2c0: i2c0 {
+		compatible = "i2c-gpio";
+		gpios = <&gpio 0 0 /* sda */
+			&gpio 1 0 /* scl */
+			>;
+		i2c-gpio,sda-open-drain;
+		i2c-gpio,scl-open-drain;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	uart2: serial@bf000900 {
 		compatible = "ns16550a";
 		reg = <0xbf000900 0x40>;
@@ -58,3 +70,7 @@
 		};
 	};
 };
+
+&i2c0 {
+	status = "okay";
+};
-- 
1.9.2


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