* [PATCH] Phytec phyCORE AM335x updates
@ 2014-08-01 13:29 Sascha Hauer
2014-08-01 13:29 ` [PATCH 1/7] ARM: AM33xx: Add SDRAM size detection Sascha Hauer
` (6 more replies)
0 siblings, 7 replies; 8+ messages in thread
From: Sascha Hauer @ 2014-08-01 13:29 UTC (permalink / raw)
To: barebox
The Phytec phyCORE-AM335x comes in various different RAM settings.
This series adds support for the 128MB and 256MB configurations.
Also the NAND ECC mode setting is fixed, it is now compatible to
the Kernel.
With this the phyBOARD WEGA is working. Some of the devices are
different from the phyCORE on the RDK, so we'll need a different
device tree in the future, but for now it's enough to get something
started.
Sascha
----------------------------------------------------------------
Sascha Hauer (7):
ARM: AM33xx: Add SDRAM size detection
ARM: phyCORE-am335x: read back SDRAM controller settings
ARM: phyCORE-am335x: Add support for more SDRAM configurations
mtd: omap gpmc: fix ecc bytes/size
mtd: omap gpmc: reserve 14 byte/subpage for ECC in BCH8 romcode
mtd: omap gpmc: fix bch8 nand-ecc-opt property
ARM: AM3355x: Update defconfig
arch/arm/boards/phytec-phycore-am335x/lowlevel.c | 113 ++++++++++++++++++-----
arch/arm/configs/am335x_defconfig | 83 +++++++++--------
arch/arm/dts/am335x-phytec-phycore.dts | 5 -
arch/arm/mach-omap/Makefile | 1 +
arch/arm/mach-omap/am33xx_generic.c | 56 +++++++++++
arch/arm/mach-omap/am33xx_scrm.c | 51 ++++++++++
arch/arm/mach-omap/include/mach/am33xx-silicon.h | 2 +
drivers/bus/omap-gpmc.c | 3 -
drivers/mtd/nand/nand_omap_gpmc.c | 20 ++--
images/Makefile.am33xx | 14 ++-
10 files changed, 261 insertions(+), 87 deletions(-)
create mode 100644 arch/arm/mach-omap/am33xx_scrm.c
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/7] ARM: AM33xx: Add SDRAM size detection
2014-08-01 13:29 [PATCH] Phytec phyCORE AM335x updates Sascha Hauer
@ 2014-08-01 13:29 ` Sascha Hauer
2014-08-01 13:29 ` [PATCH 2/7] ARM: phyCORE-am335x: read back SDRAM controller settings Sascha Hauer
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Sascha Hauer @ 2014-08-01 13:29 UTC (permalink / raw)
To: barebox
This adds a function which reads back the SDRAM controller settings.
This is used in a AM33xx specific barebox entry function and a
SDRAM driver which registers a SDRAM memory bank.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/Makefile | 1 +
arch/arm/mach-omap/am33xx_generic.c | 56 ++++++++++++++++++++++++
arch/arm/mach-omap/am33xx_scrm.c | 51 +++++++++++++++++++++
arch/arm/mach-omap/include/mach/am33xx-silicon.h | 2 +
4 files changed, 110 insertions(+)
create mode 100644 arch/arm/mach-omap/am33xx_scrm.c
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index c9b6f4b..0ebfae7 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -24,6 +24,7 @@ pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o
+obj-$(CONFIG_ARCH_AM33XX) += am33xx_scrm.o
obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c
index 606e391..71c528c 100644
--- a/arch/arm/mach-omap/am33xx_generic.c
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -19,6 +19,7 @@
#include <init.h>
#include <io.h>
#include <net.h>
+#include <asm/barebox-arm.h>
#include <mach/am33xx-silicon.h>
#include <mach/am33xx-clock.h>
#include <mach/generic.h>
@@ -318,6 +319,61 @@ void am33xx_config_sdram(const struct am33xx_emif_regs *regs)
writel(regs->sdram_config, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
}
+/**
+ * am335x_sdram_size - read back SDRAM size from sdram_config register
+ *
+ * @return: The SDRAM size
+ */
+unsigned long am335x_sdram_size(void)
+{
+ int rows, cols, width, banks;
+ unsigned long size;
+ uint32_t sdram_config = readl(CM_EMIF_SDRAM_CONFIG);
+
+ rows = ((sdram_config >> 7) & 0x7) + 9;
+ cols = (sdram_config & 0x7) + 8;
+
+ switch ((sdram_config >> 14) & 0x3) {
+ case 0:
+ width = 4;
+ break;
+ case 1:
+ width = 2;
+ break;
+ default:
+ return 0;
+ }
+
+ switch ((sdram_config >> 4) & 0x7) {
+ case 0:
+ banks = 1;
+ break;
+ case 1:
+ banks = 2;
+ break;
+ case 2:
+ banks = 4;
+ break;
+ case 3:
+ banks = 8;
+ break;
+ default:
+ return 0;
+ }
+
+ size = (1 << rows) * (1 << cols) * banks * width;
+
+ debug("%s: sdram_config: 0x%08x cols: %2d rows: %2d width: %2d banks: %2d size: 0x%08lx\n",
+ __func__, sdram_config, cols, rows, width, banks, size);
+
+ return size;
+}
+
+void __noreturn am335x_barebox_entry(void *boarddata)
+{
+ barebox_arm_entry(0x80000000, am335x_sdram_size(), boarddata);
+}
+
void am33xx_config_io_ctrl(int ioctrl)
{
writel(ioctrl, AM33XX_DDR_CMD0_IOCTRL);
diff --git a/arch/arm/mach-omap/am33xx_scrm.c b/arch/arm/mach-omap/am33xx_scrm.c
new file mode 100644
index 0000000..67529f8
--- /dev/null
+++ b/arch/arm/mach-omap/am33xx_scrm.c
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2014 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <common.h>
+#include <io.h>
+#include <errno.h>
+#include <sizes.h>
+#include <init.h>
+#include <of.h>
+#include <asm/barebox-arm.h>
+#include <asm/memory.h>
+#include <mach/am33xx-silicon.h>
+
+static int am33xx_scrm_probe(struct device_d *dev)
+{
+ arm_add_mem_device("ram0", 0x80000000, am335x_sdram_size());
+
+ return 0;
+}
+
+static __maybe_unused struct of_device_id am33xx_scrm_dt_ids[] = {
+ {
+ .compatible = "ti,am3-scrm",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d am33xx_scrm_driver = {
+ .name = "am33xx-scrm",
+ .probe = am33xx_scrm_probe,
+ .of_compatible = DRV_OF_COMPAT(am33xx_scrm_dt_ids),
+};
+
+static int am33xx_scrm_init(void)
+{
+ return platform_driver_register(&am33xx_scrm_driver);
+}
+
+mem_initcall(am33xx_scrm_init);
diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
index 20b8e81..ceca10a 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
@@ -237,5 +237,7 @@ void am33xx_config_ddr_data(const struct am33xx_ddr_data *data, int macronr);
void am335x_sdram_init(int ioctrl, const struct am33xx_cmd_control *cmd_ctrl,
const struct am33xx_emif_regs *emif_regs,
const struct am33xx_ddr_data *ddr_data);
+unsigned long am335x_sdram_size(void);
+void am335x_barebox_entry(void *boarddata);
#endif
--
2.0.1
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/7] ARM: phyCORE-am335x: read back SDRAM controller settings
2014-08-01 13:29 [PATCH] Phytec phyCORE AM335x updates Sascha Hauer
2014-08-01 13:29 ` [PATCH 1/7] ARM: AM33xx: Add SDRAM size detection Sascha Hauer
@ 2014-08-01 13:29 ` Sascha Hauer
2014-08-01 13:29 ` [PATCH 3/7] ARM: phyCORE-am335x: Add support for more SDRAM configurations Sascha Hauer
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Sascha Hauer @ 2014-08-01 13:29 UTC (permalink / raw)
To: barebox
- use am335x_barebox_entry() to remove the need for hardcoded SDRAM
size
- remove hardcoded memory settings from device tree since there are
different memory sizes available for this board.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/phytec-phycore-am335x/lowlevel.c | 4 ++--
arch/arm/dts/am335x-phytec-phycore.dts | 5 -----
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
index 855b692..200cf57 100644
--- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
@@ -81,7 +81,7 @@ static noinline void pcm051_board_init(void)
fdt = __dtb_am335x_phytec_phycore_start - get_runtime_offset();
- barebox_arm_entry(0x80000000, SZ_512M, fdt);
+ am335x_barebox_entry(fdt);
}
ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram, bootinfo, r1, r2)
@@ -106,5 +106,5 @@ ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2)
fdt = __dtb_am335x_phytec_phycore_start - get_runtime_offset();
- barebox_arm_entry(0x80000000, SZ_512M, fdt);
+ am335x_barebox_entry(fdt);
}
diff --git a/arch/arm/dts/am335x-phytec-phycore.dts b/arch/arm/dts/am335x-phytec-phycore.dts
index 6196eb3..8966b32 100644
--- a/arch/arm/dts/am335x-phytec-phycore.dts
+++ b/arch/arm/dts/am335x-phytec-phycore.dts
@@ -22,11 +22,6 @@
};
};
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000>; /* 512 MB */
- };
-
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
--
2.0.1
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/7] ARM: phyCORE-am335x: Add support for more SDRAM configurations
2014-08-01 13:29 [PATCH] Phytec phyCORE AM335x updates Sascha Hauer
2014-08-01 13:29 ` [PATCH 1/7] ARM: AM33xx: Add SDRAM size detection Sascha Hauer
2014-08-01 13:29 ` [PATCH 2/7] ARM: phyCORE-am335x: read back SDRAM controller settings Sascha Hauer
@ 2014-08-01 13:29 ` Sascha Hauer
2014-08-01 13:29 ` [PATCH 4/7] mtd: omap gpmc: fix ecc bytes/size Sascha Hauer
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Sascha Hauer @ 2014-08-01 13:29 UTC (permalink / raw)
To: barebox
This adds support for 256MB and 128MB RAM configurations of the
phyCORE-AM335x. This is done as new images.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/phytec-phycore-am335x/lowlevel.c | 109 ++++++++++++++++++-----
images/Makefile.am33xx | 14 ++-
2 files changed, 100 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
index 200cf57..ff1f04e 100644
--- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
@@ -15,7 +15,7 @@
#include <mach/wdt.h>
#include <debug_ll.h>
-static const struct am33xx_cmd_control MT41J256M16HA15EIT_1x512MB_cmd = {
+static const struct am33xx_cmd_control pcm051_cmd = {
.slave_ratio0 = 0x40,
.dll_lock_diff0 = 0x0,
.invert_clkout0 = 0x1,
@@ -27,21 +27,74 @@ static const struct am33xx_cmd_control MT41J256M16HA15EIT_1x512MB_cmd = {
.invert_clkout2 = 0x1,
};
-static const struct am33xx_emif_regs MT41J256M16HA15EIT_1x512MB_regs = {
- .emif_read_latency = 0x6,
- .emif_tim1 = 0x0888A39B,
- .emif_tim2 = 0x26517FDA,
- .emif_tim3 = 0x501F84EF,
- .sdram_config = 0x61C04B32,
- .zq_config = 0x50074BE4,
- .sdram_ref_ctrl = 0x0000093B,
+struct pcm051_sdram_timings {
+ struct am33xx_emif_regs regs;
+ struct am33xx_ddr_data data;
};
-static const struct am33xx_ddr_data MT41J256M16HA15EIT_1x512MB_data = {
- .rd_slave_ratio0 = 0x3B,
- .wr_dqs_slave_ratio0 = 0x3B,
- .fifo_we_slave_ratio0 = 0x96,
- .wr_slave_ratio0 = 0x76,
+enum {
+ MT41J128M16125IT_1x256M16,
+ MT41J64M1615IT_1x128M16,
+ MT41J256M16HA15EIT_1x512M16,
+};
+
+struct pcm051_sdram_timings timings[] = {
+ /* 1x256M16 */
+ [MT41J128M16125IT_1x256M16] = {
+ .regs = {
+ .emif_read_latency = 0x6,
+ .emif_tim1 = 0x0888A39B,
+ .emif_tim2 = 0x26337FDA,
+ .emif_tim3 = 0x501F830F,
+ .sdram_config = 0x61C04AB2,
+ .zq_config = 0x50074BE4,
+ .sdram_ref_ctrl = 0x0000093B,
+ },
+ .data = {
+ .rd_slave_ratio0 = 0x3B,
+ .wr_dqs_slave_ratio0 = 0x3B,
+ .fifo_we_slave_ratio0 = 0x97,
+ .wr_slave_ratio0 = 0x76,
+ },
+ },
+
+ /* 1x128M16 */
+ [MT41J64M1615IT_1x128M16] = {
+ .regs = {
+ .emif_read_latency = 0x6,
+ .emif_tim1 = 0x0888A39B,
+ .emif_tim2 = 0x26247FDA,
+ .emif_tim3 = 0x501F821F,
+ .sdram_config = 0x61C04A32,
+ .zq_config = 0x50074BE4,
+ .sdram_ref_ctrl = 0x0000093B,
+ },
+ .data = {
+ .rd_slave_ratio0 = 0x3A,
+ .wr_dqs_slave_ratio0 = 0x36,
+ .fifo_we_slave_ratio0 = 0xA2,
+ .wr_slave_ratio0 = 0x74,
+ },
+ },
+
+ /* 1x512MB */
+ [MT41J256M16HA15EIT_1x512M16] = {
+ .regs = {
+ .emif_read_latency = 0x6,
+ .emif_tim1 = 0x0888A39B,
+ .emif_tim2 = 0x26517FDA,
+ .emif_tim3 = 0x501F84EF,
+ .sdram_config = 0x61C04B32,
+ .zq_config = 0x50074BE4,
+ .sdram_ref_ctrl = 0x0000093B,
+ },
+ .data = {
+ .rd_slave_ratio0 = 0x3B,
+ .wr_dqs_slave_ratio0 = 0x3B,
+ .fifo_we_slave_ratio0 = 0x96,
+ .wr_slave_ratio0 = 0x76,
+ },
+ },
};
extern char __dtb_am335x_phytec_phycore_start[];
@@ -55,9 +108,10 @@ extern char __dtb_am335x_phytec_phycore_start[];
*
* @return void
*/
-static noinline void pcm051_board_init(void)
+static noinline void pcm051_board_init(int sdram)
{
void *fdt;
+ struct pcm051_sdram_timings *timing = &timings[sdram];
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
@@ -70,9 +124,9 @@ static noinline void pcm051_board_init(void)
am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_303);
- am335x_sdram_init(0x18B, &MT41J256M16HA15EIT_1x512MB_cmd,
- &MT41J256M16HA15EIT_1x512MB_regs,
- &MT41J256M16HA15EIT_1x512MB_data);
+ am335x_sdram_init(0x18B, &pcm051_cmd,
+ &timing->regs,
+ &timing->data);
am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE);
am33xx_enable_uart0_pin_mux();
@@ -84,7 +138,7 @@ static noinline void pcm051_board_init(void)
am335x_barebox_entry(fdt);
}
-ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram, bootinfo, r1, r2)
+static noinline void pcm051_board_entry(unsigned long bootinfo, int sdram)
{
am33xx_save_bootinfo((void *)bootinfo);
@@ -97,7 +151,22 @@ ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram, bootinfo, r1, r2)
relocate_to_current_adr();
setup_c();
- pcm051_board_init();
+ pcm051_board_init(sdram);
+}
+
+ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_1x256m16, bootinfo, r1, r2)
+{
+ pcm051_board_entry(bootinfo, MT41J128M16125IT_1x256M16);
+}
+
+ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_1x128m16, bootinfo, r1, r2)
+{
+ pcm051_board_entry(bootinfo, MT41J64M1615IT_1x128M16);
+}
+
+ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_1x512m16, bootinfo, r1, r2)
+{
+ pcm051_board_entry(bootinfo, MT41J256M16HA15EIT_1x512M16);
}
ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2)
diff --git a/images/Makefile.am33xx b/images/Makefile.am33xx
index dacc2d1..fa1f848 100644
--- a/images/Makefile.am33xx
+++ b/images/Makefile.am33xx
@@ -11,9 +11,17 @@ pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sdram
FILE_barebox-am33xx-phytec-phycore.img = start_am33xx_phytec_phycore_sdram.pblx
am33xx-barebox-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore.img
-pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram
-FILE_barebox-am33xx-phytec-phycore-mlo.img = start_am33xx_phytec_phycore_sram.pblx.mlo
-am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo.img
+pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_1x256m16
+FILE_barebox-am33xx-phytec-phycore-mlo-1x256m16.img = start_am33xx_phytec_phycore_sram_1x256m16.pblx.mlo
+am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-1x256m16.img
+
+pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_1x128m16
+FILE_barebox-am33xx-phytec-phycore-mlo-1x128m16.img = start_am33xx_phytec_phycore_sram_1x128m16.pblx.mlo
+am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-1x128m16.img
+
+pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_1x512m16
+FILE_barebox-am33xx-phytec-phycore-mlo-1x512m16.img = start_am33xx_phytec_phycore_sram_1x512m16.pblx.mlo
+am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-1x512m16.img
pblx-$(CONFIG_MACH_BEAGLEBONE) += start_am33xx_beaglebone_sdram
FILE_barebox-am33xx-beaglebone.img = start_am33xx_beaglebone_sdram.pblx
--
2.0.1
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 4/7] mtd: omap gpmc: fix ecc bytes/size
2014-08-01 13:29 [PATCH] Phytec phyCORE AM335x updates Sascha Hauer
` (2 preceding siblings ...)
2014-08-01 13:29 ` [PATCH 3/7] ARM: phyCORE-am335x: Add support for more SDRAM configurations Sascha Hauer
@ 2014-08-01 13:29 ` Sascha Hauer
2014-08-01 13:29 ` [PATCH 5/7] mtd: omap gpmc: reserve 14 byte/subpage for ECC in BCH8 romcode Sascha Hauer
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Sascha Hauer @ 2014-08-01 13:29 UTC (permalink / raw)
To: barebox
The ecc bytes / size are per subpage, not per page.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/mtd/nand/nand_omap_gpmc.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c
index 59712b8..5ff1647 100644
--- a/drivers/mtd/nand/nand_omap_gpmc.c
+++ b/drivers/mtd/nand/nand_omap_gpmc.c
@@ -804,8 +804,8 @@ static int omap_gpmc_eccmode(struct gpmc_nand_info *oinfo,
offset - omap_oobinfo.eccbytes;
break;
case OMAP_ECC_BCH4_CODE_HW:
- oinfo->nand.ecc.bytes = 4 * 7;
- oinfo->nand.ecc.size = 4 * 512;
+ oinfo->nand.ecc.bytes = 7;
+ oinfo->nand.ecc.size = 512;
oinfo->nand.ecc.strength = BCH4_MAX_ERROR;
omap_oobinfo.oobfree->offset = offset;
omap_oobinfo.oobfree->length = minfo->oobsize -
@@ -815,8 +815,8 @@ static int omap_gpmc_eccmode(struct gpmc_nand_info *oinfo,
omap_oobinfo.eccpos[i] = i + offset;
break;
case OMAP_ECC_BCH8_CODE_HW:
- oinfo->nand.ecc.bytes = 4 * 13;
- oinfo->nand.ecc.size = 4 * 512;
+ oinfo->nand.ecc.bytes = 13;
+ oinfo->nand.ecc.size = 512;
oinfo->nand.ecc.strength = BCH8_MAX_ERROR;
omap_oobinfo.oobfree->offset = offset;
omap_oobinfo.oobfree->length = minfo->oobsize -
@@ -826,8 +826,8 @@ static int omap_gpmc_eccmode(struct gpmc_nand_info *oinfo,
omap_oobinfo.eccpos[i] = i + offset;
break;
case OMAP_ECC_BCH8_CODE_HW_ROMCODE:
- oinfo->nand.ecc.bytes = 4 * 13;
- oinfo->nand.ecc.size = 4 * 512;
+ oinfo->nand.ecc.bytes = 13;
+ oinfo->nand.ecc.size = 512;
oinfo->nand.ecc.strength = BCH8_MAX_ERROR;
nand->ecc.read_page = omap_gpmc_read_page_bch_rom_mode;
omap_oobinfo.oobfree->length = 0;
--
2.0.1
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 5/7] mtd: omap gpmc: reserve 14 byte/subpage for ECC in BCH8 romcode
2014-08-01 13:29 [PATCH] Phytec phyCORE AM335x updates Sascha Hauer
` (3 preceding siblings ...)
2014-08-01 13:29 ` [PATCH 4/7] mtd: omap gpmc: fix ecc bytes/size Sascha Hauer
@ 2014-08-01 13:29 ` Sascha Hauer
2014-08-01 13:29 ` [PATCH 6/7] mtd: omap gpmc: fix bch8 nand-ecc-opt property Sascha Hauer
2014-08-01 13:29 ` [PATCH 7/7] ARM: AM3355x: Update defconfig Sascha Hauer
6 siblings, 0 replies; 8+ messages in thread
From: Sascha Hauer @ 2014-08-01 13:29 UTC (permalink / raw)
To: barebox
As done in the Kernel. The Kernel has a comment this is done to
be compatible with the ROM code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/mtd/nand/nand_omap_gpmc.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c
index 5ff1647..b1d266f 100644
--- a/drivers/mtd/nand/nand_omap_gpmc.c
+++ b/drivers/mtd/nand/nand_omap_gpmc.c
@@ -826,19 +826,13 @@ static int omap_gpmc_eccmode(struct gpmc_nand_info *oinfo,
omap_oobinfo.eccpos[i] = i + offset;
break;
case OMAP_ECC_BCH8_CODE_HW_ROMCODE:
- oinfo->nand.ecc.bytes = 13;
+ oinfo->nand.ecc.bytes = 13 + 1;
oinfo->nand.ecc.size = 512;
oinfo->nand.ecc.strength = BCH8_MAX_ERROR;
nand->ecc.read_page = omap_gpmc_read_page_bch_rom_mode;
omap_oobinfo.oobfree->length = 0;
j = 0;
- for (i = 2; i < 15; i++)
- omap_oobinfo.eccpos[j++] = i;
- for (i = 16; i < 29; i++)
- omap_oobinfo.eccpos[j++] = i;
- for (i = 30; i < 43; i++)
- omap_oobinfo.eccpos[j++] = i;
- for (i = 44; i < 57; i++)
+ for (i = 2; i < 58; i++)
omap_oobinfo.eccpos[j++] = i;
break;
case OMAP_ECC_SOFT:
--
2.0.1
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 6/7] mtd: omap gpmc: fix bch8 nand-ecc-opt property
2014-08-01 13:29 [PATCH] Phytec phyCORE AM335x updates Sascha Hauer
` (4 preceding siblings ...)
2014-08-01 13:29 ` [PATCH 5/7] mtd: omap gpmc: reserve 14 byte/subpage for ECC in BCH8 romcode Sascha Hauer
@ 2014-08-01 13:29 ` Sascha Hauer
2014-08-01 13:29 ` [PATCH 7/7] ARM: AM3355x: Update defconfig Sascha Hauer
6 siblings, 0 replies; 8+ messages in thread
From: Sascha Hauer @ 2014-08-01 13:29 UTC (permalink / raw)
To: barebox
We interpret the ECC option "bch8" as OMAP_ECC_BCH8_CODE_HW, but the
Kernel uses OMAP_ECC_BCH8_CODE_HW_ROMCODE in this case instead. To make
the interpretation of the ti,nand-ecc-opt property compatible to the
Kernel we have to use OMAP_ECC_BCH8_CODE_HW_ROMCODE for "bch8"
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/bus/omap-gpmc.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/bus/omap-gpmc.c b/drivers/bus/omap-gpmc.c
index ad21af2..d7b02cf 100644
--- a/drivers/bus/omap-gpmc.c
+++ b/drivers/bus/omap-gpmc.c
@@ -382,9 +382,6 @@ static struct dt_eccmode modes[] = {
.mode = OMAP_ECC_BCH4_CODE_HW,
}, {
.name = "bch8",
- .mode = OMAP_ECC_BCH8_CODE_HW,
- }, {
- .name = "bch8-romcode",
.mode = OMAP_ECC_BCH8_CODE_HW_ROMCODE,
},
};
--
2.0.1
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 7/7] ARM: AM3355x: Update defconfig
2014-08-01 13:29 [PATCH] Phytec phyCORE AM335x updates Sascha Hauer
` (5 preceding siblings ...)
2014-08-01 13:29 ` [PATCH 6/7] mtd: omap gpmc: fix bch8 nand-ecc-opt property Sascha Hauer
@ 2014-08-01 13:29 ` Sascha Hauer
6 siblings, 0 replies; 8+ messages in thread
From: Sascha Hauer @ 2014-08-01 13:29 UTC (permalink / raw)
To: barebox
Most diffstat comes from refreshing the config. The only real change
is that the NAND xload update handler is enabled now.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/configs/am335x_defconfig | 83 ++++++++++++++++++++-------------------
1 file changed, 42 insertions(+), 41 deletions(-)
diff --git a/arch/arm/configs/am335x_defconfig b/arch/arm/configs/am335x_defconfig
index 0c92c96..d3feb10 100644
--- a/arch/arm/configs/am335x_defconfig
+++ b/arch/arm/configs/am335x_defconfig
@@ -1,11 +1,11 @@
CONFIG_ARCH_OMAP=y
CONFIG_BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO=y
+CONFIG_BAREBOX_UPDATE_AM33XX_NAND_XLOADSLOTS=y
CONFIG_OMAP_MULTI_BOARDS=y
CONFIG_MACH_BEAGLEBONE=y
CONFIG_MACH_PCM051=y
CONFIG_THUMB2_BAREBOX=y
CONFIG_ARM_BOARD_APPEND_ATAG=y
-CONFIG_CMD_ARM_MMUINFO=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
@@ -15,7 +15,6 @@ CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_RELOCATABLE=y
CONFIG_PROMPT="barebox> "
-CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
@@ -25,61 +24,63 @@ CONFIG_BLSPEC=y
CONFIG_CONSOLE_ACTIVATE_NONE=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEBUG_INFO=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_MSLEEP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_READF=y
-CONFIG_CMD_LET=y
-CONFIG_CMD_MENU=y
-CONFIG_CMD_MENUTREE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_LN=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_FILETYPE=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_MEMINFO=y
+CONFIG_LONGHELP=y
CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MM=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_CRC_CMP=y
-CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_UBIFORMAT=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_ARM_MMUINFO=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_RESET=y
+CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GO=y
-CONFIG_CMD_OFTREE=y
-CONFIG_CMD_OF_PROPERTY=y
-CONFIG_CMD_OF_NODE=y
-CONFIG_CMD_BAREBOX_UPDATE=y
-CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_UIMAGE=y
CONFIG_CMD_PARTITION=y
+CONFIG_CMD_UBIFORMAT=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_PRINTENV=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_GPIO=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_MD5SUM=y
CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_READF=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TFTP=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENUTREE=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_LED=y
+CONFIG_CMD_SPI=y
CONFIG_CMD_LED_TRIGGER=y
-CONFIG_CMD_MIITOOL=y
-CONFIG_CMD_DETECT=y
+CONFIG_CMD_BAREBOX_UPDATE=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
CONFIG_NET=y
-CONFIG_CMD_DHCP=y
CONFIG_NET_NFS=y
-CONFIG_CMD_PING=y
CONFIG_NET_NETCONSOLE=y
CONFIG_NET_RESOLV=y
CONFIG_OFDEVICE=y
--
2.0.1
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2014-08-01 13:29 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-08-01 13:29 [PATCH] Phytec phyCORE AM335x updates Sascha Hauer
2014-08-01 13:29 ` [PATCH 1/7] ARM: AM33xx: Add SDRAM size detection Sascha Hauer
2014-08-01 13:29 ` [PATCH 2/7] ARM: phyCORE-am335x: read back SDRAM controller settings Sascha Hauer
2014-08-01 13:29 ` [PATCH 3/7] ARM: phyCORE-am335x: Add support for more SDRAM configurations Sascha Hauer
2014-08-01 13:29 ` [PATCH 4/7] mtd: omap gpmc: fix ecc bytes/size Sascha Hauer
2014-08-01 13:29 ` [PATCH 5/7] mtd: omap gpmc: reserve 14 byte/subpage for ECC in BCH8 romcode Sascha Hauer
2014-08-01 13:29 ` [PATCH 6/7] mtd: omap gpmc: fix bch8 nand-ecc-opt property Sascha Hauer
2014-08-01 13:29 ` [PATCH 7/7] ARM: AM3355x: Update defconfig Sascha Hauer
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