From: "Raphaël Poggi" <poggi.raph@gmail.com>
To: barebox@lists.infradead.org
Cc: "Raphaël Poggi" <poggi.raph@gmail.com>
Subject: [PATCH v3 1/3] mtd: nand: add has_pmecc member
Date: Mon, 1 Sep 2014 14:27:33 +0200 [thread overview]
Message-ID: <1409574455-15746-2-git-send-email-poggi.raph@gmail.com> (raw)
In-Reply-To: <1409574455-15746-1-git-send-email-poggi.raph@gmail.com>
By adding this structure member, we can retrieve the pmecc config, through the device tree.
Signed-off-by: Raphaël Poggi <poggi.raph@gmail.com>
---
arch/arm/boards/at91sam9n12ek/init.c | 1 +
arch/arm/boards/at91sam9x5ek/init.c | 1 +
arch/arm/boards/sama5d3_xplained/init.c | 1 +
arch/arm/boards/sama5d3xek/init.c | 1 +
arch/arm/mach-at91/include/mach/board.h | 1 +
drivers/mtd/nand/atmel_nand.c | 2 +-
6 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boards/at91sam9n12ek/init.c b/arch/arm/boards/at91sam9n12ek/init.c
index a206d6b..818a598 100644
--- a/arch/arm/boards/at91sam9n12ek/init.c
+++ b/arch/arm/boards/at91sam9n12ek/init.c
@@ -47,6 +47,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin = -EINVAL,
.rdy_pin = AT91_PIN_PD5,
.enable_pin = AT91_PIN_PD4,
+ .has_pmecc = 1,
.ecc_mode = NAND_ECC_HW,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 2,
diff --git a/arch/arm/boards/at91sam9x5ek/init.c b/arch/arm/boards/at91sam9x5ek/init.c
index 62e5652..183ddc7 100644
--- a/arch/arm/boards/at91sam9x5ek/init.c
+++ b/arch/arm/boards/at91sam9x5ek/init.c
@@ -57,6 +57,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin = -EINVAL,
.rdy_pin = AT91_PIN_PD5,
.enable_pin = AT91_PIN_PD4,
+ .has_pmecc = 1,
.ecc_mode = NAND_ECC_HW,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 2,
diff --git a/arch/arm/boards/sama5d3_xplained/init.c b/arch/arm/boards/sama5d3_xplained/init.c
index ae18863..b182802 100644
--- a/arch/arm/boards/sama5d3_xplained/init.c
+++ b/arch/arm/boards/sama5d3_xplained/init.c
@@ -48,6 +48,7 @@ static struct atmel_nand_data nand_pdata = {
.rdy_pin = -EINVAL,
.enable_pin = -EINVAL,
.ecc_mode = NAND_ECC_HW,
+ .has_pmecc = 1,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 4,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
diff --git a/arch/arm/boards/sama5d3xek/init.c b/arch/arm/boards/sama5d3xek/init.c
index 743197f..49d2b37 100644
--- a/arch/arm/boards/sama5d3xek/init.c
+++ b/arch/arm/boards/sama5d3xek/init.c
@@ -63,6 +63,7 @@ static struct atmel_nand_data nand_pdata = {
.rdy_pin = -EINVAL,
.enable_pin = -EINVAL,
.ecc_mode = NAND_ECC_HW,
+ .has_pmecc = 1,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 4,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index aa0fdae..e2307ed 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -63,6 +63,7 @@ struct atmel_nand_data {
u8 bus_width_16; /* buswidth is 16 bit */
u8 ecc_mode; /* NAND_ECC_* */
u8 on_flash_bbt; /* Use flash based bbt */
+ u8 has_pmecc; /* Use PMECC */
u8 bus_on_d0;
u8 pmecc_corr_cap;
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 337e225..220ec5c 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1219,7 +1219,7 @@ static int __init atmel_nand_probe(struct device_d *dev)
if (IS_ENABLED(CONFIG_NAND_ECC_HW) &&
nand_chip->ecc.mode == NAND_ECC_HW) {
- if (IS_ENABLED(CONFIG_NAND_ATMEL_PMECC))
+ if (IS_ENABLED(CONFIG_NAND_ATMEL_PMECC) && pdata->has_pmecc)
res = atmel_pmecc_nand_init_params(dev, host);
else
res = atmel_hw_nand_init_params(dev, host);
--
1.7.9.5
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next prev parent reply other threads:[~2014-09-01 12:27 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-01 12:27 [PATCH v3 0/3] Add device tree support of Atmel NAND driver Raphaël Poggi
2014-09-01 12:27 ` Raphaël Poggi [this message]
2014-09-01 12:27 ` [PATCH v3 2/3] mtd: atmel_nand: retrieve ecc_mode from pdata Raphaël Poggi
2014-09-01 12:27 ` [PATCH v3 3/3] mtd: atmel_nand: add support for device tree Raphaël Poggi
2014-09-02 7:17 ` [PATCH v3 0/3] Add device tree support of Atmel NAND driver Sascha Hauer
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