* [PATCH 2/4] ARM:phyFLEX-iMX6: Remove eth phy reset form board
2014-09-15 12:56 [PATCH 1/4] phy/micrel: disable Asym_Pause support Christian Hemp
@ 2014-09-15 12:56 ` Christian Hemp
2014-09-15 12:56 ` [PATCH 3/4] ARM:phyFLEX-iMX6: Remove mmd_write_reg from board Christian Hemp
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Christian Hemp @ 2014-09-15 12:56 UTC (permalink / raw)
To: barebox
Remove ethernet phy reset from board file. The reset is now made by the fec
driver since commit:
|commit 5c1846b625247f4b99eb429dcd5b0854699a4298
|Author: Rostislav Lisovy <lisovy@gmail.com>
|Date: Wed Nov 20 22:22:25 2013 +0100
|
| ARM: i.mx53: Parse Reset GPIO pin in FEC driver from Devicetree
|
| Signed-off-by: Rostislav Lisovy <lisovy@gmail.com>
| Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
---
arch/arm/boards/phytec-phyflex-imx6/board.c | 13 -------------
1 files changed, 0 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c
index fe3d1b2..131861d 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/board.c
+++ b/arch/arm/boards/phytec-phyflex-imx6/board.c
@@ -32,8 +32,6 @@
#include <mach/iomux-mx6.h>
#include <mach/imx6.h>
-#define ETH_PHY_RST IMX_GPIO_NR(3, 23)
-
#define GPIO_2_11_PD_CTL MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_PUE | MX6_PAD_CTL_PKE | \
MX6_PAD_CTL_SPEED_MED | MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS
@@ -65,16 +63,6 @@ static void phyflex_err006282_workaround(void)
gpio_direction_input(MX6_PHYFLEX_ERR006282);
}
-static int eth_phy_reset(void)
-{
- gpio_request(ETH_PHY_RST, "phy reset");
- gpio_direction_output(ETH_PHY_RST, 0);
- mdelay(1);
- gpio_set_value(ETH_PHY_RST, 1);
-
- return 0;
-}
-
static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
{
phy_write(dev, 0x0d, device);
@@ -99,7 +87,6 @@ static int phytec_pfla02_init(void)
phyflex_err006282_workaround();
- eth_phy_reset();
phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
ksz9031rn_phy_fixup);
--
1.7.0.4
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^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 3/4] ARM:phyFLEX-iMX6: Remove mmd_write_reg from board
2014-09-15 12:56 [PATCH 1/4] phy/micrel: disable Asym_Pause support Christian Hemp
2014-09-15 12:56 ` [PATCH 2/4] ARM:phyFLEX-iMX6: Remove eth phy reset form board Christian Hemp
@ 2014-09-15 12:56 ` Christian Hemp
2014-09-15 12:56 ` [PATCH 4/4] ARM:phyFLEX-iMX6 New Ram Timings for Q/DL Christian Hemp
2014-09-17 6:55 ` [PATCH 1/4] phy/micrel: disable Asym_Pause support Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Christian Hemp @ 2014-09-15 12:56 UTC (permalink / raw)
To: barebox
Remove mmd_write_reg function from board file and use phy_write_mmd_indirect.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
---
arch/arm/boards/phytec-phyflex-imx6/board.c | 10 +---------
1 files changed, 1 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c
index 131861d..09a5c79 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/board.c
+++ b/arch/arm/boards/phytec-phyflex-imx6/board.c
@@ -63,17 +63,9 @@ static void phyflex_err006282_workaround(void)
gpio_direction_input(MX6_PHYFLEX_ERR006282);
}
-static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
-{
- phy_write(dev, 0x0d, device);
- phy_write(dev, 0x0e, reg);
- phy_write(dev, 0x0d, (1 << 14) | device);
- phy_write(dev, 0x0e, val);
-}
-
static int ksz9031rn_phy_fixup(struct phy_device *dev)
{
- mmd_write_reg(dev, 2, 8, 0x039F);
+ phy_write_mmd_indirect(dev, 8, 2, 0x039F);
return 0;
}
--
1.7.0.4
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 4/4] ARM:phyFLEX-iMX6 New Ram Timings for Q/DL
2014-09-15 12:56 [PATCH 1/4] phy/micrel: disable Asym_Pause support Christian Hemp
2014-09-15 12:56 ` [PATCH 2/4] ARM:phyFLEX-iMX6: Remove eth phy reset form board Christian Hemp
2014-09-15 12:56 ` [PATCH 3/4] ARM:phyFLEX-iMX6: Remove mmd_write_reg from board Christian Hemp
@ 2014-09-15 12:56 ` Christian Hemp
2014-09-17 6:55 ` [PATCH 1/4] phy/micrel: disable Asym_Pause support Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Christian Hemp @ 2014-09-15 12:56 UTC (permalink / raw)
To: barebox; +Cc: Maik Otto
From: Maik Otto <m.otto@phytec.de>
Signed-off-by: Maik Otto <m.otto@phytec.de>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
---
| 2 +
| 2 +
| 7 +-
| 138 ++++++++++----------
| 2 +
| 125 +++++++++---------
| 2 +
7 files changed, 148 insertions(+), 130 deletions(-)
--git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg
index d73207c..f6061f2 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg
+++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg
@@ -1,3 +1,5 @@
+#define SETUP_MDCFG0 \
+ wm 32 0x021b000c 0x3c409b85
#define SETUP_1GIB_2GIB_4GIB \
wm 32 0x021b0040 0x00000017; \
--git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg
index 2291b71..2bfa836 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg
+++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg
@@ -1,3 +1,5 @@
+#define SETUP_MDCFG0 \
+ wm 32 0x021b000c 0x565c9b85
#define SETUP_1GIB_2GIB_4GIB \
wm 32 0x021b0040 0x00000027; \
--git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg
index c6dc775..4121018 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg
+++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg
@@ -1,6 +1,9 @@
+#define SETUP_MDCFG0 \
+ wm 32 0x021b000c 0x8c929b85
#define SETUP_1GIB_2GIB_4GIB \
- wm 32 0x021b0040 0x00000047; \
- wm 32 0x021b0000 0xC41A0000
+ wm 32 0x021b0040 0x00000047; \
+ wm 32 0x021b0000 0xC41A0000
#include "flash-header-phytec-pfla02.h"
+
--git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h
index 138ae36..900fbaa 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h
+++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h
@@ -2,46 +2,60 @@ soc imx6
loadaddr 0x20000000
dcdofs 0x400
-wm 32 0x020e05a8 0x00000030
-wm 32 0x020e05b0 0x00000030
-wm 32 0x020e0524 0x00000030
-wm 32 0x020e051c 0x00000030
-wm 32 0x020e0518 0x00000030
-wm 32 0x020e050c 0x00000030
-wm 32 0x020e05b8 0x00000030
-wm 32 0x020e05c0 0x00000030
-wm 32 0x020e05ac 0x00020030
-wm 32 0x020e05b4 0x00020030
-wm 32 0x020e0528 0x00020030
-wm 32 0x020e0520 0x00020030
-wm 32 0x020e0514 0x00020030
-wm 32 0x020e0510 0x00020030
-wm 32 0x020e05bc 0x00020030
-wm 32 0x020e05c4 0x00020030
-wm 32 0x020e056c 0x00020030
-wm 32 0x020e0578 0x00020030
-wm 32 0x020e0588 0x00020030
-wm 32 0x020e0594 0x00020030
-wm 32 0x020e057c 0x00020030
+wm 32 0x020e0798 0x000C0000
+wm 32 0x020e0758 0x00000000
+wm 32 0x020e0588 0x00000030
+wm 32 0x020e0594 0x00000030
+wm 32 0x020e056c 0x00000030
+wm 32 0x020e0578 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e057c 0x00000030
+wm 32 0x020e058c 0x00000000
+wm 32 0x020e059c 0x00000030
+wm 32 0x020e05a0 0x00000030
wm 32 0x020e0590 0x00003000
wm 32 0x020e0598 0x00003000
-wm 32 0x020e058c 0x00000000
-wm 32 0x020e059c 0x00003030
-wm 32 0x020e05a0 0x00003030
-wm 32 0x020e0784 0x00000030
-wm 32 0x020e0788 0x00000030
-wm 32 0x020e0794 0x00000030
-wm 32 0x020e079c 0x00000030
-wm 32 0x020e07a0 0x00000030
-wm 32 0x020e07a4 0x00000030
-wm 32 0x020e07a8 0x00000030
-wm 32 0x020e0748 0x00000030
-wm 32 0x020e074c 0x00000030
+wm 32 0x020e078c 0x00000030
wm 32 0x020e0750 0x00020000
-wm 32 0x020e0758 0x00000000
+wm 32 0x020e05a8 0x00000028
+wm 32 0x020e05b0 0x00000028
+wm 32 0x020e0524 0x00000028
+wm 32 0x020e051c 0x00000028
+wm 32 0x020e0518 0x00000028
+wm 32 0x020e050c 0x00000028
+wm 32 0x020e05b8 0x00000028
+wm 32 0x020e05c0 0x00000028
wm 32 0x020e0774 0x00020000
-wm 32 0x020e078c 0x00000030
-wm 32 0x020e0798 0x000c0000
+wm 32 0x020e0784 0x00000028
+wm 32 0x020e0788 0x00000028
+wm 32 0x020e0794 0x00000028
+wm 32 0x020e079c 0x00000028
+wm 32 0x020e07a0 0x00000028
+wm 32 0x020e07a4 0x00000028
+wm 32 0x020e07a8 0x00000028
+wm 32 0x020e0748 0x00000028
+wm 32 0x020e05ac 0x00000028
+wm 32 0x020e05b4 0x00000028
+wm 32 0x020e0528 0x00000028
+wm 32 0x020e0520 0x00000028
+wm 32 0x020e0514 0x00000028
+wm 32 0x020e0510 0x00000028
+wm 32 0x020e05bc 0x00000028
+wm 32 0x020e05c4 0x00000028
+wm 32 0x021b0800 0xa1390003
+wm 32 0x021b4800 0xa1380003
+wm 32 0x021b080c 0x00110011
+wm 32 0x021b0810 0x00240024
+wm 32 0x021b480c 0x00260038
+wm 32 0x021b4810 0x002C0038
+wm 32 0x021b083c 0x03400350
+wm 32 0x021b0840 0x03440340
+wm 32 0x021b483c 0x034C0354
+wm 32 0x021b4840 0x035C033C
+wm 32 0x021b0848 0x322A2A2A
+wm 32 0x021b4848 0x302C2834
+wm 32 0x021b0850 0x34303834
+wm 32 0x021b4850 0x422A3E36
wm 32 0x021b081c 0x33333333
wm 32 0x021b0820 0x33333333
wm 32 0x021b0824 0x33333333
@@ -50,15 +64,19 @@ wm 32 0x021b481c 0x33333333
wm 32 0x021b4820 0x33333333
wm 32 0x021b4824 0x33333333
wm 32 0x021b4828 0x33333333
-wm 32 0x021b0018 0x00081740
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+wm 32 0x021b0004 0x00025576
+wm 32 0x021b0008 0x09444040
+
+SETUP_MDCFG0
+
+wm 32 0x021b0010 0xff538f64
+wm 32 0x021b0014 0x01ff0124
+wm 32 0x021b0018 0x00091740
wm 32 0x021b001c 0x00008000
-wm 32 0x021b000c 0x555a7975
-wm 32 0x021b0010 0xff538e64
-wm 32 0x021b0014 0x01ff00db
wm 32 0x021b002c 0x000026d2
-wm 32 0x021b0030 0x005b0e21
-wm 32 0x021b0008 0x09444040
-wm 32 0x021b0004 0x00025576
+wm 32 0x021b0030 0x003F1023
SETUP_1GIB_2GIB_4GIB
@@ -66,34 +84,20 @@ wm 32 0x021b001c 0x04088032
wm 32 0x021b001c 0x0408803a
wm 32 0x021b001c 0x00008033
wm 32 0x021b001c 0x0000803b
-wm 32 0x021b001c 0x00428031
-wm 32 0x021b001c 0x00428039
+wm 32 0x021b001c 0x00048031
+wm 32 0x021b001c 0x00048039
wm 32 0x021b001c 0x09408030
wm 32 0x021b001c 0x09408038
wm 32 0x021b001c 0x04008040
wm 32 0x021b001c 0x04008048
-wm 32 0x021b0800 0xa1380003
-wm 32 0x021b4800 0xa1380003
-wm 32 0x021b0020 0x00005800
-wm 32 0x021b0818 0x00022227
-wm 32 0x021b4818 0x00022227
-wm 32 0x021b083c 0x433c033f
-wm 32 0x021b0840 0x033e033d
-wm 32 0x021b483c 0x43490351
-wm 32 0x021b4840 0x0344032f
-wm 32 0x021b0848 0x4a434146
-wm 32 0x021b4848 0x4745434b
-wm 32 0x021b0850 0x3d3d433a
-wm 32 0x021b4850 0x48334b3e
-wm 32 0x021b080c 0x000f0011
-wm 32 0x021b0810 0x00200022
-wm 32 0x021b480c 0x0033002e
-wm 32 0x021b4810 0x003e003b
-wm 32 0x021b08b8 0x00000800
-wm 32 0x021b48b8 0x00000800
-wm 32 0x021b001c 0x00000000
+wm 32 0x021b0020 0x00007800
+wm 32 0x021b0818 0x00011117
+wm 32 0x021b4818 0x00011117
+wm 32 0x021b0004 0x00025576
wm 32 0x021b0404 0x00011006
+wm 32 0x021b001c 0x00000000
wm 32 0x020e0010 0xf00000ff
-wm 32 0x020e0018 0x007f007f
-wm 32 0x020e001c 0x007f007f
+wm 32 0x020e0018 0x007F007F
+wm 32 0x020e001c 0x007F007F
wm 32 0x020c8000 0x80002021
+
--git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
index e5a7292..dfd4336 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
+++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
@@ -1,3 +1,5 @@
+#define SETUP_MDCFG0 \
+ wm 32 0x021b000c 0x8c929b85
#define SETUP_S_DL_512MB_1GB \
wm 32 0x021b0040 0x00000017; \
--git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h
index 0f83bc9..8fbd661 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h
+++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h
@@ -2,46 +2,60 @@ soc imx6
loadaddr 0x20000000
dcdofs 0x400
-wm 32 0x020e04bc 0x00000030
-wm 32 0x020e04c0 0x00000030
-wm 32 0x020e04c4 0x00000030
-wm 32 0x020e04c8 0x00000030
-wm 32 0x020e04cc 0x00000030
-wm 32 0x020e04d0 0x00000030
-wm 32 0x020e04d4 0x00000030
-wm 32 0x020e04d8 0x00000030
-wm 32 0x020e0470 0x00020030
-wm 32 0x020e0474 0x00020030
-wm 32 0x020e0478 0x00020030
-wm 32 0x020e047c 0x00020030
-wm 32 0x020e0480 0x00020030
-wm 32 0x020e0484 0x00020030
-wm 32 0x020e0488 0x00020030
-wm 32 0x020e048c 0x00020030
-wm 32 0x020e0464 0x00020030
-wm 32 0x020e0490 0x00020030
-wm 32 0x020e04ac 0x00020030
-wm 32 0x020e04b0 0x00020030
-wm 32 0x020e0494 0x00020030
+wm 32 0x020e0774 0x000C0000
+wm 32 0x020e0754 0x00000000
+wm 32 0x020e04ac 0x00000030
+wm 32 0x020e04b0 0x00000030
+wm 32 0x020e0464 0x00000030
+wm 32 0x020e0490 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e0494 0x00000030
+wm 32 0x020e04a0 0x00000000
+wm 32 0x020e04b4 0x00000030
+wm 32 0x020e04b8 0x00000030
wm 32 0x020e04a4 0x00003000
wm 32 0x020e04a8 0x00003000
-wm 32 0x020e04a0 0x00000000
-wm 32 0x020e04b4 0x00003030
-wm 32 0x020e04b8 0x00003030
-wm 32 0x020e0764 0x00000030
-wm 32 0x020e0770 0x00000030
-wm 32 0x020e0778 0x00000030
-wm 32 0x020e077c 0x00000030
-wm 32 0x020e0780 0x00000030
-wm 32 0x020e0784 0x00000030
-wm 32 0x020e078c 0x00000030
-wm 32 0x020e0748 0x00000030
-wm 32 0x020e074c 0x00000030
+wm 32 0x020e076c 0x00000030
wm 32 0x020e0750 0x00020000
-wm 32 0x020e0754 0x00000000
+wm 32 0x020e04bc 0x00000028
+wm 32 0x020e04c0 0x00000028
+wm 32 0x020e04c4 0x00000028
+wm 32 0x020e04c8 0x00000028
+wm 32 0x020e04cc 0x00000028
+wm 32 0x020e04d0 0x00000028
+wm 32 0x020e04d4 0x00000028
+wm 32 0x020e04d8 0x00000028
wm 32 0x020e0760 0x00020000
-wm 32 0x020e076c 0x00000030
-wm 32 0x020e0774 0x000c0000
+wm 32 0x020e0764 0x00000028
+wm 32 0x020e0770 0x00000028
+wm 32 0x020e0778 0x00000028
+wm 32 0x020e077c 0x00000028
+wm 32 0x020e0780 0x00000028
+wm 32 0x020e0784 0x00000028
+wm 32 0x020e078c 0x00000028
+wm 32 0x020e0748 0x00000028
+wm 32 0x020e0470 0x00000028
+wm 32 0x020e0474 0x00000028
+wm 32 0x020e0478 0x00000028
+wm 32 0x020e047c 0x00000028
+wm 32 0x020e0480 0x00000028
+wm 32 0x020e0484 0x00000028
+wm 32 0x020e0488 0x00000028
+wm 32 0x020e048c 0x00000028
+wm 32 0x021b0800 0xa1390003
+wm 32 0x021b4800 0xa1380003
+wm 32 0x021b080c 0x00110011
+wm 32 0x021b0810 0x00240024
+wm 32 0x021b480c 0x00260038
+wm 32 0x021b4810 0x002C0038
+wm 32 0x021b083c 0x02480248
+wm 32 0x021b0840 0x022f022d
+wm 32 0x021b483c 0x02540258
+wm 32 0x021b4840 0x0236021e
+wm 32 0x021b0848 0x332f3033
+wm 32 0x021b4848 0x302d2c35
+wm 32 0x021b0850 0x3030362a
+wm 32 0x021b4850 0x3423372d
wm 32 0x021b081c 0x33333333
wm 32 0x021b0820 0x33333333
wm 32 0x021b0824 0x33333333
@@ -50,15 +64,19 @@ wm 32 0x021b481c 0x33333333
wm 32 0x021b4820 0x33333333
wm 32 0x021b4824 0x33333333
wm 32 0x021b4828 0x33333333
-wm 32 0x021b0018 0x00081740
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+wm 32 0x021b0004 0x00025576
+wm 32 0x021b0008 0x09444040
+
+SETUP_MDCFG0
+
+wm 32 0x021b0010 0xff538f64
+wm 32 0x021b0014 0x01ff0124
+wm 32 0x021b0018 0x00091740
wm 32 0x021b001c 0x00008000
-wm 32 0x021b000c 0x555a7975
-wm 32 0x021b0010 0xff538e64
-wm 32 0x021b0014 0x01ff00db
wm 32 0x021b002c 0x000026d2
-wm 32 0x021b0030 0x005b0e21
-wm 32 0x021b0008 0x09444040
-wm 32 0x021b0004 0x00025576
+wm 32 0x021b0030 0x003F1023
SETUP_S_DL_512MB_1GB
@@ -72,24 +90,9 @@ wm 32 0x021b001c 0x09408030
wm 32 0x021b001c 0x09408038
wm 32 0x021b001c 0x04008040
wm 32 0x021b001c 0x04008048
-wm 32 0x021b0800 0xa1380003
-wm 32 0x021b4800 0xa1380003
-wm 32 0x021b0020 0x00005800
+wm 32 0x021b0020 0x00007800
wm 32 0x021b0818 0x00011117
wm 32 0x021b4818 0x00011117
-wm 32 0x021b083c 0x422D0230
-wm 32 0x021b0840 0x022F022E
-wm 32 0x021b483c 0x4237023D
-wm 32 0x021b4840 0x02340224
-wm 32 0x021b0848 0x38333135
-wm 32 0x021b4848 0x36353338
-wm 32 0x021b0850 0x2E2E332C
-wm 32 0x021b4850 0x3727382F
-wm 32 0x021b080c 0x000C000D
-wm 32 0x021b0810 0x0018001A
-wm 32 0x021b480c 0x00270023
-wm 32 0x021b4810 0x002F002D
-wm 32 0x021b08b8 0x00000800
-wm 32 0x021b48b8 0x00000800
-wm 32 0x021b001c 0x00000000
+wm 32 0x021b0004 0x00025576
wm 32 0x021b0404 0x00011006
+wm 32 0x021b001c 0x00000000
--git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg
index 3116e36..2e428f9 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg
+++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg
@@ -1,3 +1,5 @@
+#define SETUP_MDCFG0 \
+ wm 32 0x021b000c 0x565c9b85
#define SETUP_S_DL_512MB_1GB \
wm 32 0x021b0040 0x00000017; \
--
1.7.0.4
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^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH 1/4] phy/micrel: disable Asym_Pause support
2014-09-15 12:56 [PATCH 1/4] phy/micrel: disable Asym_Pause support Christian Hemp
` (2 preceding siblings ...)
2014-09-15 12:56 ` [PATCH 4/4] ARM:phyFLEX-iMX6 New Ram Timings for Q/DL Christian Hemp
@ 2014-09-17 6:55 ` Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2014-09-17 6:55 UTC (permalink / raw)
To: Christian Hemp; +Cc: barebox
On Mon, Sep 15, 2014 at 02:56:28PM +0200, Christian Hemp wrote:
> From: Jan Weitzel <j.weitzel@phytec.de>
>
> With SUPPORTED_Asym_Pause enabled we need to hotplug the ethernet cable.
> So disable it like done with PHY_ID_KSZ9021.
>
> Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
> Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Applied all, thanks
Sascha
> ---
> drivers/net/phy/micrel.c | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
> index 8aea653..88c64e5 100644
> --- a/drivers/net/phy/micrel.c
> +++ b/drivers/net/phy/micrel.c
> @@ -254,11 +254,11 @@ static struct phy_driver ksphy_driver[] = {
> .config_aneg = genphy_config_aneg,
> .read_status = genphy_read_status,
> }, {
> + /* I saw the same issue like PHY_ID_KSZ9021 for Asym_Pause */
> .phy_id = PHY_ID_KSZ9031,
> .phy_id_mask = 0x00fffff0,
> .drv.name = "Micrel KSZ9031 Gigabit PHY",
> - .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause
> - | SUPPORTED_Asym_Pause),
> + .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
> .config_init = kszphy_config_init,
> .config_aneg = genphy_config_aneg,
> .read_status = genphy_read_status,
> --
> 1.7.0.4
>
>
> _______________________________________________
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> barebox@lists.infradead.org
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^ permalink raw reply [flat|nested] 5+ messages in thread