* [PATCH v2 1/6] ARM: mvebu: Add common reset_cpu function
2014-09-17 20:22 [PATCH v2 0/6] mvebu multi SoC support Sebastian Hesselbarth
@ 2014-09-17 20:22 ` Sebastian Hesselbarth
2014-09-17 20:22 ` [PATCH v2 2/6] ARM: mvebu: Add machine compatible to mbus ranges Sebastian Hesselbarth
` (5 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Sebastian Hesselbarth @ 2014-09-17 20:22 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
mvebu has a reset_cpu function per SoC this does not work when multiple
SoCs are selected, so add a common reset_cpu function which calls into
the SoC specific ones.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- do not remove pure_initcall(mvebu_memory_fixup_register)
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: barebox@lists.infradead.org
---
arch/arm/mach-mvebu/armada-370-xp.c | 19 ++++++++++---------
arch/arm/mach-mvebu/common.c | 14 ++++++++++++++
arch/arm/mach-mvebu/dove.c | 21 +++++++++++----------
arch/arm/mach-mvebu/include/mach/common.h | 1 +
arch/arm/mach-mvebu/kirkwood.c | 19 ++++++++++---------
5 files changed, 46 insertions(+), 28 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index f2b991e5a79f..6251100e886d 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -44,11 +44,21 @@ static inline void armada_370_xp_memory_find(unsigned long *phys_base,
}
}
+static void __noreturn armada_370_xp_reset_cpu(unsigned long addr)
+{
+ writel(0x1, ARMADA_370_XP_SYSCTL_BASE + 0x60);
+ writel(0x1, ARMADA_370_XP_SYSCTL_BASE + 0x64);
+ while (1)
+ ;
+}
+
static int armada_370_xp_init_soc(void)
{
unsigned long phys_base, phys_size;
u32 reg;
+ mvebu_set_reset(armada_370_xp_reset_cpu);
+
barebox_set_model("Marvell Armada 370/XP");
barebox_set_hostname("armada");
@@ -65,12 +75,3 @@ static int armada_370_xp_init_soc(void)
return 0;
}
core_initcall(armada_370_xp_init_soc);
-
-void __noreturn reset_cpu(unsigned long addr)
-{
- writel(0x1, ARMADA_370_XP_SYSCTL_BASE + 0x60);
- writel(0x1, ARMADA_370_XP_SYSCTL_BASE + 0x64);
- while (1)
- ;
-}
-EXPORT_SYMBOL(reset_cpu);
diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c
index ac4b332e0180..05c9ae4c493e 100644
--- a/arch/arm/mach-mvebu/common.c
+++ b/arch/arm/mach-mvebu/common.c
@@ -21,6 +21,7 @@
#include <of.h>
#include <of_address.h>
#include <linux/clk.h>
+#include <mach/common.h>
/*
* Marvell MVEBU SoC id and revision can be read from any PCIe
@@ -138,3 +139,16 @@ static int mvebu_memory_fixup_register(void) {
return of_register_fixup(mvebu_memory_of_fixup, NULL);
}
pure_initcall(mvebu_memory_fixup_register);
+
+static __noreturn void (*mvebu_reset_cpu)(unsigned long addr);
+
+void __noreturn reset_cpu(unsigned long addr)
+{
+ mvebu_reset_cpu(addr);
+}
+EXPORT_SYMBOL(reset_cpu);
+
+void mvebu_set_reset(void __noreturn (*reset)(unsigned long addr))
+{
+ mvebu_reset_cpu = reset;
+}
diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index 69c6436b2491..17cee0b9017c 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -68,10 +68,21 @@ static inline void dove_memory_find(unsigned long *phys_base,
}
}
+static void __noreturn dove_reset_cpu(unsigned long addr)
+{
+ /* enable and assert RSTOUTn */
+ writel(SOFT_RESET_OUT_EN, DOVE_BRIDGE_BASE + BRIDGE_RSTOUT_MASK);
+ writel(SOFT_RESET_EN, DOVE_BRIDGE_BASE + BRIDGE_SYS_SOFT_RESET);
+ while (1)
+ ;
+}
+
static int dove_init_soc(void)
{
unsigned long phys_base, phys_size;
+ mvebu_set_reset(dove_reset_cpu);
+
barebox_set_model("Marvell Dove");
barebox_set_hostname("dove");
@@ -85,13 +96,3 @@ static int dove_init_soc(void)
return 0;
}
core_initcall(dove_init_soc);
-
-void __noreturn reset_cpu(unsigned long addr)
-{
- /* enable and assert RSTOUTn */
- writel(SOFT_RESET_OUT_EN, DOVE_BRIDGE_BASE + BRIDGE_RSTOUT_MASK);
- writel(SOFT_RESET_EN, DOVE_BRIDGE_BASE + BRIDGE_SYS_SOFT_RESET);
- while (1)
- ;
-}
-EXPORT_SYMBOL(reset_cpu);
diff --git a/arch/arm/mach-mvebu/include/mach/common.h b/arch/arm/mach-mvebu/include/mach/common.h
index 9f6118e4ec84..30862e02c7da 100644
--- a/arch/arm/mach-mvebu/include/mach/common.h
+++ b/arch/arm/mach-mvebu/include/mach/common.h
@@ -21,5 +21,6 @@
#define MVEBU_REMAP_INT_REG_BASE 0xf1000000
void mvebu_set_memory(u64 phys_base, u64 phys_size);
+void mvebu_set_reset(void __noreturn (*reset)(unsigned long addr));
#endif
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index c114bdb36006..7c0526b885a0 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -43,10 +43,20 @@ static inline void kirkwood_memory_find(unsigned long *phys_base,
}
}
+static void __noreturn kirkwood_reset_cpu(unsigned long addr)
+{
+ writel(SOFT_RESET_OUT_EN, KIRKWOOD_BRIDGE_BASE + BRIDGE_RSTOUT_MASK);
+ writel(SOFT_RESET_EN, KIRKWOOD_BRIDGE_BASE + BRIDGE_SYS_SOFT_RESET);
+ for(;;)
+ ;
+}
+
static int kirkwood_init_soc(void)
{
unsigned long phys_base, phys_size;
+ mvebu_set_reset(kirkwood_reset_cpu);
+
barebox_set_model("Marvell Kirkwood");
barebox_set_hostname("kirkwood");
@@ -58,12 +68,3 @@ static int kirkwood_init_soc(void)
return 0;
}
core_initcall(kirkwood_init_soc);
-
-void __noreturn reset_cpu(unsigned long addr)
-{
- writel(SOFT_RESET_OUT_EN, KIRKWOOD_BRIDGE_BASE + BRIDGE_RSTOUT_MASK);
- writel(SOFT_RESET_EN, KIRKWOOD_BRIDGE_BASE + BRIDGE_SYS_SOFT_RESET);
- for(;;)
- ;
-}
-EXPORT_SYMBOL(reset_cpu);
--
2.0.0
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^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v2 2/6] ARM: mvebu: Add machine compatible to mbus ranges
2014-09-17 20:22 [PATCH v2 0/6] mvebu multi SoC support Sebastian Hesselbarth
2014-09-17 20:22 ` [PATCH v2 1/6] ARM: mvebu: Add common reset_cpu function Sebastian Hesselbarth
@ 2014-09-17 20:22 ` Sebastian Hesselbarth
2014-09-17 20:22 ` [PATCH v2 3/6] ARM: mvebu: Simplify memory init order Sebastian Hesselbarth
` (4 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Sebastian Hesselbarth @ 2014-09-17 20:22 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: barebox
Multi-SoC support for MVEBU will add mbus ranges for all compiled
SoCs. To protect the mbus node of the SoC barebox is executed on
from others ranges, pass machine's compatible to mvebu_mbus_add_range
and check before applying the fixup.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: barebox@lists.infradead.org
---
arch/arm/mach-mvebu/armada-370-xp.c | 3 ++-
arch/arm/mach-mvebu/dove.c | 6 ++++--
arch/arm/mach-mvebu/kirkwood.c | 3 ++-
drivers/bus/mvebu-mbus.c | 6 +++++-
include/linux/mbus.h | 3 ++-
5 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 6251100e886d..92096fcccabe 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -70,7 +70,8 @@ static int armada_370_xp_init_soc(void)
armada_370_xp_memory_find(&phys_base, &phys_size);
mvebu_set_memory(phys_base, phys_size);
- mvebu_mbus_add_range(0xf0, 0x01, MVEBU_REMAP_INT_REG_BASE);
+ mvebu_mbus_add_range("marvell,armada-370-xp", 0xf0, 0x01,
+ MVEBU_REMAP_INT_REG_BASE);
return 0;
}
diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index 17cee0b9017c..85fdbe41b55c 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -90,8 +90,10 @@ static int dove_init_soc(void)
dove_memory_find(&phys_base, &phys_size);
mvebu_set_memory(phys_base, phys_size);
- mvebu_mbus_add_range(0xf0, 0x01, MVEBU_REMAP_INT_REG_BASE);
- mvebu_mbus_add_range(0xf0, 0x02, DOVE_REMAP_MC_REGS);
+ mvebu_mbus_add_range("marvell,dove", 0xf0, 0x01,
+ MVEBU_REMAP_INT_REG_BASE);
+ mvebu_mbus_add_range("marvell,dove", 0xf0, 0x02,
+ DOVE_REMAP_MC_REGS);
return 0;
}
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index 7c0526b885a0..b6cbd02592a4 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -63,7 +63,8 @@ static int kirkwood_init_soc(void)
kirkwood_memory_find(&phys_base, &phys_size);
mvebu_set_memory(phys_base, phys_size);
- mvebu_mbus_add_range(0xf0, 0x01, MVEBU_REMAP_INT_REG_BASE);
+ mvebu_mbus_add_range("marvell,kirkwood", 0xf0, 0x01,
+ MVEBU_REMAP_INT_REG_BASE);
return 0;
}
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index b7f78367d4a7..9dc43011b964 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -744,6 +744,7 @@ static int mvebu_mbus_init(void)
postcore_initcall(mvebu_mbus_init);
struct mbus_range {
+ const char *compatible;
u32 mbusid;
u32 remap;
struct list_head list;
@@ -752,10 +753,11 @@ struct mbus_range {
#define MBUS_ID(t,a) (((t) << 24) | ((attr) << 16))
static LIST_HEAD(mbus_ranges);
-void mvebu_mbus_add_range(u8 target, u8 attr, u32 remap)
+void mvebu_mbus_add_range(const char *compatible, u8 target, u8 attr, u32 remap)
{
struct mbus_range *r = xzalloc(sizeof(*r));
+ r->compatible = strdup(compatible);
r->mbusid = MBUS_ID(target, attr);
r->remap = remap;
list_add_tail(&r->list, &mbus_ranges);
@@ -811,6 +813,8 @@ static int mvebu_mbus_of_fixup(struct device_node *root, void *context)
continue;
list_for_each_entry(r, &mbus_ranges, list) {
+ if (!of_machine_is_compatible(r->compatible))
+ continue;
if (r->mbusid == mbusid)
ranges[n + na + pa - 1] = r->remap;
}
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
index ac149828757b..b90fabbfb7e5 100644
--- a/include/linux/mbus.h
+++ b/include/linux/mbus.h
@@ -58,6 +58,7 @@ int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
phys_addr_t base, size_t size);
int mvebu_mbus_del_window(phys_addr_t base, size_t size);
-void mvebu_mbus_add_range(u8 target, u8 attr, u32 remap);
+void mvebu_mbus_add_range(const char *compatible,
+ u8 target, u8 attr, u32 remap);
#endif /* __LINUX_MBUS_H */
--
2.0.0
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^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v2 3/6] ARM: mvebu: Simplify memory init order
2014-09-17 20:22 [PATCH v2 0/6] mvebu multi SoC support Sebastian Hesselbarth
2014-09-17 20:22 ` [PATCH v2 1/6] ARM: mvebu: Add common reset_cpu function Sebastian Hesselbarth
2014-09-17 20:22 ` [PATCH v2 2/6] ARM: mvebu: Add machine compatible to mbus ranges Sebastian Hesselbarth
@ 2014-09-17 20:22 ` Sebastian Hesselbarth
2014-09-17 20:22 ` [PATCH v2 4/6] ARM: mvebu: Check for correct SoC in of_fixup callback Sebastian Hesselbarth
` (3 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Sebastian Hesselbarth @ 2014-09-17 20:22 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
The initialisation of the memory nodes on mvebu is a bit
compilcated:
pure_initcall(mvebu_memory_fixup_register)
of_register_fixup(mvebu_memory_of_fixup, NULL)
core_initcall(kirkwood_init_soc)
mvebu_set_memory()
core_initcall(of_arm_init)
of_fix_tree()
mvebu_memory_of_fixup()
First a mvebu common of_fixup function is registered, then the SoC
calls mvebu_set_memory which stores the memory base and size in global
variables. Afterwards the of_fixup is executed which fixes the memory
nodes according to the global variables.
Instead register a SoC specific fixup which directly calls mvebu_set_memory
with the memory base and size as arguments:
pure_initcall(kirkwood_register_soc_fixup);
of_register_fixup(kirkwood_init_soc, NULL);
core_initcall(of_arm_init)
of_fix_tree()
kirkwood_init_soc()
mvebu_set_memory(phys_base, phys_size);
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- remove pure_initcall(mvebu_memory_fixup_register) here
- also move mvebu_mbus_add_range() to pure_initcall(foo_soc_init)
- fix missing _xp_ in armada_370_register_soc_fixup()
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: barebox@lists.infradead.org
---
arch/arm/mach-mvebu/armada-370-xp.c | 13 ++++++++----
arch/arm/mach-mvebu/common.c | 35 ++++++++++---------------------
arch/arm/mach-mvebu/dove.c | 13 ++++++++----
arch/arm/mach-mvebu/include/mach/common.h | 2 +-
arch/arm/mach-mvebu/kirkwood.c | 13 ++++++++----
5 files changed, 39 insertions(+), 37 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 92096fcccabe..1dedcfc55467 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -52,7 +52,7 @@ static void __noreturn armada_370_xp_reset_cpu(unsigned long addr)
;
}
-static int armada_370_xp_init_soc(void)
+static int armada_370_xp_init_soc(struct device_node *root, void *context)
{
unsigned long phys_base, phys_size;
u32 reg;
@@ -70,9 +70,14 @@ static int armada_370_xp_init_soc(void)
armada_370_xp_memory_find(&phys_base, &phys_size);
mvebu_set_memory(phys_base, phys_size);
- mvebu_mbus_add_range("marvell,armada-370-xp", 0xf0, 0x01,
- MVEBU_REMAP_INT_REG_BASE);
return 0;
}
-core_initcall(armada_370_xp_init_soc);
+
+static int armada_370_xp_register_soc_fixup(void)
+{
+ mvebu_mbus_add_range("marvell,armada-370-xp", 0xf0, 0x01,
+ MVEBU_REMAP_INT_REG_BASE);
+ return of_register_fixup(armada_370_xp_init_soc, NULL);
+}
+pure_initcall(armada_370_xp_register_soc_fixup);
diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c
index 05c9ae4c493e..309f7a6aaa52 100644
--- a/arch/arm/mach-mvebu/common.c
+++ b/arch/arm/mach-mvebu/common.c
@@ -81,29 +81,21 @@ static int mvebu_soc_id_init(void)
}
postcore_initcall(mvebu_soc_id_init);
-static u64 mvebu_mem[2];
-
-void mvebu_set_memory(u64 phys_base, u64 phys_size)
-{
- mvebu_mem[0] = phys_base;
- mvebu_mem[1] = phys_size;
-}
-
/*
* Memory size is set up by BootROM and can be read from SoC's ram controller
* registers. Fixup provided DTs to reflect accessible amount of directly
* attached RAM. Removable RAM, e.g. SODIMM, should be added by a per-board
* fixup.
*/
-static int mvebu_memory_of_fixup(struct device_node *root, void *context)
+int mvebu_set_memory(u64 phys_base, u64 phys_size)
{
- struct device_node *np;
+ struct device_node *np, *root;
__be32 reg[4];
int na, ns;
- /* bail out on zero-sized mem */
- if (!mvebu_mem[1])
- return -ENODEV;
+ root = of_get_root_node();
+ if (!root)
+ return -EINVAL;
np = of_find_node_by_path("/memory");
if (!np)
@@ -115,17 +107,17 @@ static int mvebu_memory_of_fixup(struct device_node *root, void *context)
ns = of_n_size_cells(np);
if (na == 2) {
- reg[0] = cpu_to_be32(mvebu_mem[0] >> 32);
- reg[1] = cpu_to_be32(mvebu_mem[0] & 0xffffffff);
+ reg[0] = cpu_to_be32(phys_base >> 32);
+ reg[1] = cpu_to_be32(phys_base & 0xffffffff);
} else {
- reg[0] = cpu_to_be32(mvebu_mem[0] & 0xffffffff);
+ reg[0] = cpu_to_be32(phys_base & 0xffffffff);
}
if (ns == 2) {
- reg[2] = cpu_to_be32(mvebu_mem[1] >> 32);
- reg[3] = cpu_to_be32(mvebu_mem[1] & 0xffffffff);
+ reg[2] = cpu_to_be32(phys_size >> 32);
+ reg[3] = cpu_to_be32(phys_size & 0xffffffff);
} else {
- reg[1] = cpu_to_be32(mvebu_mem[1] & 0xffffffff);
+ reg[1] = cpu_to_be32(phys_size & 0xffffffff);
}
if (of_set_property(np, "device_type", "memory", sizeof("memory"), 1) ||
@@ -135,11 +127,6 @@ static int mvebu_memory_of_fixup(struct device_node *root, void *context)
return 0;
}
-static int mvebu_memory_fixup_register(void) {
- return of_register_fixup(mvebu_memory_of_fixup, NULL);
-}
-pure_initcall(mvebu_memory_fixup_register);
-
static __noreturn void (*mvebu_reset_cpu)(unsigned long addr);
void __noreturn reset_cpu(unsigned long addr)
diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index 85fdbe41b55c..31d2bb57f832 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -77,7 +77,7 @@ static void __noreturn dove_reset_cpu(unsigned long addr)
;
}
-static int dove_init_soc(void)
+static int dove_init_soc(struct device_node *root, void *context)
{
unsigned long phys_base, phys_size;
@@ -90,11 +90,16 @@ static int dove_init_soc(void)
dove_memory_find(&phys_base, &phys_size);
mvebu_set_memory(phys_base, phys_size);
+
+ return 0;
+}
+
+static int dove_register_soc_fixup(void)
+{
mvebu_mbus_add_range("marvell,dove", 0xf0, 0x01,
MVEBU_REMAP_INT_REG_BASE);
mvebu_mbus_add_range("marvell,dove", 0xf0, 0x02,
DOVE_REMAP_MC_REGS);
-
- return 0;
+ return of_register_fixup(dove_init_soc, NULL);
}
-core_initcall(dove_init_soc);
+pure_initcall(dove_register_soc_fixup);
diff --git a/arch/arm/mach-mvebu/include/mach/common.h b/arch/arm/mach-mvebu/include/mach/common.h
index 30862e02c7da..5ce33fd88274 100644
--- a/arch/arm/mach-mvebu/include/mach/common.h
+++ b/arch/arm/mach-mvebu/include/mach/common.h
@@ -20,7 +20,7 @@
#define MVEBU_REMAP_INT_REG_BASE 0xf1000000
-void mvebu_set_memory(u64 phys_base, u64 phys_size);
+int mvebu_set_memory(u64 phys_base, u64 phys_size);
void mvebu_set_reset(void __noreturn (*reset)(unsigned long addr));
#endif
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index b6cbd02592a4..8ab2849ba2e4 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -51,7 +51,7 @@ static void __noreturn kirkwood_reset_cpu(unsigned long addr)
;
}
-static int kirkwood_init_soc(void)
+static int kirkwood_init_soc(struct device_node *root, void *context)
{
unsigned long phys_base, phys_size;
@@ -63,9 +63,14 @@ static int kirkwood_init_soc(void)
kirkwood_memory_find(&phys_base, &phys_size);
mvebu_set_memory(phys_base, phys_size);
- mvebu_mbus_add_range("marvell,kirkwood", 0xf0, 0x01,
- MVEBU_REMAP_INT_REG_BASE);
return 0;
}
-core_initcall(kirkwood_init_soc);
+
+static int kirkwood_register_soc_fixup(void)
+{
+ mvebu_mbus_add_range("marvell,kirkwood", 0xf0, 0x01,
+ MVEBU_REMAP_INT_REG_BASE);
+ return of_register_fixup(kirkwood_init_soc, NULL);
+}
+pure_initcall(kirkwood_register_soc_fixup);
--
2.0.0
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^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v2 4/6] ARM: mvebu: Check for correct SoC in of_fixup callback
2014-09-17 20:22 [PATCH v2 0/6] mvebu multi SoC support Sebastian Hesselbarth
` (2 preceding siblings ...)
2014-09-17 20:22 ` [PATCH v2 3/6] ARM: mvebu: Simplify memory init order Sebastian Hesselbarth
@ 2014-09-17 20:22 ` Sebastian Hesselbarth
2014-09-17 20:22 ` [PATCH v2 5/6] ARM: mvebu: Allow multiple SoCs Sebastian Hesselbarth
` (2 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Sebastian Hesselbarth @ 2014-09-17 20:22 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Only run the fixup when we are actually on the corresponding
SoC.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: barebox@lists.infradead.org
---
arch/arm/mach-mvebu/armada-370-xp.c | 3 +++
arch/arm/mach-mvebu/dove.c | 3 +++
arch/arm/mach-mvebu/kirkwood.c | 3 +++
3 files changed, 9 insertions(+)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 1dedcfc55467..57f6a5fe0ddc 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -57,6 +57,9 @@ static int armada_370_xp_init_soc(struct device_node *root, void *context)
unsigned long phys_base, phys_size;
u32 reg;
+ if (!of_machine_is_compatible("marvell,armada-370-xp"))
+ return 0;
+
mvebu_set_reset(armada_370_xp_reset_cpu);
barebox_set_model("Marvell Armada 370/XP");
diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index 31d2bb57f832..c2852f8986ae 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -81,6 +81,9 @@ static int dove_init_soc(struct device_node *root, void *context)
{
unsigned long phys_base, phys_size;
+ if (!of_machine_is_compatible("marvell,dove"))
+ return 0;
+
mvebu_set_reset(dove_reset_cpu);
barebox_set_model("Marvell Dove");
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index 8ab2849ba2e4..d7903f732eac 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -55,6 +55,9 @@ static int kirkwood_init_soc(struct device_node *root, void *context)
{
unsigned long phys_base, phys_size;
+ if (!of_machine_is_compatible("marvell,kirkwood"))
+ return 0;
+
mvebu_set_reset(kirkwood_reset_cpu);
barebox_set_model("Marvell Kirkwood");
--
2.0.0
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^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v2 5/6] ARM: mvebu: Allow multiple SoCs
2014-09-17 20:22 [PATCH v2 0/6] mvebu multi SoC support Sebastian Hesselbarth
` (3 preceding siblings ...)
2014-09-17 20:22 ` [PATCH v2 4/6] ARM: mvebu: Check for correct SoC in of_fixup callback Sebastian Hesselbarth
@ 2014-09-17 20:22 ` Sebastian Hesselbarth
2014-09-17 20:22 ` [PATCH v2 6/6] ARM: Add mvebu_defconfig Sebastian Hesselbarth
2014-09-19 5:47 ` [PATCH v2 0/6] mvebu multi SoC support Sascha Hauer
6 siblings, 0 replies; 13+ messages in thread
From: Sebastian Hesselbarth @ 2014-09-17 20:22 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Now that the correct SoC specific memory fixup function is called
we can allow to select multiple SoCs in Kconfig.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- add Kconfig comment lines for each SoC
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: barebox@lists.infradead.org
---
arch/arm/mach-mvebu/Kconfig | 37 ++++++++++++++++---------------------
1 file changed, 16 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 7f6e44e7fc7b..f92c72f46ae1 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -7,83 +7,78 @@ config ARCH_TEXT_BASE
default 0x2000000 if ARCH_DOVE
default 0x2000000 if ARCH_KIRKWOOD
-choice
- prompt "Marvell EBU Processor"
-
config ARCH_ARMADA_370
- bool "Armada 370"
+ bool
select CPU_V7
select CLOCKSOURCE_MVEBU
config ARCH_ARMADA_XP
- bool "Armada XP"
+ bool
select CPU_V7
select CLOCKSOURCE_MVEBU
config ARCH_DOVE
- bool "Dove 88AP510"
+ bool
select CPU_V7
select CLOCKSOURCE_ORION
config ARCH_KIRKWOOD
- bool "Kirkwood"
+ bool
select CPU_FEROCEON
select CLOCKSOURCE_ORION
-endchoice
-
#
# Armada 370 SoC boards
#
+#
-if ARCH_ARMADA_370
+comment "Armada 370 based boards"
config MACH_GLOBALSCALE_MIRABOX
bool "Globalscale Mirabox"
-
-endif # ARCH_ARMADA_370
+ select ARCH_ARMADA_370
#
# Armada XP SoC boards
#
-if ARCH_ARMADA_XP
+comment "Armada XP based boards"
config MACH_PLATHOME_OPENBLOCKS_AX3
bool "PlatHome OpenBlocks AX3"
+ select ARCH_ARMADA_XP
config MACH_MARVELL_ARMADA_XP_GP
bool "Marvell Armada XP GP"
-
-endif # ARCH_ARMADA_XP
+ select ARCH_ARMADA_XP
#
# Dove 88AP510 SoC boards
#
-if ARCH_DOVE
+comment "Dove based boards"
config MACH_SOLIDRUN_CUBOX
bool "SolidRun CuBox"
-
-endif # ARCH_DOVE
+ select ARCH_DOVE
#
# Kirkwood SoC boards
#
-if ARCH_KIRKWOOD
+comment "Kirkwood based boards"
config MACH_GLOBALSCALE_GURUPLUG
bool "Guruplug"
+ select ARCH_KIRKWOOD
config MACH_PLATHOME_OPENBLOCKS_A6
bool "PlatHome OpenBlocks A6"
+ select ARCH_KIRKWOOD
config MACH_USI_TOPKICK
bool "Topkick"
-
-endif # ARCH_KIRKWOOD
+ select ARCH_KIRKWOOD
#
# Common options
--
2.0.0
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^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v2 6/6] ARM: Add mvebu_defconfig
2014-09-17 20:22 [PATCH v2 0/6] mvebu multi SoC support Sebastian Hesselbarth
` (4 preceding siblings ...)
2014-09-17 20:22 ` [PATCH v2 5/6] ARM: mvebu: Allow multiple SoCs Sebastian Hesselbarth
@ 2014-09-17 20:22 ` Sebastian Hesselbarth
2014-09-20 17:24 ` Sebastian Hesselbarth
2014-09-19 5:47 ` [PATCH v2 0/6] mvebu multi SoC support Sascha Hauer
6 siblings, 1 reply; 13+ messages in thread
From: Sebastian Hesselbarth @ 2014-09-17 20:22 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
This adds a mvebu_defconfig which enables all mvebu based boards.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- remove CONFIG_AEABI and CONFIG_ARM_UNWIND until someone confirms
it is working on ARMv5TE (Kirkwood)
- add networking commands
- add Orion ethernet and Marvell PHY drivers
- add MVEBU SPI and AT25 driver
- add MVEBU I2C driver
- add Orion NAND driver
- add Orion GPIO and LED GPIO drivers
- add MVEBU PCI driver
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: barebox@lists.infradead.org
---
arch/arm/configs/mvebu_defconfig | 123 +++++++++++++++++++++++++++++++++++++++
1 file changed, 123 insertions(+)
create mode 100644 arch/arm/configs/mvebu_defconfig
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
new file mode 100644
index 000000000000..26be4ecfe022
--- /dev/null
+++ b/arch/arm/configs/mvebu_defconfig
@@ -0,0 +1,123 @@
+CONFIG_ARCH_MVEBU=y
+CONFIG_MACH_GLOBALSCALE_MIRABOX=y
+CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3=y
+CONFIG_MACH_MARVELL_ARMADA_XP_GP=y
+CONFIG_MACH_SOLIDRUN_CUBOX=y
+CONFIG_MACH_GLOBALSCALE_GURUPLUG=y
+CONFIG_MACH_PLATHOME_OPENBLOCKS_A6=y
+CONFIG_MACH_USI_TOPKICK=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x0
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_RELOCATABLE=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+CONFIG_BLSPEC=y
+CONFIG_IMD_TARGET=y
+CONFIG_CONSOLE_ACTIVATE_NONE=y
+CONFIG_PARTITION_DISK_EFI=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_IMD=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_ARM_MMUINFO=y
+CONFIG_CMD_BOOT=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_AUTOMOUNT=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_GLOBAL=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_BASENAME=y
+CONFIG_CMD_DIRNAME=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_READLINK=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SHA224SUM=y
+CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_GETOPT=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_READF=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_HOST=y
+CONFIG_NET_CMD_IFUP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
+CONFIG_CMD_MENUTREE=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_LED_TRIGGER=y
+CONFIG_CMD_WD=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
+CONFIG_NET=y
+CONFIG_OFDEVICE=y
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_NET_ORION=y
+CONFIG_MARVELL_PHY=y
+CONFIG_DRIVER_SPI_MVEBU=y
+CONFIG_I2C=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_MTD=y
+CONFIG_MTD_M25P80=y
+CONFIG_NAND=y
+CONFIG_NAND_ORION=y
+CONFIG_DISK_AHCI=y
+CONFIG_USB_HOST=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_MMC_BOOT_PARTITIONS=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_GPIO_OF=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_EEPROM_AT25=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_WATCHDOG=y
+CONFIG_GPIO_ORION=y
+CONFIG_PCI_MVEBU=y
+CONFIG_FS_CRAMFS=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_BZLIB=y
+CONFIG_LZO_DECOMPRESS=y
--
2.0.0
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 6/6] ARM: Add mvebu_defconfig
2014-09-17 20:22 ` [PATCH v2 6/6] ARM: Add mvebu_defconfig Sebastian Hesselbarth
@ 2014-09-20 17:24 ` Sebastian Hesselbarth
2014-09-23 5:58 ` Sascha Hauer
0 siblings, 1 reply; 13+ messages in thread
From: Sebastian Hesselbarth @ 2014-09-20 17:24 UTC (permalink / raw)
Cc: barebox
On 09/17/2014 10:22 PM, Sebastian Hesselbarth wrote:
> From: Sascha Hauer <s.hauer@pengutronix.de>
>
> This adds a mvebu_defconfig which enables all mvebu based boards.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
...
> ---
> arch/arm/configs/mvebu_defconfig | 123 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 123 insertions(+)
> create mode 100644 arch/arm/configs/mvebu_defconfig
>
> diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
> new file mode 100644
> index 000000000000..26be4ecfe022
> --- /dev/null
> +++ b/arch/arm/configs/mvebu_defconfig
> @@ -0,0 +1,123 @@
[...]
> +CONFIG_MMU=y
Sascha,
can you please drop CONFIG_MMU for mvebu_defconfig for now? I did some
more testing today and realized that Armada 370 and XP are CPU_V7 but
have a different cache controller. We currently have no support for
Marvell Aurora and therefore flush/inv ranges will not work and break
any driver using dma_flush/inv_range.
Sebastian
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 6/6] ARM: Add mvebu_defconfig
2014-09-20 17:24 ` Sebastian Hesselbarth
@ 2014-09-23 5:58 ` Sascha Hauer
0 siblings, 0 replies; 13+ messages in thread
From: Sascha Hauer @ 2014-09-23 5:58 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: barebox
On Sat, Sep 20, 2014 at 07:24:28PM +0200, Sebastian Hesselbarth wrote:
> On 09/17/2014 10:22 PM, Sebastian Hesselbarth wrote:
> > From: Sascha Hauer <s.hauer@pengutronix.de>
> >
> > This adds a mvebu_defconfig which enables all mvebu based boards.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> > ---
> ...
> > ---
> > arch/arm/configs/mvebu_defconfig | 123 +++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 123 insertions(+)
> > create mode 100644 arch/arm/configs/mvebu_defconfig
> >
> > diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
> > new file mode 100644
> > index 000000000000..26be4ecfe022
> > --- /dev/null
> > +++ b/arch/arm/configs/mvebu_defconfig
> > @@ -0,0 +1,123 @@
> [...]
> > +CONFIG_MMU=y
>
> Sascha,
>
> can you please drop CONFIG_MMU for mvebu_defconfig for now? I did some
> more testing today and realized that Armada 370 and XP are CPU_V7 but
> have a different cache controller. We currently have no support for
> Marvell Aurora and therefore flush/inv ranges will not work and break
> any driver using dma_flush/inv_range.
Ok, just did that.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/6] mvebu multi SoC support
2014-09-17 20:22 [PATCH v2 0/6] mvebu multi SoC support Sebastian Hesselbarth
` (5 preceding siblings ...)
2014-09-17 20:22 ` [PATCH v2 6/6] ARM: Add mvebu_defconfig Sebastian Hesselbarth
@ 2014-09-19 5:47 ` Sascha Hauer
2014-09-19 6:44 ` Sebastian Hesselbarth
6 siblings, 1 reply; 13+ messages in thread
From: Sascha Hauer @ 2014-09-19 5:47 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: barebox
Sebastian, Ezequiel,
On Wed, Sep 17, 2014 at 10:22:38PM +0200, Sebastian Hesselbarth wrote:
> This is v2 of the Multi-SoC series for MVEBU. It has been tested
> on Kirkwood (Guruplug), Dove (CuBox), and Armada 370 (Mirabox)
> with the very same non-EABI binary. It should also work on Armada
> XP but I cannot test right now.
Do you want to give it a test on Armada XP before I apply this series or
are you fine with this without testing it on Armada XP?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 0/6] mvebu multi SoC support
2014-09-19 5:47 ` [PATCH v2 0/6] mvebu multi SoC support Sascha Hauer
@ 2014-09-19 6:44 ` Sebastian Hesselbarth
2014-09-19 7:55 ` Sascha Hauer
0 siblings, 1 reply; 13+ messages in thread
From: Sebastian Hesselbarth @ 2014-09-19 6:44 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 09/19/2014 07:47 AM, Sascha Hauer wrote:
> On Wed, Sep 17, 2014 at 10:22:38PM +0200, Sebastian Hesselbarth wrote:
>> This is v2 of the Multi-SoC series for MVEBU. It has been tested
>> on Kirkwood (Guruplug), Dove (CuBox), and Armada 370 (Mirabox)
>> with the very same non-EABI binary. It should also work on Armada
>> XP but I cannot test right now.
>
> Do you want to give it a test on Armada XP before I apply this series or
> are you fine with this without testing it on Armada XP?
I just tested it on Lenovo ix4-300d with Armada XP MV78230-A0, so feel
free to pick it up.
If I find some time, I'll polish ix4-300d patches and send them, too.
Sebastian
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/6] mvebu multi SoC support
2014-09-19 6:44 ` Sebastian Hesselbarth
@ 2014-09-19 7:55 ` Sascha Hauer
2014-09-19 8:25 ` Sebastian Hesselbarth
0 siblings, 1 reply; 13+ messages in thread
From: Sascha Hauer @ 2014-09-19 7:55 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: barebox
On Fri, Sep 19, 2014 at 08:44:09AM +0200, Sebastian Hesselbarth wrote:
> On 09/19/2014 07:47 AM, Sascha Hauer wrote:
> > On Wed, Sep 17, 2014 at 10:22:38PM +0200, Sebastian Hesselbarth wrote:
> >> This is v2 of the Multi-SoC series for MVEBU. It has been tested
> >> on Kirkwood (Guruplug), Dove (CuBox), and Armada 370 (Mirabox)
> >> with the very same non-EABI binary. It should also work on Armada
> >> XP but I cannot test right now.
> >
> > Do you want to give it a test on Armada XP before I apply this series or
> > are you fine with this without testing it on Armada XP?
>
> I just tested it on Lenovo ix4-300d with Armada XP MV78230-A0, so feel
> free to pick it up.
Cool, just did that. Are you fine with removing the board specific
configs now that we have a mvebu_defconfig?
> If I find some time, I'll polish ix4-300d patches and send them, too.
Nice.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/6] mvebu multi SoC support
2014-09-19 7:55 ` Sascha Hauer
@ 2014-09-19 8:25 ` Sebastian Hesselbarth
0 siblings, 0 replies; 13+ messages in thread
From: Sebastian Hesselbarth @ 2014-09-19 8:25 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 09/19/2014 09:55 AM, Sascha Hauer wrote:
> On Fri, Sep 19, 2014 at 08:44:09AM +0200, Sebastian Hesselbarth wrote:
>> On 09/19/2014 07:47 AM, Sascha Hauer wrote:
>>> On Wed, Sep 17, 2014 at 10:22:38PM +0200, Sebastian Hesselbarth wrote:
>>>> This is v2 of the Multi-SoC series for MVEBU. It has been tested
>>>> on Kirkwood (Guruplug), Dove (CuBox), and Armada 370 (Mirabox)
>>>> with the very same non-EABI binary. It should also work on Armada
>>>> XP but I cannot test right now.
>>>
>>> Do you want to give it a test on Armada XP before I apply this series or
>>> are you fine with this without testing it on Armada XP?
>>
>> I just tested it on Lenovo ix4-300d with Armada XP MV78230-A0, so feel
>> free to pick it up.
>
> Cool, just did that. Are you fine with removing the board specific
> configs now that we have a mvebu_defconfig?
Yes, please. As you already pointed out, the board specific configs are
horribly out-dated and should be nuked.
>> If I find some time, I'll polish ix4-300d patches and send them, too.
>
> Nice.
It may also include deferred probing support as the ix4-300d has a gpio
attached gpio-expander (aka 74HC138) with LEDs. And as you may guess,
requesting GPIOs from that expander which needs GPIOs itself does not
quite work yet.
I have it running, the deferred probing is simple, but I'll have to
review the whole set first (and sync with Linux dts of ix4).
Sebastian
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