[For next PATCH 1/2] arm: am33xx: Add rmii2_crs_dv mux selection in SMA2 register

[For next PATCH 1/2] arm: am33xx: Add rmii2_crs_dv mux selection in SMA2 register

[Wadim Egorov]

"Silicon revision 1.0 devices only provide the MMC2_DAT7 signal when Mode3 is
selected. Silicon revision 2.0 and newer devices implement another level of
pin multiplexing which provides the original MMC2_DAT7 signal or RMII2_CRS_DV
signal when Mode3 is selected. This new level of of pin multiplexing is
selected with bit zero of the SMA2 register."

See AM335x Sitara Processors Manual.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
 arch/arm/mach-omap/am33xx_generic.c              |   12 ++++++++++++
 arch/arm/mach-omap/include/mach/am33xx-generic.h |    1 +
 2 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c
index f293134..12764bc 100644
--- a/arch/arm/mach-omap/am33xx_generic.c
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -428,3 +428,15 @@ void am335x_sdram_init(int ioctrl, const struct am33xx_cmd_control *cmd_ctrl,
 
 	am33xx_config_sdram(emif_regs);
 }
+
+#define AM33XX_CONTROL_SMA2_OFS	0x1320
+
+/**
+ * am33xx_select_rmii2_crs_dv - Select RMII2_CRS_DV on GPMC_A9 pin in MODE3
+ */
+void am33xx_select_rmii2_crs_dv(void)
+{
+	uint32_t val = readl(AM33XX_CTRL_BASE + AM33XX_CONTROL_SMA2_OFS);
+	val |= 0x00000001;
+	writel(val, AM33XX_CTRL_BASE + AM33XX_CONTROL_SMA2_OFS);
+}
diff --git a/arch/arm/mach-omap/include/mach/am33xx-generic.h b/arch/arm/mach-omap/include/mach/am33xx-generic.h
index 6c85d51..1264e7e 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-generic.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-generic.h
@@ -33,5 +33,6 @@ void __noreturn am33xx_reset_cpu(unsigned long addr);
 void am33xx_enable_per_clocks(void);
 int am33xx_init(void);
 int am33xx_devices_init(void);
+void am33xx_select_rmii2_crs_dv(void);
 
 #endif /* __MACH_AM33XX_GENERIC_H */
-- 
1.7.0.4


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[For next PATCH 2/2] phyFLEX: Select RMII2_CRS_DV on GPMC_A9 pin

[Wadim Egorov]

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
 arch/arm/boards/phytec-phyflex-am335x/board.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boards/phytec-phyflex-am335x/board.c b/arch/arm/boards/phytec-phyflex-am335x/board.c
index 12fad8f..cf7dd2e 100644
--- a/arch/arm/boards/phytec-phyflex-am335x/board.c
+++ b/arch/arm/boards/phytec-phyflex-am335x/board.c
@@ -89,6 +89,8 @@ static int pfla03_devices_init(void)
 	armlinux_set_architecture(MACH_TYPE_PFLA03);
 	defaultenv_append_directory(defaultenv_phyflex_am335x);
 
+	am33xx_select_rmii2_crs_dv();
+
 	am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload");
 	am33xx_bbu_spi_nor_register_handler("spi", "/dev/m25p0.barebox");
 	am33xx_bbu_nand_xloadslots_register_handler("MLO.nand",
-- 
1.7.0.4


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Re: [For next PATCH 1/2] arm: am33xx: Add rmii2_crs_dv mux selection in SMA2 register

[Sascha Hauer]

Hi Wadim,

On Thu, Oct 30, 2014 at 01:01:35PM +0100, Wadim Egorov wrote:
> "Silicon revision 1.0 devices only provide the MMC2_DAT7 signal when Mode3 is
> selected. Silicon revision 2.0 and newer devices implement another level of
> pin multiplexing which provides the original MMC2_DAT7 signal or RMII2_CRS_DV
> signal when Mode3 is selected. This new level of of pin multiplexing is
> selected with bit zero of the SMA2 register."
> 
> See AM335x Sitara Processors Manual.
> 
> Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
> ---
>  arch/arm/mach-omap/am33xx_generic.c              |   12 ++++++++++++
>  arch/arm/mach-omap/include/mach/am33xx-generic.h |    1 +
>  2 files changed, 13 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c
> index f293134..12764bc 100644
> --- a/arch/arm/mach-omap/am33xx_generic.c
> +++ b/arch/arm/mach-omap/am33xx_generic.c
> @@ -428,3 +428,15 @@ void am335x_sdram_init(int ioctrl, const struct am33xx_cmd_control *cmd_ctrl,
>  
>  	am33xx_config_sdram(emif_regs);
>  }
> +
> +#define AM33XX_CONTROL_SMA2_OFS	0x1320
> +
> +/**
> + * am33xx_select_rmii2_crs_dv - Select RMII2_CRS_DV on GPMC_A9 pin in MODE3
> + */
> +void am33xx_select_rmii2_crs_dv(void)
> +{
> +	uint32_t val = readl(AM33XX_CTRL_BASE + AM33XX_CONTROL_SMA2_OFS);
> +	val |= 0x00000001;
> +	writel(val, AM33XX_CTRL_BASE + AM33XX_CONTROL_SMA2_OFS);
> +}

Is it OK to call this for Silicon revision 1.0 aswell? You seem to do so
in your second patch.

Sascha

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