[PATCH 01/12] tegra: beaver: set hostname in board init

[PATCH 01/12] tegra: beaver: set hostname in board init

[Lucas Stach]

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/boards/nvidia-beaver/board.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boards/nvidia-beaver/board.c b/arch/arm/boards/nvidia-beaver/board.c
index 20707d8..d270301 100644
--- a/arch/arm/boards/nvidia-beaver/board.c
+++ b/arch/arm/boards/nvidia-beaver/board.c
@@ -20,7 +20,7 @@
 #include <i2c/i2c.h>
 #include <init.h>
 
-static int nvidia_beaver_devices_init(void)
+static int nvidia_beaver_fs_init(void)
 {
 	struct i2c_client client;
 	u8 data;
@@ -44,4 +44,15 @@ static int nvidia_beaver_devices_init(void)
 
 	return 0;
 }
-fs_initcall(nvidia_beaver_devices_init);
+fs_initcall(nvidia_beaver_fs_init);
+
+static int nvidia_beaver_device_init(void)
+{
+	if (!of_machine_is_compatible("nvidia,beaver"))
+		return 0;
+
+	barebox_set_hostname("beaver");
+
+	return 0;
+}
+device_initcall(nvidia_beaver_device_init);
-- 
1.9.3


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[PATCH 02/12] tegra: jetson-tk1: set hostname in board init

[Lucas Stach]

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/boards/nvidia-jetson-tk1/board.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boards/nvidia-jetson-tk1/board.c b/arch/arm/boards/nvidia-jetson-tk1/board.c
index c20f56a..564e6a0 100644
--- a/arch/arm/boards/nvidia-jetson-tk1/board.c
+++ b/arch/arm/boards/nvidia-jetson-tk1/board.c
@@ -26,7 +26,7 @@
 #define AS3722_GPIO_SIGNAL_OUT	0x20
 #define AS3722_SD_CONTROL	0x4d
 
-static int nvidia_jetson_tk1_devices_init(void)
+static int nvidia_jetson_tk1_fs_init(void)
 {
 	struct i2c_client client;
 	u8 data;
@@ -47,4 +47,15 @@ static int nvidia_jetson_tk1_devices_init(void)
 
 	return 0;
 }
-fs_initcall(nvidia_jetson_tk1_devices_init);
+fs_initcall(nvidia_jetson_tk1_fs_init);
+
+static int nvidia_jetson_tk1_device_init(void)
+{
+	if (!of_machine_is_compatible("nvidia,jetson-tk1"))
+		return 0;
+
+	barebox_set_hostname("jetson-tk1");
+
+	return 0;
+}
+device_initcall(nvidia_jetson_tk1_device_init);
-- 
1.9.3


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[PATCH 03/12] tegra: colibri-t20: set hostname in board init

[Lucas Stach]

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/boards/toradex-colibri-t20/Makefile |  1 +
 arch/arm/boards/toradex-colibri-t20/board.c  | 29 ++++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 arch/arm/boards/toradex-colibri-t20/board.c

diff --git a/arch/arm/boards/toradex-colibri-t20/Makefile b/arch/arm/boards/toradex-colibri-t20/Makefile
index 1f76732..d0347f2 100644
--- a/arch/arm/boards/toradex-colibri-t20/Makefile
+++ b/arch/arm/boards/toradex-colibri-t20/Makefile
@@ -3,6 +3,7 @@ CFLAGS_pbl-entry.o := \
 	-fno-tree-switch-conversion -fno-jump-tables
 soc := tegra20
 lwl-y += entry.o
+obj-y += board.o
 extra-y += colibri-t20_256_hsmmc.bct colibri-t20_256_v11_nand.bct \
            colibri-t20_256_v12_nand.bct colibri-t20_512_hsmmc.bct \
            colibri-t20_512_v11_nand.bct colibri-t20_512_v12_nand.bct
\ No newline at end of file
diff --git a/arch/arm/boards/toradex-colibri-t20/board.c b/arch/arm/boards/toradex-colibri-t20/board.c
new file mode 100644
index 0000000..7061981
--- /dev/null
+++ b/arch/arm/boards/toradex-colibri-t20/board.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <init.h>
+
+static int toradex_colibri_t20_device_init(void)
+{
+	if (!of_machine_is_compatible("toradex,colibri_t20-512"))
+		return 0;
+
+	barebox_set_hostname("colibri-t20");
+
+	return 0;
+}
+device_initcall(toradex_colibri_t20_device_init);
-- 
1.9.3


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[PATCH 04/12] tegra: beaver: switch to upstream Tegra30 dtsi

[Lucas Stach]

It's the same as our version, so no need to carry it
around any longer.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/dts/tegra30-beaver.dts |   2 +-
 arch/arm/dts/tegra30.dtsi       | 892 ----------------------------------------
 2 files changed, 1 insertion(+), 893 deletions(-)
 delete mode 100644 arch/arm/dts/tegra30.dtsi

diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts
index 94955f9..d2809bb 100644
--- a/arch/arm/dts/tegra30-beaver.dts
+++ b/arch/arm/dts/tegra30-beaver.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-#include "tegra30.dtsi"
+#include <arm/tegra30.dtsi>
 
 / {
 	model = "NVIDIA Tegra30 Beaver evaluation board";
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
deleted file mode 100644
index 19a84e9..0000000
--- a/arch/arm/dts/tegra30.dtsi
+++ /dev/null
@@ -1,892 +0,0 @@
-#include <dt-bindings/clock/tegra30-car.h>
-#include <dt-bindings/gpio/tegra-gpio.h>
-#include <dt-bindings/pinctrl/pinctrl-tegra.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-#include "skeleton.dtsi"
-
-/ {
-	compatible = "nvidia,tegra30";
-	interrupt-parent = <&intc>;
-
-	aliases {
-		serial0 = &uarta;
-		serial1 = &uartb;
-		serial2 = &uartc;
-		serial3 = &uartd;
-		serial4 = &uarte;
-	};
-
-	pcie-controller@00003000 {
-		compatible = "nvidia,tegra30-pcie";
-		device_type = "pci";
-		reg = <0x00003000 0x00000800   /* PADS registers */
-		       0x00003800 0x00000200   /* AFI registers */
-		       0x10000000 0x10000000>; /* configuration space */
-		reg-names = "pads", "afi", "cs";
-		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
-			      GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
-		interrupt-names = "intr", "msi";
-
-		bus-range = <0x00 0xff>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
-			  0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
-			  0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
-			  0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
-			  0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
-			  0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
-
-		clocks = <&tegra_car TEGRA30_CLK_PCIE>,
-			 <&tegra_car TEGRA30_CLK_AFI>,
-			 <&tegra_car TEGRA30_CLK_PLL_E>,
-			 <&tegra_car TEGRA30_CLK_CML0>;
-		clock-names = "pex", "afi", "pll_e", "cml";
-		resets = <&tegra_car 70>,
-		         <&tegra_car 72>,
-		         <&tegra_car 74>;
-		reset-names = "pex", "afi", "pcie_x";
-		status = "disabled";
-
-		pci@1,0 {
-			device_type = "pci";
-			assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
-			reg = <0x000800 0 0 0 0>;
-			status = "disabled";
-
-			#address-cells = <3>;
-			#size-cells = <2>;
-			ranges;
-
-			nvidia,num-lanes = <2>;
-		};
-
-		pci@2,0 {
-			device_type = "pci";
-			assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
-			reg = <0x001000 0 0 0 0>;
-			status = "disabled";
-
-			#address-cells = <3>;
-			#size-cells = <2>;
-			ranges;
-
-			nvidia,num-lanes = <2>;
-		};
-
-		pci@3,0 {
-			device_type = "pci";
-			assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
-			reg = <0x001800 0 0 0 0>;
-			status = "disabled";
-
-			#address-cells = <3>;
-			#size-cells = <2>;
-			ranges;
-
-			nvidia,num-lanes = <2>;
-		};
-	};
-
-	host1x@50000000 {
-		compatible = "nvidia,tegra30-host1x", "simple-bus";
-		reg = <0x50000000 0x00024000>;
-		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
-			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
-		clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
-		resets = <&tegra_car 28>;
-		reset-names = "host1x";
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		ranges = <0x54000000 0x54000000 0x04000000>;
-
-		mpe@54040000 {
-			compatible = "nvidia,tegra30-mpe";
-			reg = <0x54040000 0x00040000>;
-			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car TEGRA30_CLK_MPE>;
-			resets = <&tegra_car 60>;
-			reset-names = "mpe";
-		};
-
-		vi@54080000 {
-			compatible = "nvidia,tegra30-vi";
-			reg = <0x54080000 0x00040000>;
-			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car TEGRA30_CLK_VI>;
-			resets = <&tegra_car 20>;
-			reset-names = "vi";
-		};
-
-		epp@540c0000 {
-			compatible = "nvidia,tegra30-epp";
-			reg = <0x540c0000 0x00040000>;
-			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car TEGRA30_CLK_EPP>;
-			resets = <&tegra_car 19>;
-			reset-names = "epp";
-		};
-
-		isp@54100000 {
-			compatible = "nvidia,tegra30-isp";
-			reg = <0x54100000 0x00040000>;
-			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car TEGRA30_CLK_ISP>;
-			resets = <&tegra_car 23>;
-			reset-names = "isp";
-		};
-
-		gr2d@54140000 {
-			compatible = "nvidia,tegra30-gr2d";
-			reg = <0x54140000 0x00040000>;
-			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&tegra_car 21>;
-			reset-names = "2d";
-			clocks = <&tegra_car TEGRA30_CLK_GR2D>;
-		};
-
-		gr3d@54180000 {
-			compatible = "nvidia,tegra30-gr3d";
-			reg = <0x54180000 0x00040000>;
-			clocks = <&tegra_car TEGRA30_CLK_GR3D
-				  &tegra_car TEGRA30_CLK_GR3D2>;
-			clock-names = "3d", "3d2";
-			resets = <&tegra_car 24>,
-			         <&tegra_car 98>;
-			reset-names = "3d", "3d2";
-		};
-
-		dc@54200000 {
-			compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
-			reg = <0x54200000 0x00040000>;
-			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car TEGRA30_CLK_DISP1>,
-				 <&tegra_car TEGRA30_CLK_PLL_P>;
-			clock-names = "dc", "parent";
-			resets = <&tegra_car 27>;
-			reset-names = "dc";
-
-			nvidia,head = <0>;
-
-			rgb {
-				status = "disabled";
-			};
-		};
-
-		dc@54240000 {
-			compatible = "nvidia,tegra30-dc";
-			reg = <0x54240000 0x00040000>;
-			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car TEGRA30_CLK_DISP2>,
-				 <&tegra_car TEGRA30_CLK_PLL_P>;
-			clock-names = "dc", "parent";
-			resets = <&tegra_car 26>;
-			reset-names = "dc";
-
-			nvidia,head = <1>;
-
-			rgb {
-				status = "disabled";
-			};
-		};
-
-		hdmi@54280000 {
-			compatible = "nvidia,tegra30-hdmi";
-			reg = <0x54280000 0x00040000>;
-			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car TEGRA30_CLK_HDMI>,
-				 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
-			clock-names = "hdmi", "parent";
-			resets = <&tegra_car 51>;
-			reset-names = "hdmi";
-			status = "disabled";
-		};
-
-		tvo@542c0000 {
-			compatible = "nvidia,tegra30-tvo";
-			reg = <0x542c0000 0x00040000>;
-			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car TEGRA30_CLK_TVO>;
-			status = "disabled";
-		};
-
-		dsi@54300000 {
-			compatible = "nvidia,tegra30-dsi";
-			reg = <0x54300000 0x00040000>;
-			clocks = <&tegra_car TEGRA30_CLK_DSIA>;
-			resets = <&tegra_car 48>;
-			reset-names = "dsi";
-			status = "disabled";
-		};
-	};
-
-	timer@50004600 {
-		compatible = "arm,cortex-a9-twd-timer";
-		reg = <0x50040600 0x20>;
-		interrupts = <GIC_PPI 13
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-		clocks = <&tegra_car TEGRA30_CLK_TWD>;
-	};
-
-	intc: interrupt-controller@50041000 {
-		compatible = "arm,cortex-a9-gic";
-		reg = <0x50041000 0x1000
-		       0x50040100 0x0100>;
-		interrupt-controller;
-		#interrupt-cells = <3>;
-	};
-
-	cache-controller@50043000 {
-		compatible = "arm,pl310-cache";
-		reg = <0x50043000 0x1000>;
-		arm,data-latency = <6 6 2>;
-		arm,tag-latency = <5 5 2>;
-		cache-unified;
-		cache-level = <2>;
-	};
-
-	timer@60005000 {
-		compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
-		reg = <0x60005000 0x400>;
-		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA30_CLK_TIMER>;
-	};
-
-	tegra_car: clock@60006000 {
-		compatible = "nvidia,tegra30-car";
-		reg = <0x60006000 0x1000>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
-
-	apbdma: dma@6000a000 {
-		compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
-		reg = <0x6000a000 0x1400>;
-		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
-		resets = <&tegra_car 34>;
-		reset-names = "dma";
-		#dma-cells = <1>;
-	};
-
-	ahb: ahb@6000c004 {
-		compatible = "nvidia,tegra30-ahb";
-		reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
-	};
-
-	gpio: gpio@6000d000 {
-		compatible = "nvidia,tegra30-gpio";
-		reg = <0x6000d000 0x1000>;
-		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-		#gpio-cells = <2>;
-		gpio-controller;
-		#interrupt-cells = <2>;
-		interrupt-controller;
-	};
-
-	pinmux: pinmux@70000868 {
-		compatible = "nvidia,tegra30-pinmux";
-		reg = <0x70000868 0xd4    /* Pad control registers */
-		       0x70003000 0x3e4>; /* Mux registers */
-	};
-
-	/*
-	 * There are two serial driver i.e. 8250 based simple serial
-	 * driver and APB DMA based serial driver for higher baudrate
-	 * and performace. To enable the 8250 based driver, the compatible
-	 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
-	 * the APB DMA based serial driver, the comptible is
-	 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
-	 */
-	uarta: serial@70006000 {
-		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
-		reg = <0x70006000 0x40>;
-		reg-shift = <2>;
-		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA30_CLK_UARTA>;
-		resets = <&tegra_car 6>;
-		reset-names = "serial";
-		dmas = <&apbdma 8>, <&apbdma 8>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	uartb: serial@70006040 {
-		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
-		reg = <0x70006040 0x40>;
-		reg-shift = <2>;
-		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA30_CLK_UARTB>;
-		resets = <&tegra_car 7>;
-		reset-names = "serial";
-		dmas = <&apbdma 9>, <&apbdma 9>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	uartc: serial@70006200 {
-		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
-		reg = <0x70006200 0x100>;
-		reg-shift = <2>;
-		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA30_CLK_UARTC>;
-		resets = <&tegra_car 55>;
-		reset-names = "serial";
-		dmas = <&apbdma 10>, <&apbdma 10>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	uartd: serial@70006300 {
-		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
-		reg = <0x70006300 0x100>;
-		reg-shift = <2>;
-		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA30_CLK_UARTD>;
-		resets = <&tegra_car 65>;
-		reset-names = "serial";
-		dmas = <&apbdma 19>, <&apbdma 19>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	uarte: serial@70006400 {
-		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
-		reg = <0x70006400 0x100>;
-		reg-shift = <2>;
-		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA30_CLK_UARTE>;
-		resets = <&tegra_car 66>;
-		reset-names = "serial";
-		dmas = <&apbdma 20>, <&apbdma 20>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	pwm: pwm@7000a000 {
-		compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
-		reg = <0x7000a000 0x100>;
-		#pwm-cells = <2>;
-		clocks = <&tegra_car TEGRA30_CLK_PWM>;
-		resets = <&tegra_car 17>;
-		reset-names = "pwm";
-		status = "disabled";
-	};
-
-	rtc@7000e000 {
-		compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
-		reg = <0x7000e000 0x100>;
-		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA30_CLK_RTC>;
-	};
-
-	i2c@7000c000 {
-		compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
-		reg = <0x7000c000 0x100>;
-		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA30_CLK_I2C1>,
-			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
-		clock-names = "div-clk", "fast-clk";
-		resets = <&tegra_car 12>;
-		reset-names = "i2c";
-		dmas = <&apbdma 21>, <&apbdma 21>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	i2c@7000c400 {
-		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
-		reg = <0x7000c400 0x100>;
-		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA30_CLK_I2C2>,
-			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
-		clock-names = "div-clk", "fast-clk";
-		resets = <&tegra_car 54>;
-		reset-names = "i2c";
-		dmas = <&apbdma 22>, <&apbdma 22>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	i2c@7000c500 {
-		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
-		reg = <0x7000c500 0x100>;
-		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA30_CLK_I2C3>,
-			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
-		clock-names = "div-clk", "fast-clk";
-		resets = <&tegra_car 67>;
-		reset-names = "i2c";
-		dmas = <&apbdma 23>, <&apbdma 23>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	i2c@7000c700 {
-		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
-		reg = <0x7000c700 0x100>;
-		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA30_CLK_I2C4>,
-			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
-		resets = <&tegra_car 103>;
-		reset-names = "i2c";
-		clock-names = "div-clk", "fast-clk";
-		dmas = <&apbdma 26>, <&apbdma 26>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	i2c@7000d000 {
-		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
-		reg = <0x7000d000 0x100>;
-		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA30_CLK_I2C5>,
-			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
-		clock-names = "div-clk", "fast-clk";
-		resets = <&tegra_car 47>;
-		reset-names = "i2c";
-		dmas = <&apbdma 24>, <&apbdma 24>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	spi@7000d400 {
-		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
-		reg = <0x7000d400 0x200>;
-		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA30_CLK_SBC1>;
-		resets = <&tegra_car 41>;
-		reset-names = "spi";
-		dmas = <&apbdma 15>, <&apbdma 15>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	spi@7000d600 {
-		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
-		reg = <0x7000d600 0x200>;
-		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA30_CLK_SBC2>;
-		resets = <&tegra_car 44>;
-		reset-names = "spi";
-		dmas = <&apbdma 16>, <&apbdma 16>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	spi@7000d800 {
-		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
-		reg = <0x7000d800 0x200>;
-		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA30_CLK_SBC3>;
-		resets = <&tegra_car 46>;
-		reset-names = "spi";
-		dmas = <&apbdma 17>, <&apbdma 17>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	spi@7000da00 {
-		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
-		reg = <0x7000da00 0x200>;
-		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA30_CLK_SBC4>;
-		resets = <&tegra_car 68>;
-		reset-names = "spi";
-		dmas = <&apbdma 18>, <&apbdma 18>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	spi@7000dc00 {
-		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
-		reg = <0x7000dc00 0x200>;
-		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA30_CLK_SBC5>;
-		resets = <&tegra_car 104>;
-		reset-names = "spi";
-		dmas = <&apbdma 27>, <&apbdma 27>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	spi@7000de00 {
-		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
-		reg = <0x7000de00 0x200>;
-		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA30_CLK_SBC6>;
-		resets = <&tegra_car 106>;
-		reset-names = "spi";
-		dmas = <&apbdma 28>, <&apbdma 28>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	kbc@7000e200 {
-		compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
-		reg = <0x7000e200 0x100>;
-		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA30_CLK_KBC>;
-		resets = <&tegra_car 36>;
-		reset-names = "kbc";
-		status = "disabled";
-	};
-
-	pmc@7000e400 {
-		compatible = "nvidia,tegra30-pmc";
-		reg = <0x7000e400 0x400>;
-		clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
-		clock-names = "pclk", "clk32k_in";
-	};
-
-	memory-controller@7000f000 {
-		compatible = "nvidia,tegra30-mc";
-		reg = <0x7000f000 0x010
-		       0x7000f03c 0x1b4
-		       0x7000f200 0x028
-		       0x7000f284 0x17c>;
-		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	iommu@7000f010 {
-		compatible = "nvidia,tegra30-smmu";
-		reg = <0x7000f010 0x02c
-		       0x7000f1f0 0x010
-		       0x7000f228 0x05c>;
-		nvidia,#asids = <4>;		/* # of ASIDs */
-		dma-window = <0 0x40000000>;	/* IOVA start & length */
-		nvidia,ahb = <&ahb>;
-	};
-
-	ahub@70080000 {
-		compatible = "nvidia,tegra30-ahub";
-		reg = <0x70080000 0x200
-		       0x70080200 0x100>;
-		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
-			 <&tegra_car TEGRA30_CLK_APBIF>;
-		clock-names = "d_audio", "apbif";
-		resets = <&tegra_car 106>, /* d_audio */
-			 <&tegra_car 107>, /* apbif */
-			 <&tegra_car 30>,  /* i2s0 */
-			 <&tegra_car 11>,  /* i2s1 */
-			 <&tegra_car 18>,  /* i2s2 */
-			 <&tegra_car 101>, /* i2s3 */
-			 <&tegra_car 102>, /* i2s4 */
-			 <&tegra_car 108>, /* dam0 */
-			 <&tegra_car 109>, /* dam1 */
-			 <&tegra_car 110>, /* dam2 */
-			 <&tegra_car 10>;  /* spdif */
-		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
-			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
-			      "spdif";
-		dmas = <&apbdma 1>, <&apbdma 1>,
-		       <&apbdma 2>, <&apbdma 2>,
-		       <&apbdma 3>, <&apbdma 3>,
-		       <&apbdma 4>, <&apbdma 4>;
-		dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
-			    "rx3", "tx3";
-		ranges;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		tegra_i2s0: i2s@70080300 {
-			compatible = "nvidia,tegra30-i2s";
-			reg = <0x70080300 0x100>;
-			nvidia,ahub-cif-ids = <4 4>;
-			clocks = <&tegra_car TEGRA30_CLK_I2S0>;
-			resets = <&tegra_car 30>;
-			reset-names = "i2s";
-			status = "disabled";
-		};
-
-		tegra_i2s1: i2s@70080400 {
-			compatible = "nvidia,tegra30-i2s";
-			reg = <0x70080400 0x100>;
-			nvidia,ahub-cif-ids = <5 5>;
-			clocks = <&tegra_car TEGRA30_CLK_I2S1>;
-			resets = <&tegra_car 11>;
-			reset-names = "i2s";
-			status = "disabled";
-		};
-
-		tegra_i2s2: i2s@70080500 {
-			compatible = "nvidia,tegra30-i2s";
-			reg = <0x70080500 0x100>;
-			nvidia,ahub-cif-ids = <6 6>;
-			clocks = <&tegra_car TEGRA30_CLK_I2S2>;
-			resets = <&tegra_car 18>;
-			reset-names = "i2s";
-			status = "disabled";
-		};
-
-		tegra_i2s3: i2s@70080600 {
-			compatible = "nvidia,tegra30-i2s";
-			reg = <0x70080600 0x100>;
-			nvidia,ahub-cif-ids = <7 7>;
-			clocks = <&tegra_car TEGRA30_CLK_I2S3>;
-			resets = <&tegra_car 101>;
-			reset-names = "i2s";
-			status = "disabled";
-		};
-
-		tegra_i2s4: i2s@70080700 {
-			compatible = "nvidia,tegra30-i2s";
-			reg = <0x70080700 0x100>;
-			nvidia,ahub-cif-ids = <8 8>;
-			clocks = <&tegra_car TEGRA30_CLK_I2S4>;
-			resets = <&tegra_car 102>;
-			reset-names = "i2s";
-			status = "disabled";
-		};
-	};
-
-	sdhci@78000000 {
-		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
-		reg = <0x78000000 0x200>;
-		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
-		resets = <&tegra_car 14>;
-		reset-names = "sdhci";
-		status = "disabled";
-	};
-
-	sdhci@78000200 {
-		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
-		reg = <0x78000200 0x200>;
-		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
-		resets = <&tegra_car 9>;
-		reset-names = "sdhci";
-		status = "disabled";
-	};
-
-	sdhci@78000400 {
-		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
-		reg = <0x78000400 0x200>;
-		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
-		resets = <&tegra_car 69>;
-		reset-names = "sdhci";
-		status = "disabled";
-	};
-
-	sdhci@78000600 {
-		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
-		reg = <0x78000600 0x200>;
-		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
-		resets = <&tegra_car 15>;
-		reset-names = "sdhci";
-		status = "disabled";
-	};
-
-	usb@7d000000 {
-		compatible = "nvidia,tegra30-ehci", "usb-ehci";
-		reg = <0x7d000000 0x4000>;
-		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-		phy_type = "utmi";
-		clocks = <&tegra_car TEGRA30_CLK_USBD>;
-		resets = <&tegra_car 22>;
-		reset-names = "usb";
-		nvidia,needs-double-reset;
-		nvidia,phy = <&phy1>;
-		status = "disabled";
-	};
-
-	phy1: usb-phy@7d000000 {
-		compatible = "nvidia,tegra30-usb-phy";
-		reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
-		phy_type = "utmi";
-		clocks = <&tegra_car TEGRA30_CLK_USBD>,
-			 <&tegra_car TEGRA30_CLK_PLL_U>,
-			 <&tegra_car TEGRA30_CLK_USBD>;
-		clock-names = "reg", "pll_u", "utmi-pads";
-		nvidia,hssync-start-delay = <9>;
-		nvidia,idle-wait-delay = <17>;
-		nvidia,elastic-limit = <16>;
-		nvidia,term-range-adj = <6>;
-		nvidia,xcvr-setup = <51>;
-		nvidia.xcvr-setup-use-fuses;
-		nvidia,xcvr-lsfslew = <1>;
-		nvidia,xcvr-lsrslew = <1>;
-		nvidia,xcvr-hsslew = <32>;
-		nvidia,hssquelch-level = <2>;
-		nvidia,hsdiscon-level = <5>;
-		status = "disabled";
-	};
-
-	usb@7d004000 {
-		compatible = "nvidia,tegra30-ehci", "usb-ehci";
-		reg = <0x7d004000 0x4000>;
-		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-		phy_type = "utmi";
-		clocks = <&tegra_car TEGRA30_CLK_USB2>;
-		resets = <&tegra_car 58>;
-		reset-names = "usb";
-		nvidia,phy = <&phy2>;
-		status = "disabled";
-	};
-
-	phy2: usb-phy@7d004000 {
-		compatible = "nvidia,tegra30-usb-phy";
-		reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
-		phy_type = "utmi";
-		clocks = <&tegra_car TEGRA30_CLK_USB2>,
-			 <&tegra_car TEGRA30_CLK_PLL_U>,
-			 <&tegra_car TEGRA30_CLK_USBD>;
-		clock-names = "reg", "pll_u", "utmi-pads";
-		nvidia,hssync-start-delay = <9>;
-		nvidia,idle-wait-delay = <17>;
-		nvidia,elastic-limit = <16>;
-		nvidia,term-range-adj = <6>;
-		nvidia,xcvr-setup = <51>;
-		nvidia.xcvr-setup-use-fuses;
-		nvidia,xcvr-lsfslew = <2>;
-		nvidia,xcvr-lsrslew = <2>;
-		nvidia,xcvr-hsslew = <32>;
-		nvidia,hssquelch-level = <2>;
-		nvidia,hsdiscon-level = <5>;
-		status = "disabled";
-	};
-
-	usb@7d008000 {
-		compatible = "nvidia,tegra30-ehci", "usb-ehci";
-		reg = <0x7d008000 0x4000>;
-		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-		phy_type = "utmi";
-		clocks = <&tegra_car TEGRA30_CLK_USB3>;
-		resets = <&tegra_car 59>;
-		reset-names = "usb";
-		nvidia,phy = <&phy3>;
-		status = "disabled";
-	};
-
-	phy3: usb-phy@7d008000 {
-		compatible = "nvidia,tegra30-usb-phy";
-		reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
-		phy_type = "utmi";
-		clocks = <&tegra_car TEGRA30_CLK_USB3>,
-			 <&tegra_car TEGRA30_CLK_PLL_U>,
-			 <&tegra_car TEGRA30_CLK_USBD>;
-		clock-names = "reg", "pll_u", "utmi-pads";
-		nvidia,hssync-start-delay = <0>;
-		nvidia,idle-wait-delay = <17>;
-		nvidia,elastic-limit = <16>;
-		nvidia,term-range-adj = <6>;
-		nvidia,xcvr-setup = <51>;
-		nvidia.xcvr-setup-use-fuses;
-		nvidia,xcvr-lsfslew = <2>;
-		nvidia,xcvr-lsrslew = <2>;
-		nvidia,xcvr-hsslew = <32>;
-		nvidia,hssquelch-level = <2>;
-		nvidia,hsdiscon-level = <5>;
-		status = "disabled";
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a9";
-			reg = <0>;
-		};
-
-		cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a9";
-			reg = <1>;
-		};
-
-		cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a9";
-			reg = <2>;
-		};
-
-		cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a9";
-			reg = <3>;
-		};
-	};
-
-	pmu {
-		compatible = "arm,cortex-a9-pmu";
-		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
-	};
-};
-- 
1.9.3


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[PATCH 05/12] tegra: beaver: add stdout-path

[Lucas Stach]

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/dts/tegra30-beaver.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts
index d2809bb..5879353 100644
--- a/arch/arm/dts/tegra30-beaver.dts
+++ b/arch/arm/dts/tegra30-beaver.dts
@@ -12,6 +12,8 @@
 	};
 
 	chosen {
+		stdout-path = &uarta;
+
 		environment@0 {
 			compatible = "barebox,environment";
 			device-path = &emmc, "partname:boot1";
-- 
1.9.3


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[PATCH 06/12] tegra: colibri-t20: add stdout-path

[Lucas Stach]

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/dts/tegra20-colibri-iris.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/tegra20-colibri-iris.dts b/arch/arm/dts/tegra20-colibri-iris.dts
index adfa917..9c61581 100644
--- a/arch/arm/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/dts/tegra20-colibri-iris.dts
@@ -6,6 +6,10 @@
 	model = "Toradex Colibri T20 on Iris";
 	compatible = "toradex,iris", "toradex,colibri_t20", "nvidia,tegra20";
 
+	chosen {
+		stdout-path = &uarta;
+	};
+
 	host1x@50000000 {
 		hdmi@54280000 {
 			status = "okay";
-- 
1.9.3


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[PATCH 07/12] tegra: tegra124: add serial alias nodes

[Lucas Stach]

They are missing in the upstream DT. Add them
locally for now.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/dts/tegra124.dtsi | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi
index 7d0fafa..c795811 100644
--- a/arch/arm/dts/tegra124.dtsi
+++ b/arch/arm/dts/tegra124.dtsi
@@ -1 +1,8 @@
-#include <arm/tegra124.dtsi>
+/ {
+	aliases {
+		serial0 = "/serial@0,70006000/";
+		serial1 = "/serial@0,70006040/";
+		serial2 = "/serial@0,70006200/";
+		serial3 = "/serial@0,70006300/";
+	};
+};
-- 
1.9.3


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[PATCH 08/12] tegra: jetson-tk1: add stdout-path

[Lucas Stach]

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/dts/tegra124-jetson-tk1.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts
index d2933bd..26f405c 100644
--- a/arch/arm/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/dts/tegra124-jetson-tk1.dts
@@ -1,7 +1,10 @@
 #include <arm/tegra124-jetson-tk1.dts>
+#include "tegra124.dtsi"
 
 / {
 	chosen {
+		stdout-path = "/serial@0,70006300/";
+
 		environment@0 {
 			compatible = "barebox,environment";
 			device-path = &emmc, "partname:boot1";
-- 
1.9.3


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[PATCH 09/12] serial: ns16550: enable clock if available

[Lucas Stach]

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 drivers/serial/serial_ns16550.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 53d48a0..07dedf7 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -418,6 +418,7 @@ static int ns16550_probe(struct device_d *dev)
 			ret = PTR_ERR(priv->clk);
 			goto err;
 		}
+		clk_enable(priv->clk);
 		priv->plat.clock = clk_get_rate(priv->clk);
 	}
 
-- 
1.9.3


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[PATCH 10/12] serial: ns16550: add Tegra support

[Lucas Stach]

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 drivers/serial/serial_ns16550.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 07dedf7..8f2e93f 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -311,6 +311,11 @@ static __maybe_unused struct ns16550_drvdata jz_drvdata = {
 	.init_port = ns16550_jz_init_port,
 };
 
+static __maybe_unused struct ns16550_drvdata tegra_drvdata = {
+	.init_port = ns16550_serial_init_port,
+	.linux_console_name = "ttyS",
+};
+
 static int ns16550_init_iomem(struct device_d *dev, struct ns16550_priv *priv)
 {
 	struct resource *res;
@@ -477,6 +482,12 @@ static struct of_device_id ns16550_serial_dt_ids[] = {
 		.data = (unsigned long)&omap_drvdata,
 	},
 #endif
+#if IS_ENABLED(CONFIG_ARCH_TEGRA)
+	{
+		.compatible = "nvidia,tegra20-uart",
+		.data = (unsigned long)&tegra_drvdata,
+	},
+#endif
 #if IS_ENABLED(CONFIG_MACH_MIPS_XBURST)
 	{
 		.compatible = "ingenic,jz4740-uart",
-- 
1.9.3


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[PATCH 11/12] tegra: remove custom UART setup

[Lucas Stach]

The config option doesn't make any sense anymore
when building a multiimage barebox. With a proper
DT built into the image we don't need the ODMdata
mechanism to find the debug UART anymore.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/Kconfig                 | 33 ---------------------
 arch/arm/mach-tegra/include/mach/lowlevel.h | 45 -----------------------------
 arch/arm/mach-tegra/tegra20.c               | 41 --------------------------
 3 files changed, 119 deletions(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 1bdea8e..160732f 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -7,39 +7,6 @@ config ARCH_TEXT_BASE
 config BOARDINFO
 	default ""
 
-choice
-	prompt "Tegra debug UART"
-	help
-	  This is the first serial console that gets activated by barebox.
-	  Normally each board vendor should program a valid debug UART into
-	  the ODMdata section of the boot configuration table, so it's a
-	  reasonably good bet to use that.
-	  If you know your ODMdata is broken, or you don't wish to activate
-	  any serial console at all you can override the default here.
-
-config TEGRA_UART_ODMDATA
-	bool "ODMdata defined UART"
-
-config TEGRA_UART_A
-	bool "UART A"
-
-config TEGRA_UART_B
-	bool "UART B"
-
-config TEGRA_UART_C
-	bool "UART C"
-
-config TEGRA_UART_D
-	bool "UART D"
-
-config TEGRA_UART_E
-	bool "UART E"
-
-config TEGRA_UART_NONE
-	bool "None"
-
-endchoice
-
 # ---------------------------------------------------------
 
 config ARCH_TEGRA_2x_SOC
diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h
index c65be0b..3e7e41b 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -176,37 +176,6 @@ uint32_t tegra30_get_ramsize(void)
 	}
 }
 
-static long uart_id_to_base[] = {
-	TEGRA_UARTA_BASE,
-	TEGRA_UARTB_BASE,
-	TEGRA_UARTC_BASE,
-	TEGRA_UARTD_BASE,
-	TEGRA_UARTE_BASE,
-};
-
-static __always_inline
-long tegra20_get_debuguart_base(void)
-{
-	u32 odmdata;
-	int id;
-
-	odmdata = tegra_get_odmdata();
-
-	/*
-	 * Get type, we accept both "2" and "3", as they both demark a UART,
-	 * depending on the board type.
-	 */
-	if (!(((odmdata & T20_ODMDATA_UARTTYPE_MASK) >>
-	      T20_ODMDATA_UARTTYPE_SHIFT) & 0x2))
-		return 0;
-
-	id = (odmdata & T20_ODMDATA_UARTID_MASK) >> T20_ODMDATA_UARTID_SHIFT;
-	if (id > ARRAY_SIZE(uart_id_to_base))
-		return 0;
-
-	return uart_id_to_base[id];
-}
-
 #define CRC_OSC_CTRL			0x050
 #define CRC_OSC_CTRL_OSC_FREQ_SHIFT	30
 #define CRC_OSC_CTRL_OSC_FREQ_MASK	(0x3 << CRC_OSC_CTRL_OSC_FREQ_SHIFT)
@@ -231,20 +200,6 @@ int tegra_get_osc_clock(void)
 	}
 }
 
-static __always_inline
-int tegra_get_pllp_rate(void)
-{
-	switch (tegra_get_chiptype()) {
-	case TEGRA20:
-		return 216000000;
-	case TEGRA30:
-	case TEGRA124:
-		return 408000000;
-	default:
-		return 0;
-	}
-}
-
 #define TIMER_CNTR_1US	0x00
 #define TIMER_USEC_CFG	0x04
 
diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
index dcc55ae..8d1cd5b 100644
--- a/arch/arm/mach-tegra/tegra20.c
+++ b/arch/arm/mach-tegra/tegra20.c
@@ -22,47 +22,6 @@
 #include <mach/lowlevel.h>
 #include <mach/tegra114-sysctr.h>
 
-static struct NS16550_plat debug_uart = {
-	.shift = 2,
-};
-
-static int tegra_add_debug_console(void)
-{
-	unsigned long base = 0;
-
-	if (!of_machine_is_compatible("nvidia,tegra20") &&
-	    !of_machine_is_compatible("nvidia,tegra30") &&
-	    !of_machine_is_compatible("nvidia,tegra124"))
-		return 0;
-
-	/* figure out which UART to use */
-	if (IS_ENABLED(CONFIG_TEGRA_UART_NONE))
-		return 0;
-	if (IS_ENABLED(CONFIG_TEGRA_UART_ODMDATA))
-		base = tegra20_get_debuguart_base();
-	if (IS_ENABLED(CONFIG_TEGRA_UART_A))
-		base = TEGRA_UARTA_BASE;
-	if (IS_ENABLED(CONFIG_TEGRA_UART_B))
-		base = TEGRA_UARTB_BASE;
-	if (IS_ENABLED(CONFIG_TEGRA_UART_C))
-		base = TEGRA_UARTC_BASE;
-	if (IS_ENABLED(CONFIG_TEGRA_UART_D))
-		base = TEGRA_UARTD_BASE;
-	if (IS_ENABLED(CONFIG_TEGRA_UART_E))
-		base = TEGRA_UARTE_BASE;
-
-	if (!base)
-		return -ENODEV;
-
-	debug_uart.clock = tegra_get_pllp_rate();
-
-	add_ns16550_device(DEVICE_ID_DYNAMIC, base, 8 << debug_uart.shift,
-			   IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &debug_uart);
-
-	return 0;
-}
-console_initcall(tegra_add_debug_console);
-
 static int tegra20_mem_init(void)
 {
 	if (!of_machine_is_compatible("nvidia,tegra20"))
-- 
1.9.3


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[PATCH 12/12] clk: tegra: don't enable UART clocks by default

[Lucas Stach]

Now that we are registering a proper driver for the
UARTs we no longer need to enable the clocks unconditionally.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 drivers/clk/tegra/clk-tegra124.c |  8 ++++----
 drivers/clk/tegra/clk-tegra20.c  | 10 +++++-----
 drivers/clk/tegra/clk-tegra30.c  | 10 +++++-----
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index d597a23..7a2f7c0 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -322,10 +322,10 @@ static struct tegra_clk_init_table init_table[] = {
 	{TEGRA124_CLK_PLL_P_OUT3,	TEGRA124_CLK_CLK_MAX,	102000000,	1},
 	{TEGRA124_CLK_PLL_P_OUT4,	TEGRA124_CLK_CLK_MAX,	204000000,	1},
 	{TEGRA124_CLK_MSELECT,		TEGRA124_CLK_PLL_P,	102000000,	1},
-	{TEGRA124_CLK_UARTA,		TEGRA124_CLK_PLL_P,	0,		1},
-	{TEGRA124_CLK_UARTB,		TEGRA124_CLK_PLL_P,	0,		1},
-	{TEGRA124_CLK_UARTC,		TEGRA124_CLK_PLL_P,	0,		1},
-	{TEGRA124_CLK_UARTD,		TEGRA124_CLK_PLL_P,	0,		1},
+	{TEGRA124_CLK_UARTA,		TEGRA124_CLK_PLL_P,	0,		0},
+	{TEGRA124_CLK_UARTB,		TEGRA124_CLK_PLL_P,	0,		0},
+	{TEGRA124_CLK_UARTC,		TEGRA124_CLK_PLL_P,	0,		0},
+	{TEGRA124_CLK_UARTD,		TEGRA124_CLK_PLL_P,	0,		0},
 	{TEGRA124_CLK_SDMMC1,		TEGRA124_CLK_PLL_P,	48000000,	0},
 	{TEGRA124_CLK_SDMMC2,		TEGRA124_CLK_PLL_P,	48000000,	0},
 	{TEGRA124_CLK_SDMMC3,		TEGRA124_CLK_PLL_P,	48000000,	0},
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 5b4365d..2ff42d8 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -324,11 +324,11 @@ static struct tegra_clk_init_table init_table[] = {
 	{TEGRA20_CLK_PLL_P_OUT4,	TEGRA20_CLK_CLK_MAX,	24000000,	1},
 	{TEGRA20_CLK_PLL_C,		TEGRA20_CLK_CLK_MAX,	600000000,	1},
 	{TEGRA20_CLK_PLL_C_OUT1,	TEGRA20_CLK_CLK_MAX,	120000000,	1},
-	{TEGRA20_CLK_UARTA,		TEGRA20_CLK_PLL_P,	0,		1},
-	{TEGRA20_CLK_UARTB,		TEGRA20_CLK_PLL_P,	0,		1},
-	{TEGRA20_CLK_UARTC,		TEGRA20_CLK_PLL_P,	0,		1},
-	{TEGRA20_CLK_UARTD,		TEGRA20_CLK_PLL_P,	0,		1},
-	{TEGRA20_CLK_UARTE,		TEGRA20_CLK_PLL_P,	0,		1},
+	{TEGRA20_CLK_UARTA,		TEGRA20_CLK_PLL_P,	0,		0},
+	{TEGRA20_CLK_UARTB,		TEGRA20_CLK_PLL_P,	0,		0},
+	{TEGRA20_CLK_UARTC,		TEGRA20_CLK_PLL_P,	0,		0},
+	{TEGRA20_CLK_UARTD,		TEGRA20_CLK_PLL_P,	0,		0},
+	{TEGRA20_CLK_UARTE,		TEGRA20_CLK_PLL_P,	0,		0},
 	{TEGRA20_CLK_SDMMC1,		TEGRA20_CLK_PLL_P,	48000000,	0},
 	{TEGRA20_CLK_SDMMC2,		TEGRA20_CLK_PLL_P,	48000000,	0},
 	{TEGRA20_CLK_SDMMC3,		TEGRA20_CLK_PLL_P,	48000000,	0},
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 7210053..46fd6dd 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -352,11 +352,11 @@ static struct tegra_clk_init_table init_table[] = {
 	{TEGRA30_CLK_PLL_P_OUT3,	TEGRA30_CLK_CLK_MAX,	102000000,	1},
 	{TEGRA30_CLK_PLL_P_OUT4,	TEGRA30_CLK_CLK_MAX,	204000000,	1},
 	{TEGRA30_CLK_MSELECT,		TEGRA30_CLK_PLL_P,	102000000,	1},
-	{TEGRA30_CLK_UARTA,		TEGRA30_CLK_PLL_P,	0,		1},
-	{TEGRA30_CLK_UARTB,		TEGRA30_CLK_PLL_P,	0,		1},
-	{TEGRA30_CLK_UARTC,		TEGRA30_CLK_PLL_P,	0,		1},
-	{TEGRA30_CLK_UARTD,		TEGRA30_CLK_PLL_P,	0,		1},
-	{TEGRA30_CLK_UARTE,		TEGRA30_CLK_PLL_P,	0,		1},
+	{TEGRA30_CLK_UARTA,		TEGRA30_CLK_PLL_P,	0,		0},
+	{TEGRA30_CLK_UARTB,		TEGRA30_CLK_PLL_P,	0,		0},
+	{TEGRA30_CLK_UARTC,		TEGRA30_CLK_PLL_P,	0,		0},
+	{TEGRA30_CLK_UARTD,		TEGRA30_CLK_PLL_P,	0,		0},
+	{TEGRA30_CLK_UARTE,		TEGRA30_CLK_PLL_P,	0,		0},
 	{TEGRA30_CLK_SDMMC1,		TEGRA30_CLK_PLL_P,	48000000,	0},
 	{TEGRA30_CLK_SDMMC2,		TEGRA30_CLK_PLL_P,	48000000,	0},
 	{TEGRA30_CLK_SDMMC3,		TEGRA30_CLK_PLL_P,	48000000,	0},
-- 
1.9.3


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Re: [PATCH 01/12] tegra: beaver: set hostname in board init

[Sascha Hauer]

On Mon, Nov 03, 2014 at 11:52:13PM +0100, Lucas Stach wrote:
> Signed-off-by: Lucas Stach <dev@lynxeye.de>

Applied all, thanks

Sascha

> ---
>  arch/arm/boards/nvidia-beaver/board.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boards/nvidia-beaver/board.c b/arch/arm/boards/nvidia-beaver/board.c
> index 20707d8..d270301 100644
> --- a/arch/arm/boards/nvidia-beaver/board.c
> +++ b/arch/arm/boards/nvidia-beaver/board.c
> @@ -20,7 +20,7 @@
>  #include <i2c/i2c.h>
>  #include <init.h>
>  
> -static int nvidia_beaver_devices_init(void)
> +static int nvidia_beaver_fs_init(void)
>  {
>  	struct i2c_client client;
>  	u8 data;
> @@ -44,4 +44,15 @@ static int nvidia_beaver_devices_init(void)
>  
>  	return 0;
>  }
> -fs_initcall(nvidia_beaver_devices_init);
> +fs_initcall(nvidia_beaver_fs_init);
> +
> +static int nvidia_beaver_device_init(void)
> +{
> +	if (!of_machine_is_compatible("nvidia,beaver"))
> +		return 0;
> +
> +	barebox_set_hostname("beaver");
> +
> +	return 0;
> +}
> +device_initcall(nvidia_beaver_device_init);
> -- 
> 1.9.3
> 
> 
> _______________________________________________
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> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

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