From: Lucas Stach <dev@lynxeye.de>
To: barebox@lists.infradead.org
Subject: [PATCH 2/3] pci: align bridge windows
Date: Wed, 12 Nov 2014 21:24:36 +0100 [thread overview]
Message-ID: <1415823877-7379-2-git-send-email-dev@lynxeye.de> (raw)
In-Reply-To: <1415823877-7379-1-git-send-email-dev@lynxeye.de>
The bridge filtering logic needs a minimum
alignment of 1MB for mem and 4KB for io resources.
Take this into account while assigning resources
to devices in oredr to not produce overlapping
windows between different bridges.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
drivers/pci/pci.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 87c2fca..7f8ebcf 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1,4 +1,5 @@
#include <common.h>
+#include <sizes.h>
#include <linux/pci.h>
#ifdef DEBUG
@@ -259,14 +260,17 @@ static void postscan_setup_bridge(struct pci_dev *dev)
pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, bus_index - 1);
if (last_mem)
+ last_mem = ALIGN(last_mem, SZ_1M);
pci_write_config_word(dev, PCI_MEMORY_LIMIT,
((last_mem - 1) & 0xfff00000) >> 16);
if (last_mem_pref)
+ last_mem_pref = ALIGN(last_mem_pref, SZ_1M);
pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT,
((last_mem_pref - 1) & 0xfff00000) >> 16);
if (last_io) {
+ last_io = ALIGN(last_io, SZ_4K);
pci_write_config_byte(dev, PCI_IO_LIMIT,
((last_io - 1) & 0x0000f000) >> 8);
pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
--
1.9.3
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next prev parent reply other threads:[~2014-11-12 20:18 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-12 20:24 [PATCH 1/3] pci: correct BAR size calculation Lucas Stach
2014-11-12 20:24 ` Lucas Stach [this message]
2014-11-12 20:24 ` [PATCH 3/3] pci: tegra: relax link-up timeout Lucas Stach
2014-11-17 7:36 ` [PATCH 1/3] pci: correct BAR size calculation Sascha Hauer
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