[PATCH v2 04/18] CLK: clk-mux: Respect CLK_MUX_HIWORD_MASK flag

[Andrey Panov <rockford@yandex.ru>]

It is required for Rockchip SoCs where clock settings registers have
write-enable mask in high word.

Signed-off-by: Andrey Panov <rockford@yandex.ru>
---
 drivers/clk/clk-mux.c | 3 +++
 include/linux/clk.h   | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 4ce86f4..22e131f 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -45,6 +45,9 @@ static int clk_mux_set_parent(struct clk *clk, u8 idx)
 	val = readl(m->reg);
 	val &= ~(((1 << m->width) - 1) << m->shift);
 	val |= idx << m->shift;
+
+	if (clk->flags & CLK_MUX_HIWORD_MASK)
+		val |= ((1 << m->width) - 1) << (m->shift + 16);
 	writel(val, m->reg);
 
 	return 0;
diff --git a/include/linux/clk.h b/include/linux/clk.h
index de2d4a5..89cb44e 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -248,6 +248,8 @@ struct clk_divider {
 	int table_size;
 };
 
+#define CLK_MUX_HIWORD_MASK		(1 << 2)
+
 extern struct clk_ops clk_divider_ops;
 
 struct clk *clk_divider(const char *name, const char *parent,
-- 
2.1.4


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