* [PATCH v2 01/14] net: phy: Support Marvell 88E1318S PHY
2015-04-20 20:11 [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sebastian Hesselbarth
@ 2015-04-20 20:11 ` Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 02/14] gpio: Add driver for 74x164 compatible shift-registers Sebastian Hesselbarth
` (13 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Sebastian Hesselbarth @ 2015-04-20 20:11 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: Thomas Petazzoni, barebox
This adds support for the Marvell 88E1318S Gigabit Ethernet PHY.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/net/phy/marvell.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index aaf9f53451f4..6409f14ae2e2 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -35,6 +35,9 @@
#define MII_88E1121_PHY_MSCR_DELAY_MASK \
(MII_88E1121_PHY_MSCR_RX_DELAY | MII_88E1121_PHY_MSCR_TX_DELAY)
+#define MII_88E1318S_PHY_MSCR1_REG 16
+#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
+
#define MII_88E1540_LED_PAGE 0x3
#define MII_88E1540_LED_CONTROL 0x10
@@ -214,6 +217,25 @@ static int m88e1121_config_init(struct phy_device *phydev)
return 0;
}
+static int m88e1318s_config_init(struct phy_device *phydev)
+{
+ u16 reg;
+ int ret;
+
+ ret = phy_write(phydev, MII_MARVELL_PHY_PAGE,
+ MII_88E1121_PHY_MSCR_PAGE);
+ if (ret < 0)
+ return ret;
+
+ reg = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
+ reg |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
+ ret = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, reg);
+ if (ret < 0)
+ return ret;
+
+ return m88e1121_config_init(phydev);
+}
+
static struct phy_driver marvell_phys[] = {
{
.phy_id = MARVELL_PHY_ID_88E1121R,
@@ -225,6 +247,15 @@ static struct phy_driver marvell_phys[] = {
.read_status = marvell_read_status,
},
{
+ .phy_id = MARVELL_PHY_ID_88E1318S,
+ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .drv.name = "Marvell 88E1318S",
+ .features = PHY_GBIT_FEATURES,
+ .config_init = m88e1318s_config_init,
+ .config_aneg = genphy_config_aneg,
+ .read_status = marvell_read_status,
+ },
+ {
.phy_id = MARVELL_PHY_ID_88E1543,
.phy_id_mask = MARVELL_PHY_ID_MASK,
.drv.name = "Marvell 88E1543",
--
2.1.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v2 02/14] gpio: Add driver for 74x164 compatible shift-registers
2015-04-20 20:11 [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 01/14] net: phy: Support Marvell 88E1318S PHY Sebastian Hesselbarth
@ 2015-04-20 20:11 ` Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 03/14] spi: ath79: move spidelay from spi-bitbang-txrx Sebastian Hesselbarth
` (12 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Sebastian Hesselbarth @ 2015-04-20 20:11 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: Thomas Petazzoni, barebox
A 74x164 shift register can be seen as a SPI attached GPIO expander.
This adds a driver for those poor-man expanders based on the Linux
driver.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/gpio/Kconfig | 8 +++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-74164.c | 131 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 140 insertions(+)
create mode 100644 drivers/gpio/gpio-74164.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c8b1efb1f23a..9cb22613dd91 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -13,6 +13,14 @@ config GPIO_DIGIC
bool "GPIO support for Canon DIGIC"
depends on ARCH_DIGIC
+config GPIO_74164
+ bool "Generic SPI attached shift register"
+ depends on SPI
+ help
+ Driver for 74x164 compatible serial-in/parallel-out 8-outputs
+ shift registers. This driver can be used to provide access
+ to more gpio outputs.
+
config GPIO_BCM2835
bool "GPIO support for BCM2835"
depends on ARCH_BCM2835
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 508e228bac2c..1d946614e3a6 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_GPIOLIB) += gpiolib.o
+obj-$(CONFIG_GPIO_74164) += gpio-74164.o
obj-$(CONFIG_GPIO_BCM2835) += gpio-bcm2835.o
obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o
obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o
diff --git a/drivers/gpio/gpio-74164.c b/drivers/gpio/gpio-74164.c
new file mode 100644
index 000000000000..926207aaf7f2
--- /dev/null
+++ b/drivers/gpio/gpio-74164.c
@@ -0,0 +1,131 @@
+/*
+ * Generic serial-in/parallel-out 8-bits shift register GPIO driver
+ * e.g. for 74x164
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * Based on Linux driver
+ * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2010 Miguel Gaio <miguel.gaio@efixo.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <errno.h>
+#include <gpio.h>
+#include <init.h>
+#include <io.h>
+#include <malloc.h>
+#include <spi/spi.h>
+
+#define MAX_REGS 4
+
+struct gpio_74164 {
+ struct gpio_chip chip;
+ struct spi_device *spi;
+ u8 buffer[MAX_REGS];
+ u8 num_regs;
+};
+
+#define gc_to_gpio_74164(c) container_of(c, struct gpio_74164, chip)
+
+/*
+ * Since the registers are chained, every byte sent will make
+ * the previous byte shift to the next register in the
+ * chain. Thus, the first byte send will end up in the last
+ * register at the end of the transfer. So, to have a logical
+ * numbering, send the bytes in reverse order so that the last
+ * byte of the buffer will end up in the last register.
+ */
+static int gpio_74164_update_buffers(struct gpio_74164 *priv)
+{
+ u8 b[MAX_REGS];
+ int n;
+
+ for (n = 0; n < priv->num_regs; n++)
+ b[priv->num_regs - n - 1] = priv->buffer[n];
+ spi_write(priv->spi, b, priv->num_regs);
+
+ return 0;
+}
+
+static int gpio_74164_get_value(struct gpio_chip *chip, unsigned off)
+{
+ struct gpio_74164 *priv = gc_to_gpio_74164(chip);
+ u8 bank = off / 8;
+ u8 pin = off % 8;
+
+ return (priv->buffer[bank] >> pin) & 1;
+}
+
+static void gpio_74164_set_value(struct gpio_chip *chip,
+ unsigned off, int val)
+{
+ struct gpio_74164 *priv = gc_to_gpio_74164(chip);
+ u8 bank = off / 8;
+ u8 pin = off % 8;
+
+ if (val)
+ priv->buffer[bank] |= BIT(pin);
+ else
+ priv->buffer[bank] &= ~BIT(pin);
+
+ gpio_74164_update_buffers(priv);
+}
+
+static int gpio_74164_direction_output(struct gpio_chip *chip,
+ unsigned off, int val)
+{
+ gpio_74164_set_value(chip, off, val);
+ return 0;
+}
+
+static struct gpio_ops gpio_74164_ops = {
+ .direction_output = gpio_74164_direction_output,
+ .get = gpio_74164_get_value,
+ .set = gpio_74164_set_value,
+};
+
+static struct platform_device_id gpio_74164_ids[] = {
+ { "74hc164" },
+ { "74hc595" },
+ { }
+};
+
+static int gpio_74164_probe(struct device_d *dev)
+{
+ struct spi_device *spi = (struct spi_device *)dev->type_data;
+ struct gpio_74164 *priv;
+ u32 num_regs = 1;
+
+ dev->id = DEVICE_ID_DYNAMIC;
+ if (IS_ENABLED(CONFIG_OFDEVICE) && dev->device_node) {
+ dev->id = of_alias_get_id(dev->device_node, "gpio");
+ of_property_read_u32(dev->device_node, "registers-number",
+ &num_regs);
+ }
+
+ if (num_regs > MAX_REGS)
+ num_regs = MAX_REGS;
+
+ priv = xzalloc(sizeof(*priv));
+ priv->spi = spi;
+ priv->num_regs = num_regs;
+ priv->chip.dev = dev;
+ priv->chip.ops = &gpio_74164_ops;
+ priv->chip.base = dev->id * 32;
+ priv->chip.ngpio = num_regs * 8;
+
+ return gpiochip_add(&priv->chip);
+}
+
+static struct driver_d gpio_74164_driver = {
+ .name = "gpio-74164",
+ .probe = gpio_74164_probe,
+ .id_table = gpio_74164_ids,
+};
+device_spi_driver(gpio_74164_driver);
--
2.1.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v2 03/14] spi: ath79: move spidelay from spi-bitbang-txrx
2015-04-20 20:11 [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 01/14] net: phy: Support Marvell 88E1318S PHY Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 02/14] gpio: Add driver for 74x164 compatible shift-registers Sebastian Hesselbarth
@ 2015-04-20 20:11 ` Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 04/14] spi: Add SPI GPIO bitbang driver Sebastian Hesselbarth
` (11 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Sebastian Hesselbarth @ 2015-04-20 20:11 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: Thomas Petazzoni, barebox
Bitbang helpers for SPI require spidelay. This should be set
by the user and not the helper itself. Move it to ath79_spi
instead.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/spi/ath79_spi.c | 2 ++
drivers/spi/spi-bitbang-txrx.h | 2 --
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
index d9ab269da770..4d71eba695a5 100644
--- a/drivers/spi/ath79_spi.c
+++ b/drivers/spi/ath79_spi.c
@@ -100,6 +100,8 @@ static inline u32 getmiso(struct spi_device *spi)
return !!((ath79_spi_rr(sc, AR71XX_SPI_REG_RDS) & 1));
}
+#define spidelay(nsecs) udelay(nsecs/1000)
+
#include "spi-bitbang-txrx.h"
static inline void ath79_spi_chipselect(struct ath79_spi *sp, int chipselect)
diff --git a/drivers/spi/spi-bitbang-txrx.h b/drivers/spi/spi-bitbang-txrx.h
index 4c74d4e0c514..078ab8c6c000 100644
--- a/drivers/spi/spi-bitbang-txrx.h
+++ b/drivers/spi/spi-bitbang-txrx.h
@@ -42,8 +42,6 @@
* particular CPU clock rate.
*/
-#define spidelay(nsecs) udelay(nsecs/1000)
-
static inline u32
bitbang_txrx_be_cpha0(struct spi_device *spi,
unsigned nsecs, unsigned cpol,
--
2.1.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v2 04/14] spi: Add SPI GPIO bitbang driver
2015-04-20 20:11 [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sebastian Hesselbarth
` (2 preceding siblings ...)
2015-04-20 20:11 ` [PATCH v2 03/14] spi: ath79: move spidelay from spi-bitbang-txrx Sebastian Hesselbarth
@ 2015-04-20 20:11 ` Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 05/14] bus: mvebu-mbus: Remove coherency attribute Sebastian Hesselbarth
` (10 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Sebastian Hesselbarth @ 2015-04-20 20:11 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: Thomas Petazzoni, barebox
This adds a driver for SPI master by GPIO pins.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/spi/Kconfig | 4 +
drivers/spi/Makefile | 1 +
drivers/spi/gpio_spi.c | 240 +++++++++++++++++++++++++++++++++++++++++++++++++
include/spi/spi_gpio.h | 36 ++++++++
4 files changed, 281 insertions(+)
create mode 100644 drivers/spi/gpio_spi.c
create mode 100644 include/spi/spi_gpio.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index e4fa6a2d94bb..738b88ea5ed7 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -18,6 +18,10 @@ config DRIVER_SPI_ATMEL
bool "Atmel (AT91) SPI Master driver"
depends on ARCH_AT91
+config DRIVER_SPI_GPIO
+ bool "GPIO SPI Master driver"
+ depends on GPIOLIB
+
config DRIVER_SPI_IMX
bool "i.MX SPI Master driver"
depends on ARCH_IMX
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 7469479c31fc..74819665856e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_SPI) += spi.o
obj-$(CONFIG_DRIVER_SPI_ATH79) += ath79_spi.o
+obj-$(CONFIG_DRIVER_SPI_GPIO) += gpio_spi.o
obj-$(CONFIG_DRIVER_SPI_IMX) += imx_spi.o
obj-$(CONFIG_DRIVER_SPI_MVEBU) += mvebu_spi.o
obj-$(CONFIG_DRIVER_SPI_MXS) += mxs_spi.o
diff --git a/drivers/spi/gpio_spi.c b/drivers/spi/gpio_spi.c
new file mode 100644
index 000000000000..4ea545a2823a
--- /dev/null
+++ b/drivers/spi/gpio_spi.c
@@ -0,0 +1,240 @@
+/*
+ * SPI master driver using generic bitbanged GPIO
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * Based on Linux driver
+ * Copyright (C) 2006,2008 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <errno.h>
+#include <gpio.h>
+#include <init.h>
+#include <io.h>
+#include <malloc.h>
+#include <of_gpio.h>
+#include <spi/spi.h>
+#include <spi/spi_gpio.h>
+
+struct gpio_spi {
+ struct spi_master master;
+ struct gpio_spi_pdata *data;
+};
+
+#define priv_from_spi_device(s) container_of(s->master, struct gpio_spi, master)
+
+static inline void setsck(const struct spi_device *spi, int is_on)
+{
+ struct gpio_spi *priv = priv_from_spi_device(spi);
+ gpio_set_value(priv->data->sck, is_on);
+}
+
+static inline void setmosi(const struct spi_device *spi, int is_on)
+{
+ struct gpio_spi *priv = priv_from_spi_device(spi);
+ if (!gpio_is_valid(priv->data->mosi))
+ return;
+ gpio_set_value(priv->data->mosi, is_on);
+}
+
+static inline int getmiso(const struct spi_device *spi)
+{
+ struct gpio_spi *priv = priv_from_spi_device(spi);
+ if (!gpio_is_valid(priv->data->miso))
+ return 1;
+ return !!gpio_get_value(priv->data->miso);
+}
+
+#define spidelay(nsecs) do { } while (0)
+
+#include "spi-bitbang-txrx.h"
+
+static int gpio_spi_set_cs(struct spi_device *spi, bool en)
+{
+ struct gpio_spi *priv = priv_from_spi_device(spi);
+
+ if (!gpio_is_valid(priv->data->cs[spi->chip_select]))
+ return 0;
+
+ gpio_set_value(priv->data->cs[spi->chip_select],
+ (spi->mode & SPI_CS_HIGH) ? en : !en);
+
+ return 0;
+}
+
+static inline u32 gpio_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
+ u32 word, u8 bits)
+{
+ int cpol = !!(spi->mode & SPI_CPOL);
+ if (spi->mode & SPI_CPHA)
+ return bitbang_txrx_be_cpha1(spi, nsecs, cpol, word, bits);
+ else
+ return bitbang_txrx_be_cpha0(spi, nsecs, cpol, word, bits);
+}
+
+static int gpio_spi_transfer_one(struct spi_device *spi, struct spi_transfer *t)
+{
+ bool read = (t->rx_buf) ? true : false;
+ u32 word = 0;
+ int n;
+
+ for (n = 0; n < t->len; n++) {
+ if (!read)
+ word = ((const u8 *)t->tx_buf)[n];
+ word = gpio_spi_txrx_word(spi, 0, word, 8);
+ if (read)
+ ((u8 *)t->rx_buf)[n] = word & 0xff;
+ }
+
+ return 0;
+}
+
+static int gpio_spi_transfer(struct spi_device *spi, struct spi_message *msg)
+{
+ struct spi_transfer *t;
+ int ret;
+
+ ret = gpio_spi_set_cs(spi, true);
+ if (ret)
+ return ret;
+
+ list_for_each_entry(t, &msg->transfers, transfer_list) {
+ ret = gpio_spi_transfer_one(spi, t);
+ if (ret)
+ return ret;
+ msg->actual_length += t->len;
+ }
+
+ ret = gpio_spi_set_cs(spi, false);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int gpio_spi_setup(struct spi_device *spi)
+{
+ if (spi->bits_per_word != 8) {
+ dev_err(spi->master->dev, "master does not support %d bits per word\n",
+ spi->bits_per_word);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int gpio_spi_of_probe(struct device_d *dev)
+{
+ struct device_node *np = dev->device_node;
+ struct gpio_spi_pdata *pdata;
+ int n, sck;
+
+ if (!IS_ENABLED(CONFIG_OFDEVICE) || dev->platform_data)
+ return 0;
+
+ sck = of_get_named_gpio(np, "gpio-sck", 0);
+ if (sck == -EPROBE_DEFER)
+ return sck;
+ if (!gpio_is_valid(sck)) {
+ dev_err(dev, "missing mandatory SCK gpio\n");
+ return sck;
+ }
+
+ pdata = xzalloc(sizeof(*pdata));
+ pdata->sck = sck;
+ pdata->num_cs = MAX_CHIPSELECT;
+
+ pdata->miso = of_get_named_gpio(np, "gpio-miso", 0);
+ if (!gpio_is_valid(pdata->miso))
+ pdata->miso = SPI_GPIO_NO_MISO;
+
+ pdata->mosi = of_get_named_gpio(np, "gpio-mosi", 0);
+ if (!gpio_is_valid(pdata->mosi))
+ pdata->mosi = SPI_GPIO_NO_MOSI;
+
+ for (n = 0; n < MAX_CHIPSELECT; n++) {
+ pdata->cs[n] = of_get_named_gpio(np, "cs-gpios", n);
+ if (!gpio_is_valid(pdata->cs[n]))
+ pdata->cs[n] = SPI_GPIO_NO_CS;
+ }
+
+ dev->platform_data = pdata;
+
+ return 0;
+}
+
+static int gpio_spi_probe(struct device_d *dev)
+{
+ struct gpio_spi *priv;
+ struct gpio_spi_pdata *pdata;
+ struct spi_master *master;
+ int n, ret;
+
+ ret = gpio_spi_of_probe(dev);
+ if (ret)
+ return ret;
+ pdata = dev->platform_data;
+
+ ret = gpio_request_one(pdata->sck, GPIOF_DIR_OUT, "spi-sck");
+ if (ret)
+ return ret;
+
+ if (pdata->miso != SPI_GPIO_NO_MISO) {
+ ret = gpio_request_one(pdata->miso, GPIOF_DIR_IN, "spi-miso");
+ if (ret)
+ return ret;
+ }
+
+ if (pdata->mosi != SPI_GPIO_NO_MOSI) {
+ ret = gpio_request_one(pdata->mosi, GPIOF_DIR_OUT, "spi-mosi");
+ if (ret)
+ return ret;
+ }
+
+ for (n = 0; n < pdata->num_cs; n++) {
+ char *cs_name;
+
+ if (!gpio_is_valid(pdata->cs[n]))
+ continue;
+
+ cs_name = asprintf("spi-cs%d", n);
+ ret = gpio_request_one(pdata->cs[n], GPIOF_DIR_OUT, cs_name);
+ if (ret)
+ return ret;
+ }
+
+ priv = xzalloc(sizeof(*priv));
+ priv->data = pdata;
+ master = &priv->master;
+ master->dev = dev;
+ master->bus_num = dev->id;
+ master->setup = gpio_spi_setup;
+ master->transfer = gpio_spi_transfer;
+ master->num_chipselect = priv->data->num_cs;
+
+ return spi_register_master(&priv->master);
+}
+
+static struct of_device_id __maybe_unused gpio_spi_dt_ids[] = {
+ { .compatible = "spi-gpio", },
+ { }
+};
+
+static struct driver_d gpio_spi_driver = {
+ .name = "gpio-spi",
+ .probe = gpio_spi_probe,
+ .of_compatible = DRV_OF_COMPAT(gpio_spi_dt_ids),
+};
+device_platform_driver(gpio_spi_driver);
diff --git a/include/spi/spi_gpio.h b/include/spi/spi_gpio.h
new file mode 100644
index 000000000000..841c934f6ead
--- /dev/null
+++ b/include/spi/spi_gpio.h
@@ -0,0 +1,36 @@
+/*
+ * SPI master driver using generic bitbanged GPIO
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * Based on Linux driver
+ * Copyright (C) 2006,2008 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SPI_GPIO_H
+#define __SPI_GPIO_H
+
+#define MAX_CHIPSELECT 4
+#define SPI_GPIO_NO_CS (-1)
+#define SPI_GPIO_NO_MISO (-1)
+#define SPI_GPIO_NO_MOSI (-1)
+
+struct gpio_spi_pdata {
+ int sck;
+ int mosi;
+ int miso;
+ int cs[MAX_CHIPSELECT];
+ int num_cs;
+};
+
+#endif
--
2.1.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v2 05/14] bus: mvebu-mbus: Remove coherency attribute
2015-04-20 20:11 [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sebastian Hesselbarth
` (3 preceding siblings ...)
2015-04-20 20:11 ` [PATCH v2 04/14] spi: Add SPI GPIO bitbang driver Sebastian Hesselbarth
@ 2015-04-20 20:11 ` Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 06/14] bus: mvebu-mbus: Drop device reference Sebastian Hesselbarth
` (9 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Sebastian Hesselbarth @ 2015-04-20 20:11 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: Thomas Petazzoni, barebox
Marvell Armada 370 and XP have some coherency fabric. We are not
interested in using it, so remove checking for it in mbus driver.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/bus/mvebu-mbus.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 9dc43011b964..75c357a869ef 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -109,7 +109,6 @@ struct mvebu_mbus_state {
struct resource pcie_mem_aperture;
struct resource pcie_io_aperture;
const struct mvebu_mbus_soc_data *soc;
- int hw_io_coherency;
};
static struct mvebu_mbus_state mbus_state;
@@ -361,8 +360,6 @@ static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
w = &mbus_dram_info.cs[cs++];
w->cs_index = i;
w->mbus_attr = 0xf & ~(1 << i);
- if (mbus->hw_io_coherency)
- w->mbus_attr |= ATTR_HW_COHERENCY;
w->base = base & DDR_BASE_CS_LOW_MASK;
w->size = (size | ~DDR_SIZE_MASK) + 1;
}
@@ -719,9 +716,6 @@ static int mvebu_mbus_probe(struct device_d *dev)
mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
&mbus_state.pcie_io_aperture);
- if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"))
- mbus_state.hw_io_coherency = 1;
-
for (win = 0; win < mbus_state.soc->num_wins; win++)
mvebu_mbus_disable_window(&mbus_state, win);
--
2.1.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v2 06/14] bus: mvebu-mbus: Drop device reference
2015-04-20 20:11 [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sebastian Hesselbarth
` (4 preceding siblings ...)
2015-04-20 20:11 ` [PATCH v2 05/14] bus: mvebu-mbus: Remove coherency attribute Sebastian Hesselbarth
@ 2015-04-20 20:11 ` Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 07/14] bus: mvebu-mbus: Convert mbus platform driver to direct driver Sebastian Hesselbarth
` (8 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Sebastian Hesselbarth @ 2015-04-20 20:11 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: Thomas Petazzoni, barebox
Prior converting mbus driver from a platform device back to directly
called SoC driver, drop the device_d reference and covert dev_foo to
pr_foo.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/bus/mvebu-mbus.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 75c357a869ef..077d7ccb83ca 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -50,6 +50,8 @@
* configuration (file 'devices').
*/
+#define pr_fmt(fmt) "mvebu-mbus: " fmt
+
#include <common.h>
#include <init.h>
#include <io.h>
@@ -100,7 +102,7 @@ struct mvebu_mbus_soc_data {
};
struct mvebu_mbus_state {
- struct device_d *dev;
+ struct device_node *np;
void __iomem *mbuswins_base;
void __iomem *sdramwins_base;
struct dentry *debugfs_root;
@@ -496,7 +498,7 @@ int mvebu_mbus_add_window_remap_by_id(unsigned int target,
struct mvebu_mbus_state *s = &mbus_state;
if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
- dev_err(s->dev, "cannot add window '%x:%x', conflicts with another window\n",
+ pr_err("cannot add window '%x:%x', conflicts with another window\n",
target, attribute);
return -EINVAL;
}
@@ -552,14 +554,14 @@ static int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
u32 base, u32 size, u8 target, u8 attr)
{
if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
- dev_err(mbus->dev, "cannot add window '%04x:%04x', conflicts with another window\n",
+ pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
target, attr);
return -EBUSY;
}
if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
target, attr)) {
- dev_err(mbus->dev, "cannot add window '%04x:%04x', too many windows\n",
+ pr_err("cannot add window '%04x:%04x', too many windows\n",
target, attr);
return -ENOMEM;
}
@@ -571,7 +573,7 @@ static int mbus_parse_ranges(struct mvebu_mbus_state *mbus, int *addr_cells,
int *cell_count, const __be32 **ranges_start,
const __be32 **ranges_end)
{
- struct device_node *node = mbus->dev->device_node;
+ struct device_node *node = mbus->np;
const __be32 *prop;
int ranges_len, tuple_len;
@@ -596,8 +598,7 @@ static int mbus_parse_ranges(struct mvebu_mbus_state *mbus, int *addr_cells,
tuple_len = (*cell_count) * sizeof(__be32);
if (ranges_len % tuple_len) {
- dev_warn(mbus->dev, "malformed ranges entry '%s'\n",
- node->name);
+ pr_warn("malformed ranges entry '%s'\n", node->name);
return -EINVAL;
}
return 0;
@@ -679,36 +680,35 @@ static int mvebu_mbus_probe(struct device_d *dev)
const __be32 *prop;
int win;
- mbus_state.dev = dev;
-
np = of_find_matching_node_and_match(NULL, mvebu_mbus_dt_ids, &match);
if (!np) {
- dev_err(dev, "could not find a matching SoC family\n");
+ pr_err("could not find a matching SoC family\n");
return -ENODEV;
}
+ mbus_state.np = np;
mbus_state.soc = (struct mvebu_mbus_soc_data *)match->data;
prop = of_get_property(np, "controller", NULL);
if (!prop) {
- dev_err(dev, "required 'controller' property missing\n");
+ pr_err("required 'controller' property missing\n");
return -EINVAL;
}
controller = of_find_node_by_phandle(be32_to_cpup(prop));
if (!controller) {
- dev_err(dev, "could not find an 'mbus-controller' node\n");
+ pr_err("could not find an 'mbus-controller' node\n");
return -ENODEV;
}
mbus_state.mbuswins_base = of_iomap(controller, 0);
if (!mbus_state.mbuswins_base) {
- dev_err(dev, "cannot get MBUS register address\n");
+ pr_err("cannot get MBUS register address\n");
return -ENOMEM;
}
mbus_state.sdramwins_base = of_iomap(controller, 1);
if (!mbus_state.sdramwins_base) {
- dev_err(dev, "cannot get SDRAM register address\n");
+ pr_err("cannot get SDRAM register address\n");
return -ENOMEM;
}
--
2.1.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v2 07/14] bus: mvebu-mbus: Convert mbus platform driver to direct driver
2015-04-20 20:11 [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sebastian Hesselbarth
` (5 preceding siblings ...)
2015-04-20 20:11 ` [PATCH v2 06/14] bus: mvebu-mbus: Drop device reference Sebastian Hesselbarth
@ 2015-04-20 20:11 ` Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 08/14] ARM: mvebu: Move PCIe register defines to socid.h Sebastian Hesselbarth
` (7 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Sebastian Hesselbarth @ 2015-04-20 20:11 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: Thomas Petazzoni, barebox
Registering mbus driver as platform driver is a little late for
some register accesses to work. We have to make sure boot-up
mbus windows are disabled early, so call mbus driver directly
from SoC init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/armada-370-xp.c | 1 +
arch/arm/mach-mvebu/dove.c | 1 +
arch/arm/mach-mvebu/kirkwood.c | 1 +
drivers/bus/mvebu-mbus.c | 14 +-------------
include/linux/mbus.h | 2 ++
5 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 244f8cdd81a5..ae458b4433b3 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -73,6 +73,7 @@ static int armada_370_xp_init_soc(struct device_node *root, void *context)
armada_370_xp_memory_find(&phys_base, &phys_size);
mvebu_set_memory(phys_base, phys_size);
+ mvebu_mbus_init();
/* Enable peripherals PUP */
reg = readl(ARMADA_XP_PUP_ENABLE_BASE);
diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index c2852f8986ae..a7284fd33a63 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -93,6 +93,7 @@ static int dove_init_soc(struct device_node *root, void *context)
dove_memory_find(&phys_base, &phys_size);
mvebu_set_memory(phys_base, phys_size);
+ mvebu_mbus_init();
return 0;
}
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index d7903f732eac..19c6f0730332 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -66,6 +66,7 @@ static int kirkwood_init_soc(struct device_node *root, void *context)
kirkwood_memory_find(&phys_base, &phys_size);
mvebu_set_memory(phys_base, phys_size);
+ mvebu_mbus_init();
return 0;
}
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 077d7ccb83ca..e1898103540b 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -673,7 +673,7 @@ static void mvebu_mbus_get_pcie_resources(struct device_node *np,
}
}
-static int mvebu_mbus_probe(struct device_d *dev)
+int mvebu_mbus_init(void)
{
struct device_node *np, *controller;
const struct of_device_id *match;
@@ -725,18 +725,6 @@ static int mvebu_mbus_probe(struct device_d *dev)
return mbus_dt_setup(&mbus_state);
}
-static struct driver_d mvebu_mbus_driver = {
- .probe = mvebu_mbus_probe,
- .name = "mvebu-mbus",
- .of_compatible = DRV_OF_COMPAT(mvebu_mbus_dt_ids),
-};
-
-static int mvebu_mbus_init(void)
-{
- return platform_driver_register(&mvebu_mbus_driver);
-}
-postcore_initcall(mvebu_mbus_init);
-
struct mbus_range {
const char *compatible;
u32 mbusid;
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
index b90fabbfb7e5..bcc5949219cf 100644
--- a/include/linux/mbus.h
+++ b/include/linux/mbus.h
@@ -61,4 +61,6 @@ int mvebu_mbus_del_window(phys_addr_t base, size_t size);
void mvebu_mbus_add_range(const char *compatible,
u8 target, u8 attr, u32 remap);
+int mvebu_mbus_init(void);
+
#endif /* __LINUX_MBUS_H */
--
2.1.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v2 08/14] ARM: mvebu: Move PCIe register defines to socid.h
2015-04-20 20:11 [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sebastian Hesselbarth
` (6 preceding siblings ...)
2015-04-20 20:11 ` [PATCH v2 07/14] bus: mvebu-mbus: Convert mbus platform driver to direct driver Sebastian Hesselbarth
@ 2015-04-20 20:11 ` Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 09/14] ARM: mvebu: armada-xp: Fixup broken MV78230-A0 SoC ID Sebastian Hesselbarth
` (6 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Sebastian Hesselbarth @ 2015-04-20 20:11 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: Thomas Petazzoni, barebox
To prepare PCIe device id fixups, move PCIe register defines
to a common location.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/common.c | 5 +----
arch/arm/mach-mvebu/include/mach/socid.h | 4 ++++
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c
index 309f7a6aaa52..7d28d9c45aed 100644
--- a/arch/arm/mach-mvebu/common.c
+++ b/arch/arm/mach-mvebu/common.c
@@ -22,6 +22,7 @@
#include <of_address.h>
#include <linux/clk.h>
#include <mach/common.h>
+#include <mach/socid.h>
/*
* Marvell MVEBU SoC id and revision can be read from any PCIe
@@ -40,10 +41,6 @@ static const struct of_device_id mvebu_pcie_of_ids[] = {
{ },
};
-#define PCIE_VEN_DEV_ID 0x000
-#define PCIE_REV_ID 0x008
-#define REV_ID_MASK 0xff
-
static int mvebu_soc_id_init(void)
{
struct device_node *np, *cnp;
diff --git a/arch/arm/mach-mvebu/include/mach/socid.h b/arch/arm/mach-mvebu/include/mach/socid.h
index 36d681a9dcc1..7a29c82b30c0 100644
--- a/arch/arm/mach-mvebu/include/mach/socid.h
+++ b/arch/arm/mach-mvebu/include/mach/socid.h
@@ -16,6 +16,10 @@
#ifndef __MACH_MVEBU_SOCID_H
#define __MACH_MVEBU_SOCID_H
+#define PCIE_VEN_DEV_ID 0x000
+#define PCIE_REV_ID 0x008
+#define REV_ID_MASK 0xff
+
extern u16 soc_devid;
extern u16 soc_revid;
--
2.1.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v2 09/14] ARM: mvebu: armada-xp: Fixup broken MV78230-A0 SoC ID
2015-04-20 20:11 [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sebastian Hesselbarth
` (7 preceding siblings ...)
2015-04-20 20:11 ` [PATCH v2 08/14] ARM: mvebu: Move PCIe register defines to socid.h Sebastian Hesselbarth
@ 2015-04-20 20:11 ` Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 10/14] ARM: mvebu: armada-xp: Limit PUP access to Armada XP Sebastian Hesselbarth
` (5 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Sebastian Hesselbarth @ 2015-04-20 20:11 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: Thomas Petazzoni, barebox
Marvell Armada XP MV78230-A0 incorrectly identifies itself as MV78460.
Check number of CPUs in FABRIC_CONF and fixup PCIe DEV_ID when it is
2 CPUs instead of 4.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/armada-370-xp.c | 62 ++++++++++++++++++++++
.../mach-mvebu/include/mach/armada-370-xp-regs.h | 28 ++++++++--
2 files changed, 86 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index ae458b4433b3..9ba3247805d1 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -17,9 +17,12 @@
#include <common.h>
#include <init.h>
#include <io.h>
+#include <of.h>
+#include <of_address.h>
#include <asm/memory.h>
#include <linux/mbus.h>
#include <mach/armada-370-xp-regs.h>
+#include <mach/socid.h>
static inline void armada_370_xp_memory_find(unsigned long *phys_base,
unsigned long *phys_size)
@@ -44,6 +47,63 @@ static inline void armada_370_xp_memory_find(unsigned long *phys_base,
}
}
+static const struct of_device_id armada_370_xp_pcie_of_ids[] = {
+ { .compatible = "marvell,armada-xp-pcie", },
+ { .compatible = "marvell,armada-370-pcie", },
+ { },
+};
+
+static int armada_370_xp_soc_id_fixup(void)
+{
+ struct device_node *np, *cnp;
+ void __iomem *base;
+ u32 reg, ctrl, mask;
+ u32 socid, numcpus;
+
+ socid = readl(ARMADA_370_XP_CPU_SOC_ID) & CPU_SOC_ID_DEVICE_MASK;
+ numcpus = 1 + (readl(ARMADA_370_XP_FABRIC_CONF) & FABRIC_NUM_CPUS_MASK);
+
+ switch (socid) {
+ /*
+ * Marvell Armada XP MV78230-A0 incorrectly identifies itself as
+ * MV78460. Check for DEVID_MV78460 but if there are only 2 CPUs
+ * present in Coherency Fabric, fixup PCIe PRODUCT_ID.
+ */
+ case DEVID_MV78460:
+ if (numcpus != 2)
+ return 0;
+ socid = DEVID_MV78230;
+ mask = PCIE0_EN | PCIE1_EN | PCIE0_QUADX1_EN;
+ break;
+ default:
+ return 0;
+ }
+
+ np = of_find_matching_node(NULL, armada_370_xp_pcie_of_ids);
+ if (!np)
+ return -ENODEV;
+
+ /* Enable all individual x1 ports */
+ ctrl = readl(ARMADA_370_XP_SOC_CTRL);
+ writel(ctrl | mask, ARMADA_370_XP_SOC_CTRL);
+
+ for_each_child_of_node(np, cnp) {
+ base = of_iomap(cnp, 0);
+ if (!base)
+ continue;
+
+ /* Fixup PCIe port DEVICE_ID */
+ reg = readl(base + PCIE_VEN_DEV_ID);
+ reg = (socid << 16) | (reg & 0xffff);
+ writel(reg, base + PCIE_VEN_DEV_ID);
+ }
+
+ /* Restore SoC Control */
+ writel(ctrl, ARMADA_370_XP_SOC_CTRL);
+
+ return 0;
+}
+
static void __noreturn armada_370_xp_reset_cpu(unsigned long addr)
{
writel(0x1, ARMADA_370_XP_SYSCTL_BASE + 0x60);
@@ -75,6 +135,8 @@ static int armada_370_xp_init_soc(struct device_node *root, void *context)
mvebu_set_memory(phys_base, phys_size);
mvebu_mbus_init();
+ armada_370_xp_soc_id_fixup();
+
/* Enable peripherals PUP */
reg = readl(ARMADA_XP_PUP_ENABLE_BASE);
reg |= GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN | NAND_PUP_EN | SPI_PUP_EN;
diff --git a/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h b/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h
index bac27e5a262d..2a6e6d1aec2c 100644
--- a/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h
+++ b/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h
@@ -25,10 +25,18 @@
(ARMADA_370_XP_UART_BASE + ((n) * 0x100))
#define ARMADA_370_XP_SYSCTL_BASE (ARMADA_370_XP_INT_REGS_BASE + 0x18200)
-#define ARMADA_370_XP_SAR_BASE (ARMADA_370_XP_INT_REGS_BASE + 0x18230)
-#define SAR_LOW 0x00
+#define ARMADA_370_XP_SOC_CTRL (ARMADA_370_XP_SYSCTL_BASE + 0x004)
+#define PCIE1_QUADX1_EN BIT(8)
+#define PCIE0_QUADX1_EN BIT(7)
+#define PCIE3_EN BIT(3)
+#define PCIE2_EN BIT(2)
+#define PCIE1_EN BIT(1)
+#define PCIE0_EN BIT(0)
+#define ARMADA_370_XP_SAR_LOW (ARMADA_370_XP_SYSCTL_BASE + 0x030)
#define SAR_TCLK_FREQ BIT(20)
-#define SAR_HIGH 0x04
+#define ARMADA_370_XP_SAR_HIGH (ARMADA_370_XP_SYSCTL_BASE + 0x034)
+#define ARMADA_370_XP_CPU_SOC_ID (ARMADA_370_XP_SYSCTL_BASE + 0x03c)
+#define CPU_SOC_ID_DEVICE_MASK 0xffff
#define ARMADA_XP_PUP_ENABLE_BASE (ARMADA_370_XP_INT_REGS_BASE + 0x1864c)
#define GE0_PUP_EN BIT(0)
@@ -50,7 +58,19 @@
#define DDR_SIZE_MASK 0xff000000
#define ARMADA_370_XP_FABRIC_BASE (ARMADA_370_XP_INT_REGS_BASE + 0x20200)
+#define ARMADA_370_XP_FABRIC_CTRL (ARMADA_370_XP_FABRIC_BASE + 0x000)
+#define MBUS_ERR_PROP_EN BIT(8)
+#define ARMADA_370_XP_FABRIC_CONF (ARMADA_370_XP_FABRIC_BASE + 0x004)
+#define FABRIC_NUM_CPUS_MASK 0x3
#define ARMADA_370_XP_TIMER_BASE (ARMADA_370_XP_INT_REGS_BASE + 0x20300)
-#endif /* __MACH_MVEBU_DOVE_REGS_H */
+#define ARMADA_370_XP_PCIE_UNIT_OFFSET 0x40000
+#define ARMADA_370_XP_PCIE_PORT_OFFSET 0x04000
+#define ARMADA_370_XP_PCIE_BASE(port) \
+ (ARMADA_370_XP_INT_REGS_BASE + 0x40000 + \
+ (((port) / 4) * ARMADA_370_XP_PCIE_UNIT_OFFSET) + \
+ (((port) % 4) * ARMADA_370_XP_PCIE_PORT_OFFSET))
+#define PCIE_DEVICE_VENDOR_ID 0x000
+
+#endif /* __MACH_MVEBU_ARMADA_370_XP_REGS_H */
--
2.1.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v2 10/14] ARM: mvebu: armada-xp: Limit PUP access to Armada XP
2015-04-20 20:11 [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sebastian Hesselbarth
` (8 preceding siblings ...)
2015-04-20 20:11 ` [PATCH v2 09/14] ARM: mvebu: armada-xp: Fixup broken MV78230-A0 SoC ID Sebastian Hesselbarth
@ 2015-04-20 20:11 ` Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 11/14] ARM: mvebu: armada-xp: Use MBUS_ERR_PROP_EN define Sebastian Hesselbarth
` (4 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Sebastian Hesselbarth @ 2015-04-20 20:11 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: Thomas Petazzoni, barebox
Commit 6638760c225c37f90e822ebf4dd8f0d2cd0b0ef3
("ARM: mvebu: Enable PUP register")
correctly enables devices that are disabled after boot-up due to
some Design For Testability registers.
However, although harmless on Armada 370, call the code conditionally
on Armada XP only. While at it, move PUP register defines to SYSCTL
registers where they belong to.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/armada-370-xp.c | 18 ++++++++++++++----
arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h | 3 +--
2 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 9ba3247805d1..8e1463dd8b11 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -112,6 +112,18 @@ static void __noreturn armada_370_xp_reset_cpu(unsigned long addr)
;
}
+static int armada_xp_init_soc(struct device_node *root)
+{
+ u32 reg;
+
+ /* Enable GBE0, GBE1, LCD and NFC PUP */
+ reg = readl(ARMADA_XP_PUP_ENABLE);
+ reg |= GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN | NAND_PUP_EN | SPI_PUP_EN;
+ writel(reg, ARMADA_XP_PUP_ENABLE);
+
+ return 0;
+}
+
static int armada_370_xp_init_soc(struct device_node *root, void *context)
{
unsigned long phys_base, phys_size;
@@ -137,10 +149,8 @@ static int armada_370_xp_init_soc(struct device_node *root, void *context)
armada_370_xp_soc_id_fixup();
- /* Enable peripherals PUP */
- reg = readl(ARMADA_XP_PUP_ENABLE_BASE);
- reg |= GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN | NAND_PUP_EN | SPI_PUP_EN;
- writel(reg, ARMADA_XP_PUP_ENABLE_BASE);
+ if (of_machine_is_compatible("marvell,armadaxp"))
+ armada_xp_init_soc(root);
return 0;
}
diff --git a/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h b/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h
index 2a6e6d1aec2c..1dad05317211 100644
--- a/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h
+++ b/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h
@@ -37,8 +37,7 @@
#define ARMADA_370_XP_SAR_HIGH (ARMADA_370_XP_SYSCTL_BASE + 0x034)
#define ARMADA_370_XP_CPU_SOC_ID (ARMADA_370_XP_SYSCTL_BASE + 0x03c)
#define CPU_SOC_ID_DEVICE_MASK 0xffff
-
-#define ARMADA_XP_PUP_ENABLE_BASE (ARMADA_370_XP_INT_REGS_BASE + 0x1864c)
+#define ARMADA_XP_PUP_ENABLE (ARMADA_370_XP_SYSCTL_BASE + 0x44c)
#define GE0_PUP_EN BIT(0)
#define GE1_PUP_EN BIT(1)
#define LCD_PUP_EN BIT(2)
--
2.1.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v2 11/14] ARM: mvebu: armada-xp: Use MBUS_ERR_PROP_EN define
2015-04-20 20:11 [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sebastian Hesselbarth
` (9 preceding siblings ...)
2015-04-20 20:11 ` [PATCH v2 10/14] ARM: mvebu: armada-xp: Limit PUP access to Armada XP Sebastian Hesselbarth
@ 2015-04-20 20:11 ` Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 12/14] ARM: mvebu: armada-xp: Sort boards and images alphabetically Sebastian Hesselbarth
` (3 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Sebastian Hesselbarth @ 2015-04-20 20:11 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: Thomas Petazzoni, barebox
With proper defines for ARMADA_370_XP_FABRIC_CTRL and MBUS_ERR_PROP_EN
make use of it.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/armada-370-xp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 8e1463dd8b11..2405629526e0 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -138,9 +138,9 @@ static int armada_370_xp_init_soc(struct device_node *root, void *context)
barebox_set_hostname("armada");
/* Disable MBUS error propagation */
- reg = readl(ARMADA_370_XP_FABRIC_BASE);
- reg &= ~BIT(8);
- writel(reg, ARMADA_370_XP_FABRIC_BASE);
+ reg = readl(ARMADA_370_XP_FABRIC_CTRL);
+ reg &= ~MBUS_ERR_PROP_EN;
+ writel(reg, ARMADA_370_XP_FABRIC_CTRL);
armada_370_xp_memory_find(&phys_base, &phys_size);
--
2.1.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v2 12/14] ARM: mvebu: armada-xp: Sort boards and images alphabetically
2015-04-20 20:11 [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sebastian Hesselbarth
` (10 preceding siblings ...)
2015-04-20 20:11 ` [PATCH v2 11/14] ARM: mvebu: armada-xp: Use MBUS_ERR_PROP_EN define Sebastian Hesselbarth
@ 2015-04-20 20:11 ` Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 13/14] ARM: mvebu: armada-xp: Add Lenovo Iomega ix4-300d Sebastian Hesselbarth
` (2 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Sebastian Hesselbarth @ 2015-04-20 20:11 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: Thomas Petazzoni, barebox
Before adding new Armada XP based boards becomes messier than necessary,
sort Armada XP based board Kconfig and image Makefile alphabetically.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/Kconfig | 8 ++++----
images/Makefile.mvebu | 22 +++++++++++-----------
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 8323b6604174..9394cf71a998 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -43,14 +43,14 @@ config MACH_GLOBALSCALE_MIRABOX
comment "Armada XP based boards"
-config MACH_PLATHOME_OPENBLOCKS_AX3
- bool "PlatHome OpenBlocks AX3"
- select ARCH_ARMADA_XP
-
config MACH_MARVELL_ARMADA_XP_GP
bool "Marvell Armada XP GP"
select ARCH_ARMADA_XP
+config MACH_PLATHOME_OPENBLOCKS_AX3
+ bool "PlatHome OpenBlocks AX3"
+ select ARCH_ARMADA_XP
+
#
# Dove 88AP510 SoC boards
#
diff --git a/images/Makefile.mvebu b/images/Makefile.mvebu
index c3923e4ecc8f..82f370576468 100644
--- a/images/Makefile.mvebu
+++ b/images/Makefile.mvebu
@@ -24,17 +24,6 @@ image-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += barebox-globalscale-mirabox-uart.img
image-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += barebox-globalscale-mirabox-2nd.img
# ----------------------- Armada XP based boards ---------------------------
-PLATHOME_OPENBLOCKS_AX3_KWBOPTS = ${KWBOPTS} -i $(board)/plathome-openblocks-ax3/kwbimage.cfg
-OPTS_start_plathome_openblocks_ax3.pblx.kwbimg = $(PLATHOME_OPENBLOCKS_AX3_KWBOPTS)
-OPTS_start_plathome_openblocks_ax3.pblx.kwbuartimg = -m uart $(PLATHOME_OPENBLOCKS_AX3_KWBOPTS)
-FILE_barebox-plathome-openblocks-ax3.img = start_plathome_openblocks_ax3.pblx.kwbimg
-FILE_barebox-plathome-openblocks-ax3-uart.img = start_plathome_openblocks_ax3.pblx.kwbuartimg
-FILE_barebox-plathome-openblocks-ax3-2nd.img = start_plathome_openblocks_ax3.pblx
-pblx-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += start_plathome_openblocks_ax3
-image-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += barebox-plathome-openblocks-ax3.img
-image-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += barebox-plathome-openblocks-ax3-uart.img
-image-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += barebox-plathome-openblocks-ax3-2nd.img
-
MARVELL_ARMADA_XP_GP_KWBOPTS = ${KWBOPTS} -i $(board)/marvell-armada-xp-gp/kwbimage.cfg
OPTS_start_marvell_armada_xp_gp.pblx.kwbimg = $(MARVELL_ARMADA_XP_GP_KWBOPTS)
OPTS_start_marvell_armada_xp_gp.pblx.kwbuartimg = -m uart $(MARVELL_ARMADA_XP_GP_KWBOPTS)
@@ -46,6 +35,17 @@ image-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += barebox-marvell-armada-xp-gp.img
image-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += barebox-marvell-armada-xp-gp-uart.img
image-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += barebox-marvell-armada-xp-gp-2nd.img
+PLATHOME_OPENBLOCKS_AX3_KWBOPTS = ${KWBOPTS} -i $(board)/plathome-openblocks-ax3/kwbimage.cfg
+OPTS_start_plathome_openblocks_ax3.pblx.kwbimg = $(PLATHOME_OPENBLOCKS_AX3_KWBOPTS)
+OPTS_start_plathome_openblocks_ax3.pblx.kwbuartimg = -m uart $(PLATHOME_OPENBLOCKS_AX3_KWBOPTS)
+FILE_barebox-plathome-openblocks-ax3.img = start_plathome_openblocks_ax3.pblx.kwbimg
+FILE_barebox-plathome-openblocks-ax3-uart.img = start_plathome_openblocks_ax3.pblx.kwbuartimg
+FILE_barebox-plathome-openblocks-ax3-2nd.img = start_plathome_openblocks_ax3.pblx
+pblx-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += start_plathome_openblocks_ax3
+image-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += barebox-plathome-openblocks-ax3.img
+image-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += barebox-plathome-openblocks-ax3-uart.img
+image-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += barebox-plathome-openblocks-ax3-2nd.img
+
# ----------------------- Dove 88AP510 based boards ---------------------------
SOLIDRUN_CUBOX_KWBOPTS = ${KWBOPTS} -i $(board)/solidrun-cubox/kwbimage.cfg
OPTS_start_solidrun_cubox.pblx.kwbimg = $(SOLIDRUN_CUBOX_KWBOPTS)
--
2.1.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v2 13/14] ARM: mvebu: armada-xp: Add Lenovo Iomega ix4-300d
2015-04-20 20:11 [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sebastian Hesselbarth
` (11 preceding siblings ...)
2015-04-20 20:11 ` [PATCH v2 12/14] ARM: mvebu: armada-xp: Sort boards and images alphabetically Sebastian Hesselbarth
@ 2015-04-20 20:11 ` Sebastian Hesselbarth
2015-04-20 20:11 ` [PATCH v2 14/14] ARM: Add Lenovo ix4 and related drivers to mvebu_defconfig Sebastian Hesselbarth
2015-04-23 5:57 ` [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sascha Hauer
14 siblings, 0 replies; 16+ messages in thread
From: Sebastian Hesselbarth @ 2015-04-20 20:11 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: Thomas Petazzoni, barebox
This adds support for Marvell Armada XP based 4-bay NAS Lenovo
Iomega ix4-300d.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/boards/Makefile | 1 +
arch/arm/boards/lenovo-ix4-300d/Makefile | 1 +
arch/arm/boards/lenovo-ix4-300d/kwbimage.cfg | 5 ++++
arch/arm/boards/lenovo-ix4-300d/lowlevel.c | 35 +++++++++++++++++++++++++++
arch/arm/dts/Makefile | 1 +
arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts | 14 +++++++++++
arch/arm/mach-mvebu/Kconfig | 4 +++
images/Makefile.mvebu | 11 +++++++++
8 files changed, 72 insertions(+)
create mode 100644 arch/arm/boards/lenovo-ix4-300d/Makefile
create mode 100644 arch/arm/boards/lenovo-ix4-300d/kwbimage.cfg
create mode 100644 arch/arm/boards/lenovo-ix4-300d/lowlevel.c
create mode 100644 arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 35aa9a2f520f..d6fc17cc251e 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_MACH_HIGHBANK) += highbank/
obj-$(CONFIG_MACH_IMX21ADS) += freescale-mx21-ads/
obj-$(CONFIG_MACH_IMX233_OLINUXINO) += imx233-olinuxino/
obj-$(CONFIG_MACH_IMX27ADS) += freescale-mx27-ads/
+obj-$(CONFIG_MACH_LENOVO_IX4_300D) += lenovo-ix4-300d/
obj-$(CONFIG_MACH_LUBBOCK) += lubbock/
obj-$(CONFIG_MACH_MAINSTONE) += mainstone/
obj-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += marvell-armada-xp-gp/
diff --git a/arch/arm/boards/lenovo-ix4-300d/Makefile b/arch/arm/boards/lenovo-ix4-300d/Makefile
new file mode 100644
index 000000000000..b08c4a93ca27
--- /dev/null
+++ b/arch/arm/boards/lenovo-ix4-300d/Makefile
@@ -0,0 +1 @@
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/lenovo-ix4-300d/kwbimage.cfg b/arch/arm/boards/lenovo-ix4-300d/kwbimage.cfg
new file mode 100644
index 000000000000..713efb0b0a89
--- /dev/null
+++ b/arch/arm/boards/lenovo-ix4-300d/kwbimage.cfg
@@ -0,0 +1,5 @@
+VERSION 1
+BOOT_FROM nand
+NAND_BLKSZ 00020000
+NAND_BADBLK_LOCATION 00
+BINARY arch/arm/boards/lenovo-ix4-300d/binary.0 0000005b 00000068
diff --git a/arch/arm/boards/lenovo-ix4-300d/lowlevel.c b/arch/arm/boards/lenovo-ix4-300d/lowlevel.c
new file mode 100644
index 000000000000..8cb8bd40791c
--- /dev/null
+++ b/arch/arm/boards/lenovo-ix4-300d/lowlevel.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2014, 2015
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+#include <linux/sizes.h>
+#include <mach/lowlevel.h>
+
+extern char __dtb_armada_xp_lenovo_ix4_300d_bb_start[];
+
+ENTRY_FUNCTION(start_lenovo_ix4_300d, r0, r1, r2)
+{
+ void *fdt;
+
+ arm_cpu_lowlevel_init();
+
+ fdt = __dtb_armada_xp_lenovo_ix4_300d_bb_start -
+ get_runtime_offset();
+
+ mvebu_barebox_entry(fdt);
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cc92bdef838c..06c29c8d8017 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -23,6 +23,7 @@ pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.
pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o
pbl-dtb-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o
+pbl-dtb-$(CONFIG_MACH_LENOVO_IX4_300D) += armada-xp-lenovo-ix4-300d-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o
pbl-dtb-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o
diff --git a/arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts b/arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts
new file mode 100644
index 000000000000..5f1a6073814d
--- /dev/null
+++ b/arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts
@@ -0,0 +1,14 @@
+/*
+ * Barebox specific DT overlay for Lenovo Iomega ix4-300d
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ */
+
+#include "arm/armada-xp-lenovo-ix4-300d.dts"
+
+/ {
+ gpio-leds {
+ power-led {
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 9394cf71a998..5e96f16e8cf4 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -43,6 +43,10 @@ config MACH_GLOBALSCALE_MIRABOX
comment "Armada XP based boards"
+config MACH_LENOVO_IX4_300D
+ bool "Lenovo Iomega ix4-300d"
+ select ARCH_ARMADA_XP
+
config MACH_MARVELL_ARMADA_XP_GP
bool "Marvell Armada XP GP"
select ARCH_ARMADA_XP
diff --git a/images/Makefile.mvebu b/images/Makefile.mvebu
index 82f370576468..dcf2235f8cb5 100644
--- a/images/Makefile.mvebu
+++ b/images/Makefile.mvebu
@@ -24,6 +24,17 @@ image-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += barebox-globalscale-mirabox-uart.img
image-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += barebox-globalscale-mirabox-2nd.img
# ----------------------- Armada XP based boards ---------------------------
+LENOVO_IX4_300D_KWBOPTS = ${KWBOPTS} -i $(board)/lenovo-ix4-300d/kwbimage.cfg
+OPTS_start_lenovo_ix4_300d.pblx.kwbimg = $(LENOVO_IX4_300D_KWBOPTS)
+OPTS_start_lenovo_ix4_300d.pblx.kwbuartimg = -m uart $(LENOVO_IX4_300D_KWBOPTS)
+FILE_barebox-lenovo-ix4-300d.img = start_lenovo_ix4_300d.pblx.kwbimg
+FILE_barebox-lenovo-ix4-300d-uart.img = start_lenovo_ix4_300d.pblx.kwbuartimg
+FILE_barebox-lenovo-ix4-300d-2nd.img = start_lenovo_ix4_300d.pblx
+pblx-$(CONFIG_MACH_LENOVO_IX4_300D) += start_lenovo_ix4_300d.pblx
+image-$(CONFIG_MACH_LENOVO_IX4_300D) += barebox-lenovo-ix4-300d.img
+image-$(CONFIG_MACH_LENOVO_IX4_300D) += barebox-lenovo-ix4-300d-uart.img
+image-$(CONFIG_MACH_LENOVO_IX4_300D) += barebox-lenovo-ix4-300d-2nd.img
+
MARVELL_ARMADA_XP_GP_KWBOPTS = ${KWBOPTS} -i $(board)/marvell-armada-xp-gp/kwbimage.cfg
OPTS_start_marvell_armada_xp_gp.pblx.kwbimg = $(MARVELL_ARMADA_XP_GP_KWBOPTS)
OPTS_start_marvell_armada_xp_gp.pblx.kwbuartimg = -m uart $(MARVELL_ARMADA_XP_GP_KWBOPTS)
--
2.1.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v2 14/14] ARM: Add Lenovo ix4 and related drivers to mvebu_defconfig
2015-04-20 20:11 [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sebastian Hesselbarth
` (12 preceding siblings ...)
2015-04-20 20:11 ` [PATCH v2 13/14] ARM: mvebu: armada-xp: Add Lenovo Iomega ix4-300d Sebastian Hesselbarth
@ 2015-04-20 20:11 ` Sebastian Hesselbarth
2015-04-23 5:57 ` [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sascha Hauer
14 siblings, 0 replies; 16+ messages in thread
From: Sebastian Hesselbarth @ 2015-04-20 20:11 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: Thomas Petazzoni, barebox
Update mvebu_defconfig to cover recently introduced Lenovo ix4 and
its related drivers.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/configs/mvebu_defconfig | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 9309084cdc05..6d1b021768df 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -1,7 +1,8 @@
CONFIG_ARCH_MVEBU=y
CONFIG_MACH_GLOBALSCALE_MIRABOX=y
-CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3=y
+CONFIG_MACH_LENOVO_IX4_300D=y
CONFIG_MACH_MARVELL_ARMADA_XP_GP=y
+CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3=y
CONFIG_MACH_SOLIDRUN_CUBOX=y
CONFIG_MACH_GLOBALSCALE_GURUPLUG=y
CONFIG_MACH_USI_TOPKICK=y
@@ -90,6 +91,7 @@ CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_NET_ORION=y
CONFIG_MARVELL_PHY=y
+CONFIG_DRIVER_SPI_GPIO=y
CONFIG_DRIVER_SPI_MVEBU=y
CONFIG_I2C=y
CONFIG_I2C_MV64XXX=y
@@ -111,6 +113,7 @@ CONFIG_LED_TRIGGERS=y
CONFIG_EEPROM_AT25=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_WATCHDOG=y
+CONFIG_GPIO_74164=y
CONFIG_GPIO_ORION=y
CONFIG_PCI_MVEBU=y
CONFIG_FS_CRAMFS=y
--
2.1.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS
2015-04-20 20:11 [PATCH v2 00/14] Add support for Lenovo ix4-300d NAS Sebastian Hesselbarth
` (13 preceding siblings ...)
2015-04-20 20:11 ` [PATCH v2 14/14] ARM: Add Lenovo ix4 and related drivers to mvebu_defconfig Sebastian Hesselbarth
@ 2015-04-23 5:57 ` Sascha Hauer
14 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2015-04-23 5:57 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: Thomas Petazzoni, barebox
On Mon, Apr 20, 2015 at 10:11:12PM +0200, Sebastian Hesselbarth wrote:
> This is v2 of the patch set adding support for the Lenovo ix4-300d
> NAS based on Marvell Armada XP MV78230 SoC. Compared to v1 [1] there
> have been the following changes:
>
> - SPI GPIO bitbang driver now respects -EPROBE_DEFER
> - Add ix4 and its drivers to mvebu_defconfig
>
> [1] http://www.spinics.net/lists/u-boot-v2/msg23048.html
>
> Sebastian Hesselbarth (14):
> net: phy: Support Marvell 88E1318S PHY
> gpio: Add driver for 74x164 compatible shift-registers
> spi: ath79: move spidelay from spi-bitbang-txrx
> spi: Add SPI GPIO bitbang driver
> bus: mvebu-mbus: Remove coherency attribute
> bus: mvebu-mbus: Drop device reference
> bus: mvebu-mbus: Convert mbus platform driver to direct driver
> ARM: mvebu: Move PCIe register defines to socid.h
> ARM: mvebu: armada-xp: Fixup broken MV78230-A0 SoC ID
> ARM: mvebu: armada-xp: Limit PUP access to Armada XP
> ARM: mvebu: armada-xp: Use MBUS_ERR_PROP_EN define
> ARM: mvebu: armada-xp: Sort boards and images alphabetically
> ARM: mvebu: armada-xp: Add Lenovo Iomega ix4-300d
> ARM: Add Lenovo ix4 and related drivers to mvebu_defconfig
Applied, thanks
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 16+ messages in thread