[RFC, PATCH] i.MX: Add provisions to boot from IRAM

[RFC, PATCH] i.MX: Add provisions to boot from IRAM

[Andrey Smirnov]

This commit add a very basic code to allow Barebox to be booted from
IRAM. Given that the amount of IRAM on most i.MX variants is
insufficient to contain a copy of Barebox with any reasonable degree
of functionality this code uses IRAM only as a temporary location and
eventually bootstraps from DRAM. But the presense of the intermediate
IRAM-only stage allows to add provisions to test the area of DRAM that
Barebox would be using to facilitate various testing scenarious.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/boards/freescale-mx51-babbage/Makefile    |  3 ++
 .../flash-header-imx51-babbage-xload.imxcfg        | 59 ++++++++++++++++++++++
 arch/arm/boards/freescale-mx51-babbage/lowlevel.c  | 25 +++++++++
 arch/arm/configs/imx_v7-xload_defconfig            | 46 +++++++++++++++++
 arch/arm/mach-imx/Kconfig                          | 15 ++++++
 arch/arm/mach-imx/Makefile                         |  1 +
 arch/arm/mach-imx/xload.c                          | 54 ++++++++++++++++++++
 images/Makefile.imx                                | 20 +++++++-
 8 files changed, 222 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg
 create mode 100644 arch/arm/configs/imx_v7-xload_defconfig
 create mode 100644 arch/arm/mach-imx/xload.c

diff --git a/arch/arm/boards/freescale-mx51-babbage/Makefile b/arch/arm/boards/freescale-mx51-babbage/Makefile
index 6252c88..31b8fcd 100644
--- a/arch/arm/boards/freescale-mx51-babbage/Makefile
+++ b/arch/arm/boards/freescale-mx51-babbage/Makefile
@@ -1,3 +1,6 @@
 obj-y += board.o flash-header-imx51-babbage.dcd.o
 extra-y += flash-header-imx51-babbage.dcd.S flash-header-imx51-babbage.dcd
 lwl-y += lowlevel.o
+
+obj-$(CONFIG_ARCH_IMX_XLOAD) += flash-header-imx51-babbage-xload.dcd.o
+extra-$(CONFIG_ARCH_IMX_XLOAD) += flash-header-imx51-babbage-xload.dcd.S flash-header-imx51-babbage-xload.dcd
diff --git a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg
new file mode 100644
index 0000000..a04ac75
--- /dev/null
+++ b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg
@@ -0,0 +1,59 @@
+loadaddr CONFIG_ARCH_IMX_UNUSED_IRAM_BASE
+soc imx51
+dcdofs 0x400
+wm 32 0x73fa88a0 0x00000200
+wm 32 0x73fa850c 0x000020c5
+wm 32 0x73fa8510 0x000020c5
+wm 32 0x73fa883c 0x00000002
+wm 32 0x73fa8848 0x00000002
+wm 32 0x73fa84b8 0x000000e7
+wm 32 0x73fa84bc 0x00000045
+wm 32 0x73fa84c0 0x00000045
+wm 32 0x73fa84c4 0x00000045
+wm 32 0x73fa84c8 0x00000045
+wm 32 0x73fa8820 0x00000000
+wm 32 0x73fa84a4 0x00000003
+wm 32 0x73fa84a8 0x00000003
+wm 32 0x73fa84ac 0x000000e3
+wm 32 0x73fa84b0 0x000000e3
+wm 32 0x73fa84b4 0x000000e3
+wm 32 0x73fa84cc 0x000000e3
+wm 32 0x73fa84d0 0x000000e2
+wm 32 0x73fa882c 0x00000004
+wm 32 0x73fa88a4 0x00000004
+wm 32 0x73fa88ac 0x00000004
+wm 32 0x73fa88b8 0x00000004
+wm 32 0x83fd9000 0x82a20000
+wm 32 0x83fd9008 0x82a20000
+wm 32 0x83fd9010 0x000ad0d0
+wm 32 0x83fd9004 0x3f3584ab
+wm 32 0x83fd900c 0x3f3584ab
+wm 32 0x83fd9014 0x04008008
+wm 32 0x83fd9014 0x0000801a
+wm 32 0x83fd9014 0x0000801b
+wm 32 0x83fd9014 0x00448019
+wm 32 0x83fd9014 0x07328018
+wm 32 0x83fd9014 0x04008008
+wm 32 0x83fd9014 0x00008010
+wm 32 0x83fd9014 0x00008010
+wm 32 0x83fd9014 0x06328018
+wm 32 0x83fd9014 0x03808019
+wm 32 0x83fd9014 0x00408019
+wm 32 0x83fd9014 0x00008000
+wm 32 0x83fd9014 0x0400800c
+wm 32 0x83fd9014 0x0000801e
+wm 32 0x83fd9014 0x0000801f
+wm 32 0x83fd9014 0x0000801d
+wm 32 0x83fd9014 0x0732801c
+wm 32 0x83fd9014 0x0400800c
+wm 32 0x83fd9014 0x00008014
+wm 32 0x83fd9014 0x00008014
+wm 32 0x83fd9014 0x0632801c
+wm 32 0x83fd9014 0x0380801d
+wm 32 0x83fd9014 0x0040801d
+wm 32 0x83fd9014 0x00008004
+wm 32 0x83fd9000 0xb2a20000
+wm 32 0x83fd9008 0xb2a20000
+wm 32 0x83fd9010 0x000ad6d0
+wm 32 0x83fd9034 0x90000000
+wm 32 0x83fd9014 0x00000000
diff --git a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
index 3bb8614..e308553 100644
--- a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
+++ b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
@@ -3,6 +3,7 @@
 #include <common.h>
 #include <mach/esdctl.h>
 #include <mach/generic.h>
+#include <asm/cache.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>

@@ -53,3 +54,27 @@ ENTRY_FUNCTION(start_imx51_babbage, r0, r1, r2)

 	imx51_barebox_entry(fdt);
 }
+
+static noinline void babbage_entry(void)
+{
+	arm_early_mmu_cache_invalidate();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	puts_ll("lowlevel init done\n");
+
+	imx51_barebox_entry(NULL);
+}
+
+ENTRY_FUNCTION(start_imx51_babbage_xload, r0, r1, r2)
+{
+	imx5_cpu_lowlevel_init();
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
+	arm_setup_stack(0x20000000 - 16);
+
+	babbage_entry();
+}
diff --git a/arch/arm/configs/imx_v7-xload_defconfig b/arch/arm/configs/imx_v7-xload_defconfig
new file mode 100644
index 0000000..41293fb
--- /dev/null
+++ b/arch/arm/configs/imx_v7-xload_defconfig
@@ -0,0 +1,46 @@
+CONFIG_ARCH_IMX=y
+CONFIG_ARCH_IMX_IMXIMAGE=y
+CONFIG_ARCH_IMX_XLOAD=y
+
+CONFIG_ARCH_IMX51=y
+CONFIG_IMX_MULTI_BOARDS=y
+CONFIG_MACH_FREESCALE_MX51_PDK=y
+
+CONFIG_THUMB2_BAREBOX=y
+# CONFIG_CMD_ARM_CPUINFO is not set
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x0
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_DUMMY=y
+CONFIG_RELOCATABLE=y
+CONFIG_BAUDRATE=115200
+CONFIG_SHELL_NONE=y
+
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_IMX51_UART=y
+CONFIG_DEBUG_IMX_UART_PORT=1
+
+CONFIG_HAS_DEBUG_LL=y
+# CONFIG_ERRNO_MESSAGES is not set
+# CONFIG_TIMESTAMP is not set
+# CONFIG_DEFAULT_ENVIRONMENT is not set
+CONFIG_DRIVER_SERIAL_IMX=y
+
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+# CONFIG_MCI_WRITE is not set
+
+CONFIG_MCI_IMX_ESDHC=y
+
+CONFIG_EEPROM_AT25=y
+
+CONFIG_WATCHDOG_IMX_RESET_SOURCE=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_IMX=y
+
+# CONFIG_FS_RAMFS is not set
+# CONFIG_FS_DEVFS is not set
+CONFIG_FS_FAT=y
+CONFIG_BOOTSTRAP=y
+CONFIG_BOOTSTRAP_DISK=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index c713477..3ccd060 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -68,6 +68,21 @@ config ARCH_IMX_IMXIMAGE
 	help
 	  if enabled the imx-image tool is compiled

+config ARCH_IMX_XLOAD
+	bool
+	depends on ARCH_IMX51
+	prompt "Build preloader image"
+
+config ARCH_IMX_UNUSED_IRAM_BASE
+       hex
+       depends on ARCH_IMX_XLOAD
+       default 0x1ffe2000 if ARCH_IMX51
+
+config ARCH_IMX_UNUSED_IRAM_SIZE
+       hex
+       depends on ARCH_IMX_XLOAD
+       default 0x16000 if ARCH_IMX51
+
 choice
 	depends on ARCH_IMX_INTERNAL_BOOT
 	prompt "Internal boot source"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index ae953b1..0320d1c 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,6 +12,7 @@ pbl-$(CONFIG_ARCH_IMX53) += imx53.o imx5.o esdctl-v4.o
 obj-$(CONFIG_ARCH_IMX6) += imx6.o usb-imx6.o clk-imx6.o
 lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o
 obj-$(CONFIG_ARCH_IMX6SX) += clk-imx6sx.o
+obj-$(CONFIG_ARCH_IMX_XLOAD) += xload.o
 obj-$(CONFIG_IMX_IIM)	+= iim.o
 obj-$(CONFIG_IMX_OCOTP)	+= ocotp.o
 obj-$(CONFIG_NAND_IMX) += nand.o
diff --git a/arch/arm/mach-imx/xload.c b/arch/arm/mach-imx/xload.c
new file mode 100644
index 0000000..07d6520
--- /dev/null
+++ b/arch/arm/mach-imx/xload.c
@@ -0,0 +1,54 @@
+#include <bootsource.h>
+#include <bootstrap.h>
+#include <common.h>
+#include <malloc.h>
+#include <init.h>
+#include <envfs.h>
+#include <linux/sizes.h>
+#include <fs.h>
+#include <io.h>
+
+#include <linux/clkdev.h>
+#include <linux/stat.h>
+#include <linux/clk.h>
+
+#include <mach/devices-imx51.h>
+
+static __noreturn int imx_xload(void)
+{
+	enum bootsource bootsource = bootsource_get();
+	void *buf;
+
+	switch (bootsource) {
+	case BOOTSOURCE_MMC:
+		buf = bootstrap_read_disk("disk0.0", "fat");
+		break;
+	default:
+		pr_err("unknown bootsource %d\n", bootsource);
+		hang();
+	}
+
+	if (!buf) {
+		pr_err("failed to load barebox.bin\n");
+		hang();
+	}
+
+	pr_info("starting bootloader...\n");
+
+	bootstrap_boot(buf, 0);
+
+	hang();
+}
+
+static int imx_devices_init(void)
+{
+#ifdef CONFIG_MCI_IMX_ESDHC
+	imx51_add_mmc0(NULL);
+	imx51_add_mmc1(NULL);
+#endif
+
+	barebox_main = imx_xload;
+
+	return 0;
+}
+coredevice_initcall(imx_devices_init);
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 415b294..6b44958 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -4,8 +4,15 @@

 # %.imximg - convert into i.MX image
 # ----------------------------------------------------------------
+
+ifdef CONFIG_ARCH_IMX_XLOAD
+$(obj)/%.imximg: $(obj)/% FORCE
+	$(call cmd,check_file_size,$<,$(CONFIG_ARCH_IMX_UNUSED_IRAM_SIZE))
+	$(call if_changed,imx_image)
+else
 $(obj)/%.imximg: $(obj)/% FORCE
 	$(call if_changed,imx_image)
+endif

 # ----------------------- i.MX25 based boards ---------------------------
 pblx-$(CONFIG_MACH_TX25) += start_imx25_karo_tx25
@@ -29,7 +36,18 @@ image-$(CONFIG_MACH_PCM038) += barebox-phytec-phycore-imx27.img
 pblx-$(CONFIG_MACH_FREESCALE_MX51_PDK) += start_imx51_babbage
 CFG_start_imx51_babbage.pblx.imximg = $(board)/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg
 FILE_barebox-freescale-imx51-babbage.img = start_imx51_babbage.pblx.imximg
-image-$(CONFIG_MACH_FREESCALE_MX51_PDK) += barebox-freescale-imx51-babbage.img
+imx-barebox-$(CONFIG_MACH_FREESCALE_MX51_PDK) += barebox-freescale-imx51-babbage.img
+
+pblx-$(CONFIG_MACH_FREESCALE_MX51_PDK) += start_imx51_babbage_xload
+CFG_start_imx51_babbage_xload.pblx.imximg = $(board)/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg
+FILE_barebox-freescale-imx51-babbage-xload.img = start_imx51_babbage_xload.pblx.imximg
+imx-xload-$(CONFIG_MACH_FREESCALE_MX51_PDK) += barebox-freescale-imx51-babbage-xload.img
+
+ifdef CONFIG_ARCH_IMX_XLOAD
+image-y += $(imx-xload-y)
+else
+image-y += $(imx-barebox-y)
+endif

 pblx-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += start_imx51_genesi_efikasb
 CFG_start_imx51_genesi_efikasb.pblx.imximg = $(board)/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg
--
2.1.4

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[PATCH 1/8] i.MX: Move UART definitions into a separate file

[Andrey Smirnov]

Move UART definitions into a separate file to avoid redefinition in
<mach/debug_ll.h> and magical constants in low level UART
initialization code.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/mach-imx/include/mach/debug_ll.h |   9 +--
 arch/arm/mach-imx/include/mach/serial.h   | 112 ++++++++++++++++++++++++++++++
 drivers/serial/serial_imx.c               | 108 +---------------------------
 3 files changed, 114 insertions(+), 115 deletions(-)
 create mode 100644 arch/arm/mach-imx/include/mach/serial.h

diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
index f34eaa1..1c9f3a6 100644
--- a/arch/arm/mach-imx/include/mach/debug_ll.h
+++ b/arch/arm/mach-imx/include/mach/debug_ll.h
@@ -12,6 +12,7 @@
 #include <mach/imx51-regs.h>
 #include <mach/imx53-regs.h>
 #include <mach/imx6-regs.h>
+#include <mach/serial.h>

 #ifdef CONFIG_DEBUG_LL

@@ -40,14 +41,6 @@
 #define __IMX_UART_BASE(soc, num) soc##_UART##num##_BASE_ADDR
 #define IMX_UART_BASE(soc, num) __IMX_UART_BASE(soc, num)

-#define URTX0		0x40		/* Transmitter Register */
-
-#define UCR1		0x80		/* Control Register 1 */
-#define UCR1_UARTEN	(1 << 0)	/* UART enabled */
-
-#define USR2		0x98		/* Status Register 2 */
-#define USR2_TXDC	(1 << 3)	/* Transmitter complete */
-
 static inline void PUTC_LL(int c)
 {
 	void __iomem *base = (void *)IMX_UART_BASE(IMX_DEBUG_SOC,
diff --git a/arch/arm/mach-imx/include/mach/serial.h b/arch/arm/mach-imx/include/mach/serial.h
new file mode 100644
index 0000000..b999c58
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/serial.h
@@ -0,0 +1,112 @@
+#ifndef __MACH_SERIAL_H__
+#define __MACH_SERIAL_H__
+
+#define URXD0	0x0	/* Receiver Register */
+#define URTX0	0x40	/* Transmitter Register */
+#define UCR1	0x80	/* Control Register 1 */
+#define UCR2	0x84	/* Control Register 2 */
+#define UCR3	0x88	/* Control Register 3 */
+#define UCR4	0x8c	/* Control Register 4 */
+#define UFCR	0x90	/* FIFO Control Register */
+#define USR1	0x94	/* Status Register 1 */
+#define USR2	0x98	/* Status Register 2 */
+#define UESC	0x9c	/* Escape Character Register */
+#define UTIM	0xa0	/* Escape Timer Register */
+#define UBIR	0xa4	/* BRM Incremental Register */
+#define UBMR	0xa8	/* BRM Modulator Register */
+#define UBRC	0xac	/* Baud Rate Count Register */
+
+/* UART Control Register Bit Fields.*/
+#define  URXD_CHARRDY    (1<<15)
+#define  URXD_ERR        (1<<14)
+#define  URXD_OVRRUN     (1<<13)
+#define  URXD_FRMERR     (1<<12)
+#define  URXD_BRK        (1<<11)
+#define  URXD_PRERR      (1<<10)
+#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
+#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
+#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
+#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
+#define  UCR1_RRDYEN     (1<<9)	 /* Recv ready interrupt enable */
+#define  UCR1_RDMAEN     (1<<8)	 /* Recv ready DMA enable */
+#define  UCR1_IREN       (1<<7)	 /* Infrared interface enable */
+#define  UCR1_TXMPTYEN   (1<<6)	 /* Transimitter empty interrupt enable */
+#define  UCR1_RTSDEN     (1<<5)	 /* RTS delta interrupt enable */
+#define  UCR1_SNDBRK     (1<<4)	 /* Send break */
+#define  UCR1_TDMAEN     (1<<3)	 /* Transmitter ready DMA enable */
+#define  UCR1_UARTCLKEN  (1<<2)	 /* UART clock enabled */
+#define  UCR1_DOZE       (1<<1)	 /* Doze */
+#define  UCR1_UARTEN     (1<<0)	 /* UART enabled */
+#define  UCR2_ESCI     	 (1<<15) /* Escape seq interrupt enable */
+#define  UCR2_IRTS  	 (1<<14) /* Ignore RTS pin */
+#define  UCR2_CTSC  	 (1<<13) /* CTS pin control */
+#define  UCR2_CTS        (1<<12) /* Clear to send */
+#define  UCR2_ESCEN      (1<<11) /* Escape enable */
+#define  UCR2_PREN       (1<<8)  /* Parity enable */
+#define  UCR2_PROE       (1<<7)  /* Parity odd/even */
+#define  UCR2_STPB       (1<<6)	 /* Stop */
+#define  UCR2_WS         (1<<5)	 /* Word size */
+#define  UCR2_RTSEN      (1<<4)	 /* Request to send interrupt enable */
+#define  UCR2_TXEN       (1<<2)	 /* Transmitter enabled */
+#define  UCR2_RXEN       (1<<1)	 /* Receiver enabled */
+#define  UCR2_SRST 	 (1<<0)	 /* SW reset */
+#define  UCR3_DTREN 	 (1<<13) /* DTR interrupt enable */
+#define  UCR3_PARERREN   (1<<12) /* Parity enable */
+#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
+#define  UCR3_DSR        (1<<10) /* Data set ready */
+#define  UCR3_DCD        (1<<9)  /* Data carrier detect */
+#define  UCR3_RI         (1<<8)  /* Ring indicator */
+#define  UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
+#define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */
+#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
+#define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */
+#define  UCR3_REF25 	 (1<<3)  /* Ref freq 25 MHz (i.MXL / i.MX1) */
+#define  UCR3_REF30 	 (1<<2)  /* Ref Freq 30 MHz (i.MXL / i.MX1) */
+#define  UCR3_RXDMUXSEL  (1<<2)  /* RXD Muxed input select (i.MX27) */
+#define  UCR3_INVT  	 (1<<1)  /* Inverted Infrared transmission */
+#define  UCR3_BPEN  	 (1<<0)  /* Preset registers enable */
+#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
+#define  UCR4_INVR  	 (1<<9)  /* Inverted infrared reception */
+#define  UCR4_ENIRI 	 (1<<8)  /* Serial infrared interrupt enable */
+#define  UCR4_WKEN  	 (1<<7)  /* Wake interrupt enable */
+#define  UCR4_REF16 	 (1<<6)  /* Ref freq 16 MHz */
+#define  UCR4_IRSC  	 (1<<5)  /* IR special case */
+#define  UCR4_TCEN  	 (1<<3)  /* Transmit complete interrupt enable */
+#define  UCR4_BKEN  	 (1<<2)  /* Break condition interrupt enable */
+#define  UCR4_OREN  	 (1<<1)  /* Receiver overrun interrupt enable */
+#define  UCR4_DREN  	 (1<<0)  /* Recv data ready interrupt enable */
+#define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
+#define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
+#define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
+#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
+#define  USR1_RTSS  	 (1<<14) /* RTS pin status */
+#define  USR1_TRDY  	 (1<<13) /* Transmitter ready interrupt/dma flag */
+#define  USR1_RTSD  	 (1<<12) /* RTS delta */
+#define  USR1_ESCF  	 (1<<11) /* Escape seq interrupt flag */
+#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
+#define  USR1_RRDY       (1<<9)	 /* Receiver ready interrupt/dma flag */
+#define  USR1_TIMEOUT    (1<<7)	 /* Receive timeout interrupt status */
+#define  USR1_RXDS  	 (1<<6)	 /* Receiver idle interrupt flag */
+#define  USR1_AIRINT	 (1<<5)	 /* Async IR wake interrupt flag */
+#define  USR1_AWAKE 	 (1<<4)	 /* Aysnc wake interrupt flag */
+#define  USR2_ADET  	 (1<<15) /* Auto baud rate detect complete */
+#define  USR2_TXFE  	 (1<<14) /* Transmit buffer FIFO empty */
+#define  USR2_DTRF  	 (1<<13) /* DTR edge interrupt flag */
+#define  USR2_IDLE  	 (1<<12) /* Idle condition */
+#define  USR2_IRINT 	 (1<<8)	 /* Serial infrared interrupt flag */
+#define  USR2_WAKE  	 (1<<7)	 /* Wake */
+#define  USR2_RTSF  	 (1<<4)	 /* RTS edge interrupt flag */
+#define  USR2_TXDC  	 (1<<3)	 /* Transmitter complete */
+#define  USR2_BRCD  	 (1<<2)	 /* Break condition */
+#define  USR2_ORE        (1<<1)	 /* Overrun error */
+#define  USR2_RDR        (1<<0)	 /* Recv data ready */
+#define  UTS_FRCPERR	 (1<<13) /* Force parity error */
+#define  UTS_LOOP        (1<<12) /* Loop tx and rx */
+#define  UTS_TXEMPTY	 (1<<6)	 /* TxFIFO empty */
+#define  UTS_RXEMPTY	 (1<<5)	 /* RxFIFO empty */
+#define  UTS_TXFULL 	 (1<<4)	 /* TxFIFO full */
+#define  UTS_RXFULL 	 (1<<3)	 /* RxFIFO full */
+#define  UTS_SOFTRST	 (1<<0)	 /* Software reset */
+
+
+#endif	/* __MACH_SERIAL_H__ */
diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c
index cd954c2..e197be8 100644
--- a/drivers/serial/serial_imx.c
+++ b/drivers/serial/serial_imx.c
@@ -23,113 +23,7 @@
 #include <of.h>
 #include <linux/err.h>
 #include <linux/clk.h>
-
-#define URXD0	0x0	/* Receiver Register */
-#define URTX0	0x40	/* Transmitter Register */
-#define UCR1	0x80	/* Control Register 1 */
-#define UCR2	0x84	/* Control Register 2 */
-#define UCR3	0x88	/* Control Register 3 */
-#define UCR4	0x8c	/* Control Register 4 */
-#define UFCR	0x90	/* FIFO Control Register */
-#define USR1	0x94	/* Status Register 1 */
-#define USR2	0x98	/* Status Register 2 */
-#define UESC	0x9c	/* Escape Character Register */
-#define UTIM	0xa0	/* Escape Timer Register */
-#define UBIR	0xa4	/* BRM Incremental Register */
-#define UBMR	0xa8	/* BRM Modulator Register */
-#define UBRC	0xac	/* Baud Rate Count Register */
-
-/* UART Control Register Bit Fields.*/
-#define  URXD_CHARRDY    (1<<15)
-#define  URXD_ERR        (1<<14)
-#define  URXD_OVRRUN     (1<<13)
-#define  URXD_FRMERR     (1<<12)
-#define  URXD_BRK        (1<<11)
-#define  URXD_PRERR      (1<<10)
-#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
-#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
-#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
-#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
-#define  UCR1_RRDYEN     (1<<9)	 /* Recv ready interrupt enable */
-#define  UCR1_RDMAEN     (1<<8)	 /* Recv ready DMA enable */
-#define  UCR1_IREN       (1<<7)	 /* Infrared interface enable */
-#define  UCR1_TXMPTYEN   (1<<6)	 /* Transimitter empty interrupt enable */
-#define  UCR1_RTSDEN     (1<<5)	 /* RTS delta interrupt enable */
-#define  UCR1_SNDBRK     (1<<4)	 /* Send break */
-#define  UCR1_TDMAEN     (1<<3)	 /* Transmitter ready DMA enable */
-#define  UCR1_UARTCLKEN  (1<<2)	 /* UART clock enabled */
-#define  UCR1_DOZE       (1<<1)	 /* Doze */
-#define  UCR1_UARTEN     (1<<0)	 /* UART enabled */
-#define  UCR2_ESCI     	 (1<<15) /* Escape seq interrupt enable */
-#define  UCR2_IRTS  	 (1<<14) /* Ignore RTS pin */
-#define  UCR2_CTSC  	 (1<<13) /* CTS pin control */
-#define  UCR2_CTS        (1<<12) /* Clear to send */
-#define  UCR2_ESCEN      (1<<11) /* Escape enable */
-#define  UCR2_PREN       (1<<8)  /* Parity enable */
-#define  UCR2_PROE       (1<<7)  /* Parity odd/even */
-#define  UCR2_STPB       (1<<6)	 /* Stop */
-#define  UCR2_WS         (1<<5)	 /* Word size */
-#define  UCR2_RTSEN      (1<<4)	 /* Request to send interrupt enable */
-#define  UCR2_TXEN       (1<<2)	 /* Transmitter enabled */
-#define  UCR2_RXEN       (1<<1)	 /* Receiver enabled */
-#define  UCR2_SRST 	 (1<<0)	 /* SW reset */
-#define  UCR3_DTREN 	 (1<<13) /* DTR interrupt enable */
-#define  UCR3_PARERREN   (1<<12) /* Parity enable */
-#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
-#define  UCR3_DSR        (1<<10) /* Data set ready */
-#define  UCR3_DCD        (1<<9)  /* Data carrier detect */
-#define  UCR3_RI         (1<<8)  /* Ring indicator */
-#define  UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
-#define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */
-#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
-#define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */
-#define  UCR3_REF25 	 (1<<3)  /* Ref freq 25 MHz (i.MXL / i.MX1) */
-#define  UCR3_REF30 	 (1<<2)  /* Ref Freq 30 MHz (i.MXL / i.MX1) */
-#define  UCR3_RXDMUXSEL  (1<<2)  /* RXD Muxed input select (i.MX27) */
-#define  UCR3_INVT  	 (1<<1)  /* Inverted Infrared transmission */
-#define  UCR3_BPEN  	 (1<<0)  /* Preset registers enable */
-#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
-#define  UCR4_INVR  	 (1<<9)  /* Inverted infrared reception */
-#define  UCR4_ENIRI 	 (1<<8)  /* Serial infrared interrupt enable */
-#define  UCR4_WKEN  	 (1<<7)  /* Wake interrupt enable */
-#define  UCR4_REF16 	 (1<<6)  /* Ref freq 16 MHz */
-#define  UCR4_IRSC  	 (1<<5)  /* IR special case */
-#define  UCR4_TCEN  	 (1<<3)  /* Transmit complete interrupt enable */
-#define  UCR4_BKEN  	 (1<<2)  /* Break condition interrupt enable */
-#define  UCR4_OREN  	 (1<<1)  /* Receiver overrun interrupt enable */
-#define  UCR4_DREN  	 (1<<0)  /* Recv data ready interrupt enable */
-#define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
-#define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
-#define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
-#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
-#define  USR1_RTSS  	 (1<<14) /* RTS pin status */
-#define  USR1_TRDY  	 (1<<13) /* Transmitter ready interrupt/dma flag */
-#define  USR1_RTSD  	 (1<<12) /* RTS delta */
-#define  USR1_ESCF  	 (1<<11) /* Escape seq interrupt flag */
-#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
-#define  USR1_RRDY       (1<<9)	 /* Receiver ready interrupt/dma flag */
-#define  USR1_TIMEOUT    (1<<7)	 /* Receive timeout interrupt status */
-#define  USR1_RXDS  	 (1<<6)	 /* Receiver idle interrupt flag */
-#define  USR1_AIRINT	 (1<<5)	 /* Async IR wake interrupt flag */
-#define  USR1_AWAKE 	 (1<<4)	 /* Aysnc wake interrupt flag */
-#define  USR2_ADET  	 (1<<15) /* Auto baud rate detect complete */
-#define  USR2_TXFE  	 (1<<14) /* Transmit buffer FIFO empty */
-#define  USR2_DTRF  	 (1<<13) /* DTR edge interrupt flag */
-#define  USR2_IDLE  	 (1<<12) /* Idle condition */
-#define  USR2_IRINT 	 (1<<8)	 /* Serial infrared interrupt flag */
-#define  USR2_WAKE  	 (1<<7)	 /* Wake */
-#define  USR2_RTSF  	 (1<<4)	 /* RTS edge interrupt flag */
-#define  USR2_TXDC  	 (1<<3)	 /* Transmitter complete */
-#define  USR2_BRCD  	 (1<<2)	 /* Break condition */
-#define  USR2_ORE        (1<<1)	 /* Overrun error */
-#define  USR2_RDR        (1<<0)	 /* Recv data ready */
-#define  UTS_FRCPERR	 (1<<13) /* Force parity error */
-#define  UTS_LOOP        (1<<12) /* Loop tx and rx */
-#define  UTS_TXEMPTY	 (1<<6)	 /* TxFIFO empty */
-#define  UTS_RXEMPTY	 (1<<5)	 /* RxFIFO empty */
-#define  UTS_TXFULL 	 (1<<4)	 /* TxFIFO full */
-#define  UTS_RXFULL 	 (1<<3)	 /* RxFIFO full */
-#define  UTS_SOFTRST	 (1<<0)	 /* Software reset */
+#include <mach/serial.h>

 /*
  * create default values for different platforms
--
2.1.4

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[PATCH 2/8] i.MX: serial: Add constants for UART clock divisor

[Andrey Smirnov]

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/mach-imx/include/mach/serial.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-imx/include/mach/serial.h b/arch/arm/mach-imx/include/mach/serial.h
index b999c58..3890fd5 100644
--- a/arch/arm/mach-imx/include/mach/serial.h
+++ b/arch/arm/mach-imx/include/mach/serial.h
@@ -77,6 +77,13 @@
 #define  UCR4_DREN  	 (1<<0)  /* Recv data ready interrupt enable */
 #define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 #define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
+#define	 UFCR_RFDIV6	  (0b000<<7)  /* Reference freq divider mask */
+#define	 UFCR_RFDIV5	  (0b001<<7)  /* Reference freq divider mask */
+#define	 UFCR_RFDIV4	  (0b010<<7)  /* Reference freq divider mask */
+#define	 UFCR_RFDIV3	  (0b011<<7)  /* Reference freq divider mask */
+#define	 UFCR_RFDIV2	  (0b100<<7)  /* Reference freq divider mask */
+#define	 UFCR_RFDIV1	  (0b101<<7)  /* Reference freq divider mask */
+#define	 UFCR_RFDIV7	  (0b110<<7)  /* Reference freq divider mask */
 #define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 #define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 #define  USR1_RTSS  	 (1<<14) /* RTS pin status */
--
2.1.4

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[PATCH 3/8] i.MX: serial: Add baud rate calculation convenience functions

[Andrey Smirnov]

Add two functions to calculate values for UBMR and UBIR
registers. This way both early serial initalization code and
serial_imx.c can use them and not duplicate the code.

Singed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/mach-imx/include/mach/serial.h | 9 +++++++++
 drivers/serial/serial_imx.c             | 4 ++--
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/include/mach/serial.h b/arch/arm/mach-imx/include/mach/serial.h
index 3890fd5..212eeeb 100644
--- a/arch/arm/mach-imx/include/mach/serial.h
+++ b/arch/arm/mach-imx/include/mach/serial.h
@@ -115,5 +115,14 @@
 #define  UTS_RXFULL 	 (1<<3)	 /* RxFIFO full */
 #define  UTS_SOFTRST	 (1<<0)	 /* Software reset */

+static inline int baudrate_to_ubir(int baudrate)
+{
+	return baudrate / 100 - 1;
+}
+
+static inline int refclock_to_ubmr(int clock_hz)
+{
+	return clock_hz / 1600 - 1;
+}

 #endif	/* __MACH_SERIAL_H__ */
diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c
index e197be8..8c4e829 100644
--- a/drivers/serial/serial_imx.c
+++ b/drivers/serial/serial_imx.c
@@ -178,9 +178,9 @@ static int imx_serial_setbaudrate(struct console_device *cdev, int baudrate)
 	writel(val, regs + UCR1);

 	/* Set the numerator value minus one of the BRM ratio */
-	writel((baudrate / 100) - 1, regs + UBIR);
+	writel(baudrate_to_ubir(baudrate), regs + UBIR);
 	/* Set the denominator value minus one of the BRM ratio    */
-	writel((imx_serial_reffreq(priv) / 1600) - 1, regs + UBMR);
+	writel(refclock_to_ubmr(imx_serial_reffreq(priv)), regs + UBMR);

 	writel(ucr1, regs + UCR1);

--
2.1.4

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[PATCH 4/8] i.MX51: babbage: Implement CONFIG_DEBUG_LL

[Andrey Smirnov]

Implement bits of configuraion needed to configure early debug output
support.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/boards/freescale-mx51-babbage/lowlevel.c | 58 +++++++++++++++++++++++
 arch/arm/mach-imx/include/mach/clock-imx51_53.h   |  5 +-
 2 files changed, 61 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
index 0f453f3..0135cb4 100644
--- a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
+++ b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
@@ -1,9 +1,63 @@
+#include <debug_ll.h>
+#include <mach/clock-imx51_53.h>
 #include <common.h>
 #include <mach/esdctl.h>
 #include <mach/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>

+#ifdef CONFIG_DEBUG_LL
+static inline void setup_uart(void)
+{
+
+	void __iomem *uartbase =
+	  (void *)IMX_UART_BASE(IMX_DEBUG_SOC,
+				CONFIG_DEBUG_IMX_UART_PORT);
+	void __iomem *iomuxbase = (void *)MX51_IOMUXC_BASE_ADDR;
+	void __iomem *ccmbase = (void *)MX51_CCM_BASE_ADDR;
+
+	/*
+	 * Restore CCM values that might be changed by the Mask ROM
+	 * code.
+	 *
+	 * Source: RealView debug scripts provided by Freescale
+	 */
+	writel(MX5_CCM_CBCDR_RESET_VALUE,  ccmbase + MX5_CCM_CBCDR);
+	writel(MX5_CCM_CSCMR1_RESET_VALUE, ccmbase + MX5_CCM_CSCMR1);
+	writel(MX5_CCM_CSCDR1_RESET_VALUE, ccmbase + MX5_CCM_CSCDR1);
+
+	/*
+	 * The code below should be more or less a "moral equivalent"
+	 * of:
+	 *	 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
+	 *
+	 * in device tree
+	 */
+	writel(0x00000000, iomuxbase + 0x022c);
+	writel(0x000001c5, iomuxbase + 0x061c);
+
+	writel(0x00000000, uartbase + UCR1);
+
+	writel(UCR2_IRTS | UCR2_WS | UCR2_TXEN | UCR2_RXEN | UCR2_SRST,
+	       uartbase + UCR2);
+	writel(UCR3_DSR | UCR3_DCD | UCR3_RI | UCR3_ADNIMP | UCR3_RXDMUXSEL,
+	       uartbase + UCR3);
+	writel((0b10 << UFCR_TXTL_SHF) | UFCR_RFDIV1 | (1 << UFCR_RXTL_SHF),
+	       uartbase + UFCR);
+
+	writel(baudrate_to_ubir(115200), uartbase + UBIR);
+	writel(refclock_to_ubmr(54000000), uartbase + UBMR);
+
+	writel(UCR1_UARTEN, uartbase + UCR1);
+
+	putc_ll('>');
+}
+#else
+static inline void setup_uart(void)
+{
+}
+#endif	/* CONFIG_DEBUG_LL */
+
 extern char __dtb_imx51_babbage_start[];

 ENTRY_FUNCTION(start_imx51_babbage, r0, r1, r2)
@@ -11,6 +65,10 @@ ENTRY_FUNCTION(start_imx51_babbage, r0, r1, r2)
 	void *fdt;

 	imx5_cpu_lowlevel_init();
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
 	arm_setup_stack(0x20000000 - 16);

 	fdt = __dtb_imx51_babbage_start - get_runtime_offset();
diff --git a/arch/arm/mach-imx/include/mach/clock-imx51_53.h b/arch/arm/mach-imx/include/mach/clock-imx51_53.h
index 6004a6d..0f25dfb 100644
--- a/arch/arm/mach-imx/include/mach/clock-imx51_53.h
+++ b/arch/arm/mach-imx/include/mach/clock-imx51_53.h
@@ -149,6 +149,7 @@
 #define MX5_CCM_CACRR_ARM_PODF_MASK	(0x7)

 /* Define the bits in register CBCDR */
+#define MX5_CCM_CBCDR_RESET_VALUE		(0x19239145)
 #define MX5_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
 #define MX5_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
 #define MX5_CCM_CBCDR_DDR_HF_SEL_OFFSET		(30)
@@ -193,6 +194,7 @@
 #define MX5_CCM_CBCMR_PERCLK_IPG_CLK_SEL	(0x1 << 0)

 /* Define the bits in register CSCMR1 */
+#define MX5_CCM_CSCMR1_RESET_VALUE			(0xa6a2a020)
 #define MX5_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		(30)
 #define MX5_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK		(0x3 << 30)
 #define MX5_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET		(28)
@@ -259,6 +261,7 @@
 #define MX5_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK		(0x3)

 /* Define the bits in register CSCDR1 */
+#define MX5_CCM_CSCDR1_RESET_VALUE			(0x00c30318)
 #define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	(22)
 #define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK	(0x7 << 22)
 #define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	(19)
@@ -585,5 +588,3 @@
 #define MX5_SRPGC_EMI_PDNSCR	(MX5_SRPGC_EMI_BASE + 0x8)

 #endif				/* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
-
-
--
2.1.4

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[PATCH 5/8] i.MX: serial: Add setup_uart_ll function

[Andrey Smirnov]

It appears that all i.MX based boards that support early debug output
inevitably do exactly the same thing with the registers of the UART
peripheral. So to avoid code duplication distill that functionality
into dedicated subroutine.

IMPORTANT: Please note that 'setup_uart_ll' function does add a slight
difference in behaviour by dropping the initialization of ONEMS and
UESC registers since those do not seem to be needed for early UART
functionality

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/mach-imx/include/mach/debug_ll.h | 34 +++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
index 1c9f3a6..5b0b33b 100644
--- a/arch/arm/mach-imx/include/mach/debug_ll.h
+++ b/arch/arm/mach-imx/include/mach/debug_ll.h
@@ -30,10 +30,12 @@
 #define IMX_DEBUG_SOC MX35
 #elif defined CONFIG_DEBUG_IMX51_UART
 #define IMX_DEBUG_SOC MX51
+#define IMX_DEBUG_UART_REFCLOCK_HZ 54000000
 #elif defined CONFIG_DEBUG_IMX53_UART
 #define IMX_DEBUG_SOC MX53
 #elif defined CONFIG_DEBUG_IMX6Q_UART
 #define IMX_DEBUG_SOC MX6
+#define IMX_DEBUG_UART_REFCLOCK_HZ 80000000
 #else
 #error "unknown i.MX debug uart soc type"
 #endif
@@ -41,6 +43,34 @@
 #define __IMX_UART_BASE(soc, num) soc##_UART##num##_BASE_ADDR
 #define IMX_UART_BASE(soc, num) __IMX_UART_BASE(soc, num)

+
+#if defined IMX_DEBUG_UART_REFCLOCK_HZ
+
+static inline void setup_uart_ll(void)
+{
+	void __iomem *uartbase =
+	  (void *)IMX_UART_BASE(IMX_DEBUG_SOC,
+				CONFIG_DEBUG_IMX_UART_PORT);
+
+	writel(0x00000000, uartbase + UCR1);
+
+	writel(UCR2_IRTS | UCR2_WS | UCR2_TXEN | UCR2_RXEN | UCR2_SRST,
+	       uartbase + UCR2);
+	writel(UCR3_DSR | UCR3_DCD | UCR3_RI | UCR3_ADNIMP | UCR3_RXDMUXSEL,
+	       uartbase + UCR3);
+	writel((0b10 << UFCR_TXTL_SHF) | UFCR_RFDIV1 | (1 << UFCR_RXTL_SHF),
+	       uartbase + UFCR);
+
+	writel(baudrate_to_ubir(CONFIG_BAUDRATE),
+	       uartbase + UBIR);
+	writel(refclock_to_ubmr(IMX_DEBUG_UART_REFCLOCK_HZ),
+	       uartbase + UBMR);
+
+	writel(UCR1_UARTEN, uartbase + UCR1);
+}
+
+#endif
+
 static inline void PUTC_LL(int c)
 {
 	void __iomem *base = (void *)IMX_UART_BASE(IMX_DEBUG_SOC,
@@ -56,5 +86,9 @@ static inline void PUTC_LL(int c)

 	writel(c, base + URTX0);
 }
+#else
+static inline void setup_uart_ll(void)
+{
+}
 #endif /* CONFIG_DEBUG_LL */
 #endif /* __MACH_DEBUG_LL_H__ */
--
2.1.4

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[PATCH 6/8] i.MX: serial: Convert i.MX51 and i.MX6 to use 'setup_uart_ll'

[Andrey Smirnov]

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---

Two boards -- 'guf-santaro' and 'eltec-hipercam' -- were not
converted to use this function because they enable low-level UART
regardless of the value of CONFIG_DEGUG_LL and so converting them to
'setup_uart_ll' would change the behaviour of the image build with
'imx_v7_defconfig'. Should those boards be converted to respect
CONFIG_DEBUG_LL?

Boards 'karo-tx25' and 'tqma53' could be converted but weren't because
I don't have any i.MX25 or i.MX53 based hardware to test on.


 arch/arm/boards/embest-riotboard/lowlevel.c        | 16 +--------------
 arch/arm/boards/freescale-mx51-babbage/lowlevel.c  | 24 +---------------------
 .../arm/boards/freescale-mx6sx-sabresdb/lowlevel.c | 11 +---------
 arch/arm/boards/karo-tx6x/lowlevel.c               | 11 +---------
 arch/arm/boards/phytec-phycard-imx6/lowlevel.c     | 11 +---------
 arch/arm/boards/phytec-phyflex-imx6/lowlevel.c     | 11 +---------
 arch/arm/boards/tqma53/lowlevel.c                  | 16 +--------------
 arch/arm/boards/tqma6x/lowlevel.c                  | 18 ++--------------
 arch/arm/boards/variscite-mx6/lowlevel.c           | 11 +---------
 9 files changed, 10 insertions(+), 119 deletions(-)

diff --git a/arch/arm/boards/embest-riotboard/lowlevel.c b/arch/arm/boards/embest-riotboard/lowlevel.c
index fe21b9a..ccd1a97 100644
--- a/arch/arm/boards/embest-riotboard/lowlevel.c
+++ b/arch/arm/boards/embest-riotboard/lowlevel.c
@@ -10,20 +10,6 @@
 #include <mach/imx6-mmdc.h>
 #include <mach/imx6.h>

-static inline void setup_uart(void)
-{
-	/* Enable UART for lowlevel debugging purposes */
-	writel(0x00000000, 0x021e8080);
-	writel(0x00004027, 0x021e8084);
-	writel(0x00000704, 0x021e8088);
-	writel(0x00000a81, 0x021e8090);
-	writel(0x0000002b, 0x021e809c);
-	writel(0x00013880, 0x021e80b0);
-	writel(0x0000047f, 0x021e80a4);
-	writel(0x0000c34f, 0x021e80a8);
-	writel(0x00000001, 0x021e8080);
-}
-
 extern char __dtb_imx6s_riotboard_start[];

 ENTRY_FUNCTION(start_imx6s_riotboard, r0, r1, r2)
@@ -34,7 +20,7 @@ ENTRY_FUNCTION(start_imx6s_riotboard, r0, r1, r2)

 	if (IS_ENABLED(CONFIG_DEBUG_LL)) {
 		writel(0x4, 0x020e016c);
-		setup_uart();
+		setup_uart_ll();
 		putc_ll('a');
 	}

diff --git a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
index 0135cb4..3bb8614 100644
--- a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
+++ b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
@@ -6,13 +6,8 @@
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>

-#ifdef CONFIG_DEBUG_LL
 static inline void setup_uart(void)
 {
-
-	void __iomem *uartbase =
-	  (void *)IMX_UART_BASE(IMX_DEBUG_SOC,
-				CONFIG_DEBUG_IMX_UART_PORT);
 	void __iomem *iomuxbase = (void *)MX51_IOMUXC_BASE_ADDR;
 	void __iomem *ccmbase = (void *)MX51_CCM_BASE_ADDR;

@@ -36,27 +31,10 @@ static inline void setup_uart(void)
 	writel(0x00000000, iomuxbase + 0x022c);
 	writel(0x000001c5, iomuxbase + 0x061c);

-	writel(0x00000000, uartbase + UCR1);
-
-	writel(UCR2_IRTS | UCR2_WS | UCR2_TXEN | UCR2_RXEN | UCR2_SRST,
-	       uartbase + UCR2);
-	writel(UCR3_DSR | UCR3_DCD | UCR3_RI | UCR3_ADNIMP | UCR3_RXDMUXSEL,
-	       uartbase + UCR3);
-	writel((0b10 << UFCR_TXTL_SHF) | UFCR_RFDIV1 | (1 << UFCR_RXTL_SHF),
-	       uartbase + UFCR);
-
-	writel(baudrate_to_ubir(115200), uartbase + UBIR);
-	writel(refclock_to_ubmr(54000000), uartbase + UBMR);
-
-	writel(UCR1_UARTEN, uartbase + UCR1);
+	setup_uart_ll();

 	putc_ll('>');
 }
-#else
-static inline void setup_uart(void)
-{
-}
-#endif	/* CONFIG_DEBUG_LL */

 extern char __dtb_imx51_babbage_start[];

diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c b/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c
index 4c5a74e..a8d16cb 100644
--- a/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c
+++ b/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c
@@ -22,7 +22,6 @@
 static inline void setup_uart(void)
 {
 	void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR;
-	void __iomem *uartbase = (void *)MX6_UART1_BASE_ADDR;
 	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;

 	writel(0xffffffff, ccmbase + 0x68);
@@ -38,15 +37,7 @@ static inline void setup_uart(void)
 	writel(0x0, iomuxbase + 0x28);
 	writel(0x1b0b1, iomuxbase + 0x0370);

-	writel(0x00000000, uartbase + 0x80);
-	writel(0x00004027, uartbase + 0x84);
-	writel(0x00000784, uartbase + 0x88);
-	writel(0x00000a81, uartbase + 0x90);
-	writel(0x0000002b, uartbase + 0x9c);
-	writel(0x0001b0b0, uartbase + 0xb0);
-	writel(0x0000047f, uartbase + 0xa4);
-	writel(0x0000c34f, uartbase + 0xa8);
-	writel(0x00000001, uartbase + 0x80);
+	setup_uart_ll();

 	putc_ll('>');
 }
diff --git a/arch/arm/boards/karo-tx6x/lowlevel.c b/arch/arm/boards/karo-tx6x/lowlevel.c
index cd4be5e..3f9fb23 100644
--- a/arch/arm/boards/karo-tx6x/lowlevel.c
+++ b/arch/arm/boards/karo-tx6x/lowlevel.c
@@ -23,7 +23,6 @@
 static inline void setup_uart(void)
 {
 	void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR;
-	void __iomem *uartbase = (void *)MX6_UART1_BASE_ADDR;
 	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;

 	writel(0x1, iomuxbase + 0x0314);
@@ -39,15 +38,7 @@ static inline void setup_uart(void)
 	writel(0xffffffff, ccmbase + 0x7c);
 	writel(0xffffffff, ccmbase + 0x80);

-	writel(0x00000000, uartbase + 0x80);
-	writel(0x00004027, uartbase + 0x84);
-	writel(0x00000784, uartbase + 0x88);
-	writel(0x00000a81, uartbase + 0x90);
-	writel(0x0000002b, uartbase + 0x9c);
-	writel(0x0001b0b0, uartbase + 0xb0);
-	writel(0x0000047f, uartbase + 0xa4);
-	writel(0x0000c34f, uartbase + 0xa8);
-	writel(0x00000001, uartbase + 0x80);
+	setup_uart_ll();

 	putc_ll('>');
 }
diff --git a/arch/arm/boards/phytec-phycard-imx6/lowlevel.c b/arch/arm/boards/phytec-phycard-imx6/lowlevel.c
index dc10649..1d48818 100644
--- a/arch/arm/boards/phytec-phycard-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-phycard-imx6/lowlevel.c
@@ -27,7 +27,6 @@
 static inline void setup_uart(void)
 {
 	void __iomem *ccmbase = IOMEM(MX6_CCM_BASE_ADDR);
-	void __iomem *uartbase = IOMEM(MX6_UART3_BASE_ADDR);
 	void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR);

 	writel(0x4, iomuxbase + 0x01f8);
@@ -40,15 +39,7 @@ static inline void setup_uart(void)
 	writel(0xffffffff, ccmbase + 0x7c);
 	writel(0xffffffff, ccmbase + 0x80);

-	writel(0x00000000, uartbase + 0x80);
-	writel(0x00004027, uartbase + 0x84);
-	writel(0x00000704, uartbase + 0x88);
-	writel(0x00000a81, uartbase + 0x90);
-	writel(0x0000002b, uartbase + 0x9c);
-	writel(0x00013880, uartbase + 0xb0);
-	writel(0x0000047f, uartbase + 0xa4);
-	writel(0x0000c34f, uartbase + 0xa8);
-	writel(0x00000001, uartbase + 0x80);
+	setup_uart_ll();

 	putc_ll('>');
 }
diff --git a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c
index ee6d7fb..367d4dc 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c
@@ -28,7 +28,6 @@
 static inline void setup_uart(void)
 {
 	void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR;
-	void __iomem *uartbase = (void *)MX6_UART4_BASE_ADDR;
 	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;

 	writel(0x4, iomuxbase + 0x01f8);
@@ -41,15 +40,7 @@ static inline void setup_uart(void)
 	writel(0xffffffff, ccmbase + 0x7c);
 	writel(0xffffffff, ccmbase + 0x80);

-	writel(0x00000000, uartbase + 0x80);
-	writel(0x00004027, uartbase + 0x84);
-	writel(0x00000704, uartbase + 0x88);
-	writel(0x00000a81, uartbase + 0x90);
-	writel(0x0000002b, uartbase + 0x9c);
-	writel(0x00013880, uartbase + 0xb0);
-	writel(0x0000047f, uartbase + 0xa4);
-	writel(0x0000c34f, uartbase + 0xa8);
-	writel(0x00000001, uartbase + 0x80);
+	setup_uart_ll();

 	putc_ll('>');
 }
diff --git a/arch/arm/boards/tqma53/lowlevel.c b/arch/arm/boards/tqma53/lowlevel.c
index 4e129e4..f3eb1ad 100644
--- a/arch/arm/boards/tqma53/lowlevel.c
+++ b/arch/arm/boards/tqma53/lowlevel.c
@@ -10,26 +10,12 @@

 extern char __dtb_imx53_mba53_start[];

-static inline void setup_uart(void __iomem *base)
-{
-	/* Enable UART for lowlevel debugging purposes */
-	writel(0x00000000, base + 0x80);
-	writel(0x00004027, base + 0x84);
-	writel(0x00000704, base + 0x88);
-	writel(0x00000a81, base + 0x90);
-	writel(0x0000002b, base + 0x9c);
-	writel(0x0001046a, base + 0xb0);
-	writel(0x0000047f, base + 0xa4);
-	writel(0x0000a2c1, base + 0xa8);
-	writel(0x00000001, base + 0x80);
-}
-
 static void __noreturn start_imx53_tqma53_common(void *fdt)
 {
 	if (IS_ENABLED(CONFIG_DEBUG_LL)) {
 		writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x278);
 		writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x27c);
-		setup_uart((void *)MX53_UART2_BASE_ADDR);
+		setup_uart_ll();
 		putc_ll('>');
 	}

diff --git a/arch/arm/boards/tqma6x/lowlevel.c b/arch/arm/boards/tqma6x/lowlevel.c
index 23f3407..1de60d8 100644
--- a/arch/arm/boards/tqma6x/lowlevel.c
+++ b/arch/arm/boards/tqma6x/lowlevel.c
@@ -24,20 +24,6 @@
 #include <mach/imx6-mmdc.h>
 #include <mach/imx6.h>

-static inline void setup_uart(void)
-{
-	/* Enable UART for lowlevel debugging purposes */
-	writel(0x00000000, 0x021e8080);
-	writel(0x00004027, 0x021e8084);
-	writel(0x00000704, 0x021e8088);
-	writel(0x00000a81, 0x021e8090);
-	writel(0x0000002b, 0x021e809c);
-	writel(0x00013880, 0x021e80b0);
-	writel(0x0000047f, 0x021e80a4);
-	writel(0x0000c34f, 0x021e80a8);
-	writel(0x00000001, 0x021e8080);
-}
-
 extern char __dtb_imx6q_mba6x_start[];
 extern char __dtb_imx6dl_mba6x_start[];

@@ -51,7 +37,7 @@ ENTRY_FUNCTION(start_imx6q_mba6x, r0, r1, r2)

 	if (IS_ENABLED(CONFIG_DEBUG_LL)) {
 		writel(0x2, 0x020e0338);
-		setup_uart();
+		setup_uart_ll();
 		putc_ll('a');
 	}

@@ -72,7 +58,7 @@ ENTRY_FUNCTION(start_imx6dl_mba6x, r0, r1, r2)

 	if (IS_ENABLED(CONFIG_DEBUG_LL)) {
 		writel(0x2, 0x020e035c);
-		setup_uart();
+		setup_uart_ll();
 		putc_ll('a');
 	}

diff --git a/arch/arm/boards/variscite-mx6/lowlevel.c b/arch/arm/boards/variscite-mx6/lowlevel.c
index 22e7eae..b0ab424 100644
--- a/arch/arm/boards/variscite-mx6/lowlevel.c
+++ b/arch/arm/boards/variscite-mx6/lowlevel.c
@@ -29,7 +29,6 @@
 static inline void setup_uart(void)
 {
 	void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR;
-	void __iomem *uartbase = (void *)MX6_UART1_BASE_ADDR;
 	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;

 	writel(0x03, iomuxbase + 0x0280);
@@ -43,15 +42,7 @@ static inline void setup_uart(void)
 	writel(0xffffffff, ccmbase + 0x7c);
 	writel(0xffffffff, ccmbase + 0x80);

-	writel(0x00000000, uartbase + 0x80);
-	writel(0x00004027, uartbase + 0x84);
-	writel(0x00000704, uartbase + 0x88);
-	writel(0x00000a81, uartbase + 0x90);
-	writel(0x0000002b, uartbase + 0x9c);
-	writel(0x00013880, uartbase + 0xb0);
-	writel(0x0000047f, uartbase + 0xa4);
-	writel(0x0000c34f, uartbase + 0xa8);
-	writel(0x00000001, uartbase + 0x80);
+	setup_uart_ll();

 	putc_ll('>');
 }
--
2.1.4

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[PATCH 7/8] i.MX: serial: Distil common clock ungating code

[Andrey Smirnov]

Move all of the common clock ungating code in early UART
initialization into a dedicated subroutine that can be shared by all
of the users.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c |  9 +--------
 arch/arm/boards/karo-tx6x/lowlevel.c                | 10 +---------
 arch/arm/boards/phytec-phycard-imx6/lowlevel.c      | 10 +---------
 arch/arm/boards/phytec-phyflex-imx6/lowlevel.c      | 10 +---------
 arch/arm/boards/variscite-mx6/lowlevel.c            | 10 +---------
 arch/arm/mach-imx/include/mach/debug_ll.h           | 17 +++++++++++++++++
 6 files changed, 22 insertions(+), 44 deletions(-)

diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c b/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c
index a8d16cb..fd154df 100644
--- a/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c
+++ b/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c
@@ -21,16 +21,9 @@

 static inline void setup_uart(void)
 {
-	void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR;
 	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;

-	writel(0xffffffff, ccmbase + 0x68);
-	writel(0xffffffff, ccmbase + 0x6c);
-	writel(0xffffffff, ccmbase + 0x70);
-	writel(0xffffffff, ccmbase + 0x74);
-	writel(0xffffffff, ccmbase + 0x78);
-	writel(0xffffffff, ccmbase + 0x7c);
-	writel(0xffffffff, ccmbase + 0x80);
+	ungate_all_peripherals();

 	writel(0x0, iomuxbase + 0x24);
 	writel(0x1b0b1, iomuxbase + 0x036C);
diff --git a/arch/arm/boards/karo-tx6x/lowlevel.c b/arch/arm/boards/karo-tx6x/lowlevel.c
index 3f9fb23..d7087f5 100644
--- a/arch/arm/boards/karo-tx6x/lowlevel.c
+++ b/arch/arm/boards/karo-tx6x/lowlevel.c
@@ -22,7 +22,6 @@

 static inline void setup_uart(void)
 {
-	void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR;
 	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;

 	writel(0x1, iomuxbase + 0x0314);
@@ -30,14 +29,7 @@ static inline void setup_uart(void)
 	writel(0x1, iomuxbase + 0x0330);
 	writel(0x1, iomuxbase + 0x032c);

-	writel(0xffffffff, ccmbase + 0x68);
-	writel(0xffffffff, ccmbase + 0x6c);
-	writel(0xffffffff, ccmbase + 0x70);
-	writel(0xffffffff, ccmbase + 0x74);
-	writel(0xffffffff, ccmbase + 0x78);
-	writel(0xffffffff, ccmbase + 0x7c);
-	writel(0xffffffff, ccmbase + 0x80);
-
+	ungate_all_peripherals();
 	setup_uart_ll();

 	putc_ll('>');
diff --git a/arch/arm/boards/phytec-phycard-imx6/lowlevel.c b/arch/arm/boards/phytec-phycard-imx6/lowlevel.c
index 1d48818..c8306ec 100644
--- a/arch/arm/boards/phytec-phycard-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-phycard-imx6/lowlevel.c
@@ -26,19 +26,11 @@

 static inline void setup_uart(void)
 {
-	void __iomem *ccmbase = IOMEM(MX6_CCM_BASE_ADDR);
 	void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR);

 	writel(0x4, iomuxbase + 0x01f8);

-	writel(0xffffffff, ccmbase + 0x68);
-	writel(0xffffffff, ccmbase + 0x6c);
-	writel(0xffffffff, ccmbase + 0x70);
-	writel(0xffffffff, ccmbase + 0x74);
-	writel(0xffffffff, ccmbase + 0x78);
-	writel(0xffffffff, ccmbase + 0x7c);
-	writel(0xffffffff, ccmbase + 0x80);
-
+	ungate_all_peripherals();
 	setup_uart_ll();

 	putc_ll('>');
diff --git a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c
index 367d4dc..46f788c 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c
@@ -27,19 +27,11 @@

 static inline void setup_uart(void)
 {
-	void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR;
 	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;

 	writel(0x4, iomuxbase + 0x01f8);

-	writel(0xffffffff, ccmbase + 0x68);
-	writel(0xffffffff, ccmbase + 0x6c);
-	writel(0xffffffff, ccmbase + 0x70);
-	writel(0xffffffff, ccmbase + 0x74);
-	writel(0xffffffff, ccmbase + 0x78);
-	writel(0xffffffff, ccmbase + 0x7c);
-	writel(0xffffffff, ccmbase + 0x80);
-
+	ungate_all_peripherals();
 	setup_uart_ll();

 	putc_ll('>');
diff --git a/arch/arm/boards/variscite-mx6/lowlevel.c b/arch/arm/boards/variscite-mx6/lowlevel.c
index b0ab424..01878e6 100644
--- a/arch/arm/boards/variscite-mx6/lowlevel.c
+++ b/arch/arm/boards/variscite-mx6/lowlevel.c
@@ -28,20 +28,12 @@

 static inline void setup_uart(void)
 {
-	void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR;
 	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;

 	writel(0x03, iomuxbase + 0x0280);
 	writel(0x03, iomuxbase + 0x0284);

-	writel(0xffffffff, ccmbase + 0x68);
-	writel(0xffffffff, ccmbase + 0x6c);
-	writel(0xffffffff, ccmbase + 0x70);
-	writel(0xffffffff, ccmbase + 0x74);
-	writel(0xffffffff, ccmbase + 0x78);
-	writel(0xffffffff, ccmbase + 0x7c);
-	writel(0xffffffff, ccmbase + 0x80);
-
+	ungate_all_peripherals();
 	setup_uart_ll();

 	putc_ll('>');
diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
index 5b0b33b..d831a7d 100644
--- a/arch/arm/mach-imx/include/mach/debug_ll.h
+++ b/arch/arm/mach-imx/include/mach/debug_ll.h
@@ -3,6 +3,7 @@

 #include <io.h>
 #include <config.h>
+#include <common.h>
 #include <mach/imx1-regs.h>
 #include <mach/imx21-regs.h>
 #include <mach/imx25-regs.h>
@@ -71,6 +72,18 @@ static inline void setup_uart_ll(void)

 #endif

+#define __IMX_CCM_BASE(soc) soc##_CCM_BASE_ADDR
+#define IMX_CCM_BASE(soc) __IMX_CCM_BASE(soc)
+
+static inline void ungate_all_peripherals(void)
+{
+	int i;
+	void __iomem *ccmbase = IOMEM(IMX_CCM_BASE(IMX_DEBUG_SOC));
+
+	for (i = 0x68; i <= 0x80; i += 4)
+		writel(0xffffffff, ccmbase + i);
+}
+
 static inline void PUTC_LL(int c)
 {
 	void __iomem *base = (void *)IMX_UART_BASE(IMX_DEBUG_SOC,
@@ -90,5 +103,9 @@ static inline void PUTC_LL(int c)
 static inline void setup_uart_ll(void)
 {
 }
+
+static inline void ungate_all_peripherals(void)
+{
+}
 #endif /* CONFIG_DEBUG_LL */
 #endif /* __MACH_DEBUG_LL_H__ */
--
2.1.4

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[PATCH 8/8] Makefile.lib: Make 'check_file_size' more flexible

[Andrey Smirnov]

Make 'check_file_size' more flexible by not hardcoding the file whose
size is going to be checked to '$@'. This way it is possible to use
this subroutine to check the size of files other than the target of
the rule.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 Makefile               | 2 +-
 arch/arm/pbl/Makefile  | 2 +-
 arch/mips/pbl/Makefile | 2 +-
 scripts/Makefile.lib   | 6 +++---
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/Makefile b/Makefile
index 372d18a..9ed0a1d 100644
--- a/Makefile
+++ b/Makefile
@@ -700,7 +700,7 @@ OBJCOPYFLAGS_barebox.bin = -O binary
 barebox.bin: barebox FORCE
 	$(call if_changed,objcopy)
 ifndef CONFIG_PBL_IMAGE
-	$(call cmd,check_file_size,$(CONFIG_BAREBOX_MAX_IMAGE_SIZE))
+	$(call cmd,check_file_size,$@,$(CONFIG_BAREBOX_MAX_IMAGE_SIZE))
 endif

 # By default the uImage load address is 2MB below CONFIG_TEXT_BASE,
diff --git a/arch/arm/pbl/Makefile b/arch/arm/pbl/Makefile
index 4c1788d..1ff39db 100644
--- a/arch/arm/pbl/Makefile
+++ b/arch/arm/pbl/Makefile
@@ -22,7 +22,7 @@ endif

 $(obj)/zbarebox.bin:	$(obj)/zbarebox FORCE
 	$(call if_changed,objcopy)
-	$(call cmd,check_file_size,$(CONFIG_BAREBOX_MAX_IMAGE_SIZE))
+	$(call cmd,check_file_size,$@,$(CONFIG_BAREBOX_MAX_IMAGE_SIZE))
 	$(Q)$(kecho) '  Barebox: fix size'
 	$(Q)$(objtree)/scripts/fix_size -i -f $(objtree)/$@ $(FIX_SIZE)
 	$(Q)$(kecho) '  Barebox: $@ is ready'
diff --git a/arch/mips/pbl/Makefile b/arch/mips/pbl/Makefile
index fea1f24..b03bca1 100644
--- a/arch/mips/pbl/Makefile
+++ b/arch/mips/pbl/Makefile
@@ -15,7 +15,7 @@ extra-y       += piggy.gzip piggy.lz4 piggy.lzo piggy.lzma piggy.xzkern piggy.sh

 $(obj)/zbarebox.bin:	$(obj)/zbarebox FORCE
 	$(call if_changed,objcopy)
-	$(call cmd,check_file_size,$(CONFIG_BAREBOX_MAX_IMAGE_SIZE))
+	$(call cmd,check_file_size,$@,$(CONFIG_BAREBOX_MAX_IMAGE_SIZE))
 	$(Q)$(kecho) '  Barebox: $@ is ready'

 $(obj)/zbarebox.S: $(obj)/zbarebox FORCE
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 57426d0..e991f33 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -388,10 +388,10 @@ quiet_cmd_ln = LN      $@
 cmd_ln = ln -sf $< $@

 # Check size of a file
-quiet_cmd_check_file_size = CHKSIZE $@
+quiet_cmd_check_file_size = CHKSIZE $2
       cmd_check_file_size = set -e;					\
-	size=`stat -c%s $@`;						\
-	max_size=`printf "%d" $2`;					\
+	size=`stat -c%s $2`;						\
+	max_size=`printf "%d" $3`;					\
 	if [ $$size -gt $$max_size ] ;					\
 	then								\
 		echo "$@ size $$size > of the maximum size $$max_size" >&2;	\
--
2.1.4

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Re: [PATCH 4/8] i.MX51: babbage: Implement CONFIG_DEBUG_LL

[Sascha Hauer]

On Sat, May 02, 2015 at 07:26:16PM -0700, Andrey Smirnov wrote:
> Implement bits of configuraion needed to configure early debug output
> support.
> 
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
>  arch/arm/boards/freescale-mx51-babbage/lowlevel.c | 58 +++++++++++++++++++++++
>  arch/arm/mach-imx/include/mach/clock-imx51_53.h   |  5 +-
>  2 files changed, 61 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
> index 0f453f3..0135cb4 100644
> --- a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
> +++ b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
> @@ -1,9 +1,63 @@
> +#include <debug_ll.h>
> +#include <mach/clock-imx51_53.h>
>  #include <common.h>
>  #include <mach/esdctl.h>
>  #include <mach/generic.h>
>  #include <asm/barebox-arm-head.h>
>  #include <asm/barebox-arm.h>
> 
> +#ifdef CONFIG_DEBUG_LL
> +static inline void setup_uart(void)
> +{
> +
> +	void __iomem *uartbase =
> +	  (void *)IMX_UART_BASE(IMX_DEBUG_SOC,
> +				CONFIG_DEBUG_IMX_UART_PORT);
> +	void __iomem *iomuxbase = (void *)MX51_IOMUXC_BASE_ADDR;
> +	void __iomem *ccmbase = (void *)MX51_CCM_BASE_ADDR;
> +
> +	/*
> +	 * Restore CCM values that might be changed by the Mask ROM
> +	 * code.
> +	 *
> +	 * Source: RealView debug scripts provided by Freescale
> +	 */
> +	writel(MX5_CCM_CBCDR_RESET_VALUE,  ccmbase + MX5_CCM_CBCDR);
> +	writel(MX5_CCM_CSCMR1_RESET_VALUE, ccmbase + MX5_CCM_CSCMR1);
> +	writel(MX5_CCM_CSCDR1_RESET_VALUE, ccmbase + MX5_CCM_CSCDR1);
> +
> +	/*
> +	 * The code below should be more or less a "moral equivalent"
> +	 * of:
> +	 *	 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
> +	 *
> +	 * in device tree
> +	 */
> +	writel(0x00000000, iomuxbase + 0x022c);
> +	writel(0x000001c5, iomuxbase + 0x061c);
> +
> +	writel(0x00000000, uartbase + UCR1);
> +
> +	writel(UCR2_IRTS | UCR2_WS | UCR2_TXEN | UCR2_RXEN | UCR2_SRST,
> +	       uartbase + UCR2);
> +	writel(UCR3_DSR | UCR3_DCD | UCR3_RI | UCR3_ADNIMP | UCR3_RXDMUXSEL,
> +	       uartbase + UCR3);
> +	writel((0b10 << UFCR_TXTL_SHF) | UFCR_RFDIV1 | (1 << UFCR_RXTL_SHF),
> +	       uartbase + UFCR);
> +
> +	writel(baudrate_to_ubir(115200), uartbase + UBIR);
> +	writel(refclock_to_ubmr(54000000), uartbase + UBMR);
> +
> +	writel(UCR1_UARTEN, uartbase + UCR1);

This is more generic than what I usually do when setting up the UART for
lowlevel debug. I usually hardcode the UBIR/UBMR values in board code.
From the above we could create a

static inline void imx_uart_init(int reffreq)

int arch/arm/mach-imx/include/mach/debug_ll.h. What do you think?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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Re: [PATCH 5/8] i.MX: serial: Add setup_uart_ll function

[Sascha Hauer]

On Sat, May 02, 2015 at 07:26:17PM -0700, Andrey Smirnov wrote:
> It appears that all i.MX based boards that support early debug output
> inevitably do exactly the same thing with the registers of the UART
> peripheral. So to avoid code duplication distill that functionality
> into dedicated subroutine.
> 
> IMPORTANT: Please note that 'setup_uart_ll' function does add a slight
> difference in behaviour by dropping the initialization of ONEMS and
> UESC registers since those do not seem to be needed for early UART
> functionality
> 
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
>  arch/arm/mach-imx/include/mach/debug_ll.h | 34 +++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
> index 1c9f3a6..5b0b33b 100644
> --- a/arch/arm/mach-imx/include/mach/debug_ll.h
> +++ b/arch/arm/mach-imx/include/mach/debug_ll.h
> @@ -30,10 +30,12 @@
>  #define IMX_DEBUG_SOC MX35
>  #elif defined CONFIG_DEBUG_IMX51_UART
>  #define IMX_DEBUG_SOC MX51
> +#define IMX_DEBUG_UART_REFCLOCK_HZ 54000000
>  #elif defined CONFIG_DEBUG_IMX53_UART
>  #define IMX_DEBUG_SOC MX53
>  #elif defined CONFIG_DEBUG_IMX6Q_UART
>  #define IMX_DEBUG_SOC MX6
> +#define IMX_DEBUG_UART_REFCLOCK_HZ 80000000
>  #else
>  #error "unknown i.MX debug uart soc type"
>  #endif
> @@ -41,6 +43,34 @@
>  #define __IMX_UART_BASE(soc, num) soc##_UART##num##_BASE_ADDR
>  #define IMX_UART_BASE(soc, num) __IMX_UART_BASE(soc, num)
> 
> +
> +#if defined IMX_DEBUG_UART_REFCLOCK_HZ
> +
> +static inline void setup_uart_ll(void)
> +{
> +	void __iomem *uartbase =
> +	  (void *)IMX_UART_BASE(IMX_DEBUG_SOC,
> +				CONFIG_DEBUG_IMX_UART_PORT);
> +
> +	writel(0x00000000, uartbase + UCR1);
> +
> +	writel(UCR2_IRTS | UCR2_WS | UCR2_TXEN | UCR2_RXEN | UCR2_SRST,
> +	       uartbase + UCR2);
> +	writel(UCR3_DSR | UCR3_DCD | UCR3_RI | UCR3_ADNIMP | UCR3_RXDMUXSEL,
> +	       uartbase + UCR3);
> +	writel((0b10 << UFCR_TXTL_SHF) | UFCR_RFDIV1 | (1 << UFCR_RXTL_SHF),
> +	       uartbase + UFCR);
> +
> +	writel(baudrate_to_ubir(CONFIG_BAUDRATE),
> +	       uartbase + UBIR);
> +	writel(refclock_to_ubmr(IMX_DEBUG_UART_REFCLOCK_HZ),
> +	       uartbase + UBMR);
> +
> +	writel(UCR1_UARTEN, uartbase + UCR1);
> +}
> +
> +#endif

Oh, turns out you did just that. So your patches are just in the wrong
order. You should first introduce this helper and add the babbage board
support later. This helps linear readers like me to not write
unnecessary mails ;)

Please add a imx_uart_ namespace to this function. This helps readers
to understand the scope of this function. Also I'm not sure how much we
can rely on the reference frequencies. Maybe you should use a two staged
approach. Let the imx_uart_setup_ll() function take a int reffreq
argument and add additional wrappers like imx6_uart_setup_ll() which
just calls this function.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH 6/8] i.MX: serial: Convert i.MX51 and i.MX6 to use 'setup_uart_ll'

[Sascha Hauer]

On Sat, May 02, 2015 at 07:26:18PM -0700, Andrey Smirnov wrote:
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
> 
> Two boards -- 'guf-santaro' and 'eltec-hipercam' -- were not
> converted to use this function because they enable low-level UART
> regardless of the value of CONFIG_DEGUG_LL and so converting them to
> 'setup_uart_ll' would change the behaviour of the image build with
> 'imx_v7_defconfig'. Should those boards be converted to respect
> CONFIG_DEBUG_LL?

Yes, it won't hurt to only initialize the UART when CONFIG_DEBUG_LL is
enabled.

> 
> Boards 'karo-tx25' and 'tqma53' could be converted but weren't because
> I don't have any i.MX25 or i.MX53 based hardware to test on.

No problem, they can still be converted by someone who comes along this
code and has hardware to test.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH 7/8] i.MX: serial: Distil common clock ungating code

[Sascha Hauer]

On Sat, May 02, 2015 at 07:26:19PM -0700, Andrey Smirnov wrote:
> Move all of the common clock ungating code in early UART
> initialization into a dedicated subroutine that can be shared by all
> of the users.
> 
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
>  arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c |  9 +--------
>  arch/arm/boards/karo-tx6x/lowlevel.c                | 10 +---------
>  arch/arm/boards/phytec-phycard-imx6/lowlevel.c      | 10 +---------
>  arch/arm/boards/phytec-phyflex-imx6/lowlevel.c      | 10 +---------
>  arch/arm/boards/variscite-mx6/lowlevel.c            | 10 +---------
>  arch/arm/mach-imx/include/mach/debug_ll.h           | 17 +++++++++++++++++
>  6 files changed, 22 insertions(+), 44 deletions(-)
> 
> diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c b/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c
> index a8d16cb..fd154df 100644
> --- a/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c
> +++ b/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c
> @@ -21,16 +21,9 @@
> 
>  static inline void setup_uart(void)
>  {
> -	void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR;
>  	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;
> 
> -	writel(0xffffffff, ccmbase + 0x68);
> -	writel(0xffffffff, ccmbase + 0x6c);
> -	writel(0xffffffff, ccmbase + 0x70);
> -	writel(0xffffffff, ccmbase + 0x74);
> -	writel(0xffffffff, ccmbase + 0x78);
> -	writel(0xffffffff, ccmbase + 0x7c);
> -	writel(0xffffffff, ccmbase + 0x80);
> +	ungate_all_peripherals();
> 
>  	writel(0x0, iomuxbase + 0x24);
>  	writel(0x1b0b1, iomuxbase + 0x036C);
> diff --git a/arch/arm/boards/karo-tx6x/lowlevel.c b/arch/arm/boards/karo-tx6x/lowlevel.c
> index 3f9fb23..d7087f5 100644
> --- a/arch/arm/boards/karo-tx6x/lowlevel.c
> +++ b/arch/arm/boards/karo-tx6x/lowlevel.c
> @@ -22,7 +22,6 @@
> 
>  static inline void setup_uart(void)
>  {
> -	void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR;
>  	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;
> 
>  	writel(0x1, iomuxbase + 0x0314);
> @@ -30,14 +29,7 @@ static inline void setup_uart(void)
>  	writel(0x1, iomuxbase + 0x0330);
>  	writel(0x1, iomuxbase + 0x032c);
> 
> -	writel(0xffffffff, ccmbase + 0x68);
> -	writel(0xffffffff, ccmbase + 0x6c);
> -	writel(0xffffffff, ccmbase + 0x70);
> -	writel(0xffffffff, ccmbase + 0x74);
> -	writel(0xffffffff, ccmbase + 0x78);
> -	writel(0xffffffff, ccmbase + 0x7c);
> -	writel(0xffffffff, ccmbase + 0x80);
> -
> +	ungate_all_peripherals();
>  	setup_uart_ll();
> 
>  	putc_ll('>');
> diff --git a/arch/arm/boards/phytec-phycard-imx6/lowlevel.c b/arch/arm/boards/phytec-phycard-imx6/lowlevel.c
> index 1d48818..c8306ec 100644
> --- a/arch/arm/boards/phytec-phycard-imx6/lowlevel.c
> +++ b/arch/arm/boards/phytec-phycard-imx6/lowlevel.c
> @@ -26,19 +26,11 @@
> 
>  static inline void setup_uart(void)
>  {
> -	void __iomem *ccmbase = IOMEM(MX6_CCM_BASE_ADDR);
>  	void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR);
> 
>  	writel(0x4, iomuxbase + 0x01f8);
> 
> -	writel(0xffffffff, ccmbase + 0x68);
> -	writel(0xffffffff, ccmbase + 0x6c);
> -	writel(0xffffffff, ccmbase + 0x70);
> -	writel(0xffffffff, ccmbase + 0x74);
> -	writel(0xffffffff, ccmbase + 0x78);
> -	writel(0xffffffff, ccmbase + 0x7c);
> -	writel(0xffffffff, ccmbase + 0x80);
> -
> +	ungate_all_peripherals();
>  	setup_uart_ll();
> 
>  	putc_ll('>');
> diff --git a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c
> index 367d4dc..46f788c 100644
> --- a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c
> +++ b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c
> @@ -27,19 +27,11 @@
> 
>  static inline void setup_uart(void)
>  {
> -	void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR;
>  	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;
> 
>  	writel(0x4, iomuxbase + 0x01f8);
> 
> -	writel(0xffffffff, ccmbase + 0x68);
> -	writel(0xffffffff, ccmbase + 0x6c);
> -	writel(0xffffffff, ccmbase + 0x70);
> -	writel(0xffffffff, ccmbase + 0x74);
> -	writel(0xffffffff, ccmbase + 0x78);
> -	writel(0xffffffff, ccmbase + 0x7c);
> -	writel(0xffffffff, ccmbase + 0x80);
> -
> +	ungate_all_peripherals();
>  	setup_uart_ll();
> 
>  	putc_ll('>');
> diff --git a/arch/arm/boards/variscite-mx6/lowlevel.c b/arch/arm/boards/variscite-mx6/lowlevel.c
> index b0ab424..01878e6 100644
> --- a/arch/arm/boards/variscite-mx6/lowlevel.c
> +++ b/arch/arm/boards/variscite-mx6/lowlevel.c
> @@ -28,20 +28,12 @@
> 
>  static inline void setup_uart(void)
>  {
> -	void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR;
>  	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;
> 
>  	writel(0x03, iomuxbase + 0x0280);
>  	writel(0x03, iomuxbase + 0x0284);
> 
> -	writel(0xffffffff, ccmbase + 0x68);
> -	writel(0xffffffff, ccmbase + 0x6c);
> -	writel(0xffffffff, ccmbase + 0x70);
> -	writel(0xffffffff, ccmbase + 0x74);
> -	writel(0xffffffff, ccmbase + 0x78);
> -	writel(0xffffffff, ccmbase + 0x7c);
> -	writel(0xffffffff, ccmbase + 0x80);
> -
> +	ungate_all_peripherals();
>  	setup_uart_ll();
> 
>  	putc_ll('>');
> diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
> index 5b0b33b..d831a7d 100644
> --- a/arch/arm/mach-imx/include/mach/debug_ll.h
> +++ b/arch/arm/mach-imx/include/mach/debug_ll.h
> @@ -3,6 +3,7 @@
> 
>  #include <io.h>
>  #include <config.h>
> +#include <common.h>
>  #include <mach/imx1-regs.h>
>  #include <mach/imx21-regs.h>
>  #include <mach/imx25-regs.h>
> @@ -71,6 +72,18 @@ static inline void setup_uart_ll(void)
> 
>  #endif
> 
> +#define __IMX_CCM_BASE(soc) soc##_CCM_BASE_ADDR
> +#define IMX_CCM_BASE(soc) __IMX_CCM_BASE(soc)
> +
> +static inline void ungate_all_peripherals(void)
> +{
> +	int i;
> +	void __iomem *ccmbase = IOMEM(IMX_CCM_BASE(IMX_DEBUG_SOC));
> +
> +	for (i = 0x68; i <= 0x80; i += 4)
> +		writel(0xffffffff, ccmbase + i);
> +}
> +

Please add a imx6_ namespace to this function. The calling code always
knows that it is running on imx6, so you can use IMX6_CCM_BASE_ADDR
directly rather than using soc##_. The function above is imx6 specific
anyway since only this SoC has the gate registers on 0x68..0x80.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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Re: [PATCH 1/8] i.MX: Move UART definitions into a separate file

[Sascha Hauer]

On Sat, May 02, 2015 at 07:26:13PM -0700, Andrey Smirnov wrote:
> Move UART definitions into a separate file to avoid redefinition in
> <mach/debug_ll.h> and magical constants in low level UART
> initialization code.
> 
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
>  arch/arm/mach-imx/include/mach/debug_ll.h |   9 +--
>  arch/arm/mach-imx/include/mach/serial.h   | 112 ++++++++++++++++++++++++++++++
>  drivers/serial/serial_imx.c               | 108 +---------------------------
>  3 files changed, 114 insertions(+), 115 deletions(-)
>  create mode 100644 arch/arm/mach-imx/include/mach/serial.h
> 
> diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
> index f34eaa1..1c9f3a6 100644
> --- a/arch/arm/mach-imx/include/mach/debug_ll.h
> +++ b/arch/arm/mach-imx/include/mach/debug_ll.h
> @@ -12,6 +12,7 @@
>  #include <mach/imx51-regs.h>
>  #include <mach/imx53-regs.h>
>  #include <mach/imx6-regs.h>
> +#include <mach/serial.h>
> 
>  #ifdef CONFIG_DEBUG_LL
> 
> @@ -40,14 +41,6 @@
>  #define __IMX_UART_BASE(soc, num) soc##_UART##num##_BASE_ADDR
>  #define IMX_UART_BASE(soc, num) __IMX_UART_BASE(soc, num)
> 
> -#define URTX0		0x40		/* Transmitter Register */
> -
> -#define UCR1		0x80		/* Control Register 1 */
> -#define UCR1_UARTEN	(1 << 0)	/* UART enabled */
> -
> -#define USR2		0x98		/* Status Register 2 */
> -#define USR2_TXDC	(1 << 3)	/* Transmitter complete */
> -
>  static inline void PUTC_LL(int c)
>  {
>  	void __iomem *base = (void *)IMX_UART_BASE(IMX_DEBUG_SOC,
> diff --git a/arch/arm/mach-imx/include/mach/serial.h b/arch/arm/mach-imx/include/mach/serial.h
> new file mode 100644
> index 0000000..b999c58
> --- /dev/null
> +++ b/arch/arm/mach-imx/include/mach/serial.h

Normally we no longer put register definitions into mach/ since this
limits the driver to a single architecture. In case of the imx UART
driver this (currently) doesn't matter but I think we should use
a place include/ anyway. I think include/serial/imx-uart.h would be
appropriate.

Sascha

-- 
Pengutronix e.K.                           |                             |
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Re: [RFC, PATCH] i.MX: Add provisions to boot from IRAM

[Sascha Hauer]

Hi Andrey,

This series contains very nice cleanups. It needs some polishing, but
the patches are very welcomed.

On Sat, May 02, 2015 at 07:26:12PM -0700, Andrey Smirnov wrote:
> This commit add a very basic code to allow Barebox to be booted from
> IRAM. Given that the amount of IRAM on most i.MX variants is
> insufficient to contain a copy of Barebox with any reasonable degree
> of functionality this code uses IRAM only as a temporary location and
> eventually bootstraps from DRAM. But the presense of the intermediate
> IRAM-only stage allows to add provisions to test the area of DRAM that
> Barebox would be using to facilitate various testing scenarious.
> 
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
>  arch/arm/boards/freescale-mx51-babbage/Makefile    |  3 ++
>  .../flash-header-imx51-babbage-xload.imxcfg        | 59 ++++++++++++++++++++++
>  arch/arm/boards/freescale-mx51-babbage/lowlevel.c  | 25 +++++++++
>  arch/arm/configs/imx_v7-xload_defconfig            | 46 +++++++++++++++++
>  arch/arm/mach-imx/Kconfig                          | 15 ++++++
>  arch/arm/mach-imx/Makefile                         |  1 +
>  arch/arm/mach-imx/xload.c                          | 54 ++++++++++++++++++++
>  images/Makefile.imx                                | 20 +++++++-
>  8 files changed, 222 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg
>  create mode 100644 arch/arm/configs/imx_v7-xload_defconfig
>  create mode 100644 arch/arm/mach-imx/xload.c
> 
> diff --git a/arch/arm/boards/freescale-mx51-babbage/Makefile b/arch/arm/boards/freescale-mx51-babbage/Makefile
> index 6252c88..31b8fcd 100644
> --- a/arch/arm/boards/freescale-mx51-babbage/Makefile
> +++ b/arch/arm/boards/freescale-mx51-babbage/Makefile
> @@ -1,3 +1,6 @@
>  obj-y += board.o flash-header-imx51-babbage.dcd.o
>  extra-y += flash-header-imx51-babbage.dcd.S flash-header-imx51-babbage.dcd
>  lwl-y += lowlevel.o
> +
> +obj-$(CONFIG_ARCH_IMX_XLOAD) += flash-header-imx51-babbage-xload.dcd.o
> +extra-$(CONFIG_ARCH_IMX_XLOAD) += flash-header-imx51-babbage-xload.dcd.S flash-header-imx51-babbage-xload.dcd
> diff --git a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg
> new file mode 100644
> index 0000000..a04ac75
> --- /dev/null
> +++ b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg
> @@ -0,0 +1,59 @@
> +loadaddr CONFIG_ARCH_IMX_UNUSED_IRAM_BASE
> +soc imx51
> +dcdofs 0x400
> +wm 32 0x73fa88a0 0x00000200

Can't this and the rest of this file shared with the regular imxcfg
file?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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Re: [PATCH 7/8] i.MX: serial: Distil common clock ungating code

[Andrey Smirnov]

> Please add a imx6_ namespace to this function. The calling code always
> knows that it is running on imx6, so you can use IMX6_CCM_BASE_ADDR
> directly rather than using soc##_. The function above is imx6 specific
> anyway since only this SoC has the gate registers on 0x68..0x80.

What about i.MX51? As far as I can tell it is the same as i.MX6 in
this aspect. This function wouldn't have any consumers on i.MX51
architecture, of course, but shouldn't this function have a SoC
variant agnostic name, just for the sake of genericity?


>
> Sascha
>
> --
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH 7/8] i.MX: serial: Distil common clock ungating code

[Sascha Hauer]

On Mon, May 04, 2015 at 11:04:25AM -0700, Andrey Smirnov wrote:
> > Please add a imx6_ namespace to this function. The calling code always
> > knows that it is running on imx6, so you can use IMX6_CCM_BASE_ADDR
> > directly rather than using soc##_. The function above is imx6 specific
> > anyway since only this SoC has the gate registers on 0x68..0x80.
> 
> What about i.MX51? As far as I can tell it is the same as i.MX6 in
> this aspect. This function wouldn't have any consumers on i.MX51
> architecture, of course, but shouldn't this function have a SoC
> variant agnostic name, just for the sake of genericity?

On i.MX1/21/25/27/31/35 the function would look different, so when
trying to create a generic function we would need to decide which SoC
we are on. cpu_is_imxxy() doesn't work at that place because it needs
initialisation. #ifdefs do not work because we may have multiple SoC
supports compiled in. Even if we could decide which SoC we are on,
we still need a cascade of if() or #ifdef. Since the caller already
knows the SoC type it's easiest to create SoC specific functions.

If i.MX51 (and i.MX53 probably aswell) is the same as i.MX6 the i.MX6
function could simply call the i.MX5 function.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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