From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mail-pf0-x230.google.com ([2607:f8b0:400e:c00::230]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aEskc-0008BE-4a for barebox@lists.infradead.org; Fri, 01 Jan 2016 05:59:47 +0000 Received: by mail-pf0-x230.google.com with SMTP id q63so128531223pfb.0 for ; Thu, 31 Dec 2015 21:59:25 -0800 (PST) From: Andrey Smirnov Date: Thu, 31 Dec 2015 21:58:38 -0800 Message-Id: <1451627918-31967-6-git-send-email-andrew.smirnov@gmail.com> In-Reply-To: <1451627918-31967-1-git-send-email-andrew.smirnov@gmail.com> References: <1451627918-31967-1-git-send-email-andrew.smirnov@gmail.com> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" Errors-To: barebox-bounces+u.kleine-koenig=pengutronix.de@lists.infradead.org Subject: [PATCH 6/6] i.MX6: pci: Avoid aborts when asserting PCIe reset To: barebox@lists.infradead.org Cc: Andrey Smirnov When booting Barebox in the HW environment where PCIe core has been used but not properly shut down, writing to PCIE_PL_PFLR in imx6_pcie_assert_core_reset would cause data abort exception. The problem can be easily reproduced on a i.MX6 based board with PCIe slot populated with some device by doing: > bootm -f -e 0x1050 .img Ignoring this exception seem to allow PCIe core to successfully initialize and enumerate devices properly. This is also how Linux Kernel version of the driver handles this situation -- it installs dummy no-op abort handler at the beginning of device's probing. Signed-off-by: Andrey Smirnov --- drivers/pci/pci-imx6.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c index 713007b..3a3edd8 100644 --- a/drivers/pci/pci-imx6.c +++ b/drivers/pci/pci-imx6.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -237,7 +238,10 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp) val = readl(pp->dbi_base + PCIE_PL_PFLR); val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; val |= PCIE_PL_PFLR_FORCE_LINK; + + data_abort_mask(); writel(val, pp->dbi_base + PCIE_PL_PFLR); + data_abort_unmask(); gpr12 &= ~IMX6Q_GPR12_PCIE_CTL_2; writel(gpr12, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12); -- 2.5.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox