* [PATCH 01/15] MIPS: probe_scache(): use MIPS_CONF_M linux kernel macro
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
@ 2016-03-07 13:30 ` Antony Pavlov
2016-03-07 13:30 ` [PATCH 02/15] MIPS: pbl: import cache init code from U-Boot v2016.01-212-ga3ab2ae Antony Pavlov
` (14 subsequent siblings)
15 siblings, 0 replies; 23+ messages in thread
From: Antony Pavlov @ 2016-03-07 13:30 UTC (permalink / raw)
To: barebox; +Cc: Peter Mamonov
We already have MIPS_CONF_M macro in <asm/mipsregs.h> so
we have no need in homebrew CONFIG_M macro.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Peter Mamonov <pmamonov@gmail.com>
---
arch/mips/lib/c-r4k.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c
index 0a9dd0e..ff68677 100644
--- a/arch/mips/lib/c-r4k.c
+++ b/arch/mips/lib/c-r4k.c
@@ -91,7 +91,6 @@ static void probe_pcache(void)
}
}
-#define CONFIG_M (1 << 31)
#define CONFIG2_SS_OFFSET 8
#define CONFIG2_SL_OFFSET 4
#define CONFIG2_SA_OFFSET 0
@@ -101,10 +100,10 @@ static void probe_scache(void)
unsigned int config2, config1, config = read_c0_config();
unsigned int ss, sl, sa;
- if ((config & CONFIG_M) == 0)
+ if ((config & MIPS_CONF_M) == 0)
goto noscache;
config1 = read_c0_config1();
- if ((config1 & CONFIG_M) == 0)
+ if ((config1 & MIPS_CONF_M) == 0)
goto noscache;
config2 = read_c0_config2();
ss = 0xf & (config2 >> CONFIG2_SS_OFFSET);
--
2.7.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 02/15] MIPS: pbl: import cache init code from U-Boot v2016.01-212-ga3ab2ae
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
2016-03-07 13:30 ` [PATCH 01/15] MIPS: probe_scache(): use MIPS_CONF_M linux kernel macro Antony Pavlov
@ 2016-03-07 13:30 ` Antony Pavlov
2016-03-07 13:30 ` [PATCH 03/15] MIPS: black-swift: pbl: init cache Antony Pavlov
` (13 subsequent siblings)
15 siblings, 0 replies; 23+ messages in thread
From: Antony Pavlov @ 2016-03-07 13:30 UTC (permalink / raw)
To: barebox
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/include/asm/cacheops.h | 29 ++++++++
arch/mips/include/asm/mipsregs.h | 8 +++
arch/mips/include/asm/pbl_macros.h | 133 +++++++++++++++++++++++++++++++++++++
3 files changed, 170 insertions(+)
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
new file mode 100644
index 0000000..5bd44d5
--- /dev/null
+++ b/arch/mips/include/asm/cacheops.h
@@ -0,0 +1,29 @@
+/*
+ * Cache operations for the cache instruction.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
+ * (C) Copyright 1999 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_CACHEOPS_H
+#define __ASM_CACHEOPS_H
+
+/*
+ * Most cache ops are split into a 2 bit field identifying the cache, and a 3
+ * bit field identifying the cache operation.
+ */
+#define Cache_I 0x00
+#define Cache_D 0x01
+
+#define Index_Store_Tag 0x08
+
+/*
+ * Cache Operations available on all MIPS processors with R4000-style caches
+ */
+#define Index_Store_Tag_I (Cache_I | Index_Store_Tag)
+#define Index_Store_Tag_D (Cache_D | Index_Store_Tag)
+
+#endif /* __ASM_CACHEOPS_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index f923860..30262e6 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -409,6 +409,14 @@
#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
+#define MIPS_CONF1_DA_SHF 7
+#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
+#define MIPS_CONF1_DL_SHF 10
+#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
+#define MIPS_CONF1_DS_SHF 13
+#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
+#define MIPS_CONF1_IA_SHF 16
+
#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
index dbe3410..37b150a 100644
--- a/arch/mips/include/asm/pbl_macros.h
+++ b/arch/mips/include/asm/pbl_macros.h
@@ -27,6 +27,8 @@
#include <asm-generic/memory_layout.h>
#include <generated/compile.h>
#include <generated/utsrelease.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
.macro pbl_reg_writel val addr
.set push
@@ -212,4 +214,135 @@ copy_loop_exit:
.set pop
.endm
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
+#define INDEX_BASE CKSEG0
+
+ .macro f_fill64 dst, offset, val
+ LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
+#if LONGSIZE == 4
+ LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
+#endif
+ .endm
+
+ .macro cache_loop curr, end, line_sz, op
+10: cache \op, 0(\curr)
+ PTR_ADDU \curr, \curr, \line_sz
+ bne \curr, \end, 10b
+ .endm
+
+ .macro l1_info sz, line_sz, off
+ .set push
+ .set noat
+
+ mfc0 $1, CP0_CONFIG, 1
+
+ /* detect line size */
+ srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
+ andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
+ move \sz, zero
+ beqz \line_sz, 10f
+ li \sz, 2
+ sllv \line_sz, \sz, \line_sz
+
+ /* detect associativity */
+ srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
+ andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF)
+ addi \sz, \sz, 1
+
+ /* sz *= line_sz */
+ mul \sz, \sz, \line_sz
+
+ /* detect log32(sets) */
+ srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF
+ andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHF)
+ addiu $1, $1, 1
+ andi $1, $1, 0x7
+
+ /* sz <<= log32(sets) */
+ sllv \sz, \sz, $1
+
+ /* sz *= 32 */
+ li $1, 32
+ mul \sz, \sz, $1
+10:
+ .set pop
+ .endm
+
+/*
+ * mips_cache_reset - low level initialisation of the primary caches
+ *
+ * This routine initialises the primary caches to ensure that they have good
+ * parity. It must be called by the ROM before any cached locations are used
+ * to prevent the possibility of data with bad parity being written to memory.
+ *
+ * To initialise the instruction cache it is essential that a source of data
+ * with good parity is available. This routine will initialise an area of
+ * memory starting at location zero to be used as a source of parity.
+ *
+ */
+ .macro mips_cache_reset
+
+ l1_info t2, t8, MIPS_CONF1_IA_SHF
+ l1_info t3, t9, MIPS_CONF1_DA_SHF
+
+ /*
+ * The TagLo registers used depend upon the CPU implementation, but the
+ * architecture requires that it is safe for software to write to both
+ * TagLo selects 0 & 2 covering supported cases.
+ */
+ mtc0 zero, CP0_TAGLO
+ mtc0 zero, CP0_TAGLO, 2
+
+ /*
+ * The caches are probably in an indeterminate state, so we force good
+ * parity into them by doing an invalidate for each line.
+ */
+
+ /*
+ * Initialize the I-cache first,
+ */
+ blez t2, 1f
+ PTR_LI t0, INDEX_BASE
+ PTR_ADDU t1, t0, t2
+ /* clear tag to invalidate */
+ cache_loop t0, t1, t8, Index_Store_Tag_I
+
+ /*
+ * then initialize D-cache.
+ */
+1: blez t3, 3f
+ PTR_LI t0, INDEX_BASE
+ PTR_ADDU t1, t0, t3
+ /* clear all tags */
+ cache_loop t0, t1, t9, Index_Store_Tag_D
+
+3: nop
+
+ .endm
+
+ .macro dcache_enable
+ mfc0 t0, CP0_CONFIG
+ ori t0, CONF_CM_CMASK
+ xori t0, CONF_CM_CMASK
+ ori t0, CONFIG_SYS_MIPS_CACHE_MODE
+ mtc0 t0, CP0_CONFIG
+ .endm
+
#endif /* __ASM_PBL_MACROS_H */
--
2.7.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 03/15] MIPS: black-swift: pbl: init cache
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
2016-03-07 13:30 ` [PATCH 01/15] MIPS: probe_scache(): use MIPS_CONF_M linux kernel macro Antony Pavlov
2016-03-07 13:30 ` [PATCH 02/15] MIPS: pbl: import cache init code from U-Boot v2016.01-212-ga3ab2ae Antony Pavlov
@ 2016-03-07 13:30 ` Antony Pavlov
2016-03-07 13:30 ` [PATCH 04/15] MIPS: tplink-mr3020: " Antony Pavlov
` (12 subsequent siblings)
15 siblings, 0 replies; 23+ messages in thread
From: Antony Pavlov @ 2016-03-07 13:30 UTC (permalink / raw)
To: barebox
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/boards/black-swift/include/board/board_pbl_start.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/boards/black-swift/include/board/board_pbl_start.h b/arch/mips/boards/black-swift/include/board/board_pbl_start.h
index 3f2caa0..0d68004 100644
--- a/arch/mips/boards/black-swift/include/board/board_pbl_start.h
+++ b/arch/mips/boards/black-swift/include/board/board_pbl_start.h
@@ -35,6 +35,12 @@
pbl_ar9331_pll
pbl_ar9331_ddr2_config
+ /* Initialize caches... */
+ mips_cache_reset
+
+ /* ... and enable them */
+ dcache_enable
+
skip_pll_ram_config:
pbl_ar9331_uart_enable
debug_ll_ar9331_init
--
2.7.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 04/15] MIPS: tplink-mr3020: pbl: init cache
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
` (2 preceding siblings ...)
2016-03-07 13:30 ` [PATCH 03/15] MIPS: black-swift: pbl: init cache Antony Pavlov
@ 2016-03-07 13:30 ` Antony Pavlov
2016-03-07 13:30 ` [PATCH 05/15] MIPS: add initial R4000-style cache support Antony Pavlov
` (11 subsequent siblings)
15 siblings, 0 replies; 23+ messages in thread
From: Antony Pavlov @ 2016-03-07 13:30 UTC (permalink / raw)
To: barebox
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h b/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h
index ae548c9..2400015 100644
--- a/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h
+++ b/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h
@@ -35,6 +35,12 @@
pbl_ar9331_pll
pbl_ar9331_ddr1_config
+ /* Initialize caches... */
+ mips_cache_reset
+
+ /* ... and enable them */
+ dcache_enable
+
skip_pll_ram_config:
pbl_ar9331_uart_enable
debug_ll_ar9331_init
--
2.7.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 05/15] MIPS: add initial R4000-style cache support
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
` (3 preceding siblings ...)
2016-03-07 13:30 ` [PATCH 04/15] MIPS: tplink-mr3020: " Antony Pavlov
@ 2016-03-07 13:30 ` Antony Pavlov
2016-03-09 13:28 ` Sascha Hauer
2016-03-07 13:30 ` [PATCH 06/15] MIPS: flush cache on shutdown Antony Pavlov
` (10 subsequent siblings)
15 siblings, 1 reply; 23+ messages in thread
From: Antony Pavlov @ 2016-03-07 13:30 UTC (permalink / raw)
To: barebox; +Cc: Peter Mamonov
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
arch/mips/include/asm/cacheops.h | 7 ++++++
arch/mips/include/asm/io.h | 3 +++
arch/mips/lib/c-r4k.c | 48 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 58 insertions(+)
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 5bd44d5..3bc5852 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -18,12 +18,19 @@
#define Cache_I 0x00
#define Cache_D 0x01
+#define Index_Writeback_Inv 0x00
#define Index_Store_Tag 0x08
+#define Hit_Invalidate 0x10
+#define Hit_Writeback_Inv 0x14 /* not with Cache_I though */
/*
* Cache Operations available on all MIPS processors with R4000-style caches
*/
+#define Index_Invalidate_I (Cache_I | Index_Writeback_Inv)
+#define Index_Writeback_Inv_D (Cache_D | Index_Writeback_Inv)
#define Index_Store_Tag_I (Cache_I | Index_Store_Tag)
#define Index_Store_Tag_D (Cache_D | Index_Store_Tag)
+#define Hit_Invalidate_D (Cache_D | Hit_Invalidate)
+#define Hit_Writeback_Inv_D (Cache_D | Hit_Writeback_Inv)
#endif /* __ASM_CACHEOPS_H */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 4832be6..4bee591 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -14,6 +14,9 @@
#include <asm/types.h>
#include <asm/byteorder.h>
+void dma_flush_range(unsigned long, unsigned long);
+void dma_inv_range(unsigned long, unsigned long);
+
#define IO_SPACE_LIMIT 0
/*****************************************************************************/
diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c
index ff68677..4fe046a 100644
--- a/arch/mips/lib/c-r4k.c
+++ b/arch/mips/lib/c-r4k.c
@@ -10,10 +10,58 @@
#include <common.h>
#include <asm/io.h>
#include <asm/mipsregs.h>
+#include <asm/cache.h>
+#include <asm/cacheops.h>
#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <asm/bitops.h>
+#define cache_op(op,addr) \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noreorder \n" \
+ " .set mips3\n\t \n" \
+ " cache %0, %1 \n" \
+ " .set pop \n" \
+ : \
+ : "i" (op), "R" (*(unsigned char *)(addr)))
+
+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop) \
+static inline void blast_##pfx##cache##_range(unsigned long start, \
+ unsigned long end) \
+{ \
+ unsigned long lsize = current_cpu_data.desc.linesz; \
+ unsigned long addr = start & ~(lsize - 1); \
+ unsigned long aend = (end - 1) & ~(lsize - 1); \
+ \
+ if (current_cpu_data.desc.flags & MIPS_CACHE_NOT_PRESENT) \
+ return; \
+ \
+ while (1) { \
+ cache_op(hitop, addr); \
+ if (addr == aend) \
+ break; \
+ addr += lsize; \
+ } \
+}
+
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D)
+
+void dma_flush_range(unsigned long start, unsigned long end)
+{
+ blast_dcache_range(start, end);
+
+ /* secondatory cache skipped */
+}
+
+void dma_inv_range(unsigned long start, unsigned long end)
+{
+ blast_inv_dcache_range(start, end);
+
+ /* secondatory cache skipped */
+}
+
void r4k_cache_init(void);
static void probe_pcache(void)
--
2.7.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH 05/15] MIPS: add initial R4000-style cache support
2016-03-07 13:30 ` [PATCH 05/15] MIPS: add initial R4000-style cache support Antony Pavlov
@ 2016-03-09 13:28 ` Sascha Hauer
2016-03-09 14:23 ` Antony Pavlov
0 siblings, 1 reply; 23+ messages in thread
From: Sascha Hauer @ 2016-03-09 13:28 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox, Peter Mamonov
Hi Antony,
On Mon, Mar 07, 2016 at 04:30:16PM +0300, Antony Pavlov wrote:
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
> ---
> arch/mips/include/asm/cacheops.h | 7 ++++++
> arch/mips/include/asm/io.h | 3 +++
> arch/mips/lib/c-r4k.c | 48 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 58 insertions(+)
>
> index ff68677..4fe046a 100644
> --- a/arch/mips/lib/c-r4k.c
> +++ b/arch/mips/lib/c-r4k.c
> @@ -10,10 +10,58 @@
> #include <common.h>
> #include <asm/io.h>
> #include <asm/mipsregs.h>
> +#include <asm/cache.h>
This breaks bisectibility. asm/cache.h is introduced with the next.
patch. I tried swapping the patches but got merge conflicts. Shall I
squash both patches or do you have another preferred solution?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 05/15] MIPS: add initial R4000-style cache support
2016-03-09 13:28 ` Sascha Hauer
@ 2016-03-09 14:23 ` Antony Pavlov
2016-03-09 16:12 ` Antony Pavlov
0 siblings, 1 reply; 23+ messages in thread
From: Antony Pavlov @ 2016-03-09 14:23 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox, Peter Mamonov
On Wed, 9 Mar 2016 14:28:14 +0100
Sascha Hauer <s.hauer@pengutronix.de> wrote:
> Hi Antony,
>
> On Mon, Mar 07, 2016 at 04:30:16PM +0300, Antony Pavlov wrote:
> > Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> > Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
> > ---
> > arch/mips/include/asm/cacheops.h | 7 ++++++
> > arch/mips/include/asm/io.h | 3 +++
> > arch/mips/lib/c-r4k.c | 48 ++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 58 insertions(+)
> >
> > index ff68677..4fe046a 100644
> > --- a/arch/mips/lib/c-r4k.c
> > +++ b/arch/mips/lib/c-r4k.c
> > @@ -10,10 +10,58 @@
> > #include <common.h>
> > #include <asm/io.h>
> > #include <asm/mipsregs.h>
> > +#include <asm/cache.h>
>
> This breaks bisectibility. asm/cache.h is introduced with the next.
> patch. I tried swapping the patches but got merge conflicts. Shall I
> squash both patches or do you have another preferred solution?
I'm so sorry!
I'll fix it by myself and resend the series.
--
Best regards,
Antony Pavlov
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 05/15] MIPS: add initial R4000-style cache support
2016-03-09 14:23 ` Antony Pavlov
@ 2016-03-09 16:12 ` Antony Pavlov
2016-03-10 8:44 ` Sascha Hauer
0 siblings, 1 reply; 23+ messages in thread
From: Antony Pavlov @ 2016-03-09 16:12 UTC (permalink / raw)
To: Sascha Hauer, Peter Mamonov; +Cc: barebox
On Wed, 9 Mar 2016 17:23:24 +0300
Antony Pavlov <antonynpavlov@gmail.com> wrote:
> On Wed, 9 Mar 2016 14:28:14 +0100
> Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> > Hi Antony,
> >
> > On Mon, Mar 07, 2016 at 04:30:16PM +0300, Antony Pavlov wrote:
> > > Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> > > Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
> > > ---
> > > arch/mips/include/asm/cacheops.h | 7 ++++++
> > > arch/mips/include/asm/io.h | 3 +++
> > > arch/mips/lib/c-r4k.c | 48 ++++++++++++++++++++++++++++++++++++++++
> > > 3 files changed, 58 insertions(+)
> > >
> > > index ff68677..4fe046a 100644
> > > --- a/arch/mips/lib/c-r4k.c
> > > +++ b/arch/mips/lib/c-r4k.c
> > > @@ -10,10 +10,58 @@
> > > #include <common.h>
> > > #include <asm/io.h>
> > > #include <asm/mipsregs.h>
> > > +#include <asm/cache.h>
> >
> > This breaks bisectibility. asm/cache.h is introduced with the next.
> > patch. I tried swapping the patches but got merge conflicts. Shall I
> > squash both patches or do you have another preferred solution?
>
> I'm so sorry!
> I'll fix it by myself and resend the series.
Hmmm. It look like the patchseries is in the next branch.
So I just send fixups.
--
Best regards,
Antony Pavlov
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 05/15] MIPS: add initial R4000-style cache support
2016-03-09 16:12 ` Antony Pavlov
@ 2016-03-10 8:44 ` Sascha Hauer
0 siblings, 0 replies; 23+ messages in thread
From: Sascha Hauer @ 2016-03-10 8:44 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox, Peter Mamonov
On Wed, Mar 09, 2016 at 07:12:01PM +0300, Antony Pavlov wrote:
> On Wed, 9 Mar 2016 17:23:24 +0300
> Antony Pavlov <antonynpavlov@gmail.com> wrote:
>
> > On Wed, 9 Mar 2016 14:28:14 +0100
> > Sascha Hauer <s.hauer@pengutronix.de> wrote:
> >
> > > Hi Antony,
> > >
> > > On Mon, Mar 07, 2016 at 04:30:16PM +0300, Antony Pavlov wrote:
> > > > Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> > > > Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
> > > > ---
> > > > arch/mips/include/asm/cacheops.h | 7 ++++++
> > > > arch/mips/include/asm/io.h | 3 +++
> > > > arch/mips/lib/c-r4k.c | 48 ++++++++++++++++++++++++++++++++++++++++
> > > > 3 files changed, 58 insertions(+)
> > > >
> > > > index ff68677..4fe046a 100644
> > > > --- a/arch/mips/lib/c-r4k.c
> > > > +++ b/arch/mips/lib/c-r4k.c
> > > > @@ -10,10 +10,58 @@
> > > > #include <common.h>
> > > > #include <asm/io.h>
> > > > #include <asm/mipsregs.h>
> > > > +#include <asm/cache.h>
> > >
> > > This breaks bisectibility. asm/cache.h is introduced with the next.
> > > patch. I tried swapping the patches but got merge conflicts. Shall I
> > > squash both patches or do you have another preferred solution?
> >
> > I'm so sorry!
> > I'll fix it by myself and resend the series.
>
> Hmmm. It look like the patchseries is in the next branch.
>
> So I just send fixups.
Thanks, just applied.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 06/15] MIPS: flush cache on shutdown
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
` (4 preceding siblings ...)
2016-03-07 13:30 ` [PATCH 05/15] MIPS: add initial R4000-style cache support Antony Pavlov
@ 2016-03-07 13:30 ` Antony Pavlov
2016-03-07 13:30 ` [PATCH 07/15] MIPS: implement dma_sync_* functions Antony Pavlov
` (9 subsequent siblings)
15 siblings, 0 replies; 23+ messages in thread
From: Antony Pavlov @ 2016-03-07 13:30 UTC (permalink / raw)
To: barebox; +Cc: Peter Mamonov
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
arch/mips/include/asm/cache.h | 6 ++++++
arch/mips/lib/Makefile | 1 +
arch/mips/lib/c-r4k.c | 23 +++++++++++++++++++++++
arch/mips/lib/shutdown.c | 12 ++++++++++++
4 files changed, 42 insertions(+)
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
new file mode 100644
index 0000000..cceba0a
--- /dev/null
+++ b/arch/mips/include/asm/cache.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_MIPS_CACHE_H
+#define _ASM_MIPS_CACHE_H
+
+void flush_cache_all(void);
+
+#endif /* _ASM_MIPS_CACHE_H */
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 02ee189..43f7af7 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -6,6 +6,7 @@ obj-y += ashrdi3.o
obj-y += cpu-probe.o
obj-y += traps.o
obj-y += genex.o
+obj-y += shutdown.o
obj-$(CONFIG_MIPS_OPTIMIZED_STRING_FUNCTIONS) += memcpy.o
obj-$(CONFIG_MIPS_OPTIMIZED_STRING_FUNCTIONS) += memset.o
diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c
index 4fe046a..1502058 100644
--- a/arch/mips/lib/c-r4k.c
+++ b/arch/mips/lib/c-r4k.c
@@ -48,6 +48,29 @@ static inline void blast_##pfx##cache##_range(unsigned long start, \
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D)
+void flush_cache_all(void)
+{
+ struct cpuinfo_mips *c = ¤t_cpu_data;
+ unsigned long lsize;
+ unsigned long addr;
+ unsigned long aend;
+ unsigned int icache_size, dcache_size;
+
+ dcache_size = c->dcache.waysize * c->dcache.ways;
+ lsize = c->dcache.linesz;
+ aend = (KSEG0 + dcache_size - 1) & ~(lsize - 1);
+ for (addr = KSEG0; addr <= aend; addr += lsize)
+ cache_op(Index_Writeback_Inv_D, addr);
+
+ icache_size = c->icache.waysize * c->icache.ways;
+ lsize = c->icache.linesz;
+ aend = (KSEG0 + icache_size - 1) & ~(lsize - 1);
+ for (addr = KSEG0; addr <= aend; addr += lsize)
+ cache_op(Index_Invalidate_I, addr);
+
+ /* secondatory cache skipped */
+}
+
void dma_flush_range(unsigned long start, unsigned long end)
{
blast_dcache_range(start, end);
diff --git a/arch/mips/lib/shutdown.c b/arch/mips/lib/shutdown.c
new file mode 100644
index 0000000..973cd23
--- /dev/null
+++ b/arch/mips/lib/shutdown.c
@@ -0,0 +1,12 @@
+/**
+ * This function is called by shutdown_barebox to get a clean
+ * memory/cache state.
+ */
+#include <init.h>
+#include <asm/cache.h>
+
+static void arch_shutdown(void)
+{
+ flush_cache_all();
+}
+archshutdown_exitcall(arch_shutdown);
--
2.7.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 07/15] MIPS: implement dma_sync_* functions
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
` (5 preceding siblings ...)
2016-03-07 13:30 ` [PATCH 06/15] MIPS: flush cache on shutdown Antony Pavlov
@ 2016-03-07 13:30 ` Antony Pavlov
2016-03-07 13:30 ` [PATCH 08/15] MIPS: dtb: register only one memory bank Antony Pavlov
` (8 subsequent siblings)
15 siblings, 0 replies; 23+ messages in thread
From: Antony Pavlov @ 2016-03-07 13:30 UTC (permalink / raw)
To: barebox; +Cc: Peter Mamonov
From: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
arch/mips/Kconfig | 1 +
arch/mips/include/asm/dma-mapping.h | 11 ++++++-
arch/mips/lib/Makefile | 1 +
arch/mips/lib/dma-default.c | 57 +++++++++++++++++++++++++++++++++++++
4 files changed, 69 insertions(+), 1 deletion(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index fdf62e8..06a516d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -6,6 +6,7 @@ config MIPS
select HAS_KALLSYMS
select HAVE_CONFIGURABLE_MEMORY_LAYOUT
select HAVE_CONFIGURABLE_TEXT_BASE
+ select HAS_DMA
default y
config SYS_SUPPORTS_BIG_ENDIAN
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index 6395112..c71a087 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -1,10 +1,12 @@
#ifndef _ASM_DMA_MAPPING_H
#define _ASM_DMA_MAPPING_H
+#include <common.h>
#include <xfuncs.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <malloc.h>
+#include <asm/io.h>
static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
{
@@ -12,16 +14,23 @@ static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
ret = xmemalign(PAGE_SIZE, size);
+ memset(ret, 0, size);
+
if (dma_handle)
*dma_handle = CPHYSADDR(ret);
+ dma_flush_range((unsigned long)ret, (unsigned long)(ret + size));
+
return (void *)CKSEG1ADDR(ret);
}
static inline void dma_free_coherent(void *vaddr, dma_addr_t dma_handle,
size_t size)
{
- free(vaddr);
+ if (IS_ENABLED(CONFIG_MMU))
+ free((void *)CKSEG0ADDR(vaddr));
+ else
+ free(vaddr);
}
#endif /* _ASM_DMA_MAPPING_H */
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 43f7af7..d25d096 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -7,6 +7,7 @@ obj-y += cpu-probe.o
obj-y += traps.o
obj-y += genex.o
obj-y += shutdown.o
+obj-y += dma-default.o
obj-$(CONFIG_MIPS_OPTIMIZED_STRING_FUNCTIONS) += memcpy.o
obj-$(CONFIG_MIPS_OPTIMIZED_STRING_FUNCTIONS) += memset.o
diff --git a/arch/mips/lib/dma-default.c b/arch/mips/lib/dma-default.c
new file mode 100644
index 0000000..9b2fe7d
--- /dev/null
+++ b/arch/mips/lib/dma-default.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2015, 2016 Peter Mamonov <pmamonov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <dma.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_CPU_MIPS32) || \
+ defined(CONFIG_CPU_MIPS64)
+static inline void __dma_sync_mips(unsigned long addr, size_t size,
+ enum dma_data_direction direction)
+{
+ switch (direction) {
+ case DMA_TO_DEVICE:
+ dma_flush_range(addr, addr + size);
+ break;
+
+ case DMA_FROM_DEVICE:
+ dma_inv_range(addr, addr + size);
+ break;
+
+ case DMA_BIDIRECTIONAL:
+ dma_flush_range(addr, addr + size);
+ break;
+
+ default:
+ BUG();
+ }
+}
+#else
+static inline void __dma_sync_mips(void *addr, size_t size,
+ enum dma_data_direction direction)
+{
+}
+#endif
+
+void dma_sync_single_for_cpu(unsigned long address, size_t size,
+ enum dma_data_direction dir)
+{
+ __dma_sync_mips(address, size, dir);
+}
+
+void dma_sync_single_for_device(unsigned long address, size_t size,
+ enum dma_data_direction dir)
+{
+ __dma_sync_mips(address, size, dir);
+}
--
2.7.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 08/15] MIPS: dtb: register only one memory bank
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
` (6 preceding siblings ...)
2016-03-07 13:30 ` [PATCH 07/15] MIPS: implement dma_sync_* functions Antony Pavlov
@ 2016-03-07 13:30 ` Antony Pavlov
2016-03-07 13:30 ` [PATCH 09/15] MIPS: tplink-mr3020_defconfig: use cached memory region Antony Pavlov
` (7 subsequent siblings)
15 siblings, 0 replies; 23+ messages in thread
From: Antony Pavlov @ 2016-03-07 13:30 UTC (permalink / raw)
To: barebox; +Cc: Peter Mamonov
From: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/boot/dtb.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/mips/boot/dtb.c b/arch/mips/boot/dtb.c
index 23d8979..977c837 100644
--- a/arch/mips/boot/dtb.c
+++ b/arch/mips/boot/dtb.c
@@ -28,11 +28,13 @@ void of_add_memory_bank(struct device_node *node, bool dump, int r,
{
static char str[12];
- sprintf(str, "kseg0_ram%d", r);
- barebox_add_memory_bank(str, KSEG0 | base, size);
-
- sprintf(str, "kseg1_ram%d", r);
- barebox_add_memory_bank(str, KSEG1 | base, size);
+ if (IS_ENABLED(CONFIG_MMU)) {
+ sprintf(str, "kseg0_ram%d", r);
+ barebox_add_memory_bank(str, KSEG0 | base, size);
+ } else {
+ sprintf(str, "kseg1_ram%d", r);
+ barebox_add_memory_bank(str, KSEG1 | base, size);
+ }
if (dump)
pr_info("%s: %s: 0x%llx@0x%llx\n", node->name, str, size, base);
--
2.7.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 09/15] MIPS: tplink-mr3020_defconfig: use cached memory region
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
` (7 preceding siblings ...)
2016-03-07 13:30 ` [PATCH 08/15] MIPS: dtb: register only one memory bank Antony Pavlov
@ 2016-03-07 13:30 ` Antony Pavlov
2016-03-07 13:30 ` [PATCH 10/15] MIPS: black-swift_defconfig: " Antony Pavlov
` (6 subsequent siblings)
15 siblings, 0 replies; 23+ messages in thread
From: Antony Pavlov @ 2016-03-07 13:30 UTC (permalink / raw)
To: barebox
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/configs/tplink-mr3020_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/configs/tplink-mr3020_defconfig b/arch/mips/configs/tplink-mr3020_defconfig
index f2ba2da..93fb10d 100644
--- a/arch/mips/configs/tplink-mr3020_defconfig
+++ b/arch/mips/configs/tplink-mr3020_defconfig
@@ -3,6 +3,8 @@ CONFIG_BUILTIN_DTB_NAME="tplink-mr3020"
CONFIG_MACH_MIPS_ATH79=y
CONFIG_PBL_IMAGE=y
CONFIG_IMAGE_COMPRESSION_XZKERN=y
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x81000000
CONFIG_MALLOC_TLSF=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
--
2.7.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 10/15] MIPS: black-swift_defconfig: use cached memory region
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
` (8 preceding siblings ...)
2016-03-07 13:30 ` [PATCH 09/15] MIPS: tplink-mr3020_defconfig: use cached memory region Antony Pavlov
@ 2016-03-07 13:30 ` Antony Pavlov
2016-03-07 13:30 ` [PATCH 11/15] MIPS: ath79: pbl: add pbl_ar9331_mdio_gpio_enable macro Antony Pavlov
` (5 subsequent siblings)
15 siblings, 0 replies; 23+ messages in thread
From: Antony Pavlov @ 2016-03-07 13:30 UTC (permalink / raw)
To: barebox
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/configs/black-swift_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/configs/black-swift_defconfig b/arch/mips/configs/black-swift_defconfig
index 7444968..dda863d 100644
--- a/arch/mips/configs/black-swift_defconfig
+++ b/arch/mips/configs/black-swift_defconfig
@@ -9,6 +9,8 @@ CONFIG_NMON_USER_START_DELAY=0x5
CONFIG_NMON_HELP=y
CONFIG_PBL_IMAGE=y
CONFIG_IMAGE_COMPRESSION_XZKERN=y
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x82000000
CONFIG_MALLOC_TLSF=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
--
2.7.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 11/15] MIPS: ath79: pbl: add pbl_ar9331_mdio_gpio_enable macro
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
` (9 preceding siblings ...)
2016-03-07 13:30 ` [PATCH 10/15] MIPS: black-swift_defconfig: " Antony Pavlov
@ 2016-03-07 13:30 ` Antony Pavlov
2016-03-07 13:30 ` [PATCH 12/15] MIPS: black-swift: enable GPIO LED Antony Pavlov
` (4 subsequent siblings)
15 siblings, 0 replies; 23+ messages in thread
From: Antony Pavlov @ 2016-03-07 13:30 UTC (permalink / raw)
To: barebox
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/mach-ath79/include/mach/pbl_macros.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/mips/mach-ath79/include/mach/pbl_macros.h b/arch/mips/mach-ath79/include/mach/pbl_macros.h
index 24cfd60..8f4d09a 100644
--- a/arch/mips/mach-ath79/include/mach/pbl_macros.h
+++ b/arch/mips/mach-ath79/include/mach/pbl_macros.h
@@ -179,6 +179,14 @@
| AR933X_GPIO_FUNC_RSRV15, GPIO_FUNC
.endm
+#define RESET_REG_BOOTSTRAP ((KSEG1 | AR71XX_RESET_BASE) \
+ | AR933X_RESET_REG_BOOTSTRAP)
+
+.macro pbl_ar9331_mdio_gpio_enable
+ /* Bit 18 enables MDC and MDIO function on GPIO26 and GPIO28 */
+ pbl_reg_set (1 << 18), RESET_REG_BOOTSTRAP
+.endm
+
.macro hornet_mips24k_cp0_setup
.set push
.set noreorder
--
2.7.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 12/15] MIPS: black-swift: enable GPIO LED
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
` (10 preceding siblings ...)
2016-03-07 13:30 ` [PATCH 11/15] MIPS: ath79: pbl: add pbl_ar9331_mdio_gpio_enable macro Antony Pavlov
@ 2016-03-07 13:30 ` Antony Pavlov
2016-03-07 13:30 ` [PATCH 13/15] MIPS: black-swift: enable GPIO key Antony Pavlov
` (3 subsequent siblings)
15 siblings, 0 replies; 23+ messages in thread
From: Antony Pavlov @ 2016-03-07 13:30 UTC (permalink / raw)
To: barebox
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
.../boards/black-swift/include/board/board_pbl_start.h | 6 ++++++
arch/mips/dts/black-swift.dts | 15 +++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/arch/mips/boards/black-swift/include/board/board_pbl_start.h b/arch/mips/boards/black-swift/include/board/board_pbl_start.h
index 0d68004..ee21a85 100644
--- a/arch/mips/boards/black-swift/include/board/board_pbl_start.h
+++ b/arch/mips/boards/black-swift/include/board/board_pbl_start.h
@@ -46,6 +46,12 @@ skip_pll_ram_config:
debug_ll_ar9331_init
mips_nmon
+ /*
+ * It is amazing but we have to enable MDIO on GPIO
+ * to use GPIO27 for LED1.
+ */
+ pbl_ar9331_mdio_gpio_enable
+
copy_to_link_location pbl_start
.set pop
diff --git a/arch/mips/dts/black-swift.dts b/arch/mips/dts/black-swift.dts
index 270374d..b0fa3b0 100644
--- a/arch/mips/dts/black-swift.dts
+++ b/arch/mips/dts/black-swift.dts
@@ -1,6 +1,7 @@
/dts-v1/;
#include "ar9331.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Black Swift";
@@ -13,12 +14,26 @@
aliases {
spiflash = &spiflash;
};
+
+ leds {
+ compatible = "gpio-leds";
+
+ s1 {
+ label = "LED1";
+ gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
};
&serial0 {
status = "okay";
};
+&gpio {
+ status = "okay";
+};
+
&spi {
num-chipselects = <1>;
status = "okay";
--
2.7.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 13/15] MIPS: black-swift: enable GPIO key
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
` (11 preceding siblings ...)
2016-03-07 13:30 ` [PATCH 12/15] MIPS: black-swift: enable GPIO LED Antony Pavlov
@ 2016-03-07 13:30 ` Antony Pavlov
2016-03-07 13:30 ` [PATCH 14/15] MIPS: black-swift_defconfig: enable gpio-related stuff Antony Pavlov
` (2 subsequent siblings)
15 siblings, 0 replies; 23+ messages in thread
From: Antony Pavlov @ 2016-03-07 13:30 UTC (permalink / raw)
To: barebox
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/dts/black-swift.dts | 11 +++++++++++
arch/mips/mach-ath79/Kconfig | 1 +
2 files changed, 12 insertions(+)
diff --git a/arch/mips/dts/black-swift.dts b/arch/mips/dts/black-swift.dts
index b0fa3b0..d19c381 100644
--- a/arch/mips/dts/black-swift.dts
+++ b/arch/mips/dts/black-swift.dts
@@ -2,6 +2,7 @@
#include "ar9331.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
model = "Black Swift";
@@ -15,6 +16,16 @@
spiflash = &spiflash;
};
+ buttons {
+ compatible = "gpio-keys";
+
+ s1 {
+ label = "S1";
+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index 9b8e394..374d722 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -18,6 +18,7 @@ config BOARD_BLACK_SWIFT
select HAVE_PBL_IMAGE
select HAVE_IMAGE_COMPRESSION
select HAS_NMON
+ select INPUT
endchoice
--
2.7.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 14/15] MIPS: black-swift_defconfig: enable gpio-related stuff
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
` (12 preceding siblings ...)
2016-03-07 13:30 ` [PATCH 13/15] MIPS: black-swift: enable GPIO key Antony Pavlov
@ 2016-03-07 13:30 ` Antony Pavlov
2016-03-07 13:30 ` [PATCH 15/15] MIPS: tplink-mr3020: fix "WPS" and "3G" LEDs Antony Pavlov
2016-03-09 7:31 ` [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Sascha Hauer
15 siblings, 0 replies; 23+ messages in thread
From: Antony Pavlov @ 2016-03-07 13:30 UTC (permalink / raw)
To: barebox
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/configs/black-swift_defconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/configs/black-swift_defconfig b/arch/mips/configs/black-swift_defconfig
index dda863d..1a72cfb 100644
--- a/arch/mips/configs/black-swift_defconfig
+++ b/arch/mips/configs/black-swift_defconfig
@@ -34,6 +34,8 @@ CONFIG_CMD_EDIT=y
CONFIG_CMD_MM=y
CONFIG_CMD_CLK=y
CONFIG_CMD_FLASH=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_LED=y
CONFIG_CMD_SPI=y
CONFIG_CMD_OF_NODE=y
CONFIG_CMD_OF_PROPERTY=y
@@ -44,5 +46,9 @@ CONFIG_DRIVER_SPI_ATH79=y
CONFIG_MTD=y
# CONFIG_MTD_OOB_DEVICE is not set
CONFIG_MTD_M25P80=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_GPIO_OF=y
+CONFIG_KEYBOARD_GPIO=y
CONFIG_DIGEST_SHA224_GENERIC=y
CONFIG_DIGEST_SHA256_GENERIC=y
--
2.7.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 15/15] MIPS: tplink-mr3020: fix "WPS" and "3G" LEDs
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
` (13 preceding siblings ...)
2016-03-07 13:30 ` [PATCH 14/15] MIPS: black-swift_defconfig: enable gpio-related stuff Antony Pavlov
@ 2016-03-07 13:30 ` Antony Pavlov
2016-03-09 7:31 ` [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Sascha Hauer
15 siblings, 0 replies; 23+ messages in thread
From: Antony Pavlov @ 2016-03-07 13:30 UTC (permalink / raw)
To: barebox
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h b/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h
index 2400015..ef0d36d 100644
--- a/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h
+++ b/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h
@@ -46,6 +46,12 @@ skip_pll_ram_config:
debug_ll_ar9331_init
mips_nmon
+ /*
+ * It is amazing but we have to enable MDIO on GPIO
+ * to use GPIO26 for the "WPS" LED and GPIO27 for the "3G" LED.
+ */
+ pbl_ar9331_mdio_gpio_enable
+
copy_to_link_location pbl_start
.set pop
--
2.7.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH 00/15] MIPS: ar9331: use cache and fix gpio
2016-03-07 13:30 [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Antony Pavlov
` (14 preceding siblings ...)
2016-03-07 13:30 ` [PATCH 15/15] MIPS: tplink-mr3020: fix "WPS" and "3G" LEDs Antony Pavlov
@ 2016-03-09 7:31 ` Sascha Hauer
2016-03-09 8:45 ` Yegor Yefremov
15 siblings, 1 reply; 23+ messages in thread
From: Sascha Hauer @ 2016-03-09 7:31 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox
Hi Antony,
On Mon, Mar 07, 2016 at 04:30:11PM +0300, Antony Pavlov wrote:
> This patchseries introduces initial MIPS cache support.
> Though the cache code is usable for many MIPS-based chips
> at the moment the code is tested mostly on AR9331 SoC.
> So I have decided to submit only AR9331-related cache
> patches and add AR9331 GPIO-related patches to the series.
This series probably deserves a better review than I have given it, but
my knowledge of Mips is nearly not existent. I just applied it.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH 00/15] MIPS: ar9331: use cache and fix gpio
2016-03-09 7:31 ` [PATCH 00/15] MIPS: ar9331: use cache and fix gpio Sascha Hauer
@ 2016-03-09 8:45 ` Yegor Yefremov
2016-03-09 10:34 ` Antony Pavlov
0 siblings, 1 reply; 23+ messages in thread
From: Yegor Yefremov @ 2016-03-09 8:45 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On Wed, Mar 9, 2016 at 8:31 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> Hi Antony,
>
> On Mon, Mar 07, 2016 at 04:30:11PM +0300, Antony Pavlov wrote:
>> This patchseries introduces initial MIPS cache support.
>> Though the cache code is usable for many MIPS-based chips
>> at the moment the code is tested mostly on AR9331 SoC.
>> So I have decided to submit only AR9331-related cache
>> patches and add AR9331 GPIO-related patches to the series.
>
> This series probably deserves a better review than I have given it, but
> my knowledge of Mips is nearly not existent. I just applied it.
I haven't got my hands on this series, but I have used the previous
one. SquashFS patches were developed using the previous version
(Antony's GItHub branch).
Yegor
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 00/15] MIPS: ar9331: use cache and fix gpio
2016-03-09 8:45 ` Yegor Yefremov
@ 2016-03-09 10:34 ` Antony Pavlov
0 siblings, 0 replies; 23+ messages in thread
From: Antony Pavlov @ 2016-03-09 10:34 UTC (permalink / raw)
To: Sascha Hauer, Yegor Yefremov; +Cc: barebox
On Wed, 9 Mar 2016 09:45:11 +0100
Yegor Yefremov <yegorslists@googlemail.com> wrote:
> On Wed, Mar 9, 2016 at 8:31 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > Hi Antony,
> >
> > On Mon, Mar 07, 2016 at 04:30:11PM +0300, Antony Pavlov wrote:
> >> This patchseries introduces initial MIPS cache support.
> >> Though the cache code is usable for many MIPS-based chips
> >> at the moment the code is tested mostly on AR9331 SoC.
> >> So I have decided to submit only AR9331-related cache
> >> patches and add AR9331 GPIO-related patches to the series.
> >
> > This series probably deserves a better review than I have given it, but
> > my knowledge of Mips is nearly not existent. I just applied it.
>
> I haven't got my hands on this series, but I have used the previous
> one. SquashFS patches were developed using the previous version
> (Antony's GItHub branch).
Actually there are only very few cosmetic differences between the maillist series and my github branch.
--
Best regards,
Antony Pavlov
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 23+ messages in thread